Method for forming CMOS image sensor and CMOS image sensor

Abstract

The present invention provides a method for forming a CMOS image sensor and a CMOS image sensor, wherein the CMOS image sensor comprises: a transfer transistor, a reset transistor, and a composite transistor; the composite transistor is composed of a source follower transistor and a row gate transistor, and is used to realize the functions of the source follower transistor and the row gate transistor; wherein the gate region of the composite transistor is a two-gate structure, and the two gate structures are directly spaced by an oxide layer, so that the speed of the device can be improved while saving area.

Description

Technical Field

[0001] The invention relates to a method for forming a CMOS image sensor and a corresponding CMOS image sensor. Background Art

[0002] Image sensors have become ubiquitous. Image sensors are widely used in digital still cameras, cellular phones, surveillance cameras, as well as in medical, automotive and other applications. The technology used to manufacture image sensors continues to advance significantly. For example, the demand for higher resolution and lower power consumption has promoted the further miniaturization and integration of these devices. Currently, image sensors can be divided into charge coupled device (CCD) image sensors and metal oxide semiconductor (CMOS) image sensors. Among them, CMOS image sensors have become the mainstream technology of image sensors due to their high integration, good compatibility, and low power consumption, and with the improvement of CMOS manufacturing process.

[0003] The existing CMOS image sensor pixel unit is composed of a 3T or 4T structure, wherein the 4T (4-Transistors) is composed of a transfer transistor TG, a source follower transistor SF, a reset transistor RST, and a row selection transistor RS; the 3T (3-Transistors) is composed of a transfer transistor TG, a source follower transistor SF, and a reset transistor RST.

[0004] Please refer to Figure 1 , Figure 1 The circuit diagram of a part of the pixel unit of a 3T CMOS image sensor in the prior art is shown in the figure, where TG is a transfer transistor, SF is a source follower transistor, and RST is a reset transistor. The working principle is briefly described as follows: incident light is injected into the PD region of the photodiode to generate photogenerated carriers (electrons and holes); photogenerated electrons and holes are separated under the action of the built-in electric field of the PN junction, so that the photogenerated electrons are gathered in the N-type region of the photodiode; the TG tube is turned on to guide the photogenerated electrons gathered in the N-type region of the photodiode into the FD floating diffusion region, and the SF source follower transistor is used to sense the potential change of the FD floating diffusion region before and after the TG tube is turned on to read out the signal in the photodiode. However, the disadvantage of the 3T CMOS image sensor is: a large charge overflow effect (Big Blooming).

[0005] In order to solve the problem of 3T CMOS image sensor pixel unit, the prior art has proposed a 4T CMOS image sensor pixel unit structure. Figure 2 , Figure 2FIG. 1 is a circuit diagram of a part of a pixel unit of a 4T CMOS image sensor in the prior art, and FIG. Figure 1 compared to, Figure 2 There is an additional row-select transistor RS for realizing the row-select function and a source-drain doping region A between the source-follower transistor SF and the row-select transistor RS. However, due to the relatively short distance between the source-follower transistor SF and the row-select transistor RS and the use of the sidewall, the area of ​​the source-drain doping region is small, resulting in a large path resistance. Therefore, although the charge overflow effect is small in the pixel unit structure of the 4T CMOS image sensor, the addition of a row-select transistor RS leads to a complex structure, a large device area, and a slow speed.

[0006] Therefore, how to avoid the problems existing in the 3T and 4T CMOS image sensors in the prior art and obtain good CMOS image sensor performance has been a problem that has been explored in the industry and needs to be solved urgently. Summary of the invention

[0007] The object of the present invention is to provide a method for forming a CMOS image sensor and a CMOS image sensor, which can, on the one hand, eliminate the problem of large charge overflow effect (Big Blooming) existing in a conventional 3T CMOS image sensor, and on the other hand, eliminate the problem of large device area and slow device readout speed existing in a conventional 4T CMOS image sensor.

[0008] Based on the above considerations, the present invention provides a method for implementing a CMOS image sensor, comprising:

[0009] The CMOS image sensor comprises: a transfer transistor, a reset transistor and a composite transistor; the composite transistor is composed of a source follower transistor and a row gate transistor, and is used to realize the functions of the source follower transistor and the row gate transistor; wherein the gate region of the composite transistor is a two-gate structure, and the two gate structures are directly spaced by an oxide layer.

[0010] Preferably, the steps of the method for forming the CMOS image sensor include:

[0011] Performing conventional processes on semiconductor substrates;

[0012] forming a first oxide layer and a first gate layer in sequence;

[0013] Etching a partial area of ​​the first gate layer to expose a partial area of ​​the first oxide layer;

[0014] removing the exposed first oxide layer;

[0015] forming a second oxide layer and a second gate layer in sequence;

[0016] Removing the second gate layer on the top of the first gate layer to expose the second oxide layer on the top of the first gate layer; removing the exposed second oxide layer, wherein the first gate layer and the second gate layer are directly separated by the second oxide layer on the side wall of the remaining first gate layer;

[0017] The first gate and the second gate are etched to form gate regions that realize the functions of a source follower transistor and a row gate transistor, respectively, thereby forming a composite transistor.

[0018] Preferably, the second gate layer on top of the first gate layer is removed by chemical mechanical polishing or etching.

[0019] Preferably, the first oxide layer has a thickness of 50 angstroms to 100 angstroms.

[0020] Preferably, the thickness of the second oxide layer is 15 angstroms to 50 angstroms.

[0021] Preferably, the first gate layer and the second gate layer have the same thickness and are in a range of 1000 angstroms to 3000 angstroms.

[0022] In addition, the present invention also provides a CMOS image sensor, the CMOS image sensor comprising: forming a transfer transistor, a reset transistor and a composite transistor;

[0023] The composite transistor is a transistor composed of a source follower transistor and a row gate transistor, and is used to realize the functions of the source follower transistor and the row gate transistor; wherein the gate region of the composite transistor is a two-gate structure, and the two gate structures are directly spaced apart by a gate oxide layer.

[0024] The implementation method of the CMOS image sensor of the present invention has the following beneficial technical effects: the method realizes the functions of the source follower transistor and the row gate transistor through a composite transistor; the gate region of the composite transistor is a two-gate structure, and the two gate structures are directly spaced by an oxide layer, so that the source and drain doping regions between the source follower transistor and the row gate transistor can be omitted, ultimately achieving the purpose of saving area and improving device speed.

[0025] In addition, the CMOS image sensor provided by the present invention has the following beneficial technical effects:

[0026] 1. The function of the row-select crystal is retained, thereby eliminating the problem of large charge overflow effect (Big Blooming) in traditional 3T CMOS image sensors;

[0027] 2. By using a composite transistor, the source-drain doping region between the source follower transistor and the row gate transistor is removed, reducing the device area, thereby eliminating the problems of large device area and slow device readout speed in traditional 4T CMOS image sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] By the drawings and the subsequent appendices to the specification Figure 1 With reference to the specific embodiments used to illustrate certain principles of the present invention, other features and advantages of the present invention will become clear or be more specifically explained.

[0029] Figure 1 It is a circuit diagram of a part of the pixel unit of a 3T CMOS image sensor in conventional technology;

[0030] Figure 2 It is a circuit diagram of a part of a pixel unit of a 4T CMOS image sensor in the prior art;

[0031] Figure 3 It is a circuit diagram of a part of the pixel unit area of ​​the CMOS image sensor provided by the present invention;

[0032] Figure 4 This is a partial process cross-sectional structure diagram of a 4T CMOS image sensor in the traditional process;

[0033] Figure 5 is with Figure 4 Corresponding partial process cross-sectional structure diagram of the CMOS image sensor provided by the present invention;

[0034] Figure 6 It is a process step diagram of the method for forming a CMOS image sensor provided by the present invention;

[0035] Figures 7 to 13 It is a structural schematic diagram corresponding to the process steps of the method for forming a CMOS image sensor provided by the present invention. DETAILED DESCRIPTION

[0036] In the following specific description of preferred embodiments, reference will be made to the accompanying drawings which constitute a part of the present invention. The accompanying drawings show by way of example specific embodiments in which the present invention can be implemented. The implementation of the examples is not intended to be exhaustive of all embodiments according to the present invention. It will be appreciated that other embodiments may be utilized and structural or logical modifications may be made without departing from the scope of the present invention. Therefore, the following specific description is not restrictive, and the scope of the present invention is limited by the appended claims.

[0037] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-restrictive in any way. Furthermore, it is apparent that the term "comprising" does not exclude other elements and steps, and the wording "a" does not exclude the plural. Multiple elements stated in a device claim may also be implemented by one element. The terms first, second, etc. are used to indicate names and do not indicate any particular order.

[0038] The present invention provides a CMOS image sensor and a method for forming the same. Figures 3 to 13 . Figure 3 It is a partial circuit diagram of the CMOS image sensor provided by the present invention; Figure 4 This is a partial process cross-sectional structure diagram of a 4T CMOS image sensor in the traditional process; Figure 5 is with Figure 4 Corresponding partial process cross-sectional structure diagram of the CMOS image sensor provided by the present invention; Figure 6 It is a process step diagram of the method for forming a CMOS image sensor provided by the present invention; Figures 7 to 13 It is a structural schematic diagram corresponding to the process steps of the method for forming a CMOS image sensor provided by the present invention.

[0039] like Figure 3 As shown, the CMOS image sensor provided in the embodiment of the present invention includes: a transfer transistor TG, a reset transistor RST and a composite transistor;

[0040] As shown in the range indicated by circle F in the figure, the composite transistor is composed of a source follower transistor RS and a row selection transistor SF, and can realize the functions of the source follower transistor SF and the row selection transistor RS; wherein the gate region of the composite transistor is a two-gate structure in which the gates of the source follower transistor SF and the row selection transistor RS are directly separated by an oxide layer.

[0041] like Figure 4 As shown ( Figure 4The structure used for back-end interconnection is only shown in the figure, but not marked and described). A cross-sectional view of the process structure of a 4T CMOS image sensor in the prior art. The 4T CMOS image sensor shown includes: a transfer transistor gate (TG gate) 41, a floating diffusion region (FD) 42, a reset transistor gate (RST GT) 43, a source follower transistor gate (SF GT) 44 and a row gate transistor gate (RS GT) 45. As shown in the range indicated by the circle B in the figure, the source follower transistor (SF) and the row gate transistor (RS) are connected through a source-drain doping region 46; on the one hand, due to the narrow distance between the source follower transistor gate (SF GT) 44 and the row gate transistor gate (RS GT) 45, and the use of the sidewall, the doping amount in the source-drain doping region 46 is very small, so the resistance of the device is large and the readout speed is slow. On the other hand, the use of this source-drain doping region 46 also increases the area of ​​the device.

[0042] like Figure 5 As shown ( Figure 5 The structure used for back-end interconnection is only shown in the figure, but not marked and described). The CMOS image sensor provided in the embodiment of the present invention includes: a transfer transistor gate (TG gate) 31, a floating diffusion region (FD) 32, a reset transistor gate (RST GT) 33, and a composite transistor gate; as shown in the range indicated by the circle C in the figure, the composite transistor gate includes a source follower transistor gate (SF GT) 34 and a row gate transistor gate (RS GT) 35. In addition, the two gate structures of the source follower transistor gate (SF GT) 34 and the row gate transistor gate (RS GT) are directly spaced by an oxide layer to form a composite transistor. Compared with the traditional 4T CMOS image sensor, the composite transistor provided in the embodiment of the present invention omits the source-drain doping region between the source follower transistor and the row gate transistor, shortens the distance between the source follower transistor and the row gate transistor, and reduces the path resistance, thereby saving area and improving the image sensor performance.

[0043] like Figure 6 The method for forming the CMOS image sensor comprises the following steps:

[0044] Step S001: performing a series of conventional processes on a semiconductor substrate, the conventional processes being used to form shallow trench isolation, logic devices and a photodiode region of a pixel unit;

[0045] Step S002: forming a first oxide layer and a first gate layer in sequence;

[0046] Step S003: etching a portion of the first gate layer to expose a portion of the first oxide layer;

[0047] Step S004: removing the exposed first oxide layer;

[0048] Step S005: forming a second oxide layer and a second gate layer in sequence;

[0049] Step S006: removing the second gate layer on the top of the first gate layer to expose the second oxide layer on the top of the first gate layer;

[0050] Step S007: removing the exposed second oxide layer, wherein the first gate layer and the second gate layer are directly separated by the second oxide layer on the side wall of the remaining first gate layer;

[0051] Step S008: etching the first gate and the second gate to respectively form gate regions that realize the functions of a source follower transistor and a row gate transistor, thereby forming a composite transistor.

[0052] Specifically, in this embodiment, the method for forming the CMOS image sensor specifically includes:

[0053] Execute step S001: perform a series of conventional processes on a semiconductor substrate, the conventional processes are used to form shallow trench isolation, logic devices and a photodiode region of a pixel unit (not shown in the figure);

[0054] refer to Figure 7 , executing step S002: forming a first oxide layer and a first gate layer;

[0055] The CMOS image sensor comprises a substrate 100 , on which there is an isolation trench 102 , a first oxide layer 101 formed on the surfaces of the substrate 100 and the isolation trench 102 , a first gate layer 103 , and a photodiode region of a pixel unit (not shown in the figure).

[0056] Preferably, the first oxide layer has a thickness of 50 angstroms to 100 angstroms.

[0057] Preferably, the first gate layer is deposited to a thickness of 1000 angstroms to 3000 angstroms.

[0058] refer to Figure 8 , executing step S003: etching a partial area of ​​the first gate layer to expose a partial area of ​​the first oxide layer;

[0059] The first gate layer 103 is partially removed by photolithography and etching to expose a partial area of ​​the first oxide layer. The area where the first gate layer 103 is removed is the area where the row gate transistor gate (RS GT) in the composite transistor is located.

[0060] refer to Fig. 9, executing step S004: removing the exposed first oxide layer;

[0061] The exposed first oxide layer 103 is removed by an etching process, exposing the substrate 100 in the region where the row gate transistor gate (RS GT) in the composite transistor is located.

[0062] refer to Fig.10 , executing step S005: depositing to form a second oxide layer and a second gate layer;

[0063] A second oxide layer 104 is formed on the first gate layer 103 and the exposed surface of the substrate 100 by a deposition process. Preferably, the thickness of the second oxide layer is 15 angstroms to 50 angstroms. The area where the second oxide layer is located is the row selection transistor area. By using a thinner second oxide layer, the operating voltage can be further reduced and the readout speed of the device can be increased;

[0064] Then, a second gate layer 105 is formed on the surface of the second oxide layer 104 through a deposition process. Preferably, the first gate layer and the second gate layer are deposited to have the same thickness, which is 1000 angstroms to 3000 angstroms.

[0065] refer to Fig.11 , executing step S006: removing the second gate layer on the top of the first gate layer to expose the second oxide layer on the top of the first gate layer;

[0066] Preferably, the second gate layer on top of the first gate layer is removed by chemical mechanical polishing or etching.

[0067] Continue to refer Fig.11 , executing step S007: removing the exposed second oxide layer, wherein the first gate layer and the second gate layer are directly separated by the second oxide layer on the side wall of the remaining first gate layer;

[0068] The exposed second oxide layer 104 is removed by etching process, thereby exposing the first gate layer 103. Meanwhile, the second gate layer 105 and the second oxide layer 104 between the first gate layer 103 and the second gate layer 105 are also exposed.

[0069] refer to Figure 12 to Figure 13 , executing step S008: etching the first gate and the second gate to respectively form gate regions that realize the functions of a source follower transistor and a row gate transistor, thereby forming a 1.5T composite transistor.

[0070] like Fig.12As shown, a photoresist blocking layer 106 is formed on the first gate layer 103, the second gate layer 105, and the second oxide layer 104 therebetween by using photolithography technology, and the photoresist blocking layer 106 covers the gate region (ie, the two-gate structure) of the composite transistor.

[0071] like Fig.13 As shown, the first gate layer 103 and the second gate layer 105 in the area not covered by the photoresist barrier layer 106 are removed by etching technology, and then the photoresist barrier layer 106 is removed to expose the first gate layer 103, the second gate layer 105, and the second oxide layer 104 therebetween, thus forming a two-gate structure of the composite transistor, and further forming the 1.5T composite transistor;

[0072] The composite transistor is composed of a source follower transistor RS and a row selection transistor SF, and can realize the functions of the source follower transistor SF and the row selection transistor RS; wherein the composite transistor omits the source-drain doping region between the source follower transistor and the row selection transistor, and the gate region is a two-gate structure in which the gates of the source follower transistor SF and the row selection transistor RS are separated by an oxide layer.

[0073] In addition, in the above process steps, the two-gate structure in the composite transistor is formed in a self-aligned manner, which has a large process window.

[0074] In this embodiment, a CMOS image sensor is further provided, the CMOS image sensor comprising: forming a transfer transistor, a reset transistor and a composite transistor;

[0075] The composite transistor is a transistor composed of a source follower transistor and a row gate transistor, and can realize the functions of a source follower transistor and a row gate transistor; wherein the gate region of the composite transistor is a two-gate structure, and the two gate structures are directly spaced by a gate oxide layer, thereby saving area while improving image sensor performance.

[0076] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A CMOS image sensor, characterized in that , The CMOS image sensor comprises: a transfer transistor, a reset transistor and a composite transistor; The composite transistor is composed of a source follower transistor and a row gate transistor, and is used to realize the functions of the source follower transistor and the row gate transistor; wherein the gate region of the composite transistor is a two-gate structure, and the two gate structures are directly spaced apart by an oxide layer.

2. A method for forming a CMOS image sensor as claimed in claim 1, characterized in that the steps include: Performing conventional processes on semiconductor substrates; forming a first oxide layer and a first gate layer in sequence; Etching a portion of the first gate layer to expose a portion of the first oxide layer; removing the exposed first oxide layer; forming a second oxide layer and a second gate layer in sequence; Removing the second gate layer on the top of the first gate layer to expose the second oxide layer on the top of the first gate layer; removing the exposed second oxide layer, wherein the first gate layer and the second gate layer are directly separated by the second oxide layer on the side wall of the remaining first gate layer; The first gate and the second gate are etched to form gate regions that realize the functions of a source follower transistor and a row gate transistor, respectively, thereby forming a composite transistor.

3. The method for forming a CMOS image sensor according to claim 2, wherein: The second gate layer on top of the first gate layer is removed by chemical mechanical polishing or etching.

4. The method for forming a CMOS image sensor according to claim 2, wherein: The thickness of the first oxide layer is 50 angstroms to 100 angstroms.

5. The method for forming a CMOS image sensor according to claim 2, wherein: The thickness of the second oxide layer is 15 angstroms to 50 angstroms.

6. The method for forming a CMOS image sensor according to claim 2, wherein: The first gate layer and the second gate layer are deposited to have the same thickness of 1000 angstroms to 3000 angstroms.

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