Optical sensor and signal reading method thereof, and area optical sensor and signal reading method thereof

Abstract

Provided is a photo sensor capable of maintaining the advantages and strengths of a conventional photo sensor having a transfer switch between a photodetector (PD) and a floating diffusion capacitor (CFD), while being able to read at a higher speed than conventional ones and further reducing power consumption. The semiconductor junction of the photodetector is completely depleted, and the potential energy curve of the electrons of the photodetector is negatively tilted toward the floating diffusion capacitor and is connected to the uppermost portion of the electron potential well of the floating diffusion capacitor while maintaining the negative tilt.

Description

Technical Field

[0001] The present invention relates to an optical sensor and a signal reading method thereof, which are particularly used in an apparatus for optical measurement / analysis, and can read out clear images at a high speed of more than 1 million frames per second, as well as an area optical sensor and a signal reading method thereof. Background Art

[0002] With the development of science and technology and the penetration of the network society, the demand for linear or area optical sensors, solid-state imaging devices, etc. (hereinafter, any of them will be referred to as "optical sensors", or collectively referred to as "optical sensors") is growing rapidly. Among them, optical sensors that can cope with high sensitivity / high speed / wide dynamic range / wide light wavelength bands used in devices for optical measurement / analysis, etc., and solid-state imaging devices that can cope with still images / moving images are strongly in demand in the market as necessary items for opening up new markets. In particular, optical sensors and solid-state imaging devices with a wider dynamic range are eagerly anticipated in the medical / pharmaceutical / health / nursing markets, life science markets, disaster prevention and crime prevention markets required to form a safe and secure society, and the 4K and 8K broadcasting era.

[0003] Examples of optical sensors and solid-state imaging devices that support high sensitivity, high speed, wide dynamic range, and wide optical wavelength band are described in Patent Document 1, for example.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent document 1: International Publication No. WO2016080337 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] The optical sensor / solid-state imaging device described in Patent Document 1 (hereinafter, either or both of the optical sensor and the solid-state imaging device may sometimes be referred to as "optical sensor") is indeed better than ever in terms of handling high sensitivity / high speed / wide dynamic range / wide optical wavelength band, but in order to meet the needs of the above-mentioned market and the times, while taking advantage of these advantages, further high-speed responses are sought.

[0009] However, the above-mentioned light sensor is provided with a transfer switch between a photodiode (hereinafter sometimes referred to as "PD"), which is one of the light-receiving elements, and a floating diffusion capacitor (hereinafter sometimes referred to as "CFD"), and the charge existing in the photodiode (PD) is transferred to the floating diffusion capacitor (CFD) by turning the transfer switch on and off. For this purpose, the settling time of the pixel drive pulse required for turning the transfer switch on and off is required, which limits the speed increase of the frame rate. In addition, it is necessary to propagate multiple pixel drive pulses to the entire pixel area at a high speed, which increases power consumption.

[0010] In addition, unless otherwise specified, when a "pixel" is described in the present case, the pixel means that the pixel is composed of a light receiving element (PD) and a floating diffusion capacitor (CFD).

[0011] The present invention is completed in view of the above-mentioned points, and its main purpose is to provide a light sensor that can maintain the advantages and strengths of the previous light sensor in which a transfer switch is provided between a light receiving element (PD) such as a photodiode and a floating diffusion capacitor (CFD), while being able to read at a higher speed than before and further reduce power consumption.

[0012] Solutions for solving problems

[0013] The present invention is the result of intensive research and development in view of the above-mentioned points, and one of its characteristics is a signal reading method of a photosensor and a photosensor used in the signal reading method, characterized in that by receiving light through a light-receiving element, the semiconductor junction of the light-receiving element is completely depleted, and the potential energy curve of the electrons in the light-receiving element is negatively tilted toward the direction of the floating diffusion capacitor, and the potential energy curve is connected to the uppermost part of the electron potential well of the floating diffusion capacitor while maintaining the negative tilt state, and at least two accumulation steps are performed in sequence during the same frame period set during the period of receiving light, and the accumulation step is a step of transferring and accumulating the electrons generated inside the light-receiving element corresponding to the received light into the potential well according to the potential energy curve.

[0014] Another feature of the present invention is a photosensor and a signal readout method thereof, characterized in that it has a light receiving element, a floating diffusion capacitor, and a pixel signal output line, wherein the floating diffusion capacitor is directly electrically connected to the light receiving element and accumulates charge generated by light input to the light receiving element, and the signal readout path is connected to the pixel signal output line.

[0015] The capacitance (C PD ) and the capacitance of the floating diffusion capacitor (C FD ) has the following relationship:

[0016] 0.0008≤(C PD ) / (C FD )≤0.8··········(1)

[0017] 4.0×10 -18 F≤(C PD )≤4.0×10 -16 F·····(2)

[0018] 5.0×10 -16 F≤(C FD )≤5.0×10 -15 F······(3)

[0019] The semiconductor junction of the light-receiving element is completely depleted, and the potential energy curve of the electrons of the light-receiving element tilts negatively toward the floating diffusion capacitor, and the potential energy curve is connected to the uppermost portion of the electron potential well of the floating diffusion capacitor while maintaining the negative tilt.

[0020] Another feature of the present invention is a regional optical sensor and a signal readout method thereof, comprising:

[0021] a light sensor pixel circuit unit, comprising a light sensor pixel circuit and an intra-pixel correlated double sampling circuit, wherein the light sensor pixel circuit comprises a light receiving element and a floating diffusion capacitor, wherein the floating diffusion capacitor is directly electrically connected to the light receiving element and accumulates charges generated by light input to the light receiving element, wherein the semiconductor junction of the light receiving element is completely depleted, and the light receiving element has an electron potential curve, wherein the potential curve is negatively inclined toward the floating diffusion capacitor, and the potential curve is connected to the uppermost portion of the electron potential well of the floating diffusion capacitor while maintaining the negative inclination, wherein the light sensor pixel circuit has two output systems that are used alternately on a time axis, wherein the intra-pixel correlated double sampling circuit performs noise elimination based on a first output (a1) and a second output (b1) to output a signal (ab1), wherein the first output (a1) and the second output (b1) are outputs output from one output system based on the amount of photocharge generated in the light receiving element by light irradiation; and

[0022] An analog memory circuit unit comprises an analog memory array, a memory cell row selection switch array and a memory read circuit, wherein the analog memory array is obtained by arranging a plurality of memory cells in an array, the memory cells are used to hold the signal (ab1) and a signal outputted from either a first output (a2) or a second output (b2) outputted from another output system, the memory cell row selection switch array is used to select any memory cell configuration row, and the memory read circuit is used to read the signal held in any memory cell.

[0023] Effects of the Invention

[0024] According to the present invention, it is possible to provide an optical sensor and a signal reading method using the optical sensor that can perform reading at a higher speed than before and further reduce power consumption while maintaining the advantages and strengths of the conventional optical sensors.

[0025] Other features and advantages of the present invention will become more apparent from the following description with reference to the accompanying drawings. In addition, in the accompanying drawings, the same reference numerals are used to indicate the same or similar structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included in and constitute a part of the specification, illustrate embodiments of the present invention, and together with the description thereof, serve to explain the principles of the present invention.

[0027] Figure 1 This is a circuit diagram for explaining a pixel circuit portion which is one typical example of a preferred embodiment of the photosensor of the present invention.

[0028] Figure 2A It is a potential energy explanatory diagram for explaining the principle of pixel driving of the photosensor as a preferred embodiment of the present invention, and is an explanatory diagram at the time of resetting completion (t1).

[0029] Figure 2B It is a potential energy explanatory diagram for explaining the principle of pixel driving of the photosensor as a preferred embodiment of the present invention, and is an explanatory diagram at the time of first voltage signal reading (t2).

[0030] Figure 2C It is a potential energy explanatory diagram for explaining the principle of pixel driving of the photosensor as a preferred embodiment of the present invention, and is an explanatory diagram at the time of second voltage signal reading (t3).

[0031] Figure 3 This is a circuit diagram for explaining an analog memory circuit portion of the photosensor according to the present invention.

[0032] Figure 4This is a timing chart showing an example of the timing of driving the pixels of the photosensor according to the present invention and the time transition of the floating diffusion capacitor voltage (VFD).

[0033] Figure 5 FIG. 1 is a timing chart showing another example of the timing of driving the pixels of the photosensor according to the present invention and the time transition of the floating diffusion capacitor voltage (VFD).

[0034] Figure 6 This is a block diagram for explaining the structure of the image sensor of the present invention.

[0035] Figure 7 1 is a layout diagram showing an example of the arrangement of the photosensor pixel circuit portion 100 , the analog memory circuit portion 300 , and the pixel output signal line (PIXEL_OUT) 117 constituting the light reception signal generating and holding element according to the present invention.

[0036] Figure 8 1 is a layout diagram showing another example of the arrangement of the photosensor pixel circuit portion 100 , the analog memory circuit portion 300 , and the pixel output signal line (PIXEL_OUT) 117 constituting the light reception signal generating and holding element according to the present invention. DETAILED DESCRIPTION

[0037] Figure 1 This is a circuit diagram for explaining a pixel circuit portion which is one typical example of a preferred embodiment of the photosensor of the present invention.

[0038] Figure 1 The photosensor pixel circuit section 100 shown includes a photosensor pixel circuit 101 a and an intra-pixel correlated double sampling circuit (In-pixel CDS) 101 b .

[0039] The light sensor pixel circuit 101a includes a light receiving element (PD) 102, a floating diffusion capacitor (CFD) 103, a reset transistor (R) 104, a first source follower transistor (SF1) 105, a first selection transistor (X1) 106, a first current source transistor (CS1) 107, an intra-pixel correlated double sampling selection switch (CDS) 108, and an intra-pixel correlated double sampling bypass switch (CDSb) 109.

[0040] exist Figure 1 In FIG. 1 , a photodiode (PD) is shown as one of the preferred examples of the light receiving element (PD) 102 , but a phototransistor other than this may also be used.

[0041] The intra-pixel correlated double sampling circuit 101b has an intra-pixel correlated double sampling coupling capacitor (C C )110, In-pixel correlated double sample and hold capacitor (CSH ) 111, an intra-pixel correlated double sampling reset transistor (NS) 112, a second source follower transistor (SF2) 113, a second selection transistor (X2) 114, a second selection transistor (X2') 115 and a second current source transistor (CS2) 116.

[0042] A pixel output signal line (PIXEL_OUT) 117 for transmitting a signal to a next electrical circuit is wired from the intra-pixel correlated double sampling circuit 101 b .

[0043] The most significant, useful, and improved feature of the photosensor of the present invention over prior art examples is the physical structure of the photodetecting element (PD) 102 and the potential associated with its photocharges (electrons).

[0044] The internal structure of the light receiving element (PD) 102 is provided with at least one semiconductor type (P + Type, P type, P - Type, I type, N + Type, N type, N - A semiconductor junction formed by joining semiconductor layer regions of the same type (type).

[0045] In the present invention, a fully depleted or substantially fully depleted (hereinafter sometimes referred to as "fully depleted type" including any meaning) potential energy (related to photocharge) is formed in the semiconductor junction region of the light receiving element (PD) 102 .

[0046] In the present invention, "complete exhaustion" means that Figure 2A to Figure 2C As shown, in the potential energy partition 201, the potential energy displacement (or, inclination or gradient) is from Figure 2A to Figure 2C The surface gradually decreases from the left end to the right end.

[0047] In the present invention, “substantially complete depletion” means a potential energy displacement of a shape in which photocharges generated in a semiconductor junction region of the light receiving element (PD) 102 by receiving light can be smoothly transferred to the adjacent floating diffusion capacitor (CFD) 103 .

[0048] Their details will be described later.

[0049] In the optical sensor of the present invention, it is more preferable to use the capacitance (C PD ) and the capacitance (C FD ) is set so that the capacitance (C PD ) and capacitance (C FD ).

[0050] 0.0008≤(C PD) / (C FD )≤0.8············(1)

[0051] 4.0×10 -18 F≤(C PD )≤4.0×10 -16 F····(2)

[0052] 5.0×10 -16 F≤(C FD )≤5.0×10 -15 F·····(3)

[0053] Next, the technical meanings of formulas (1) to (3) in the present invention are described.

[0054] In the pixel of the photosensor of the present invention,

[0055] The saturation charge is

[0056] “Vsat×(C FD +C PD ) / q”······(a),

[0057] Therefore, the charge-to-voltage conversion gain is given by

[0058] “q / (C FD +C PD )"············(b)

[0059] To give.

[0060] Here,

[0061] “C PD ” is set to be the capacitance of the fully depleted light receiving element (PD) 102,

[0062] “C FD ” is set to the capacitance of the floating diffusion capacitor (CFD) 103,

[0063] “Vsat” is set to the saturation signal voltage in the floating diffusion capacitor (CFD) 103,

[0064] "q" is set to the elementary charge.

[0065] In the present invention, the semiconductor junction region in the internal structure of the light receiving element (PD) 102 may be of either a lateral type or a vertical type, but the vertical type is more preferably adopted.

[0066] Capacitor "C PD ” is proportional to the bonding area of ​​the semiconductor junction of the light receiving element (PD) 102.

[0067] The “joining area” is not necessarily the same as the area of ​​the light incident side of the light receiving element (PD) 102 (the area actually irradiated with light: the light receiving area), and may be larger than the light receiving area.

[0068] Hereinafter, “the area on the light incident side” may be abbreviated as “area”.

[0069] In order to improve the sensitivity of the light receiving element 102 and make the photosensor more sensitive, if the light receiving area of ​​the light receiving element 102 is increased, the number of photocharges per pixel (one light receiving element) under the same irradiation light amount conditions increases, thereby increasing the sensitivity. However, since the maximum movement distance of the photocharges becomes longer, it becomes difficult to improve the time resolution (hereinafter sometimes also referred to as "simultaneity") (high-speed readout).

[0070] The "maximum movement distance of photocharges" mentioned here refers to the maximum movement distance (movement distance) of photocharges generated at the semiconductor junction of the photoreceiving element (PD) 102 when the photoreceiving element (PD) 102 receives light from the outside and moves to the floating diffusion capacitor (CFD) 103.

[0071] The time taken for the photocharge generated near the floating diffusion capacitor (CFD) 103 and the photocharge generated farther from the floating diffusion capacitor (CFD) 103 to reach the floating diffusion capacitor (CFD) 103 is different. The time taken for the photocharge generated farther from the floating diffusion capacitor (CFD) 103 to reach the floating diffusion capacitor (CFD) 103 (arrival time) is longer. If the difference in arrival time becomes larger, for example, when the frame rate is continuously increased to perform high-speed video recording, although the photocharge is generated at the same time, the photocharge whose arrival time is slower than the frame rate is detected as a light signal in the subsequent frame, and the effective time resolution is inferior to the frame rate.

[0072] In the present invention, the physical structure of the photosensitive element (PD) 102 is designed on the premise of ensuring high photosensitivity, so that the difference in the movement time of the photocharges generated in the photosensitive element (PD) 102 is minimized to improve the time resolution to cope with high-speed readout.

[0073] The light receiving area of ​​the fully depleted light receiving element (PD) 102 in the present invention is preferably an area that can sufficiently ensure the amount of light received and collect the generated photocharge within 10 nsec. Such an area is preferably 5 μm square (Japanese: 5 μm angle) to 50 μm square (Japanese: 50 μm angle).

[0074] Therefore, it is desirable that the capacitance (C PD) is in the range of 4.0×10-18F or more for a light receiving area equivalent to 5µm square to 4.0×10-16F or less for a light receiving area equivalent to 50µm square.

[0075] In the present invention, since the floating diffusion capacitor (CFD) 103 is directly connected to the fully depleted light receiving element (PD) 102 that forms an electric field for drifting and transporting photocharges in the direction of the floating diffusion capacitor (CFD) 103, it is preferable to FD ) and capacitance (C PD ) is set so that the charge-to-voltage conversion gain and the saturation charge number are less likely to affect the light receiving area and layout of the photosensitive element (PD) 102.

[0076] Preferably, the desired capacitance (C FD ) is greater than the capacitance (C PD ), more preferably, it is desired to be able to ignore the capacitance (C PD ) case, the capacitor (C FD ) is greater than the capacitance (C PD ), (C FD +C PD ) and capacitance (C FD ) are consistent or roughly consistent.

[0077] When the capacitor (C PD ) becomes larger than the capacitance (C FD ), even if the light receiving area of ​​the light receiving element (PD) 102 is slightly changed, the difference is not negligible. FD +C PD ) is inversely proportional to the charge-to-voltage conversion gain and (C FD +C PD ) is also affected and changes. In this case, in the present invention, the change can be ignored as long as it is within the range that can achieve the purpose of the present invention, so the deviation caused by the design of the light receiving element (PD) 102 can be allowed within the range that can ignore the change.

[0078] In the present invention, a high charge-to-voltage conversion gain can reduce noise, but if the capacitance (C FD ) value, the saturation charge decreases, so as a capacitor (C FD ) is preferably between 5.0×10 -16 f / 5.0 x 10 -15 The range of F.

[0079] In the capacitor (C FD ) is 5.0×10 -16 F or above, the capacitance (C FD) is sufficiently larger than the capacitance (C PD ) and the capacitance (C PD ), the charge-to-voltage conversion gain is 320µ; V / e - Furthermore, the capacitance (C FD ) is 80µ; when Vrms is below, the accuracy with which the number of photocharges collected can be counted can be obtained even if the number of photocharges collected is small.

[0080] On the other hand, the capacitor (C FD ) is 5.0×10 -15 When F is less than or equal to 1 V and "Vsat" is greater than or equal to 1 V, the saturation charge number is 30,000 or more, and overexposure can be suppressed even when a strong amount of light is locally irradiated to a pixel.

[0081] Capacitance (C FD )Specific capacitance (C PD ) is not affected by the area and shape of the photodiode, and only the capacitance (C FD ) is used to design the charge-to-voltage conversion gain and saturation charge number, so it is expected that (C PD / C FD ) is less than 1, but in the present invention, it is preferred that (C PD / C FD ) is expected to be in the range of 0.0008 to 0.8.

[0082] If (C PD / C FD ) is less than 0.0008, the light receiving area of ​​the photosensitive element (PD) 102 becomes substantially smaller, and the photosensitivity is so low that the purpose of the present invention cannot be achieved and the sensor is no longer suitable as a high-speed reading sensor.

[0083] If (C PD / C FD ) exceeds 0.8, the charge-voltage conversion gain becomes smaller and the photosensitivity becomes smaller, resulting in a situation where the purpose of the present invention cannot be achieved.

[0084] To be applied or given to be described later Figure 1 The numbers and names of the electrical terminals of the signals (voltage, electric pulse, etc.) used when the optical sensor shown operates are as follows.

[0085] Terminal 118 is a terminal for pixel reset voltage (VR_FD).

[0086] Terminals 119a and 119b are terminals for power supply voltage (AVDD).

[0087] Terminal 120 is a terminal for the reset voltage (VR_CDS) of the correlated double sampling circuit in the pixel.

[0088] Terminal 121 is a terminal for the first current source bias voltage (VB1).

[0089] Terminal 122 is a terminal for the second current source bias voltage (VB2).

[0090] Terminal 123 is a terminal for pixel reset pulse (φR).

[0091] Terminal 124 is a terminal for the first pixel selection pulse (φX1).

[0092] Terminal 125 is a terminal for selecting a pulse (φCDS) for the intra-pixel correlated double sampling circuit.

[0093] Terminal 126 is a terminal for bypass pulse (φCDSb) of the intra-pixel correlated double sampling circuit.

[0094] Terminal 127 is a terminal for pixel selection second pulse (φX2).

[0095] Terminal 127a is a terminal for pixel selection 2A pulse (φX2`).

[0096] The terminal 128 is a terminal for an intra-pixel correlated double sampling reset pulse (φNS).

[0097] Figure 2A to Figure 2C This is a potential energy explanatory diagram for explaining the principle of pixel driving of the photosensor according to the present invention.

[0098] Figure 2A is the potential energy diagram when reset is completed (t1), Figure 2B is the potential energy diagram when the first voltage signal is read out (t2), Figure 2C is the potential energy diagram when the second voltage signal is read out (t3).

[0099] When the reset is completed (t1), the first voltage signal is read (t2), and the second signal is read (t3), Figure 4 is shown in the timing diagram.

[0100] exist Figure 2A to Figure 2C In each figure, the vertical axis represents the electron (e - ), and the horizontal axis is an arbitrary axis in space. In each figure, the potential energy partition (PD) 201 of a fully depleted photodiode as one of the light receiving elements (PD) 102 and the electrons (e) in the potential energy (CFD) partition 202 of the floating diffusion capacitor (CFD) 103 adjacent to the partition 201 are shown. - ) associated with the potential energy.

[0101] In the present invention, "fully depleted" means that Figure 2A to Figure 2C As shown, in the potential energy partition 201, the potential energy displacement (or, inclination or gradient) is from Figure 2A to Figure 2C The surface gradually decreases from the left end to the right end.

[0102] In the present invention, the potential energy displacement is not limited to the "complete depletion type" and may be a "substantially complete depletion type".

[0103] In the present invention, "substantially fully depleted" refers to a potential energy displacement within a range that does not lose the essence of the present invention. For example, the potential energy displacement in the portion near the left end or / and the right end may be flat, or the reduction ratio may be gentle compared to the center of the potential energy displacement, or the displacement may be in the form of a small step-like reduction. In short, as long as the potential energy displacement (or potential gradient, electric field gradient) can be formed within a range that does not hinder the high-speed readout set for the desired purpose, so that the generated photocharges can drift and move or can be drifted and transported to the end point of the potential energy displacement (drifted and transported to the floating diffusion capacitor (CFD) 103) within the readout time, the displacement shape of the potential energy displacement (or, inclination or gradient) from the left end to the right end can be adopted in the present invention regardless of whether it is a uniform reduction, a step-like reduction, or a wavy reduction.

[0104] In the present invention, when “fully depleted” is not particularly described, it means both or either of the original meaning of “fully depleted” and the meaning of “substantially fully depleted” exemplified above.

[0105] Figure 3 1 is a circuit diagram for explaining an analog memory circuit section of a photosensor according to the present invention. The analog memory circuit section 300 is one typical example of a preferred embodiment.

[0106] exist Figure 3 2 and 3. The light sensor pixel circuit section 100 and the analog memory circuit section 300 are shown in FIG.

[0107] The analog memory circuit section 300 includes an analog memory array (Analog Memories) 301 , a memory cell row selection switch array 301 a , and a memory readout circuit (Memory Readout) 302 .

[0108] In this embodiment, the analog memory array 301 is composed of a memory selection switch (SW) and a storage capacitor (C AM ) constitutes a memory cell having 4 H ×20 VA total of 20 memory cells in each row share one signal wiring, and the signal wiring is selected by a row selection switch (WS1 to WS4).

[0109] In addition, Figure 3 In the simulation, the memory array 301 is set to (4 H ×20 V ) memory arrays, but only (4 H ×20 V ) memory cells, and illustration of other memory cells is omitted.

[0110] The memory cell column selection switch array 301a includes memory column selection switches (WS1 to WS4) 305 (1 to 4). Figure 3 In the figure, four switches are shown as the memory column selection switches (WS1 to WS4) 305 (1 to 4), but the present invention is not limited to this, and the number of columns of the memory array 301 may be increased or decreased according to a predetermined design.

[0111] exist Figure 3 In the pixel signal holding memory array 303, four groups of memory cells 307a are shown, which are connected by a pixel signal holding memory selection switch (SW) 306 and a pixel signal holding capacitor (C AM )307 constitute a group of memory cells 307a.

[0112] about Figure 3 The pixel signal holding memory array 304 in FIG. 1 is also set to have the same memory structure as the pixel signal holding memory array 303. That is, the analog memory array (Analog Memories) 301 is (4 H ×20 V ) memory cells 307a are arranged in an array.

[0113] Here, "4 H ×20 V " means that 4 memory cells are arranged in the horizontal direction (in each row) and 20 memory cells are arranged in the vertical direction (in each column).

[0114] The two-dimensional matrix analog memory array 301 originally has 20 rows of pixel signal holding memory arrays, but Figure 3 Only two pixel signal holding memory arrays (303, 304) are described, and illustration of other pixel signal holding memory arrays is omitted.

[0115] A total of 20 memory cells in each column share one of the four signal lines 313 (1 to 4) for transmitting pixel signals, and each signal line "1 to 4" is selected by turning on the corresponding memory column selection switch (any one of WS1 to WS4) among the four memory cell column selection switches 305 (WS1 to WS4).

[0116] In order to shorten the distance of the pixel output signal line (PIXEL_OUT) 117 and shorten the time required for signal readout, it is desirable to arrange the analog memory circuit section 300 adjacent to the photosensor pixel circuit section 100, for example, as shown in FIG. Figure 7 As shown in FIG. 1 , the light sensor pixel circuit unit 100 is disposed adjacent to the light sensor pixel circuit unit 100 on the same plane. Figure 8 As shown in FIG. 1 , the optical sensor pixel circuit section 100 is stacked and arranged. Figure 8 In the case of the stacked configuration shown, the area of ​​the photodiode (PD) 102 can be relatively increased, and thus it is preferable to increase the light receiving area and obtain higher sensitivity.

[0117] Next, a signal writing operation of writing pixel output signals into the analog memory array 301 will be described.

[0118] First, a row selection pulse is applied to the row selection switch 305 to select the row in which the memory cell to be written with a signal is located.

[0119] Next, in order to select a memory cell to be written with a signal, a memory selection pulse is applied to the memory selection switch (SW), and the pixel output is connected to a storage capacitor (C AM ) is electrically connected. AM ) writes the pixel output signal voltage. Then, the memory selection switch (SW) is turned off to keep the voltage written to the storage capacitor (C AM ) signal voltage.

[0120] When the intra-pixel correlated double sampling selection switch (CDS) 108 is turned on, one signal is output from one pixel in one frame. When the intra-pixel correlated double sampling selection switch (CDS) 108 is turned off, two or more signals are output from one pixel in one frame. Therefore, the memory selection switch (SW) 306 and the row selection switch (WS) 305 are switched during one frame to switch the storage capacitor (C ) electrically connected to the pixel output according to the pixel output signal. AM ) to perform write / hold operations.

[0121] Through the above-described readout operation, the pixel output signal is written into the memory cell of the analog memory array 301 and is held.

[0122] When the image capture frame period ends and the signal held in each memory cell is read out, the memory readout circuit 302 is driven to sequentially scan the memory cells to read out the voltage signal held in each memory cell. Specifically, first, in order to select the row where the memory cell to be read out is located, a row selection pulse is applied to the corresponding row selection switch. Next, the signal wiring is reset to a specified voltage, and then the signal wiring is set to a floating state. Next, a memory selection pulse is applied to the corresponding memory selection switch 108 to connect the capacitor (C AM ) 309 is electrically connected to the corresponding signal wiring. At this time, the capacitance of the corresponding signal wiring and the corresponding capacitance (C AM ) 309, and generates a signal voltage corresponding to the voltage held in the storage capacitor CAM in the signal wiring. In the memory read circuit 302, the signal voltage is amplified and the signal is read out to the outside of the analog memory array 301.

[0123] Figure 4 1 is a timing chart showing an example of the timing of driving the pixels of the photosensor according to the present invention and the time transition of the floating diffusion capacitor voltage (VFD).

[0124] The pulse waveform shown in the frame period (φFrame) is a pulse indicating the frame period, and the number corresponds to the frame number.

[0125] The pulse waveform shown by the reset pulse (φR) indicates turning on (ON) and turning off (OFF) the reset pulse (φR) transmitted to the reset transistor (R) 104 .

[0126] The pulse waveforms shown by the first voltage signal readout pulse (φSig1) and the second voltage signal readout pulse (φSig2) respectively indicate the timings related to the signal readout of the first voltage signal (1) and the second voltage signal (2).

[0127] The waveform represented by the floating diffusion capacitor voltage (VFD) indicates the temporal change in the potential energy of the floating diffusion capacitor portion.

[0128] In the case of bypassing the intra-pixel correlated double sampling circuit 101b, the falling times (t2, t3) of the first voltage signal readout pulse (φSig1) and the second voltage signal readout pulse (φSig2) respectively represent the pixel signal holding capacitors (C AM ) starts to maintain the timing of the first voltage signal (A1) and the second voltage signal (A2).

[0129] When the intra-pixel correlated double sampling circuit 101b is used, the falling time (t2) of the first voltage signal readout pulse (φSig1) indicates that the intra-pixel correlated double sampling holding capacitor (CSH )111 is reset to the timing of the reset voltage (VR_CDS) of the correlated double sampling circuit in the pixel.

[0130] The falling time (t3) of the second voltage signal readout pulse (φSig2) indicates that the voltage signal (B) starts to be held until the pixel signal holding capacitor (C AM ), the voltage signal (B) being a voltage signal based on the voltage signal (A) obtained by eliminating the reset noise voltage signal (VN) by subtracting the first voltage signal (1) from the second voltage signal (2).

[0131] In addition, light is irradiated during a frame period (φFrame).

[0132] like Figure 4 As shown, in either the case of bypassing the intra-pixel correlated double sampling circuit 101b or the case of using the intra-pixel correlated double sampling circuit 101b, at the beginning of the frame period (φFrame), the reset pulse (φR) rises first, and the capacitance (C FD ) is reset to a predetermined reset voltage (VR_FD). Time t1 indicates the moment when the reset pulse (φR) falls, the reset action is completed, and the reset noise voltage (VN) is taken in the floating diffusion capacitor voltage (VFD). After the reset action is completed, the photocharge corresponding to the amount of irradiated light is continuously accumulated in the floating diffusion capacitor capacitance (C FD ), the floating diffusion capacitor voltage (VFD) changes with time. Time t2 indicates that after a predetermined period (t2-t1) from time t1, the first voltage signal read pulse (φSig1) drops, and the reset noise voltage (VN) and the capacitance (C FD ) is read out.

[0133] In addition, time t3 indicates the time when φSig2 decreases after a predetermined accumulation period (t3-t2) from time t2, and a second voltage signal (A2) based on a signal voltage (Vsig2) generated by a reset noise voltage (VN) and photocharge accumulated in a floating diffusion capacitor during a predetermined period (t3-t1) is read. Here, in order to increase the frame rate, it is desirable to set the accumulation time (t3-t2) to be less than 1 μ second.

[0134] By subtracting the first voltage signal (A1) from the second voltage signal (A2) thus read out in the subsequent circuit, the reset noise voltage (VN) obtained in the floating diffusion capacitor (CFD) when the reset operation is completed is eliminated, and the capacitance (C) accumulated in the floating diffusion capacitor (CFD) during the predetermined accumulation period (t3-t2) can be obtained with high accuracy. FD ) generates a voltage (Vsig2-Vsig1) from the photocharges in the .

[0135] Next, use Figure 1 to Figure 4 The driving of the optical sensor of the present invention will be described.

[0136] (1) Case where the intra-pixel correlated double sampling circuit 101b is bypassed

[0137] First, a case will be described where the intra-pixel correlated double sampling bypass switch (CDSb) 109 is turned on by applying a signal (φCDSb) through the terminal 126 and the intra-pixel correlated double sampling selection switch (CDS) 108 is turned off. In addition, light is irradiated during a frame period.

[0138] A reset pulse (φR) for resetting the pixel is applied to the terminal 123 of the reset transistor (R) 104 , and the light receiving element (PD) 102 and the floating diffusion capacitor (CFD) 103 constituting the pixel in the photosensor pixel circuit 101 a are reset.

[0139] When the reset transistor (R) 104 is turned off and the reset is completed ( t1 ), a reset noise voltage signal (VN) is induced in the floating diffusion capacitor (CFD) 103 .

[0140] Next, after a predetermined period ( t2 − t1 ) has elapsed from t1 , the first voltage signal ( A1 ) is read out from the photosensor pixel circuit 101 a as follows.

[0141] The first voltage signal (A1) read out to the pixel output signal line (PIXEL_OUT) 117 after reset is completed is a voltage signal based on a voltage signal (A1-A) composed of the reset noise voltage signal (VN) and the first photocharge voltage signal (VsigA1), and the first photocharge voltage signal (VsigA1) is formed by photocharges collected by the photosensitive element (PD) 102 and transmitted to the floating diffusion capacitor (CFD) 103 during a specified period (t2-t1) from the completion of reset to the reading of the first voltage signal (A1).

[0142] First, when the first pixel selection pulse (φX1) is applied to the terminal 124 of the first selection transistor (X1) 106, the first source follower transistor (SF1) 105 becomes effective, and the first voltage signal (A1) corresponding to the voltage signal (A1-A) is output to the pixel output signal line (PIXEL_OUT) 117. At the same time, one of the four memory column selection switches 305 (WS1 to WS4) is turned on to select the corresponding memory column, and a pulse signal of a predetermined combination is applied to the pulse signal line (311 to 320) for selecting the signal holding memory unit, so that the pixel output signal line (PIXEL_OUT) 117 and the pixel signal holding capacitor (C AM )307 electrical coupling.

[0143] Specifically, for example, a combination of pulses is transmitted to the pulse signal lines (311 to 320) for selecting the signal holding memory, and only the pulse signal lines 310-1 and 311-1 are set to a high level, while the other pulse signal lines are set to a low level.

[0144] In this condition, a corresponding one of the four memory column selection switches 305 (WS1 to WS4) and a corresponding one of the four pixel signal holding memory selection selection switches 306 (SW1 to SW4) are turned on to select the memory cell 307a in the pixel signal holding memory array 303 via the signal line 313-1 for pixel signal transmission.

[0145] As a result, the first voltage signal (A1) corresponding to the voltage signal (A1-A) is transmitted to the pixel signal holding capacitor (C AM )307.

[0146] Next, by changing the pulse state transmitted to the pulse signal line 311-1 for selecting the signal holding memory, the pulse signal line 311-1 for selecting the signal holding memory is set to a low level, so that the selection switch (SW1) 306 for selecting the corresponding pixel signal holding memory is turned off, thereby the first voltage signal (A1) is held in the pixel signal holding capacitor (C1) before being read out by driving the memory readout circuit 302. AM )307.

[0147] Next, an accumulation period (t3-t2) is set.

[0148] The photocharges generated during the accumulation period (t3-t2) pass through Figure 2A to Figure 2C The potential energy gradient of the light receiving element (PD) 102 shown in the potential energy interval 201 is transferred to the floating diffusion capacitor (CFD) 103 and accumulated in the capacitance (C FD ).

[0149] During the accumulation period (t3-t2), by setting the first selection transistor (X1) 106 to the off state, the power consumed by the first source follower transistor (SF1) 105 can be suppressed. However, when the accumulation period (t3-t2) is as short as a few nsec or less, the proportion of the time during which the first source follower (SF1) 105 is driven during the accumulation period (t3-t2) becomes larger, so the effect of low power consumption obtained by setting the first selection transistor (X1) 106 to the off state becomes relatively smaller. Therefore, in the above case, saving the time required to switch the state of the first selection transistor (X1) 106 to on / off has the effect of obtaining a higher camera speed, so the first selection transistor (X1) 106 can be kept in the on state in advance during the accumulation period (t3-t2).

[0150] Next, after the accumulation period (t3-t2) is completed, the second voltage signal (A2) is read out.

[0151] The second voltage signal (A2) is a voltage signal based on a voltage signal (A2-A) composed of a reset noise voltage signal (VN) and a second photocharge voltage signal (VsigA2), and the second photocharge voltage signal (VsigA2) is formed by photocharges collected by the photosensitive element (PD) 102 and transmitted to the floating diffusion capacitor (CFD) 103 from the completion of reset until the second voltage signal (A2) is read out.

[0152] First, when the first selection transistor (X1) 106 is in the off state, the pixel selection first pulse (φX1) is applied to the terminal 124, so that the first source follower transistor (SF1) 105 becomes effective, and the second voltage signal (A2) corresponding to the voltage signal (A2-A) is output to the pixel output signal line (PIXEL_OUT) 117. At the same time, one of the four memory column selection switches 305 (WS1 to WS4) is turned on to select the corresponding memory column, and a pulse signal of a predetermined combination is applied to the pulse signal line (311 to 320) for signal holding memory selection, and the pixel output signal line (PIXEL_OUT) 117 is connected to the pixel signal holding capacitor (C) of a memory unit, for example, the memory unit 309a. AM )309 electrical coupling.

[0153] Specifically, for example, a combination of pulses is transmitted to the pulse signal lines 310 to 320 for selecting the signal holding memory so that only the pulse signal line 310 - 1 and the pulse signal line 312 - 1 are set to high level and the other pulse signal lines are set to low level.

[0154] Thus, one of the selection switches 306 (SW1 to SW4) for selecting the pixel signal holding memory, for example, the selection switch 306 (SW1) and the memory column selection switch (WS1) 305 are turned on, and the memory cell 309a is selected via the signal line 313-1 for pixel signal transmission.

[0155] As a result, the second voltage signal (A2) corresponding to the voltage signal (A2-A) is held in the pixel signal holding capacitor (C AM )309.

[0156] Next, the pulse state transmitted to the pulse signal line 312-1 for selecting the signal holding memory is changed to set the pulse signal line 312-1 for selecting the signal holding memory to a low level, so that the selection switch 308 for selecting the pixel signal holding memory is turned off, and the pixel signal holding capacitor (C AM )309 write signal, the second voltage signal (A2) is held in the pixel signal holding capacitor (C) during the period before the memory read circuit 302 is driven and read out. AM )309.

[0157] By subtracting the first voltage signal (A1) written to the memory cell 307a from the second voltage signal (A2) written to the memory cell 309a, a voltage signal (VsigA2-VsigA1) after eliminating the reset noise voltage signal (VN) can be obtained.

[0158] In this embodiment, the voltage signal (VsigA2-VsigA1) which is the difference between the signals is obtained by subtracting the first voltage signal (A1) and the second voltage signal (A2) outside the chip after reading them out of the chip by a method described later.

[0159] The above is a result of reading out the capacitance (C FD ) formed in the capacitor (C FD), but it is also possible to read the pixel signal three or more times in the same frame period (φFrame) as described later while bypassing the intra-pixel correlated double sampling circuit 101b. In the case of reading more than three times, a pulse signal of a predetermined combination is applied to the pulse signal line 310 for selecting the signal holding memory in the same manner as described above to select the corresponding memory unit to write the signal output and hold it when each signal is read.

[0160] After one frame period is completed, a reset pulse (φR) for resetting the pixel is input to the terminal 123 of the reset transistor (R) 104, and the next frame period starts.

[0161] The above-described series of operations are repeated, imaging is performed during a plurality of frame periods, and signal writing is performed to all memory cells of the analog memory array 301 .

[0162] After the signal is written to all the memory cells, the selected memory cell can be returned to the head address and the overwriting operation can be repeated until a trigger signal for stopping imaging is input from the camera.

[0163] After the imaging operation is completed, the signal written in the memory cell is read out by the method described later.

[0164] (2) When using the intra-pixel correlated double sampling circuit 101b

[0165] Next, a description will be given of a case where the intra-pixel correlated double sampling selection switch (CDS) 108 is in the on state and the intra-pixel correlated double sampling bypass switch (CDSb) 109 is in the off state.

[0166] First, a reset pulse (φR) for resetting the pixel is applied to the terminal 123 of the reset transistor (R) 104, and the light receiving element (PD) 102 and the floating diffusion capacitor (CFD) 103 constituting the pixel in the light sensor pixel circuit 101a are reset. When the reset transistor (R) 104 is turned off and the reset is completed (t1), a reset noise voltage signal (VN) is generated in the floating diffusion capacitor (CFD) 103.

[0167] Next, after a predetermined period (t2-t1) has passed from t1, the first voltage signal (B1) is read from the photosensor pixel circuit 101a to the intra-pixel correlated double sampling circuit 101b as follows.

[0168] After the reset is completed, the first voltage signal (B1) read out from the photosensor pixel circuit 101a to the intra-pixel correlated double sampling circuit 101b is a voltage signal based on the voltage signal (B1-A), which is composed of a reset noise voltage signal (VN) taken into the floating diffusion capacitor (CFD) 103 after the reset is completed and a first photocharge voltage signal (VsigB1) formed by photocharges collected by the light receiving element (PD) 102 and transmitted to the floating diffusion capacitor (CFD) 103 during a specified period (t2-t1) after the reset is completed until the first voltage signal (B1) is read out.

[0169] First, when the first pulse (φX1) for pixel selection is applied to the terminal 124 of the first selection transistor 106, the first source follower transistor (SF1) 105 becomes active, and the correlated double sampling coupling capacitor (C C ) 110 on the side of the correlated double sampling bypass switch (CDS) 108 within the pixel generates a first voltage signal (B1) based on the voltage signal (B1-A).

[0170] At the same time, an intra-pixel correlated double sampling reset pulse (φNS) is applied to the terminal 128 to turn on / off the intra-pixel correlated double sampling reset switch (NS) 112, thereby setting the intra-pixel correlated double sampling coupling capacitor (C C ) 110, that is, the correlated double sampling and holding capacitor (C SH )111 is reset to the reset voltage of the correlated double sampling circuit in the pixel (VR_CDS).

[0171] Next, an accumulation period (t3-t2) is set.

[0172] The photocharge generated during the storage period (t3-t2) is transferred to the floating diffusion capacitor (CFD) 103 by the potential gradient 201 of the light receiving element (PD) 102 and is stored in the capacitance (C FD ).

[0173] During the accumulation period (t3-t2), the first selection transistor (X1) 106 is turned off, thereby making it possible to suppress the power consumed by the first source follower transistor (SF1) 105.

[0174] On the other hand, when the accumulation period (t3-t2) is as short as several nsec, the first selection transistor (X1) 106 may be turned on in advance during the accumulation period (t3-t2) for the reasons described above.

[0175] After the accumulation period (t3-t2) is completed, the second voltage signal (B2) is read from the photosensor pixel circuit 101a to the intra-pixel correlated double sampling circuit 101b as follows.

[0176] The second voltage signal (B2) is formed based on a voltage signal (B2-A) composed of a reset noise voltage signal (VN) and a second photocharge voltage signal (VsigB2), and the second photocharge voltage signal (VsigB2) is formed by photocharges collected by the photosensitive element (PD) 102 and transmitted to the floating diffusion capacitor (CFD) 103 from the completion of reset until the second voltage signal (B2) is read out.

[0177] First, when the first selection transistor (X1) 106 is in the off state, the first pixel selection pulse (φX1) is applied to the terminal 124 and the first source follower transistor (SF1) 105 becomes active, and the correlated double sampling coupling capacitor (C C ) 110 generates a second voltage signal (B2) corresponding to the second photo charge voltage signal (VsigB2) in the electrode located on the intra-pixel correlated double sampling bypass switch (CDS) 108 side.

[0178] At this time, the double sampling coupling capacitor (C C )110 is a capacitively coupled pixel correlated double sampling and holding capacitor (C SH The voltage of )111 is based on the reset voltage (VR_CDS) of the correlated double sampling circuit in the pixel and changes from the first voltage signal (B1) to the second voltage signal (B2) by a voltage change (VsigB2-VsigB1) and C C / (C C +C SH )

[0179] As described above, by subtracting the first voltage signal (B1) from the second voltage signal (B2), a voltage signal (BA) is obtained in which the reset noise voltage signal (VN) is eliminated.

[0180] Next, a pixel selection second pulse (φX2) is applied to terminal 127 to turn on the second selection transistor (X2) 114, and a pixel selection 2A pulse (φX2`) is applied to terminal 127a to turn on the second selection transistor (X2`) 115, thereby outputting a voltage signal (BB) corresponding to the voltage signal (BA) to the pixel output signal line 117.

[0181] At the same time, one of the four memory column selection switches (WS1 to WS4) in the memory column selection switch array 301a is turned on to select the corresponding memory column, and a pulse signal of a predetermined combination is applied to the pulse signal line (311 to 320) for selecting the signal holding memory to connect the pixel output signal line 117 to the pixel signal holding capacitor (C ) of one memory unit, for example, the memory unit 307a. AM )307 electrical coupling.

[0182] As a specific example, by applying a pulse signal of a combination of pulses to the pulse signal lines 310 to 320 for selecting the signal holding memory, only the pulse signal line 310-1 and the pulse signal line 311-1 are set to a high level, and the other pulse signal lines are set to a low level, thereby turning on the memory column row selection switch (WS1) 305 and the selection switch (SW1) 306 for selecting the pixel signal holding memory, and selecting the memory cell 307a in the pixel signal holding memory array 303 via the signal line 313-1 for pixel signal transmission, and the pixel signal holding capacitor (C AM )307 senses the voltage signal (BB).

[0183] Next, the pulse state transmitted to the pulse signal line 311-1 for selecting the signal holding memory is changed to set the pulse signal line 311-1 for selecting the signal holding memory to a low level, so that the selection switch (SW1) 306 for selecting the pixel signal holding memory is turned off, thereby the voltage signal (BB) is held in the pixel signal holding capacitor (C AM ) 307. The voltage signal (BB) is held in the pixel signal holding capacitor (C) before being read out by driving the memory readout circuit 302. AM )307.

[0184] When the corresponding frame period is completed as described above, after the completion, a reset pulse (φR) for resetting the pixel is input to the terminal 123 of the reset transistor (R) 104, and the next frame period starts.

[0185] The above series of operations are repeated to perform imaging in a plurality of frame periods (φFrame). Signals are written to all memory cells in the analog memory array 301 .

[0186] Furthermore, after the signal is written to all the memory cells, the selected memory cell may be returned to the head address and the overwriting operation may be repeated until a trigger signal for stopping imaging is input from the camera.

[0187] After the imaging operation is completed, the signal written in each memory cell is read out by the method described later.

[0188] (3) A case where the intra-pixel correlated double sampling circuit 101b is bypassed and the pixel signal is read four times during one frame period

[0189] Figure 5 The timing diagram for reading pixel signals four times in the same frame period (φFrame) is shown. Here, t1 indicates the time when reset is completed, t2 indicates the time when the first voltage signal is read from the light sensor pixel circuit 101a after a predetermined period (t2-t1) has passed since t1, t3, t4, and t5 indicate the times when the second voltage signal, the third voltage signal, and the fourth voltage signal are read from the light sensor pixel circuit 101a, respectively, and the accumulation periods T1, T2, and T3 indicate the accumulation periods (t3-t2), (t4-t3), and (t5-t4), respectively.

[0190] A case where the intra-pixel correlated double sampling bypass switch (CDSb) 109 is turned on by applying a signal (φCDSb) through the terminal 126 and the intra-pixel correlated double sampling selection switch (CDS) 108 is turned off will be described. Light is irradiated during a frame period.

[0191] A reset pulse (φR) for resetting the pixel is applied to the terminal 123 of the reset transistor (R) 104 , and the light receiving element (PD) 102 and the floating diffusion capacitor (CFD) 103 constituting the pixel in the photosensor pixel circuit 101 a are reset.

[0192] When the reset transistor (R) 104 is turned off and the reset is completed ( t1 ), a reset noise voltage signal (VN) is induced in the floating diffusion capacitor (CFD) 103 .

[0193] Next, after a predetermined period ( t2 − t1 ) has elapsed from t1 , the first voltage signal ( C1 ) is read out from the photosensor pixel circuit 101 a as follows.

[0194] The first voltage signal (C1) read out to the pixel output signal line (PIXEL_OUT) 117 after reset is completed is a voltage signal based on a voltage signal (C1-A) composed of the reset noise voltage signal (VN) and the first photocharge voltage signal (VsigC1), and the first photocharge voltage signal (VsigC1) is formed by photocharges collected by the photosensitive element (PD) 102 and transmitted to the floating diffusion capacitor (CFD) 103 during a specified period (t2-t1) after reset is completed until the first voltage signal (C1) is read out.

[0195] First, when the first pixel selection pulse (φX1) is applied to the terminal 124 of the first selection transistor (X1) 106, the first source follower transistor (SF1) 105 becomes effective, and the first voltage signal (C1) corresponding to the voltage signal (C1-A) is output to the pixel output signal line (PIXEL_OUT) 117.

[0196] At the same time, one of the four memory column selection switches 305 (WS1 to WS4) is turned on to select the corresponding memory column, and a pulse signal of a predetermined combination is applied to the pulse signal line (311 to 320) for selecting the signal holding memory unit, so that the pixel output signal line (PIXEL_OUT) 117 is connected to the pixel signal holding capacitor (C AM ) 307 is electrically coupled to transmit the first voltage signal (C1) corresponding to the voltage signal (C1-A) to the pixel signal holding capacitor (C AM )307 and is maintained until it is read out by driving the memory read circuit 302.

[0197] Next, an accumulation period 1 (t3-t2) is set.

[0198] The photocharges generated during the storage period 1 (t3-t2) are Figure 2A to Figure 2C The potential energy gradient of the light receiving element (PD) 102 shown in the potential energy interval 201 is transferred to the floating diffusion capacitor (CFD) 103 and accumulated in the capacitance (C FD ).

[0199] Next, after the accumulation period 1 (t3-t2) is completed, the second voltage signal (C2) is read out.

[0200] The second voltage signal (C2) is a voltage signal based on a voltage signal (C2-A) composed of a reset noise voltage signal (VN) and a second photocharge voltage signal (VsigC2), and the second photocharge voltage signal (VsigC2) is formed by photocharges collected by the photosensitive element (PD) 102 and transmitted to the floating diffusion capacitor (CFD) 103 from the completion of reset until the second voltage signal (C2) is read out.

[0201] First, when the first selection transistor (X1) 106 is in the off state, the pixel selection first pulse (φX1) is applied to the terminal 124, so that the first source follower transistor (SF1) 105 becomes effective, and the second voltage signal (C2) corresponding to the voltage signal (C2-A) is output to the pixel output signal line (PIXEL_OUT) 117.

[0202] At the same time, one of the four memory column selection switches 305 (WS1 to WS4) is turned on to select the corresponding memory column, and a pulse signal of a predetermined combination is applied to the pulse signal lines (311 to 320) for selecting the signal holding memory, so that the pixel output signal line (PIXEL_OUT) 117 is connected to the pixel signal holding capacitor (C AM )309 is electrically coupled to transmit the first voltage signal (C2) corresponding to the voltage signal (C2-A) to the pixel signal holding capacitor (C AM )307 and is maintained until it is read out by driving the memory read circuit 302.

[0203] Next, through the same process as the reading of the second voltage signal (C2), the third voltage signal (C3) is read after the accumulation period 2 (t4-t3) ends, and the fourth voltage signal (C4) is read after the accumulation period 3 (t5-t4) ends.

[0204] The capacitance (C ) accumulated in the floating diffusion capacitor (CFD) 103 during the accumulation period 1 of the reset noise voltage signal (VN) is obtained by subtracting the first voltage signal (C1) written to one memory cell from the second voltage signal (C2) written to another memory cell. FD Similarly, the capacitance (C ) accumulated in the floating diffusion capacitor (CFD) 103 during the accumulation period 2 is obtained by subtracting the second voltage signal (C2) from the third voltage signal (C3). FD ) is obtained based on the capacitance (C ) accumulated in the floating diffusion capacitor (CFD) 103 during the accumulation period 3 by subtracting the third voltage signal (C3) from the fourth voltage signal (C4). FD ) in the photocharge signal.

[0205] In addition, the method of processing the second to fourth voltage signals is not limited to the above method, and the second voltage signal (C2) may be subtracted from the fourth voltage signal (C4), and the first voltage signal (C1) may be subtracted from the third voltage signal (C3), so as to substantially obtain the capacitance (C1) accumulated in the floating diffusion capacitor (CFD) 103 during the accumulation period 2-1 (t5-t3) and the accumulation period 2-2 (t4-t2). FD ) in the photocharge. In addition, it can also be used to reduce the readout of random noise superimposed during signal readout by adding and averaging the second to fourth voltage signals and then subtracting the first voltage signal (C1). It is also possible to synchronize the timing of t1 to t5 with the modulated light irradiation to be applied to time-of-flight distance imaging or fluorescence lifetime imaging.

[0206] In this embodiment, the capacitance (C) accumulated in the floating diffusion capacitor (CFD) 103 can be obtained by dividing the one frame period into shorter accumulation periods 1, 2, and 3. FD ) in the analog memory array 301, thereby obtaining a higher time resolution. In this embodiment, an example of reading out pixel signals four times during one frame is shown, but this is not limited to four times. The maximum number of pixel signals read out during one frame is a number corresponding to the number of memory cells included in the analog memory array 301, which is 80 times in this embodiment.

[0207] As is clear from the above description of the operation, when the intra-pixel correlated double sampling circuit 101b is bypassed, the pulse operation in the frame period (φFrame) is suppressed to a minimum, which is preferable for high-speed operation. Furthermore, when the pixel signal is read three or more times in one frame period, the frame period can be divided into shorter parts, which is preferable for obtaining a higher time resolution.

[0208] On the other hand, when the intra-pixel correlated double sampling circuit 101b is used, the frame period (φFrame) extends the time taken to drive the intra-pixel correlated double sampling circuit 101b, but the memory unit used in one frame can be set to one, so even when a memory array with a limited number of cells is used, the number of consecutive recorded frames can be maximized.

[0209] As described above, the present invention has an advantage over the conventional example in that the operation mode can be switched according to the priority of the frame rate and the number of recorded frames.

[0210] The choice between using the intra-pixel correlated double sampling circuit 101b and bypassing it without using it is arbitrary, but in order to maximize the advantages of the present invention, it is preferable to appropriately distinguish between the use / non-use of the circuit 101b based on the following criteria.

[0211] When it is desired to prioritize the number of consecutively recorded frames, the intra-pixel correlated double sampling circuit 101 b is preferably used because its effect can be maximized.

[0212] Specific examples of situations where it is desirable to prioritize the number of continuously recorded frames include shooting of combustion jets in automobile engines, spark discharges, and ink ejection in inkjet printers, which are phenomena that occur over a relatively long period of time.

[0213] Furthermore, when synchronization of the photographing timing is required for the first photographed object, by first adjusting the timing of the trigger using the mode (A) of the intra-pixel correlated double sampling circuit 101b, preparations for the work of obtaining synchronization can be performed, which is advantageous.

[0214] On the other hand, the mode (B) of bypassing the circuit 101b is preferable because it can maximize its effect when it is desired to prioritize the imaging speed.

[0215] Specifically, the use of this mode (B) is suitable for photographing high-speed phenomena such as material destruction phenomena, laser ablation, and discharge phenomena.

[0216] Furthermore, in the present invention, it is also possible to switch from a case of using the circuit 101 b (“mode (A)”) to a case of bypassing the circuit 101 b (“mode (B)”) for each frame.

[0217] For example, since the number of recorded frames can be increased by using the circuit 101b, the operation can be performed in mode (A) in advance, and from the point in time when a high-speed phenomenon to be photographed occurs, photographing can be performed at a higher speed in mode (B).

[0218] As a specific example, when photographing a phenomenon in which a resin bullet hits a target material at high speed and causes destruction, the photograph is taken in mode (A) before the resin bullet hits the target material, and then switched to mode (B) when the resin bullet is about to hit the target material, thereby photographing the destruction phenomenon caused by the impact at a higher speed.

[0219] In this case, in the analog memory array 301, a capacitor (C AM )A and a capacitor (CAM) B for holding the signal after noise elimination using circuit 101b, so the following technical preparations are required when imaging the held signal.

[0220] That is, the frame number for the upcoming mode switching is recorded in advance, and after reading out all the signals held in the analog memory array 301, the signal before the mode switching is imaged as a signal after noise is eliminated. The signal after the mode switching is imaged after noise elimination is performed by subtracting the first voltage signal (A1) for noise elimination recorded for each frame from the second voltage signal (A2).

[0221] exist Figure 3In the example described, the number of memory cells included in the analog memory array 301 is 80, but the number of memory cells is not limited thereto and can be determined according to the design. The number of memory cells is restricted by the area of ​​the analog memory array 301 and thus becomes a design factor that determines the aperture ratio and the pixel size. Therefore, the number of memory cells is determined by striking a balance between the aperture ratio and the pixel size according to the performance required of the optical sensor.

[0222] In the present invention, the number of memory cells is preferably 10 or more, but in order to increase the number of recording frames, it is desirably 40 or more, more desirably 128 or more, and in order to further increase the number of recording frames, it is desirably 256 or more.

[0223] In order to further reduce the surface area of ​​the photosensor chip, it is preferable to adopt a multilayer structure in which the analog memory circuit section 300 is provided in a lower layer of the photosensor pixel circuit section 100 .

[0224] Figure 6 is a block diagram of an image sensor according to the present invention.

[0225] Figure 6 The image sensor 600 of the illustrated example includes a light receiving signal generating and holding element array 602 in which a plurality of light receiving signal generating and holding elements 601 are two-dimensionally arranged, a memory selection circuit 603 , a pixel driving pulse buffer column circuit 604 , and a column selection circuit 605 .

[0226] The pixel driving pulse buffer column circuit 604 is provided with an output buffer 606 and a signal output terminal 607 on the downstream side of the signal transmission path.

[0227] The light reception signal generating and holding element 601 is composed of the photosensor pixel circuit portion 100 and the analog memory circuit portion 300 .

[0228] use Figure 3 and Figure 6 The drive for reading out a signal from the analog memory array 301 of the image sensor 600 of the present invention will be described.

[0229] First, when a trigger signal indicating that imaging is completed is input to the image sensor 600 , the imaging period of the image sensor 600 ends, and then the process shifts to a signal output period of the image sensor 600 .

[0230] During the signal output period of the image sensor 600, the analog memory arrays 301 corresponding to the pixels of each row are read out. That is, the memory selection circuit 603 is driven to select the memory readout circuit 302 of one pixel row, and the output signal line 302a of the memory readout circuit 302 is coupled to the vertical signal line 608.

[0231] Next, the row of the memory cell to be read is selected in the analog memory 301. For example, only 310-1 among 310-1 to 4 is set to high level and the memory row selection switch WS1 is selectively turned on to couple the pixel signal transmission signal line 313-1 to the memory read circuit 302.

[0232] Next, after resetting the pixel signal transmission signal line 313-1 to a predetermined voltage (5A), the pixel signal transmission signal line 313-1 is set to a floating state. Next, a memory cell is selected and the corresponding pixel signal holding capacitor (C AM ) is coupled to the corresponding pixel signal transmission signal line 313-1. At this time, the corresponding pixel signal holding capacitor (C AM ) is written into the voltage signal (5S-1) through the corresponding pixel signal holding capacitor (C AM ) and the capacitance parasitic on the corresponding pixel signal transmission signal line 313-1 are divided into capacitances and input to the memory readout circuit 302. In the memory readout circuit 302, a voltage signal (5S-2) based on the voltage signal (5S-1) is output to the vertical signal line 608. At this time, the voltage signal (5S-2) of the vertical signal line 608 is temporarily held by the column circuit 604. Next, the column selection circuit 605 is sequentially driven, and the voltage signal (5S-1) held in the column circuit 604 is sequentially output to the signal output terminal 607 via the output buffer 606.

[0233] Similarly, the signals of all the memory cells selected by the memory column selection switch (WS1) 305 are read out by repeatedly resetting the signal line 313-1 for transmitting pixel signals, performing capacitor division of the voltage signal by selecting the memory cell to be read out next, driving the memory read circuit 302, driving the column circuit 504, and outputting the chip.

[0234] Similarly, other columns in the analog memory 301 are sequentially selected, and signals of all memory cells in each column are read out, and signals of all memory cells in the selected analog memory 301 are read out of the chip.

[0235] Next, the memory selection circuit 603 is driven to select the memory cell of the pixel column to be read next, and the same operation is repeated. This signal reading operation is performed for the memory cells of all pixel columns.

[0236] Through the above-described operation, signals from the memory cells of all pixels are read out.

[0237] The present invention can be accurately understood through the above description, and its main advantages are summarized as follows.

[0238] (1) The transfer period and the setup time of the pixel driving pulse required to turn on / off the transfer gate required in the prior art are no longer required.

[0239] (2) The frame rate is limited only by the charge collection and transfer time in the photosensitive element, and the frame rate can be increased to 125Mfps.

[0240] (3) Since the signal is read from the memory connected to the pixel at the shortest distance, the circuit drive current required for pixel readout can be reduced. In addition, since the number of pixel drive pulses is small, the power consumption related to the pixel drive pulses can be reduced. Therefore, it is possible to provide a low-power optical sensor product on the market.

[0241] (4) Since there are fewer types of pixel driving pulses, the pixel driving pulse circuit can be arranged in a pixel or a pixel block without sacrificing area.

[0242] (5) Since the fully depleted light-receiving element with low capacitance density is coupled to the floating diffusion capacitor, the increase in capacitance of the floating diffusion capacitor, which is inversely proportional to the charge-to-voltage conversion gain, can be suppressed to a minimum, thereby obtaining a high charge-to-voltage conversion gain. Furthermore, since the reset noise of the floating diffusion capacitor can be eliminated, high-sensitivity signal reading with low signal reading noise can be performed.

[0243] (5) By reading out the signal N times after resetting the light receiving element and the floating diffusion capacitor, a higher frame rate can be obtained even before the floating diffusion capacitor is saturated.

[0244] (6) By performing signal readout in synchronization with the modulated light irradiation, it is possible to apply to light-flight time-type distance imaging or fluorescence lifetime imaging.

[0245] The above are some of the advantages of the present invention, and the present invention can be developed into various products based on these advantages. An example is described below.

[0246] Since it is possible to visualize high-speed phenomena,

[0247] Observation of material failure phenomena: analysis of the failure process and improvement of materials

[0248] Observation of microbubbles

[0249] Observation of discharge phenomenon

[0250] Observation of cancer cell treatment

[0251] Inkjet observation

[0252] Observation of MEMS drive

[0253] Observation of shock waves

[0254] Observation of fuel spray into the engine room

[0255] Laser beam processing

[0256] All of these require image information of continuous frames in a two-dimensional image, and the high-speed camera involved in the present invention that meets this requirement is useful.

[0257] Furthermore, the present invention is useful for a camera with high time resolution used in the field of distance imaging or biological imaging, which requires imaging the distance or biological response in a two-dimensional image.

[0258] The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, in order to disclose the scope of the present invention, the above-described claims are appended.

[0259] Description of Reference Numerals

[0260] 100: photosensor pixel circuit unit; 101a: photosensor pixel circuit; 101b: intra-pixel correlated double sampling circuit (In-pixel 10: a first source follower transistor (SF1); 106: a first selection transistor (X1); 107: a first current source transistor (CS1); 108: an intra-pixel correlated double sampling selection switch (CDS); 109: an intra-pixel correlated double sampling bypass switch (CDSb); 110: an intra-pixel correlated double sampling coupling capacitor (CC); 111: an intra-pixel correlated double sampling holding capacitor (CSH); 112: an intra-pixel correlated double sampling reset transistor (NS); 113: a second source follower transistor (SF2); 114: a second selection transistor (X2); 115: a second selection transistor (X2'); 116: a second current source transistor CS2; 117: a pixel output signal line (PIXEL_OUT); 118: an electrical terminal for applying a pixel reset voltage (VR_FD) ; 119a, 119b: electrical terminals for applying power supply voltage (AVDD); 120: electrical terminal for reset voltage (VR_CDS) of correlated double sampling circuit in pixel; 121: electrical terminal for applying first current source bias voltage (VB1); 122: electrical terminal for applying second current source bias voltage (VB2); 123: electrical terminal for applying pixel reset pulse (φR); 124: electrical terminal for applying first pulse (φX1) for pixel selection; 125: electrical terminal for inputting select pulse (φCDS) of correlated double sampling circuit in pixel; 126: electrical terminal for inputting bypass pulse (φCDSb) of correlated double sampling circuit in pixel; 127: electrical terminal for inputting second pulse (φX2) for pixel selection; 128: reset pulse (φNS) of correlated double sampling in pixel; 201: potential energy partition of fully depleted light receiving element (PD) 102; 202: capacitance (C FD ) potential energy partition; 300: analog memory circuit unit; 301: analog memory array (Analog Memories: 4 H ×20 V ); 301a: memory cell row selection switch array; 302: memory readout circuit; 302a: output signal line; 303, 304: pixel signal holding memory array; 305: memory cell row selection switch (WS1~WS4) (1~4); 306: pixel signal holding memory selection switch (SW1~SW4); 307: pixel signal holding capacitor (C AM); 307a: memory unit; 308: switch for selecting pixel signal holding memory; 309: capacitor for holding pixel signal; 310: pulse signal line (1 to 4) for selecting row of memory unit for signal holding; 311, 312 to 320: pulse signal line (1 to 4) for selecting memory unit for signal holding; 313: signal line (1 to 4) for transmitting pixel signal; 600: image sensor; 601: light receiving signal generating and holding element; 602: light receiving signal generating and holding element array; 603: memory selection circuit; 604: pixel driving pulse buffer column circuit; 605: column selection circuit; 606: output buffer; 607: signal output terminal; 608: vertical signal line.

Claims

1. A signal reading method of an optical sensor, characterized in that: By receiving light from the light receiving element, the semiconductor junction of the light receiving element is completely depleted, and the potential energy curve of the electrons of the light receiving element is negatively tilted toward the floating diffusion capacitor, and the potential energy curve is connected to the uppermost portion of the electron potential well of the floating diffusion capacitor while maintaining the negative tilt. At least two accumulation steps are sequentially performed in the same frame period set within the period of receiving light. The accumulation step is a step of transferring the electrons generated inside the light receiving element in response to the received light and accumulating them in the potential well according to the potential energy curve. The capacitance (C PD ) and the capacitance of the floating diffusion capacitor (C FD ) has the following relationship: 0.0008≤(C PD ) / (C FD )≤0.8 (1) 4.0×10 -18 F≤(C PD )≤4.0×10 -16 F (2) 5.0×10 -16 F≤(C FD )≤5.0×10 -15 F (3)。 2. The signal reading method of the optical sensor according to claim 1, characterized in that: The accumulation period in the accumulation step is 1 μs or less.

3. A light sensor, characterized in that: The invention comprises a light receiving element, a floating diffusion capacitor and a pixel signal output line, wherein the floating diffusion capacitor is directly electrically connected to the light receiving element and accumulates the charge generated by the light input to the light receiving element, and the signal readout path is connected to the pixel signal output line. The capacitance (C PD ) and the capacitance of the floating diffusion capacitor (C FD ) has the following relationship: 0.0008≤(C PD ) / (C FD )≤0.8 (1) 4.0×10 -18 F≤(C PD )≤4.0×10 -16 F (2) 5.0×10 -16 F≤(C FD )≤5.0×10 -15 F (3) The semiconductor junction of the light-receiving element is completely depleted, and the potential energy curve of the electrons of the light-receiving element tilts negatively toward the floating diffusion capacitor, and the potential energy curve is connected to the uppermost portion of the electron potential well of the floating diffusion capacitor while maintaining the negative tilt.

4. A regional light sensor, characterized in that: have: (1) a light sensor pixel circuit unit, comprising a light sensor pixel circuit and an intra-pixel correlated double sampling circuit, the light sensor pixel circuit comprising a light receiving element and a floating diffusion capacitor, the floating diffusion capacitor being directly electrically connected to the light receiving element and accumulating charge generated by light input to the light receiving element, the semiconductor junction of the light receiving element being completely depleted, the light receiving element having an electron potential curve, the potential curve being negatively inclined toward the floating diffusion capacitor, the potential curve being connected to the uppermost portion of the electron potential well of the floating diffusion capacitor while maintaining the negative inclination, the light sensor pixel circuit having two output systems which are used alternately on a time axis, the intra-pixel correlated double sampling circuit outputting a signal (ab1) by performing noise elimination based on a first output (a1) and a second output (b1), the first output (a1) and the second output (b1) being outputs output from one output system based on the amount of photocharge generated in the light receiving element by light irradiation; and (2) An analog memory circuit unit, comprising an analog memory array, a memory cell row selection switch array, and a memory read circuit, wherein the analog memory array is obtained by arranging a plurality of memory cells in an array, the memory cells are used to hold the signal (ab1) and a signal outputted from another output system, either a first output (a2) or a second output (b2), the memory cell row selection switch array is used to select any memory cell configuration row, and the memory read circuit is used to read the signal held in any memory cell.

5. The area optical sensor according to claim 4, characterized in that: The capacitance (C PD ) and the capacitance of the floating diffusion capacitor (C FD ) has the following relationship: 0.0008≤(C PD ) / (C FD )≤0.8 (1) 4.0×10 -18 F≤(C PD )≤4.0×10 -16 F (2) 5.0×10 -16 F≤(C FD )≤5.0×10 -15 F (3)。 6. The area optical sensor according to claim 4, characterized in that: The photosensor pixel circuit portion and the analog memory circuit portion are arranged adjacent to each other on the same plane.

7. The area optical sensor according to claim 4, characterized in that: The photosensor pixel circuit portion and the analog memory circuit portion are stacked adjacent to each other.

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