Light Detection Devices

Abstract

The present invention relates to a light detection device. The light detection device may include: a plurality of pixels arranged in rows and columns, a first pixel of the plurality of pixels including: a first avalanche photodiode; and an inverter coupled to an anode or a cathode of the first avalanche photodiode, wherein the first pixel is configured to output a first logic signal; a pixel control circuit configured to output a pixel control signal; and a first logic circuit configured to receive the first logic signal and the pixel control signal.

Description

[0001] This application is a divisional application of the patent application with application number 201880006334.6, whose application date is September 10, 2018 and invention name is “Time measurement device and time measurement unit”. Technical Field

[0002] The present disclosure relates to a time measurement device and a time measurement unit for measuring the time from the timing of light emission to the timing of light detection. Background Art

[0003] When measuring the distance to a measurement object, a time of flight (TOF) method is often used. The TOF method emits light and also detects reflected light reflected by the measurement object. Subsequently, the TOF method measures the distance to the measurement object by measuring the time difference between the light emission time and the detection time of the reflected light (for example, see Patent Document 1).

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2015-78953 Summary of the invention

[0007] Note that generally in semiconductor devices, it is desirable to facilitate circuit layout. Similarly, also in time measurement devices, it is desirable that layout can be easily achieved.

[0008] It is desirable to provide a time measurement device and a time measurement unit that can be easily laid out.

[0009] According to an embodiment of the present disclosure, a first time measurement device includes a plurality of pixels and a time measurement unit. The plurality of pixels are arranged side by side in a first direction, and each pixel includes a single-photon avalanche diode arranged on a first semiconductor substrate and generates a first logic signal depending on the detection moment in the single-photon avalanche diode. The time measurement unit is arranged on a second semiconductor substrate combined with the first semiconductor substrate, and measures the detection moment of each of the plurality of pixels. Each pixel among the plurality of pixels except a first pixel arranged at one end in the first direction generates an output signal based on an output signal of a pixel other than the pixel and based on the first logic signal generated in the pixel, and the time measurement unit measures the detection moment of each of the plurality of pixels based on the output signal of a second pixel arranged at the other end in the first direction among the plurality of pixels.

[0010] According to an embodiment of the present disclosure, a second time measurement device includes a plurality of pixels and a time measurement unit. The plurality of pixels are arranged side by side in a first direction, and each pixel includes a light receiving element and generates a first logic signal depending on the detection moment in the light receiving element. The time measurement unit measures the detection moment of each of the plurality of pixels. Each pixel among the plurality of pixels except a first pixel arranged at one end in the first direction generates an output signal based on an output signal of a pixel other than the pixel and based on the first logic signal generated in the pixel, and the time measurement unit measures the detection moment of each of the plurality of pixels based on the output signal of a second pixel arranged at the other end in the first direction among the plurality of pixels.

[0011] According to an embodiment of the present disclosure, a third time measurement device includes a first pixel, a second pixel, a third pixel, and a time measurement unit. Each of the first pixel, the second pixel, and the third pixel includes a single-photon avalanche diode arranged on a first semiconductor substrate and generates a first logic signal depending on the detection moment in the single-photon avalanche diode. The time measurement unit is arranged on a second semiconductor substrate combined with the first semiconductor substrate, and measures the detection moment of each of the first pixel, the second pixel, and the third pixel. The second pixel generates an output signal based on the output signal of the first pixel and based on the first logic signal generated in the second pixel, the third pixel generates an output signal based on the output signal of the second pixel and based on the first logic signal generated in the third pixel, and the time measurement unit measures the detection moment of each of the first pixel, the second pixel, and the third pixel based on the output signal of the third pixel.

[0012] According to an embodiment of the present disclosure, a first time measurement unit includes a light emitting unit, a reflector, a plurality of pixels, and a time measurement unit. The light emitting unit emits light. The reflector reflects reflected light corresponding to the light. A plurality of pixels are arranged side by side in a first direction, each pixel includes a single-photon avalanche diode arranged on a first semiconductor substrate and detecting reflected light reflected by the reflector, and each pixel generates a first logic signal depending on the detection moment in the single-photon avalanche diode. The time measurement unit is arranged on a second semiconductor substrate combined with the first semiconductor substrate, and measures the detection moment of each of the plurality of pixels. Each of the plurality of pixels except a first pixel arranged at one end in the first direction generates an output signal based on an output signal of a pixel other than the pixel and based on a first logic signal generated in the pixel, and the time measurement unit measures the detection moment of each of the plurality of pixels based on an output signal of a second pixel arranged at the other end in the first direction among the plurality of pixels.

[0013] According to an embodiment of the present disclosure, a second time measurement unit includes a light emitting unit, a reflector, a plurality of pixels, and a time measurement unit. The light emitting unit emits. The reflector reflects reflected light corresponding to the light. A plurality of pixels are arranged side by side in a first direction, each pixel includes a light receiving element for detecting reflected light reflected by the reflector, and each pixel generates a first logic signal depending on the detection moment in the light receiving element. The time measurement unit measures the detection moment of each of the plurality of pixels. Each pixel except a first pixel arranged at one end in the first direction among the plurality of pixels generates an output signal based on an output signal of a pixel except the pixel and based on the first logic signal generated in the pixel, and the time measurement unit measures the detection moment of each of the plurality of pixels based on the output signal of a second pixel arranged at the other end in the first direction among the plurality of pixels.

[0014] According to an embodiment of the present disclosure, a third time measurement unit includes a light emitting portion, a reflector, a first pixel, a second pixel, a third pixel, and a time measurement portion. The light emitting portion emits light. The reflector reflects reflected light corresponding to the light. Each of the first pixel, the second pixel, and the third pixel includes a single-photon avalanche diode arranged on a first semiconductor substrate and detecting reflected light reflected by the reflector, and generates a first logic signal depending on the detection moment in the single-photon avalanche diode. The time measurement portion is arranged on a second semiconductor substrate combined with the first semiconductor substrate, and measures the detection moment of each of the first pixel, the second pixel, and the third pixel. The second pixel generates an output signal based on the output signal of the first pixel and based on the first logic signal generated in the second pixel, the third pixel generates an output signal based on the output signal of the second pixel and based on the first logic signal generated in the third pixel, and the time measurement portion measures the detection moment of each of the first pixel, the second pixel, and the third pixel based on the output signal of the third pixel.

[0015] In the first time measurement device and the first time measurement unit according to the embodiment of the present disclosure, in each pixel, light is detected by a single-photon avalanche diode arranged on a first semiconductor substrate, and a first logic signal depending on the detection moment is generated. In each pixel among a plurality of pixels except a first pixel arranged at one end in a first direction, an output signal is generated based on an output signal of a pixel other than the pixel and based on the first logic signal generated in the pixel. In the time measurement unit, the detection moment of each of the plurality of pixels is measured based on the output signal of a second pixel arranged at the other end in the first direction among the plurality of pixels.

[0016] In the second time measurement device and the second time measurement unit according to the embodiment of the present disclosure, in each pixel, light is detected by a light receiving element, and a first logic signal depending on the detection moment is generated. In each pixel except a first pixel arranged at one end in the first direction among a plurality of pixels, an output signal is generated based on an output signal of a pixel other than the pixel and based on the first logic signal generated in the pixel. In the time measurement unit, the detection moment of each of the plurality of pixels is measured based on the output signal of a second pixel arranged at the other end in the first direction among the plurality of pixels.

[0017] In the third time measurement device and the third time measurement unit according to the embodiment of the present disclosure, in each pixel, light is detected by a single-photon avalanche diode arranged on a first semiconductor substrate, and a first logic signal depending on the detection moment is generated. In the second pixel, an output signal is generated based on the output signal of the first pixel and based on the first logic signal generated in the second pixel. In the third pixel, an output signal is generated based on the output signal of the second pixel and based on the first logic signal generated in the third pixel. In the time measurement unit, the detection moment of each of the first pixel, the second pixel and the third pixel is measured based on the output signal of the third pixel.

[0018] In the first time measurement device, the second time measurement device, the first time measurement unit, and the second time measurement unit according to the embodiments of the present disclosure, each pixel among a plurality of pixels except a first pixel arranged at one end in a first direction generates an output signal based on an output signal of a pixel other than the pixel and based on a first logic signal generated in the pixel, and the time measurement unit measures the detection moment of each of the plurality of pixels based on the output signal of a second pixel among the plurality of pixels arranged at the other end in the first direction, thereby allowing easy implementation of the layout.

[0019] In the third time measurement device and the third time measurement unit according to an embodiment of the present disclosure, the second pixel generates an output signal based on the output signal of the first pixel and based on the first logic signal generated in the second pixel, the third pixel generates an output signal based on the output signal of the second pixel and based on the first logic signal generated in the third pixel, and the time measurement part measures the detection moment of each of the first pixel, the second pixel and the third pixel based on the output signal of the third pixel, thereby allowing easy implementation of the layout.

[0020] It should be noted that the above-mentioned effects are not necessarily limitative, and any effects described in the present disclosure can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1is a block diagram of a configuration example of a time measurement unit according to an embodiment of the present disclosure.

[0022] Figure 2 is a block diagram of a configuration example of a time measurement device according to the first embodiment.

[0023] Figure 3 yes Figure 2 A circuit diagram of a configuration example of a pixel shown.

[0024] Figure 4 yes Figure 2 A circuit diagram showing a configuration example of a waveform shaping section and a time measurement unit.

[0025] Figure 5 yes Figure 1 A structural diagram of a structural example of a time measurement device shown.

[0026] Figure 6 is a timing waveform chart showing an example of the time measurement operation in the time measurement unit according to the first embodiment.

[0027] Figure 7 yes Figure 3 The waveform diagram of the operation example of the light receiving element shown.

[0028] Figure 8 is a timing waveform chart showing an operation example of the time measurement unit according to the first embodiment.

[0029] Fig. 9 is a timing waveform chart of an example of the calibration operation in the time measurement unit according to the first embodiment.

[0030] Fig.10 is a circuit diagram of a configuration example of a waveform shaping section and a time measurement unit according to a modification of the first embodiment.

[0031] Fig.11 is a circuit diagram showing a configuration example of a pixel according to another modification of the first embodiment.

[0032] Fig.12 is a block diagram of a configuration example of a time measurement device according to another modification of the first embodiment.

[0033] Fig.13 yes Fig.12 A circuit diagram of a configuration example of a pixel shown.

[0034] Fig.14 is a timing waveform chart showing an example of a test operation in a time measurement unit according to another modification of the first embodiment.

[0035] Fig.15is a block diagram of a configuration example of a time measurement device according to another modification of the first embodiment.

[0036] Fig.16 is a block diagram of a configuration example of a time measurement device according to another modification of the first embodiment.

[0037] Fig.17 is a block diagram of a configuration example of a time measurement device according to the second embodiment.

[0038] Fig.18 yes Fig.17 A circuit diagram of a configuration example of a pixel shown.

[0039] Fig.19 is a timing waveform chart showing an example of the time measurement operation in the time measurement unit according to the second embodiment.

[0040] Fig. 20 is a circuit diagram showing a configuration example of a pixel according to a modification example of the second embodiment.

[0041] Fig.21 is a block diagram of a configuration example of a distance measurement device according to an application example.

[0042] Fig. 22 is a block diagram depicting an example of a schematic configuration of a vehicle control system.

[0043] Fig.23 2 is a diagram to help explain an example of the installation positions of the vehicle exterior information detection portion and the imaging portion.

[0044] Fig.24 is a configuration diagram showing a configuration example of a time measurement device according to a modification.

[0045] Fig.25 is a cross-sectional view showing an example of the structure of a SPAD. DETAILED DESCRIPTION

[0046] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the description is given in the following order.

[0047] 1. First Embodiment

[0048] 2. Second Embodiment

[0049] 3. Application Examples

[0050] 4. Application examples of moving objects

[0051] [1. First embodiment]

[0052] [Construction example]

[0053] Figure 1The configuration example of a time measurement unit (time measurement unit 1) according to one embodiment is shown. The time measurement unit 1 emits light and also detects reflected light reflected by the measured object, and measures the time difference between the light emission time and the detection time of the reflected light. The time measurement unit 1 includes a light emitting unit 11, a scattering lens 12, a condenser lens 13, a time measurement device 20, and a controller 14.

[0054] The light emitting section 11 performs a light emitting operation of emitting light at a timing depending on a light emitting control signal C1 , and is configured using a pulse laser source, for example.

[0055] The scattering lens 12 scatters, within a predetermined angle range, the light emitted from the light emitting section 11. The light scattered by the scattering lens 12 is output from the time measurement unit 1 (output light L1).

[0056] The condenser 13 reflects the light (reflected light L2) reflected by the measured object 9 and entering the time measurement unit 1 toward the light receiving surface S of the time measurement device 20. It should be noted that the condenser 13 is not an essential component, but any configuration is allowed as long as the reflected light L2 can reach the receiving surface S of the time measurement device 20.

[0057] The time measurement device 20 detects light reflected by the condenser mirror 13 and measures a time difference between the timing when the light emitting section 11 emits light and the timing when a light receiving element 31 (described later) of the time measurement device 20 detects the light.

[0058] The controller 14 controls the operation of the light emitting section 11 and the time measuring device 20. Specifically, the controller 14 controls the light emitting operation of the light emitting section 11 by supplying a light emitting control signal C1 to the light emitting section 11. In addition, the controller 14 controls the operation of the time measuring device 20 by supplying various control signals (a calibration signal CAL, a selection control signal CTRL, a clock signal CK, and a count start signal ST described later) to the time measuring device 20.

[0059] Figure 2 2 shows an example of the configuration of the time measurement device 20. It should be noted that for ease of description, Figure 2 The controller 14 is also shown. The time measurement device 20 has a pixel array 21 , a selection signal generator 22 , a waveform shaping section 23 , and a time measurement unit 24 .

[0060] The pixel array 21 has a plurality of pixels 30 arranged in a matrix pattern. In the pixel array 21, for example, M (for example, 600) pixels 30 are arranged in Figure 2 In the lateral direction, N (e.g., 150) pixels 30 are arranged Figure 2In the longitudinal direction of the image sensor 30, the number M of pixels 30 arranged in the transverse direction is set to be greater than the number N of pixels 30 arranged in the longitudinal direction. For example, the number M of pixels 30 arranged in the transverse direction is preferably 200 or more. For example, the number N of pixels 30 arranged in the longitudinal direction is preferably 100 or more.

[0061] Figure 3 A configuration example of the pixel 30 is shown. Figure 3 Four (=2×2) adjacent pixels 30 are shown among the plurality of (M×N) pixels 30. The pixel 30 includes a light receiving element 31, a resistor 32, an inverter 33, an AND circuit 34, a flip-flop (F / F) 35, and an XOR circuit 36.

[0062] The light receiving element 31 is used to detect light, and includes, for example, a single photon avalanche diode (SPAD). The cathode of the light receiving element 31 is coupled to the other end of the resistor element 32 and the input terminal of the inverter 33, and its anode is grounded. Preferably, for example, the single photon avalanche diode is operated in Geiger mode. It should be noted that a single photon avalanche diode is used in this example; however, the photodetector is not limited thereto, and as an alternative, for example, an avalanche photodiode (APD) may be used, or a high-sensitivity photodiode (PD) may be used.

[0063] The bias voltage Vbias is supplied to one end of the resistance element 32 , and the other end of the resistance element 32 is coupled to the cathode of the light receiving element 31 and the input terminal of the inverter 33 .

[0064] An input terminal of the inverter 33 is coupled to the other end of the resistance element 32 and the cathode of the light receiving element 31 , and the other end thereof is coupled to a first input terminal of the AND circuit 34 .

[0065] The AND gate circuit 34 obtains the logical product (AND) of the signal input to the first input terminal and the signal input to the second input terminal, and outputs the obtained result from the output terminal. The first input terminal of the AND gate circuit 34 is coupled to the output terminal of the inverter 33; the selection signal SEL is provided to the second input terminal; and the output terminal is coupled to the clock input terminal of the flip-flop (F / F) 35.

[0066] The flip-flop (F / F) 35 is a D-type flip-flop, and samples the signal input to the data input terminal D based on the rising edge of the signal input to the clock input terminal. The flip-flop (F / F) 35 outputs the sampling result from the output terminal Q, and also outputs the inverted signal of the sampling result from the inverted output terminal QB. The clock input terminal of the flip-flop (F / F) 35 is coupled to the output terminal of the AND gate circuit 34; the data input terminal D is coupled to the inverted output terminal QB; the output terminal Q is coupled to the first input terminal of the XOR gate circuit 36; and the inverted output terminal QB is coupled to the data input terminal D. With this configuration, the flip-flop (F / F) 35 performs a toggle operation based on the rising edge of the signal input to the clock input terminal.

[0067] The XOR gate circuit 36 ​​obtains an exclusive OR (ExOR) of a signal input to the first input terminal and a signal input to the second input terminal, and outputs the obtained result from the output terminal. The first input terminal of the XOR gate circuit 36 ​​is coupled to the output terminal Q of the trigger (F / F) 35; the second input terminal is coupled to the input terminal IN of the pixel 30; and the output terminal is coupled to the output terminal OUT of the pixel 30.

[0068] like Figure 2 As shown in FIG. 1 , the calibration signal CAL supplied from the controller 14 is input to the input terminal IN of the leftmost pixel 30 among the M pixels 30 arranged side by side in a single row in the lateral direction. Figure 3 As shown, the input terminals IN of the pixels 30 other than the leftmost pixel 30 among the M pixels 30 are coupled to the output terminals OUT of the pixels 30 adjacent to the left thereof. Figure 2 As shown, the output terminal OUT of the rightmost pixel 30 among the M pixels 30 is coupled to the waveform shaping section 23. The rightmost pixel 30 outputs a signal S1. Specifically, the rightmost pixel 30 among the M pixels 30 in the first row outputs a signal S1(1), and the rightmost pixel 30 among the M pixels 30 in the second row outputs a signal S1(2). The same is true for the 3rd to Nth rows. Therefore, in the pixel array 21, Figure 2 The M pixels 30 arranged side by side in a single row in the lateral direction are coupled to each other in a so-called daisy chain manner.

[0069] In addition, a single selection signal SEL is supplied to the N pixels 30 arranged side by side in a single column in the longitudinal direction, and different selection signals SEL are supplied to the pixels 30 belonging to columns different from each other. In other words, a corresponding selection signal SEL is supplied to each of the M pixels 30 arranged side by side in a single row in the lateral direction. With this configuration, in the pixel array 21, a plurality of pixels 30 are selected in units of pixels of a single column using the selection signal SEL.

[0070] The selection signal generator 22 generates a plurality of selection signals SEL (in this example, M selection signals SEL(1) to SEL(M)) based on the selection control signal CTRL supplied from the controller 14. The selection signal generator 22 supplies the M selection signals SEL(1) to SEL(M) to the M columns of pixels 30 in the pixel array 21, respectively. This allows the selection signal generator 22 to sequentially select the plurality of pixels 30 on a per-column basis.

[0071] The waveform shaping section 23 shapes the waveforms of a plurality of signals S1 (in this example, N signals S1(1) to S1(N)) provided from the pixel array 21, thereby generating a plurality of signals S2 (in this example, N signals S2(1) to S2(N)). The waveform shaping section 23 has a plurality of waveform shaping circuits (in this example, N waveform shaping circuits 40(1) to 40(N)). The waveform shaping circuit 40(1) generates the signal S2(1) by shaping the waveform of the signal S1(1), and the waveform shaping circuit 40(2) generates the signal S2(2) by shaping the waveform of the signal S1(2). The same is true for the waveform shaping circuits 40(3) to 40(N). It should be noted that the waveform shaping section 23 is not an essential component, but any configuration is permitted as long as the information that light is detected can be accurately transmitted.

[0072] The time measurement unit 24 performs a time measurement operation based on a plurality of signals S2 (in this example, N signals S2(1) to S2(N)). The time measurement unit 24 has a counter 28 and a plurality of latches 29 (in this example, N latches 29(1) to 29(N)). The counter 28 increments the count value CNT by performing an operation of counting clock pulses of the clock signal CK. The latch 29(1) generates a signal S3(1) by latching the count value CNT based on the signal S2(1), and the latch 29(2) generates a signal S3(2) by latching the count value CNT based on the signal S2(2). The same is true for the latches 29(3) to 29(N).

[0073] Figure 4 A configuration example of the waveform shaping section 23 and the time measurement unit 24 is shown.

[0074] The waveform shaping circuit 40 of the waveform shaping section 23 includes flip-flops (F / F) 42 and 43 and an exclusive OR gate circuit 44 .

[0075] The flip-flops (F / F) 42 and 43 are D-type flip-flops. The clock signal CK is supplied to the clock input terminal of the flip-flop (F / F) 42; the signal S1 is supplied to the data input terminal D; and the output terminal Q is coupled to the first input terminal of the XOR gate circuit 44 and the data input terminal D of the flip-flop (F / F) 43. The clock signal CK is supplied to the clock input terminal of the flip-flop (F / F) 43; the data input terminal D is coupled to the output terminal Q of the flip-flop (F / F) 42 and the first input terminal of the XOR gate circuit 44; and the output terminal Q is coupled to the second input terminal of the XOR gate circuit 44.

[0076] The XOR gate circuit 44 has a first input terminal coupled to the output terminal Q of the flip-flop (F / F) 42 and a data input terminal D of the flip-flop (F / F) 43 , and a second input terminal coupled to the output terminal Q of the flip-flop (F / F) 43 .

[0077] With such a configuration, the waveform shaping circuit 40 detects the transition of the signal S1 to generate a pulse having the same time width as the cycle of the clock signal CK in accordance with the transition.

[0078] In the time measurement unit 24, the clock signal CK is supplied to the clock input terminal of the counter 28, and the count start signal ST is supplied to the reset terminal RST. The counter 28 outputs the count value CNT from the output terminal using a signal of multiple bits (in this example, K bits).

[0079] The latch 29 latches an N-bit signal (count value CNT) input to the data input terminal D at a timing depending on a signal input to the input terminal LD. The count value CNT is supplied to the data input terminal of the latch 29; a signal S2 is supplied to the input terminal LD; and a count start signal ST is supplied to the reset terminal RST. The latch 29 outputs the latched count value (count value CNT1) from the output terminal using a signal S3 of a plurality of bits (in this example, K bits).

[0080] These elements and circuits of the time measurement device 20 are arranged on, for example, two semiconductor substrates.

[0081] Figure 5An example of the configuration of the time measurement device 20 is shown. In this example, the time measurement device 20 includes two stacked semiconductor substrates 110 and 120. The semiconductor substrate 110 is provided with the light receiving element 31 in the pixel array 21, and the surface where the light receiving element 31 is arranged serves as the light receiving surface S of the time measurement device 20. On the semiconductor substrate 120, the resistor element 32 and the circuit in the pixel array 21 are arranged in a region 121 corresponding to the region where the light receiving element 31 is arranged on the semiconductor substrate 110. In addition, the selection signal generator 22, the waveform shaping section 23, and the time measurement unit 24 are arranged in the region 122. The semiconductor substrate 110 and the semiconductor substrate 120 are electrically coupled to each other by using, for example, Cu-Cu bonding.

[0082] Here, the pixel 30 corresponds to a specific example of a “pixel” in the present disclosure. The input signal applied to the first input terminal of the XOR gate circuit 36 ​​corresponds to a specific example of a “first logic signal” in the present disclosure. The XOR gate circuit 36 ​​corresponds to a specific example of a “first logic circuit” in the present disclosure. The AND gate circuit 34 corresponds to a specific example of a “second logic circuit” in the present disclosure. The output signal of the AND gate circuit 34 corresponds to a specific example of a “second logic signal” in the present disclosure. The flip-flop (F / F) 35 corresponds to a specific example of a “third logic circuit” in the present disclosure. The selection signal generator 22 corresponds to a specific example of a “control signal generator” in the present disclosure. The plurality of selection signals SEL correspond to a specific example of a “plurality of first control signals” in the present disclosure. The calibration signal CAL corresponds to a specific example of a “third logic signal” in the present disclosure. The semiconductor substrate 110 corresponds to a specific example of a “first semiconductor substrate” in the present disclosure. The semiconductor substrate 120 corresponds to a specific example of a “second semiconductor substrate” in the present disclosure.

[0083] [Operation and principle]

[0084] Next, the operation and principle of the time measurement unit 1 of the present embodiment will be described.

[0085] [Overview of overall operation]

[0086] First, refer to Figure 1 and Figure 2An overview of the overall operation of the time measurement unit 1 is described. The light emitting section 11 performs a light emitting operation at a time depending on the light emitting control signal C1. The scattering lens 12 scatters the light emitted from the light emitting section 11 within a predetermined angle range. The light (output L1) scattered by the scattering lens 12 is output from the output time measurement unit 1. The light collecting mirror 13 reflects the light (reflected light L2) reflected by the measured object 9 and entering the time measurement unit 1 toward the light receiving surface S of the time measurement device 20. The time measurement device 20 detects the light reflected by the light collecting mirror 13, and measures the time difference between the time when the light emitting section 11 emits light and the time when the light receiving element 31 detects the light. The controller 14 controls the light emitting operation of the light emitting section 11 by providing the light emitting control signal C1 to the light emitting section 11, and controls the operation of the time measurement device 20 by providing the calibration signal CAL, the selection control signal CTRL, the clock signal CK and the count start signal ST to the time measurement device 20.

[0087] [Operation details]

[0088] Next, the operation of the time measurement unit 1 is described in detail while focusing on two pixels 30A and 30B adjacent to each other in the lateral direction among the M pixels 30 belonging to one row of the pixel array 21 .

[0089] Figure 6 An example of the time measurement operation of the time measurement unit 1 is shown. (A) shows the waveforms of the signals S31A and S31B output from the corresponding light receiving elements 31 in the pixels 30A and 30B; (B) shows the waveforms of the selection signals SEL (selection signals SELA and SELB) respectively supplied to the pixels 30A and 30B; (C) shows the waveforms of the signals S35A and S35B output from the corresponding flip-flops (F / F) 35 in the pixels 30A and 30B; (D) shows the waveform of the signal S1 supplied to the waveform shaping circuit 40 corresponding to the pixels 30A, 30B; (E) shows the waveform of the signal S2 output from the waveform shaping circuit 40 corresponding to the pixels 30A and 30B; (F) shows the waveform of the count start signal ST; (G) shows the count value CNT; and (H) shows the count value CNT1 represented by the signal S3 output from the latch 29 corresponding to the pixels 30A and 30B. In this time measurement operation, the voltage of the calibration signal CAL is fixed to a low level or a high level.

[0090] At the beginning, at time t1, when the light emitting section 11 emits light based on the light emission control signal C1, the control section 14 changes the voltage of the count start signal ST from a low level to a high level ( Figure 6Thus, at the time t1, the counter 28 of the time measurement unit 24 starts the counting operation of the clock pulse, and starts to increase the count value CNT ( Figure 6 At the same time, the selection signal generator 22 changes the voltage of the selection signal SELA supplied to the pixel 30A from a low level to a high level based on the selection control signal CTRL ( Figure 6 (B)). Thus, selection of N pixels 30A including the pixel 30A belonging to a single column corresponding to the selection signal SELA is achieved.

[0091] Next, in this example, at time t2, the light receiving element 31 of the pixel 30A detects light, and the voltage of the signal S31A output from the light receiving element 31 drops instantaneously ( Figure 6 Since the voltage of the selection signal SELA is kept at a high level ( Figure 6 (B)), so the trigger (F / F) 35 of the pixel 30A performs a trigger operation, and the voltage of the signal S35A output from the trigger (F / F) 35 changes from a low level to a high level ( Figure 6 As a result, the voltage of the signal S1 supplied to the waveform shaping circuit 40 corresponding to the pixels 30A and 30B changes from a low level to a high level ( Figure 6 It should be noted that in this example, for the convenience of description, it is assumed that the delay time of the signal from the pixel 30A to the waveform shaping circuit 40 is zero.

[0092] Based on this transition of the signal S1, the waveform shaping circuit 40 changes the voltage of the signal S2 from a low level to a high level at time t3, and changes the voltage of the signal S2 from a high level to a low level at time t4 ( Figure 6 (E)).

[0093] The latches 29 corresponding to the pixels 30A and 30B latch the count value CNT based on the signal S2, and output the latched count value (in this example, "2") as the count value CNT1 at time t4 ( Figure 6 (G) and (H)).

[0094] In this example, at time t5, the light receiving element 31 of the pixel 30A detects light, and the voltage of the signal S31A output from the light receiving element 31 drops instantaneously ( Figure 6 Since the voltage of the selection signal SELA is kept at a high level ( Figure 6 (B)), so the trigger (F / F) 35 of the pixel 30A performs a trigger operation, and the voltage of the signal S35A output from the trigger (F / F) 35 changes from a high level to a low level ( Figure 6As a result, the voltage of the signal S1 supplied to the waveform shaping circuit 40 corresponding to the pixels 30A and 30B changes from a high level to a low level ( Figure 6 Based on this transition of the signal S1, the waveform shaping circuit 40 changes the voltage of the signal S2 from a low level to a high level at time t6, and changes the voltage of the signal S2 from a high level to a low level at time t7 ( Figure 6 The latches 29 corresponding to the pixels 30A and 30B latch the count value CNT based on the signal S2, and output the latched count value (in this example, "7") as the count value CNT1 at time t7 ( Figure 6 (G) and (H)).

[0095] It should be noted that in this example, at the time between the time t2 and the time t5, the light receiving element 31 of the pixel 30B detects light, and the voltage of the signal S31B output from the light receiving element 31 drops instantaneously ( Figure 6 However, in this example, since the voltage of the selection signal SELB is at a low level ( Figure 6 (B)), and the pixel 30B is not selected, so the trigger (F / F) 35 of the pixel 30B does not perform the trigger operation. Therefore, in this example, the voltage of the signal S35B output from the trigger (F / F) 35 is maintained at a low level ( Figure 6 (C)).

[0096] Next, at time t8, the selection signal generator 22 changes the voltage of the selection signal SELA supplied to the pixel 30A from the high level to the low level based on the selection control signal CTRL ( Figure 6 (B)). Thus, the selection of the N pixels 30 including the pixel 30A belonging to the single column corresponding to the selection signal SELA is canceled. At the same time, the controller 14 changes the voltage of the count start signal ST from the high level to the low level ( Figure 6 Therefore, at this time t8, the counter 28 of the time measurement unit 24 ends the counting operation of the clock pulse and resets the count value CNT to zero ( Figure 6 In addition, latch 29 resets count value CNT1 to zero ( Figure 6 (H)).

[0097] In this way, the time measurement unit 1 obtains two count values ​​CNT1 (in this example, "2" and "7") corresponding to the time difference between the time t1 when the light emitting section 11 emits light and the time t2 when the light receiving element 31 of the pixel 30A detects the light, and the time difference between the time t1 and the time t5 when the light receiving element 31 of the pixel 30A detects the light. The time measurement unit 1 outputs these count values ​​CNT1.

[0098] Next, at time t9, when the light emitting section 11 emits light based on the light emission control signal C1, the control section 14 changes the voltage of the count start signal ST from the low level to the high level ( Figure 6 Therefore, at this time t9, the counter 28 of the time measurement unit 24 starts the counting operation of the clock pulse, and starts to increase the count value CNT ( Figure 6 At the same time, the selection signal generator 22 changes the voltage of the selection signal SELB supplied to the pixel 30B from a low level to a high level based on the selection control signal CTRL ( Figure 6 This realizes the selection of N pixels 30 including the pixel 30B belonging to a single column corresponding to the selection signal SELB.

[0099] Next, in this example, at time t10, the light receiving element 31 of the pixel 30B detects light, and the voltage of the signal S31B output from the light receiving element 31 drops instantaneously ( Figure 6 (A)). Since the voltage of the selection signal SELB is at a high level ( Figure 6 (B)), so the trigger (F / F) 35 of the pixel 30B performs a trigger operation, and the voltage of the signal S35B output from the trigger (F / F) 35 changes from a low level to a high level ( Figure 6 Therefore, the voltage of the signal S1 supplied to the waveform shaping circuit 40 corresponding to the pixels 30A and 30B changes from a low level to a high level ( Figure 6 (D)).

[0100] Based on this transition of the signal S1, the waveform shaping circuit 40 changes the voltage of the signal S2 from a low level to a high level at time t11, and changes the voltage of the voltage signal S2 from a high level to a low level at time t12 ( Figure 6 (E)).

[0101] The latches 29 corresponding to the pixels 30A and 30B latch the count value CNT based on the signal S2, and output the latched count value (in this example, "4") as the count value CNT1 at time t12 ( Figure 6 (G) and (H)).

[0102] It should be noted that in this example, starting from time t10, the light receiving element 31 of the pixel 30A detects light, and the voltage of the signal S31A output from the light receiving element 31 drops instantaneously ( Figure 6 However, in this example, since the voltage of the selection signal SELA is at a low level ( Figure 6 (B)), and the pixel 30A is not selected, so the trigger (F / F) 35 of the pixel 30A does not perform the trigger operation. Therefore, in this example, the voltage of the signal S35A output from the trigger (F / F) 35 is maintained at a low level ( Figure 6 (C)).

[0103] Next, at time t13, the selection signal generator 22 changes the voltage of the selection signal SELB supplied to the pixel 30B from the low level to the high level based on the selection control signal CTRL ( Figure 6 (B)). Thus, the selection of the N pixels 30 including the pixel 30B belonging to the single column corresponding to the selection signal SELB is canceled. At the same time, the controller 14 changes the voltage of the count start signal ST from the high level to the low level ( Figure 6 Therefore, at this time t13, the counter 28 of the time measurement unit 24 ends the counting operation of the clock pulse and resets the count value CNT to zero ( Figure 6 In addition, latch 29 resets count value CNT1 to zero ( Figure 6 (H)).

[0104] In this way, the time measurement unit 1 obtains a count value CNT1 (in this example, “4”) corresponding to the time difference between time t9 when the light emitting section 11 emits light and time t10 when the light receiving element 31 of the pixel 30B detects light, and outputs the count value CNT1.

[0105] In this way, the time measurement unit 1 is provided with a trigger (F / F) 35 that performs a trigger operation every time the light receiving element 31 detects light, and a waveform shaping circuit 40 that converts the transition of the signal S1 into a pulse based on the trigger operation on each pixel 30. As described below, this allows the time measurement unit 1 to reduce power consumption and achieve stable operation.

[0106] Figure 7 The waveform of the signal S31 output from the light receiving element 31 in the pixel 30 is shown. Figure 8An operation example of the time measurement unit 1 is shown. (A) shows the waveform of the signal S34 output from the AND gate circuit 34 of the pixel 30; (B) shows the waveform of the signal S35 output from the flip-flop (F / F) 35; (C) shows the waveform of the signal S1 input to the waveform shaping circuit 40. (D) shows the waveform of the clock signal CK; (E) and (F) show the waveforms of the signals S42 and S43 output from the flip-flops (F / F) 42 and 43 of the waveform shaping circuit 40, respectively; and (G) shows the waveform of the signal S2 output from the waveform shaping circuit 40.

[0107] like Figure 7 As shown, when light enters the light receiving element 31 at time t19, electron-hole pairs are generated in the light receiving element 31. Subsequently, the generated electrons and holes are accelerated by the electric field, and electron-hole pairs are successively formed by impact ionization. In a manner in which the light receiving element 31 performs so-called avalanche amplification, the voltage of the signal S31 drops from the bias voltage Vbias at one time. Subsequently, the voltage of the signal S31 gradually rises to eventually return to the bias voltage Vbias.

[0108] In response to this voltage change, Figure 8 As shown in (A), the AND gate circuit 34 in the pixel 30 generates a signal S34 ( Figure 8 The trigger (F / F) 35 performs a trigger operation based on the rising edge of the signal S34, so that the voltage of the signal S35 changes from a low level to a high level ( Figure 8 As a result, the voltage of the signal S1 supplied to the waveform shaping circuit 40 changes from a low level to a high level ( Figure 8 (C)).

[0109] The trigger (F / F) 42 of the waveform shaping circuit 40 samples the signal S1 at the rising time of the clock signal CK, thereby changing the voltage of the signal S42 from a low level to a high level at time t22 ( Figure 8 The trigger (F / F) 43 samples the signal S42 at the rising moment of the clock signal CK, thereby changing the voltage of the signal S43 from a low level to a high level at time t23 ( Figure 8 Based on the signals S42 and S43, the XOR gate circuit 44 changes the voltage of the signal S2 from the low level to the high level at the time t22, and changes the voltage of the signal S2 from the high level to the low level at the time t23.

[0110] In the above, the operation at the time between t21 and t23 is exemplarily described; however, the same is true for the operation at the time between t24 and t26.

[0111] In this way, the time measurement unit 1 is provided with the trigger (F / F) 35, which performs a trigger-type operation every time the light receiving element 31 detects light, on each pixel 30. For example, compared with the case where the trigger (F / F) 35 is not provided, this can reduce the number of signal transitions in the path from the pixel 30 to the waveform shaping circuit 40, thereby allowing power consumption to be reduced.

[0112] Furthermore, in this operation, since the pulse width PW of the pulse of the signal S34 output from the AND gate circuit 34 is determined by the operation of the light receiving element 31 as described above, such pulse width PW is easily changed due to, for example, manufacturing deviation or environmental deviation. The time measurement unit 1 is provided with a trigger (F / F) 35, which performs a trigger operation on each pixel 30, and therefore, the pixel 30 does not output a narrow width pulse, thereby allowing the possibility that the circuit operation may become unstable to be reduced. Furthermore, the time measurement unit 1 is provided with a waveform shaping circuit 40, which converts the transition of the signal S1 into a pulse based on the trigger operation. Thus, the pulse width of the pulse of the signal S1 becomes a time width corresponding to the period of the clock signal CK, thereby allowing the possibility that the circuit operation may become unstable to be reduced.

[0113] In the above description, the delay time of the signal from each pixel 30 to the waveform shaping circuit 40 is assumed to be zero; however, there is a possibility that the delay time occurs in practice. The delay time may vary due to manufacturing deviation or environmental deviation. In this case, there is a possibility that the delay time is caused by the time measurement operation ( Figure 6 ) may deteriorate the accuracy of the measurement result obtained. Therefore, the time measurement unit 1 can measure the delay time td of the signal from the leftmost pixel 30 in the pixel array 21 to the waveform shaping circuit 40 by performing a calibration operation. Hereinafter, this operation is described in detail.

[0114] Fig. 9 An example of a calibration operation in the time measurement unit 1 is shown. (A) shows the waveform of the calibration signal CAL; (B) shows the corresponding waveforms of the selection signals SELA and SELB; (C) shows the waveform of the signal S1 provided to the waveform shaping circuit 40 corresponding to the pixels 30A, 30B; (D) shows the waveform of the signal S2 output from the waveform shaping circuit 40 corresponding to the pixels 30A and 30B; (E) shows the waveform of the count start signal ST; (F) shows the count value CNT; and (G) shows the count value CNT1 represented by the signal S3 output from the latch 29 corresponding to the pixels 30A and 30B. Fig. 9 As shown in (B), in this calibration operation, the voltages of the M selection signals SEL are respectively fixed to a low level.

[0115] At the beginning, at time t31, the controller 14 changes the voltage of the count start signal ST from the low level to the high level ( Fig. 9 Thus, at this time t31, the counter 28 of the time measurement unit 24 starts the counting operation of the clock pulse, and starts to increase the count value CNT ( Fig. 9 (F)).

[0116] At the same time, the controller 14 changes the voltage of the calibration signal CAL from a low level to a high level ( Fig. 9 This causes the voltage of the signal S1 supplied to the waveform shaping circuit 40 corresponding to the pixels 30A and 30B to change from a low level to a high level at time t32 ( Fig. 9 In other words, the time between time t31 and time t32 corresponds to the delay time td of the signal from the leftmost pixel 30 in the pixel array 21 to the waveform shaping circuit 40.

[0117] Based on this transition of the signal S1, the waveform shaping circuit 40 changes the voltage of the signal S2 from a low level to a high level at time t33, and changes the voltage of the signal S2 from a high level to a low level at time t34 ( Fig. 9 The latch 29 latches the count value CNT based on the signal S2, and outputs the latched count value (in this example, "2") as the count value CNT1 at time t34 ( Fig. 9 (F) and (G)).

[0118] Subsequently, at time t35, the controller 14 changes the voltage of the count start signal ST from the high level to the low level ( Fig. 9 Thus, at this time t35, the counter 28 of the time measurement unit 24 ends the counting operation of the clock pulse and resets the count value CNT to zero ( Fig. 9 In addition, latch 29 resets count value CNT1 to zero ( Fig. 9 (G)).

[0119] In this way, the time measurement unit 1 obtains the count value CNT1 (in this example, "2") corresponding to the delay time td of the signal from the leftmost pixel 30 in the pixel array 21 to the waveform shaping circuit 40, and outputs the count value CNT1. The same is true for the operation between t36 and t40.

[0120] As described above, in the time measurement unit 1, the calibration signal CAL is supplied to the input terminal IN of the leftmost pixel 30 in the pixel array 21. This allows the time measurement unit 1 to measure the delay time td of the signal from the leftmost pixel 30 in the pixel array 21 to the waveform shaping circuit 40. Thus, for example, a processing circuit (e.g., an application processor or any other device) at a subsequent stage of the time measurement unit 1 determines the delay time of the signal from each pixel 30 to the waveform shaping circuit 40 based on the measurement result, and corrects the delay time caused by the time measurement operation ( Figure 6 ) is obtained, thereby allowing the measurement accuracy to be improved. It should be noted that in this example, the processing circuit at the rear stage corrects the measurement result obtained by the time measurement operation; however, the method is not limited to this, and the time measurement unit 24 can correct the measurement result obtained by the time measurement operation.

[0121] In addition, in the time measurement unit 1, a plurality of pixels 30 (in this example, M pixels 30) are coupled to each other using a so-called daisy chain connection, so that the layout can be facilitated. In other words, for example, in the case where the configuration is performed by omitting the XOR gate circuit 36 ​​from each of the M pixels 30 and providing the output signals of the M triggers (F / F) 35 to the waveform shaping circuit 40 through, for example, an AND gate circuit having M input terminals, this makes the wiring complicated and increases the possibility that it is difficult to arrange the circuit layout. In particular, for example, if the number of pixels increases to more than 200, the difficulty of the layout may become prominent. In contrast, in the time measurement unit 1, a plurality of pixels 30 (in this example, M pixels 30) are coupled to each other using a so-called daisy chain connection, which makes it possible to simplify the wiring, thereby allowing the layout to be easily implemented.

[0122] In addition, if Figure 5As shown, in the time measurement unit 1, the time measurement device 20 is constructed using two stacked semiconductor substrates 110 and 120. Specifically, the light receiving element 31 in the pixel array 21 is arranged on the semiconductor substrate 110, and the elements and circuits other than the light receiving element 31 in the pixel array 21 are arranged on the semiconductor substrate 120. In this case, for example, the inverter 33, the AND gate circuit 34, the flip-flop (F / F) 35, and the XOR gate circuit 36 ​​are arranged on the semiconductor substrate 120, which can reduce the possibility of noise propagating from these circuits to the light receiving element 31. Similarly, for example, a signal line for transmitting a selection signal SEL or a signal line for transmitting a signal through M XOR gate circuits 36 is also arranged on the semiconductor substrate 120, which can reduce the possibility of noise propagating from these circuits to the light receiving element 31. In addition, for example, the light receiving element 31 is mainly arranged on the semiconductor substrate 110, which allows the element size of the light receiving element 31 to be increased. Furthermore, for example, the semiconductor substrate 110 may be manufactured using a process optimized for manufacturing the light receiving element 31 , and the semiconductor substrate 120 may be manufactured using a process optimized for manufacturing circuits, so that the characteristics of the time measurement device 20 may be improved.

[0123] [Effect]

[0124] As described above, in the present embodiment, a plurality of pixels are coupled to each other using a so-called daisy chain connection, so that the layout can be facilitated.

[0125] In this embodiment, a trigger for performing a trigger operation whenever the light receiving element detects light is provided in each pixel, and a waveform shaping circuit for converting the transition of the signal into a pulse based on the trigger operation is also provided, thereby reducing power consumption and achieving stable operation.

[0126] In this embodiment, the calibration signal is provided to the input terminal of the leftmost pixel in the pixel array, thereby measuring the delay time of the signal from the leftmost pixel in the pixel array to the waveform shaping circuit, thereby improving the measurement accuracy.

[0127] In this embodiment, two stacked semiconductor substrates are used to construct the time measurement device, thereby reducing the possibility of noise propagation to the light receiving element and increasing the element size of the light receiving element. In addition, the two semiconductor substrates can be manufactured using corresponding optimized processes, thereby allowing improved characteristics.

[0128] [Variation 1-1]

[0129] In the above embodiment, the time measuring device 20 uses Figure 3The time measurement device 1C is configured by the waveform shaping section 23 and the time measurement unit 24 shown in the figure; however, the configuration is not limited to this. Hereinafter, the time measurement unit 1C according to this modification is described in detail. The time measurement unit 1C includes a time measurement device 20C. The time measurement device 20C has a waveform shaping section 23C and a time measurement unit 24C.

[0130] Fig.10 2 shows a configuration example of a waveform shaping section 23C and a time measurement unit 24C. The waveform shaping section 23C has a plurality of waveform shaping circuits 40C (in this example, N waveform shaping circuits 40C(1) to 40C(N)). The waveform shaping circuit 40C has flip-flops (F / F) 41 to 43 and an exclusive OR gate circuit 44. In other words, in the waveform shaping circuit 40C, a flip-flop (F / F) 41 is added to the waveform shaping circuit 40( Figure 4 ). The clock signal CK is supplied to the clock input terminal of the flip-flop (F / F) 41; the signal S1 is supplied to the data input terminal D; and the output terminal Q is coupled to the data input terminal D of the flip-flop (F / F) 42.

[0131] The time measurement unit 24C has a counter 28 and a plurality of latches 29C (in this example, N latches 29C(1) to 29C(N)). The latch 29C operates based on the clock signal CK to latch an N-bit signal (count value CNT) input to the data input terminal D at a timing depending on the signal input to the input terminal LD. The count value CNT is supplied to the data input terminal of the latch 29C; the clock signal CK is supplied to the clock input terminal; the signal S2 is supplied to the input terminal LD; and the count start signal ST is supplied to the reset terminal RST.

[0132] [Variation 1-2]

[0133] In the above embodiment, if Figure 3 As shown, the anode of the light receiving element 31 is grounded; however, this is not restrictive. As an alternative, for example, as in Fig.11 As shown in the pixel 30D, the resistor element can be grounded. The pixel 30D has a light-receiving element 31D, a resistor element 32D and a buffer 37D. The anode of the light-receiving element 31D is coupled to one end of the resistor element 32D and the input terminal of the buffer 37D, and the bias voltage Vbias is provided to the cathode. The end of the resistor element 32D is coupled to the anode of the light-receiving element 31D and the input terminal of the buffer 37D, and the cathode is grounded. The input terminal of the buffer 37D is coupled to the anode of the light-receiving element 31D and the end of the resistor element 32D, and the output terminal is coupled to the first input terminal of the AND gate circuit 34.

[0134] [Variation 1-3]

[0135] In the above-described embodiment, a configuration is adopted that allows measurement of the delay time td of the signal from the leftmost pixel 30 in the pixel array 21 to the waveform shaping circuit 40. In addition to this, for example, a configuration that allows measurement of the delay time of the signal from each pixel to the waveform shaping circuit 40 may be adopted. Hereinafter, the time measurement unit 1E according to the present modification is described in detail. The time measurement unit 1E has a time measurement device 20E and a controller 14E.

[0136] Fig.12 An example of a configuration of a time measurement device 20E is shown. The time measurement device 20E has a pixel array 21E. The pixel array 21E has a plurality of pixels 30E arranged in a matrix pattern.

[0137] Fig.13 An example of the construction of a pixel 30E is shown. The pixel 30E has an OR gate circuit 38E. The OR gate circuit 38E obtains a logical sum (OR) of a signal input to a first input terminal and a signal input to a second input terminal, and outputs the obtained result from an output terminal. A test mode signal TE is input to a first input terminal of the OR gate circuit 38E; a second input terminal is coupled to an output terminal of an inverter 33; and an output terminal is coupled to a first input terminal of an AND gate circuit 34. A single test mode signal TE is provided to all pixels 30E in a pixel array 21E. Here, the test mode signal TE corresponds to a specific example of a “second logic signal” in the present disclosure. Each of the OR gate circuit 38E and the AND gate circuit 34 corresponds to a specific example of a “fourth logic circuit” in the present disclosure.

[0138] like Fig.12 As shown, the controller 14E also has a function of generating a test mode signal TE.

[0139] Next, the operation of the time measurement unit 1E is described in detail while focusing on two pixels 30A and 30B adjacent to each other in the lateral direction among the M pixels 30E belonging to one row in the pixel array 21E.

[0140] Fig.14An example of a test operation of the time measurement unit 1E is shown. (A) shows the waveform of the test mode signal TE; (B) shows the waveforms of the selection signals SELA and SELB; (C) shows the waveforms of the signals S35A and S35B output from the corresponding triggers (F / F) 35 in the pixels 30A and 30B; (D) shows the waveform of the signal S1 provided to the waveform shaping circuit 40 corresponding to the pixels 30A and 30B; (E) shows the waveform of the signal S2 output from the waveform shaping circuit 40 corresponding to the pixels 30A and 30B; (F) shows the waveform of the count start signal ST; (G) shows a count value CNT; and (H) shows a count value CNT1 represented by the signal S3 output from the latch 29 corresponding to the pixels 30A and 30B. Fig.14 As shown in (A), in this test operation, the voltage of the test mode signal TE is fixed to a high level. It should be noted that in the time measurement operation and the calibration operation, the voltage of the test mode signal TE is fixed to a low level.

[0141] At the beginning, at time t41, the controller 14E changes the voltage of the count start signal ST from the low level to the high level ( Fig.14 Thus, at this time t41, the counter 28 of the time measurement unit 24 starts the counting operation of the clock pulse, and starts to increase the count value CNT ( Fig.14 (G)).

[0142] Next, in this example, at time t42, when the count value CNT becomes "3", the selection signal generator 22 changes the voltage of the selection signal SELA supplied to the pixel 30A from the low level to the high level based on the selection control signal CTRL, and changes the voltage of the selection signal SELA from the high level to the low level at the subsequent time ( Fig.14 As a result, the trigger (F / F) 35 of the pixel 30A performs a trigger operation, and the voltage of the signal S35 output from the trigger (F / F) 35 changes from a low level to a high level ( Fig.14 Thus, the voltage of the signal S1 supplied to the waveform shaping circuit 40 corresponding to the pixels 30A and 30B changes from a low level to a high level at time t43 ( Fig.14 In other words, the time between time t42 and time t43 corresponds to the delay time tdA of the signal from the pixel 30A to the waveform shaping circuit 40.

[0143] Based on this transition of the signal S1, the waveform shaping circuit 40 changes the voltage of the signal S2 from the low level to the high level at time t44, and changes the voltage of the signal S2 from the high level to the low level at time t45 ( Fig.14(E)).

[0144] The latches 29 corresponding to the pixels 30A and 30B latch the count value CNT based on the signal S2, and output the latched count value (in this example, "4") as the count value CNT1 at time t45 ( Fig.14 (G) and (H)).

[0145] Subsequently, at time t46, the controller 14E changes the voltage of the count start signal ST from the high level to the low level ( Fig.14 Thus, at this time t46, the counter 28 of the time measurement unit 24 ends the counting operation of the clock pulse and resets the count value CNT to zero ( Fig.14 In addition, latch 29 resets count value CNT1 to zero ( Fig.14 (H)).

[0146] In this way, the time measurement unit 1E outputs the count value CNT1 (in this example, "4"). It should be noted that in this example, the voltage of the selection signal SELA is changed from the low level to the high level at the time t42 when the count value CNT becomes "3", and therefore the count value corresponding to the delay time of the signal from the pixel 30A to the waveform shaping circuit 40 is obtained by subtracting the count value "3" from the count value CNT1 (in this example, "4"), "1".

[0147] Next, at time t47, the controller 14E changes the voltage of the count start signal ST from the low level to the high level ( Fig.14 Therefore, at this time t47, the counter 28 of the time measurement unit 24 starts the counting operation of the clock pulse, and starts to increase the count value CNT ( Fig.14 (G)).

[0148] Next, in this example, at time t48 when the count value CNT becomes "4", the selection signal generator 22 changes the voltage of the selection signal SELB supplied to the pixel 30B from the low level to the high level based on the selection control signal CTRL, and changes the voltage of the selection signal SELB from the high level to the low level at the subsequent time ( Fig.14 This causes the trigger (F / F) 35 of the pixel 30B to perform a trigger operation, and the voltage of the signal S35B output from the trigger (F / F) 35 changes from a low level to a high level ( Fig.14 Therefore, the voltage of the signal S1 supplied to the waveform shaping circuit 40 corresponding to the pixels 30A and 30B changes from a high level to a low level at time t49 ( Fig.14In other words, the time between time t48 and time t49 corresponds to the delay time tdB of the signal from the pixel 30B to the waveform shaping circuit 40.

[0149] Based on this transition of the signal S1, the waveform shaping circuit 40 changes the voltage of the signal S2 from a low level to a high level at time t50, and changes the voltage of the signal S2 from a high level to a low level at time t51 ( Fig.14 (E)).

[0150] The latches 29 corresponding to the pixels 30A and 30B latch the count value CNT based on the signal S2, and output the latched count value (in this example, "5") as the count value CNT1 at time t51 ( Fig.14 (G) and (H)).

[0151] Subsequently, at time t52, the controller 14E changes the voltage of the count start signal ST from the high level to the low level ( Fig.14 Therefore, at this time t52, the counter 28 of the time measurement unit 24 ends the counting operation of the clock pulse and resets the count value CNT to zero ( Fig.14 In addition, latch 29 resets count value CNT1 to zero ( Fig.14 (H)).

[0152] In this way, the time measurement unit 1E outputs the count value CNT1 (in this example, "5"). It should be noted that in this example, the voltage of the selection signal SELB is changed from the low level to the high level at the time t48 when the count value CNT becomes "4", and therefore the count value corresponding to the delay time tdB of the signal from the pixel 30B to the waveform shaping circuit 40 is obtained by subtracting the count value "4" from the count value CNT1 (in this example, "5") "1".

[0153] As described above, in the time measurement unit 1E, the OR gate circuit 38E is provided in each pixel 30E, and the flip-flop (F / F) 35 performs a trigger operation based on the selection signal SEL at the time of the test operation. This allows the time measurement unit 1E to measure the delay time of the signal from each pixel 30E to the waveform shaping circuit 40. Therefore, for example, the processing circuit (e.g., an application processor or any other device) at the subsequent stage of the time measurement unit 1E corrects the measurement result obtained by the time measurement operation using the measured delay time ( Figure 6 ), thereby allowing the measurement accuracy to be improved. It should be noted that in this example, the processing circuit at the rear stage corrects the measurement result obtained by the time measurement operation; however, this is not restrictive, and the time measurement unit 24 may correct the measurement result obtained by the time measurement operation.

[0154] In the time measurement unit 1E, the calibration signal CAL supplied from the controller 14 is input to the input terminal IN of the leftmost pixel 30 among the plurality of pixels 30E in the pixel array 21E; however, the configuration is not limited thereto. Fig.15 The time measurement device 20F of the time measurement unit 1F shown can input a voltage of a predetermined level (in this example, a low level) to the input terminal IN of the leftmost pixel 30 among the plurality of pixels 30E. The time measurement unit 1F has a controller 14F. The controller 14F omits the function of generating the calibration signal CAL in the controller 14E. Also in this case, the delay time of the signal from each pixel 30E to the waveform shaping circuit 40 can be measured, thereby allowing the measurement accuracy to be improved.

[0155] [Variation 1-4]

[0156] In the above-described embodiment, the calibration signal CAL supplied from the controller 14 is input to the input terminal IN of the leftmost pixel 30 among the plurality of pixels 30 in the pixel array 21; however, the configuration is not limited thereto. Fig.16 The time measurement device 20G of the time measurement unit 1G shown can input a voltage of a predetermined level (in this example, a low level) to the input terminal IN of the leftmost pixel 30 among the plurality of pixels 30. For example, the time measurement unit 1G can be used for applications in which the signal delay time in the pixel array 21 has no significant influence on the measurement accuracy. In addition, for example, a processing circuit (e.g., an application processor or any other device) at a subsequent stage of the time measurement unit 1G can correct the measurement result obtained by the time measurement operation using a delay time estimated at the time of design, a delay time actually measured during a diagnosis before shipment, or any other delay time. Figure 6 ).

[0157] [Other Modifications]

[0158] Furthermore, two or more of these modifications may be combined.

[0159] [2. Second embodiment]

[0160] Next, a time measurement unit 2 according to a second embodiment will be described. This embodiment constructs a time measurement device using a pixel that does not include a trigger (F / F) 35. It should be noted that any component that is substantially the same as the component according to the above-mentioned first embodiment is denoted by the same reference numerals, and the related description is appropriately omitted.

[0161] like Fig.17 As shown, the time measuring unit 2 has a time measuring device 50 .

[0162] Fig.17 There is shown a configuration example of a time measurement device 50. The time measurement device 50 has a pixel array 51, a selection signal generator 22, and a time measurement unit 24. The pixel array 51 has a plurality of pixels 60 arranged in a matrix pattern.

[0163] Fig.18 An example of the construction of a pixel 60 is shown. The pixel 60 has a light receiving element 31, a resistor element 32, an inverter 33, an AND gate circuit 34, and an OR gate circuit 66. The OR gate circuit 66 obtains a logical sum (OR) of a signal input to a first input terminal and a signal input to a second input terminal, and outputs the obtained result from an output terminal. A first input terminal of the OR gate circuit 66 is coupled to an output terminal of the AND gate circuit 34; a second input terminal is coupled to an input terminal IN of the pixel 60; and an output terminal is coupled to an output terminal OUT of the pixel 60. In other words, the pixel 60 omits the trigger (F / F) 35, and the XOR gate circuit 36 ​​( Figure 3 ) is replaced by an OR gate circuit 66.

[0164] like Fig.17 As shown in FIG. 1 , the calibration signal CAL supplied from the controller 14 is input to the input terminal IN of the leftmost pixel 60 among the M pixels 60 arranged side by side in a single row in the lateral direction. Fig.18 As shown, the input terminals IN of the pixels 60 except the leftmost pixel 60 among the M pixels 60 are coupled to the output terminals OUT of the pixels 60 adjacent to the left thereof. Fig.17 As shown, the output terminal OUT of the rightmost pixel 60 among the M pixels 60 is coupled to the time measurement unit 24. The rightmost pixel 60 outputs a signal S2. Specifically, the rightmost pixel 60 among the M pixels 60 in the first row outputs a signal S2(1), and the rightmost pixel 60 among the M pixels 60 in the second row outputs a signal S2(2). The same is true for the 3rd to Nth rows.

[0165] Here, the pixel 60 corresponds to a specific example of a “pixel” in the present disclosure. The input signal applied to the first input terminal of the OR circuit 66 corresponds to a specific example of a “first logic signal” in the present disclosure. The OR circuit 66 corresponds to a specific example of a “first logic circuit” in the present disclosure.

[0166] Next, the operation of the time measurement unit 2 is described with attention paid to two pixels 60A and 60B adjacent to each other in the lateral direction among the M pixels 60 belonging to one row in the pixel array 51 .

[0167] Fig.19An example of the time measurement operation in the time measurement unit 2 is shown. (A) shows the waveforms of the signals S31A and S31B output from the respective light receiving elements 31 in the pixels 60A and 60B; (B) shows the waveforms of the selection signals SEL (selection signals SELA and SELB) respectively supplied to the pixels 60A and 60B; (C) shows the waveforms of the signals S34A and S34B output from the respective AND gate circuits 34 in the pixels 60A and 60B; (D) shows the waveform of the signal S2 supplied to the latches 29 corresponding to the pixels 60A and 60B; (E) shows the waveform of the count start signal ST; (F) shows the count value CNT; and (G) shows the count value CNT1 represented by the signal S3 output from the latches 29 corresponding to the pixels 60A and 60B.

[0168] At the beginning, at time t61, when the light emitting section 11 emits light based on the light emission control signal C1, the controller 14 changes the voltage of the count start signal ST from a low level to a high level ( Fig.19 Therefore, at this time t61, the counter 28 of the time measurement unit 24 starts the counting operation of the clock pulse, and starts to increase the count value CNT ( Fig.19 At the same time, the selection signal generator 22 changes the voltage supplied to the pixel 60A from a low level to a high level based on the selection control signal CTRL ( Fig.19 (B)). Thus, the pixels 60 including the pixel 60A belonging to a single column corresponding to the selection signal SELA are selected.

[0169] Next, in this example, at time t62, the light receiving element 31 of the pixel 60A detects light, and the voltage of the signal S31A output from the light receiving element 31 drops instantaneously ( Fig.19 (A)). Since the voltage of the selection signal SELA is at a high level ( Fig.19 (B)), so the voltage of the signal S34A generated from the AND gate circuit changes from a low level to a high level at time t62, and changes from a high level to a low level at the subsequent time ( Fig.19 Therefore, the voltage of the signal S2 supplied to the latch 29 corresponding to the pixels 60A and 60B changes from a low level to a high level at a time S63, and changes from a high level to a low level at a subsequent time ( Fig.19 (D)).

[0170] The latches 29 corresponding to the pixels 60A and 60B latch the count value CNT based on the signal S2, and output the latched count value (in this example, "2") as the count value CNT1 at time t64 ( Fig.19 (F) and (G)).

[0171] In this example, at time t65, the light receiving element 31 of the pixel 60A detects light, and the voltage of the signal S31A output from the light receiving element 31A drops instantaneously ( Fig.19 (A)). Since the voltage of the selection signal SELA is at a high level ( Fig.19 (B)), so the voltage of the signal S34B output from the AND gate circuit 34 changes from a low level to a high level at time t65, and changes from a high level to a low level at the subsequent time ( Fig.19 Therefore, the voltage of the signal S2 supplied to the latch 29 corresponding to the pixels 60A and 60B changes from a low level to a high level at time t66, and changes from a high level to a low level at a subsequent time ( Fig.19 The latches 29 corresponding to the pixels 60A and 60B latch the count value CNT based on the signal S2, and output the latched count value (in this example, "7") as the count value CNT1 at time t67 ( Fig.19 (F) and (G)).

[0172] It should be noted that in this example, at the time between the time t62 and t65, the light receiving element 31 of the pixel 60B detects light, and the voltage of the signal S31B output from the light receiving element 31 drops instantaneously ( Fig.19 However, in this example, since the voltage of the selection signal SELB is at a low level ( Fig.19 (B)), and the pixel 60B is not selected, so the voltage of the signal S34B output from the AND gate circuit 34 of the pixel 60B remains at a low level in this example ( Fig.19 (C)).

[0173] Subsequently, at time t68, the selection signal generator 22 changes the voltage of the selection signal SELA supplied to the pixel 60A from the high level to the low level based on the selection control signal CTRL ( Fig.19 (B)). Thus, the selection of the N pixels 60 including the pixel 60A belonging to the single column corresponding to the selection signal SELA is canceled. At the same time, the controller 14 changes the voltage of the count start signal ST from the high level to the low level ( Fig.19 Therefore, at time t68, the counter 28 of the time measurement unit 24 ends the counting operation of the clock pulse and resets the count value CNT to zero ( Fig.19 In addition, latch 29 resets count value CNT1 to zero ( Fig.19 (G)).

[0174] In this way, the time measurement unit 2 obtains two count values ​​CNT1 (in this example, "2" and "7") corresponding to the time difference between the time t61 when the light emitting section 11 emits light and the time t62 when the light receiving element 31 of the pixel 60A detects the light, and between the time t61 and the time t65 when the light receiving element 31 of the pixel 60A detects the light. The time measurement unit 2 outputs these count values ​​CNT1.

[0175] Next, at time t69, when the light emitting unit 11 emits light based on the light emission control signal C1, the controller 14 changes the voltage of the count start signal ST from the low level to the high level ( Fig.19 Therefore, at this time t69, the counter 28 of the time measurement unit 24 starts the counting operation of the clock pulse, and starts to increase the count value CNT ( Fig.19 At the same time, the selection signal generator 22 changes the voltage of the selection signal SELB supplied to the pixel 60B from a low level to a high level based on the selection control signal CTRL ( Fig.19 (B)). Thus, selection of N pixels 60 including the pixel 60B belonging to a single column corresponding to the selection signal SELB is achieved.

[0176] Next, in this example, at time t70, the light receiving element 31 of the pixel 60B detects light, and the voltage of the signal S31B output from the light receiving element 31 drops instantaneously ( Fig.19 (A)). Since the voltage of the selection signal SELB is at a high level ( Fig.19 (B)), so the voltage of the signal S34B output from the AND gate circuit 34 changes from a low level to a high level at the time t70, and changes from a high level to a low level at the subsequent time ( Fig.19 Therefore, the voltage of the signal S2 supplied to the latch 29 corresponding to the pixels 60A and 60B changes from a low level to a high level at time t71, and changes from a high level to a low level at a subsequent time ( Fig.19 (D)).

[0177] The latches 29 corresponding to the pixels 60A and 60B latch the count value CNT based on the signal S2, and output the latched count value (in this example, "4") as the count value CNT1 at time t72 ( Fig.19 (F) and (G)).

[0178] It should be noted that in this example, starting from time t70, the light receiving element 31 of the pixel 60A detects light, and the voltage of the signal S31A output from the light receiving element 31 drops instantaneously ( Fig.19However, in this example, since the voltage of the selection signal SELA is at a low level ( Fig.19 (B)), and the pixel 60A is not selected, so the voltage of the signal S34A output from the AND gate circuit 34 of the pixel 60A remains at a low level in this example ( Fig.19 (C)).

[0179] Subsequently, at time t73, the selection signal generator 22 changes the voltage of the selection signal SELB supplied to the pixel 60B from the high level to the low level based on the selection control signal CTRL ( Fig.19 (B)). Thus, the pixels 60 including the pixel 60B belonging to the single column corresponding to the selection signal SELB are deselected. At the same time, the controller 14 changes the voltage of the count start signal ST from the high level to the low level ( Fig.19 Therefore, at this time t73, the counter 28 of the time measurement unit 24 ends the counting operation of the clock pulse and resets the count value CNT to zero ( Fig.19 In addition, latch 29 resets count value CNT1 to zero ( Fig.19 (G)).

[0180] In this way, the time measurement unit 2 obtains the count value CNT1 (in this example, "4") and outputs the count value CNT1, which corresponds to the time difference between the time t69 when the light emitting section 11 emits light and the time t70 when the light receiving element 31 of the pixel 60B detects the light.

[0181] This configuration can also achieve effects similar to those obtained in the case of the above-described first embodiment.

[0182] In other words, in the present embodiment, a plurality of pixels are coupled to each other using a so-called daisy chain connection, so that the layout can be facilitated.

[0183] In this embodiment, a calibration signal is provided to the input terminal of the leftmost pixel in the pixel array, so that the delay time of the signal from the leftmost pixel in the pixel array to the waveform shaping circuit can be measured, thereby improving the measurement accuracy.

[0184] In this embodiment, two stacked semiconductor substrates are used to construct the time measurement device, thereby reducing the possibility of noise propagation to the light receiving element and increasing the element size of the light receiving element. In addition, the two semiconductor substrates can be manufactured using corresponding optimized processes, thereby allowing improved characteristics.

[0185] [Modification 2]

[0186] Each modification example of the above-described first embodiment can be applied to the time measurement unit 2 according to the above-described embodiment. Fig. 20 1 is an example in which the modification 1-3 according to the above-described first embodiment is applied to the time measurement unit 2. As in the pixel 30E according to the above-described first embodiment ( Fig.13 ), Fig. 20 The OR circuit 38E shown has an OR circuit 38E to which the test mode signal TE is inputted, a first input terminal of the OR circuit 38E, a second input terminal coupled to the output terminal of the inverter 33 , and an output terminal coupled to a first input terminal of the AND circuit 34 .

[0187] [3. Application examples]

[0188] Next, application examples of any of the time measurement devices according to the above-described embodiments will be described.

[0189] Fig.21 1 shows a configuration example of a distance measurement device 70 according to Application Example 1. The distance measurement device 70 includes a SPAD array 71, a SPAD controller 72, a controller 73, a phase locked loop (PLL: Phase Locked Loop) 74, a clock generator 7, a reference current source 76, a thermometer 77, a light emission timing controller 78, a distance measurement processing section 80, and a transmitter 79.

[0190] The SPAD array 71 includes single photon avalanche diodes (SPADs) arranged in a matrix pattern. The SPAD controller 72 controls the operation of the SPAD array 71 based on instructions from the controller 73. The controller 73 controls the operation of the distance measurement device 70. In addition, the controller 73 also has a function for controlling the distance measurement device 70 through the COM terminal, for example, using I 2C is a function of communicating with an external device. PLL 74 operates based on an input clock provided through the CKIN terminal. Clock generator 75 generates one or more clock signals used in distance measuring device 70. Reference current source 76 generates one or more reference currents used in distance measuring device 70. Thermometer 77 detects the temperature in distance measuring device 70. Light emission timing controller 78 controls light emission timing based on a light emission trigger signal provided through TRGIN terminal. Light emission timing controller 78 generates a light emission trigger signal to provide the final light emission trigger signal to ranging processing unit 80, and also outputs such light emission trigger signal through TRGOUT terminal. Ranging processing unit 80 generates a depth image based on the detection result of SPAD array 71. Ranging processing unit 80 has TDC (time to digital converter) 81, histogram generator 82 and processing unit 83. TDC 81 converts light emission timing into digital value based on the detection result of SPAD array 71. Histogram generator 82 generates a histogram based on the digital value obtained from TDC 81. The processing unit 83 performs various processes based on the histogram generated by the histogram generator 82. For example, the processing unit 83 performs FIR (finite impulse response) filtering, echo determination, depth value (distance value) calculation processing, peak detection processing, etc. The transmitter 79 outputs the depth image generated by the ranging processing unit 80 through the DOUT terminal, for example, using serial data. As an interface of the transmitter 79, for example, MIPI (Mobile Industry Processor Interface) can be used.

[0191] The distance measuring device 70 is constructed using, for example, two stacked semiconductor substrates 88 and 89. The SPAD array 71 is arranged on the semiconductor substrate 88. In addition, other circuits in the distance measuring device 70 other than the SPAD array 71 are arranged on the semiconductor substrate 89. Specifically, the SPAD controller 72, the controller 73, the PLL 74, the clock generator 75, the reference current source 76, the thermometer 77, the light emission timing controller 78, the distance measurement processing unit 80 and the transmitter 79 are arranged on the semiconductor substrate 89.

[0192] [4. Application examples of moving objects]

[0193] The technology according to the embodiments of the present disclosure (the present technology) is applicable to various products. For example, the technology according to the embodiments of the present disclosure can be implemented in the form of a device installed on any type of mobile body. Examples of mobile bodies include automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0194] Fig. 22 : is a block diagram depicting an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0195] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Fig. 22 In the depicted example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. A microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as a functional configuration of the integrated control unit 12050.

[0196] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 is used as a control device for a drive force generating device such as an internal combustion engine, a drive motor, etc. for generating a drive force for the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force for the vehicle, etc.

[0197] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for the following devices: a keyless entry system, a smart key system, a power window device, various lights such as headlights, reverse lights, brake lights, turn lights, or fog lights, etc. In this case, radio waves sent from a mobile device that replaces the key or signals of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives input of these radio waves or signals and controls the door lock device, power window device, lights, etc. of the vehicle.

[0198] The vehicle exterior information detection unit 12030 detects information of the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform target detection processing or distance detection processing of objects such as people, vehicles, obstacles, signs, characters on the road surface, etc.

[0199] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image or measured distance information. In addition, the light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0200] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 may include a camera for photographing the driver. The in-vehicle information detection unit 12040 may calculate the driver's fatigue level or the driver's concentration level based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off in the seat.

[0201] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism or the braking device based on the vehicle interior / exterior information acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control instruction to the system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), such as collision avoidance or shock reduction of the vehicle, following driving based on the vehicle-to-vehicle distance, speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0202] In addition, the microcomputer 12051 can perform collaborative control aimed at autonomous driving, which is used to perform automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040 without depending on the driver's operation.

[0203] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the exterior of the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030 or the like.

[0204] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device that can visually or acoustically notify information to a passenger of the vehicle or outside the vehicle. Fig. 22 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0205] Fig.23 This is a diagram illustrating an example of the installation position of the camera unit 12031.

[0206] exist Fig.23 In the figure, the vehicle 12100 includes cameras 12101, 12102, 12103, 12104 and 12105 as the camera unit 12031.

[0207] For example, the camera units 12101, 12102, 12103, 12104 and 12105 are installed at locations such as the front nose, rearview mirror, rear bumper and rear door of the vehicle 12100 and the upper part of the windshield inside the cab. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield inside the cab mainly acquire images in front of the vehicle 12100. The camera units 12102 and 12103 arranged at the rearview mirror mainly acquire images on both sides of the vehicle. The camera unit 12104 arranged at the rear bumper or rear door mainly acquires images at the rear of the vehicle 12100. The images in front acquired by the camera units 12101 and 12105 are mainly used to detect vehicles in front, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0208] Notice, Fig.23 Depicted are examples of imaging ranges of the imaging units 12101 to 12104. An imaging range 12111 shows an imaging range of the imaging unit 12101 disposed at the front nose, imaging ranges 12112 and 12113 respectively show imaging ranges of the imaging units 12102 and 12103 disposed at the rearview mirror, and an imaging range 12114 shows an imaging range of the imaging unit 12104 disposed at the rear bumper or the rear door. For example, by superimposing image data obtained by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 observed from the upper side is obtained.

[0209] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a three-dimensional camera formed by a plurality of imaging devices or may be an imaging device including pixels for detecting phase differences.

[0210] For example, the microcomputer 12051 can obtain the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, so that the three-dimensional object that is the closest three-dimensional object and is traveling at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100 on the driving path of the vehicle 12100 can be extracted as the leading vehicle. In addition, the microcomputer 12051 can pre-set the inter-vehicle distance maintained in front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control of automatic driving intended for autonomous driving of the vehicle without relying on the operation of the driver, etc. can be performed.

[0211] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and extract the three-dimensional object based on the distance information acquired by the camera units 12101 to 12104, and use the extracted three-dimensional objects to automatically avoid the obstacle object. For example, the microcomputer 12051 classifies the obstacles around the vehicle 12100 into obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult to be visually recognized by the driver. Then, the microcomputer 12051 determines the collision risk for indicating the degree of risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering through the drive system control unit 12010. Thus, the microcomputer 12051 can perform driving assistance to avoid collision.

[0212] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 may identify a pedestrian by determining whether the pedestrian exists in the captured images acquired by the camera units 12101 to 12104. This recognition of the pedestrian is performed, for example, by the following process: a process for extracting feature points in the captured images of the camera units 12101 to 12104 as infrared imagers; and a process for determining whether it is a pedestrian by pattern matching a series of feature points representing the contour of the object. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the camera units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a square outline for emphasis to be superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so as to display an icon or the like representing the pedestrian at a desired position.

[0213] So far, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above-mentioned structure. Thus, for example, the layout of the camera unit 12031 in the vehicle control system 12000 can be facilitated, thereby being able to simplify the layout of the camera unit 12031 and suppress the influence of noise. Therefore, for example, the performance of the imaging unit 12031 can be improved. This allows the vehicle control system 12000 to improve the accuracy of the vehicle's collision avoidance or collision mitigation function, the following driving function based on the distance between vehicles, the vehicle speed maintenance driving function, the vehicle's collision warning function, the vehicle's lane departure warning function, and the like.

[0214] So far, the present technology has been described with reference to some embodiments and their modified examples; however, the present technology is not limited to these embodiments and the like, and various modifications can be made.

[0215] For example, in the above-mentioned embodiments, the plurality of light receiving elements 31 in the pixel array are arranged on the semiconductor substrate 110, and the other elements and circuits in the pixel array other than the light receiving elements 31 are arranged on the semiconductor substrate 120; however, the configuration is not limited thereto. Alternatively, for example, the plurality of light receiving elements 31 and the plurality of resistance elements 32 in the pixel array may be arranged on the semiconductor substrate 110.

[0216] In addition, for example, in each of the above-mentioned embodiments, the time measurement device outputs the measurement result of the time measurement unit 24 as it is; however, the operation is not limited to this. Hereinafter, this is described in detail by citing an example in which this modification is applied to the time measurement unit 1H of the time measurement unit 1 according to the above-mentioned first embodiment. The time measurement unit 1H includes a time measurement device 20H and a controller 14H.

[0217] Fig.24 An example of the construction of a time measurement device 20H is shown. The time measurement device 20H has a histogram generator 25H. The histogram generator 25H has a plurality of histogram generation circuits 26 (in this example, N histogram generation circuits 26 (1) to 26 (N)). The histogram generation circuit 26 collects a plurality of count values ​​CNT1 included in a signal S3 of each pixel in a single row of pixels 30 based on a control signal CTRL2, and generates a histogram of the count values ​​CNT1 of each pixel 30. Subsequently, the histogram generation circuit 26 outputs the count value CNT1 of each pixel 30 having the highest frequency in the histogram using a signal S4.

[0218] When generating a histogram of the count value CNT1, the histogram generating circuit 26 can generate a histogram of the count value CNT1 by using, for example, the delay time ( Fig. 9 ) to correct the count value CNT1 obtained by the time measurement operation ( Figure 6 ) to generate a histogram using the corrected count values.

[0219] In this example, the present modification is applied to the time measurement unit 1 according to the above-mentioned first embodiment; however, this is not restrictive. For example, the present modification may be applied to the time measurement unit 1E according to the above-mentioned first embodiment ( Fig.12 In this case, when generating a histogram of the count value CNT1, the histogram generating circuit 26 may generate a histogram of the count value CNT1 by using, for example, the delay time ( Fig.14 ) to correct the pass time measurement operation ( Figure 6 ) to generate a histogram using the count value CNT1 obtained by the correction.

[0220] Furthermore, for example, the present modification example can be applied to the time measurement unit 2 according to the above-described second embodiment.

[0221] In addition, for example, in each of the above-described embodiments, a single photon avalanche diode (SPAD) is used to configure a pixel; however, for example, a backside illumination pixel may be used as such a pixel. Fig.25 An example of a backside illuminated pixel (pixel 230) is shown. Referring to the lower side of the figure, in pixel 230, SPAD 221 is arranged on an on-chip lens 223; a sensor substrate 241 is arranged on SPAD 221; and further, a circuit substrate 242 is arranged on sensor substrate 241. Light enters on-chip lens 223 (lower side of the figure) to enter SPAD 221.

[0222] The SPAD 221 has an N-type semiconductor layer 201 , a P-type semiconductor layer 202 , a well 203 , an anode 205 , and a hole storage layer 207 .

[0223] The N-type semiconductor layer 201 is a semiconductor layer having a high impurity concentration and an N-type conductivity type including, for example, silicon (Si). The P-type semiconductor layer 202 is a semiconductor layer having a high impurity concentration and a P-type conductivity type. The N-type semiconductor layer 201 and the P-type semiconductor layer 202 form a PN junction in the interface surface. The P-type semiconductor layer 202 is arranged below the N-type semiconductor layer 201. The N-type semiconductor layer 201 and the P-type semiconductor layer 202 are arranged in a well 203. The P-type semiconductor layer 202 has a multiplication region that performs avalanche multiplication of carriers generated by light incidence. Preferably, the P-type semiconductor layer 202 is depleted, which ensures that the photon detection efficiency (PDE: Photon Detection Efficiency) is improved.

[0224] The well 203 may be a semiconductor layer having N-type conductivity or a semiconductor layer having P-type conductivity. In addition, the impurity concentration in the well 203 is preferably, for example, 1E14 or less. This can promote depletion of the well 203, thereby allowing improvement of PDE.

[0225] The N-type semiconductor layer 201 serves as a cathode to be coupled to a circuit through a contact 204. The anode 205 is coupled to a circuit through a contact 206. The anode 205 is an N-type semiconductor layer identical to the n-type semiconductor layer 201, and is disposed between the N-type semiconductor layer 201 and a separation layer 208. Each of the contacts 204 and 206 includes a metal material such as copper (Cu) and aluminum (Al).

[0226] The hole storage layer 207 is a semiconductor layer having a P-type conductivity type. The hole storage layer 207 is arranged below the anode 205 between the separation layer 208 and the well 203, and is electrically coupled to the anode 205. The hole storage layer 207 is arranged at a contact portion where materials of different qualities contact each other. In other words, in the example shown, the separation layer 208 includes, for example, a silicon oxide film different from the constituent material of the well 203. Therefore, the hole storage layer 207 is used to suppress the dark current generated at the interface between the separation layer 208 and the well 203. In addition, the hole storage layer 207 is also arranged on the lower side of the well 203 (on the back side of the SPAD 221). In other words, the hole storage layer 207 is also arranged between the on-chip lens 223 and the well 203.

[0227] The separation layer 208 is arranged between adjacent SPADs 221 to separate the corresponding SPADs 221. The formation of the multiplication region corresponding to each SPAD 221 is thereby achieved in a one-to-one correspondence. The separation layer 208 is arranged in a two-dimensional dot pattern around the periphery of each multiplication region (SPAD 221). As shown in the figure, the separation layer 208 is arranged to penetrate from the top surface of the well 203 to the bottom surface in the stacking direction. It should be noted that in addition to the configuration of completely penetrating from the bottom surface to the bottom surface, a configuration in which the separation layer 208 is only partially penetrated to the middle position of the substrate or any other configuration is also allowed.

[0228] It should be noted that the effects described herein are merely exemplary and non-limiting, and the effects of the present invention may be other effects, or may further include other effects.

[0229] It should be noted that the present technology can be configured as follows.

[0230] (1) A time measuring device comprising:

[0231] a plurality of pixels arranged side by side in a first direction, each pixel including a single photon avalanche diode arranged on a first semiconductor substrate and generating a first logic signal depending on a detection timing in the single photon avalanche diode; and

[0232] a time measuring section disposed on a second semiconductor substrate combined with the first semiconductor substrate and measuring the detection time of each of the plurality of pixels,

[0233] wherein each pixel among the plurality of pixels except a first pixel arranged at one end in the first direction generates an output signal based on an output signal of a pixel except the pixel and based on the first logic signal generated in the pixel, and

[0234] The time measurement section measures the detection timing of each of the plurality of pixels based on an output signal of a second pixel arranged at the other end in the first direction among the plurality of pixels.

[0235] (2) A time measurement device according to (1), wherein each pixel among the plurality of pixels except the first pixel includes a first logic circuit, the first logic circuit is arranged in the second semiconductor substrate and has a first input terminal, a second input terminal and an output terminal, the first input terminal receives an output signal of a pixel other than the pixel, and the second input terminal receives the first logic signal.

[0236] (3) The time measurement device according to (1) or (2), further comprising a control signal generator disposed on the second semiconductor substrate and generating a plurality of first control signals corresponding to the plurality of pixels,

[0237] Wherein, each pixel of the plurality of pixels comprises:

[0238] a second logic circuit disposed on the second semiconductor substrate and generating a second logic signal based on a corresponding first control signal among the plurality of first control signals and based on a signal depending on a light reception result of the single photon avalanche diode of the pixel, and

[0239] A third logic circuit is disposed on the second semiconductor substrate and generates the first logic signal by performing a trigger operation based on the second logic signal.

[0240] (4) The time measurement device according to (3), further comprising a waveform shaping section that generates a pulse signal based on a transition of the output signal of the second pixel,

[0241] Here, the time measurement unit measures the detection time based on the pulse signal.

[0242] (5) The time measurement device according to (1) or (2), further comprising a control signal generator disposed on the second semiconductor substrate and generating a plurality of first control signals corresponding to the plurality of pixels,

[0243] Wherein, each of the multiple pixels includes a second logic circuit, which is arranged on the second semiconductor substrate, and the second logic circuit generates the first logic signal based on a corresponding first control signal among the multiple first control signals and based on a signal depending on the light reception result of the single photon avalanche diode of the pixel.

[0244] (6) The time measurement device according to any one of (1) to (5), wherein the time measurement unit further includes:

[0245] counter; and

[0246] A latch latches a count value of the counter based on the output signal of the second pixel.

[0247] (7) The time measurement device according to any one of (1) to (6), wherein the first pixel generates the output signal of the first pixel based on a third logic signal and based on the first logic signal generated in the first pixel.

[0248] (8) The time measurement device according to (7), wherein, in a case where the third logic signal is changed, the time measurement section measures a delay time from each pixel to the time measurement section based on the output signal of the second pixel.

[0249] (9) The time measurement device according to (8), wherein the time measurement section corrects a measurement result of the detection timing of each of the plurality of pixels based on a measurement result of the delay time.

[0250] (10) The time measurement device according to (1) or (2), further comprising a control signal generator disposed on the second semiconductor substrate and generating a plurality of first control signals corresponding to the plurality of pixels,

[0251] Wherein, each pixel of the plurality of pixels comprises:

[0252] a fourth logic circuit disposed on the second semiconductor substrate and generating a second logic signal based on a corresponding first control signal among the plurality of first control signals, based on a second control signal and based on a signal depending on a light reception result of the single photon avalanche diode of the pixel; and

[0253] A third logic circuit is disposed on the second semiconductor substrate and generates the first logic signal by performing a trigger operation based on the second logic signal.

[0254] (11) A time measurement device according to (10), wherein, when the second control signal is used to change the first logic signal of a third pixel among the plurality of pixels, the time measurement unit measures a delay time from the third pixel to the time measurement unit based on the output signal of the second pixel.

[0255] (12) The time measurement device according to (11), wherein the time measurement section corrects a measurement result of the detection timing of the third pixel based on a measurement result of the delay time.

[0256] (13) The time measurement device according to any one of (1) to (12), wherein the number of the plurality of pixels is 200 or more.

[0257] (14) A time measuring device comprising:

[0258] a plurality of pixels arranged side by side in a first direction, each pixel including a light receiving element and generating a first logic signal depending on a detection timing in the light receiving element; and

[0259] a time measuring unit that measures the detection time of each of the plurality of pixels,

[0260] wherein each pixel among the plurality of pixels except a first pixel arranged at one end in the first direction generates an output signal based on an output signal of a pixel except the pixel and based on the first logic signal generated in the pixel, and

[0261] The time measurement section measures the detection timing of each of the plurality of pixels based on an output signal of a second pixel arranged at the other end in the first direction among the plurality of pixels.

[0262] (15) A time measurement device according to (14), wherein each of the plurality of pixels includes a first logic circuit having a first input terminal, a second input terminal and an output terminal, the first input terminal receiving an output signal of a pixel other than the pixel, and the second input terminal receiving the first logic signal.

[0263] (16) The time measurement device according to (14) or (15), further comprising a control signal generator that generates a plurality of first control signals corresponding to the plurality of pixels,

[0264] Wherein, each pixel of the plurality of pixels comprises:

[0265] a second logic circuit that generates a second logic signal based on a corresponding first control signal among the plurality of first control signals and based on a signal depending on a light reception result of the light receiving element of the pixel, and

[0266] A third logic circuit generates the first logic signal by performing a trigger-type operation based on the second logic signal.

[0267] (17) The time measurement device according to (14) or (15), further comprising a control signal generator that generates a plurality of first control signals corresponding to the plurality of pixels,

[0268] Each of the plurality of pixels comprises a second logic circuit, which generates the first logic signal based on a corresponding first control signal among the plurality of first control signals and based on a signal depending on a light reception result of the light receiving element of the pixel.

[0269] (18) The time measurement device according to any one of (14) to (17), wherein the light receiving element is a single photon avalanche diode or an avalanche photodiode.

[0270] (19) A time measuring device comprising:

[0271] a first pixel, a second pixel, and a third pixel, each of which includes a single photon avalanche diode disposed on a first semiconductor substrate and generates a first logic signal depending on a detection timing in the single photon avalanche diode; and

[0272] a time measuring section disposed on a second semiconductor substrate combined with the first semiconductor substrate and measuring the detection time of each of the first pixel, the second pixel, and the third pixel,

[0273] wherein the second pixel generates an output signal based on the output signal of the first pixel and based on the first logic signal generated in the second pixel,

[0274] wherein the third pixel generates an output signal based on the output signal of the second pixel and based on the first logic signal generated in the third pixel, and

[0275] The time measurement unit measures the detection time of each of the first pixel, the second pixel, and the third pixel based on the output signal of the third pixel.

[0276] (20) A time measurement unit, comprising:

[0277] a light emitting portion, the light emitting portion emitting light;

[0278] a reflector that reflects reflected light corresponding to the light;

[0279] a plurality of pixels arranged side by side in a first direction, each pixel including a single-photon avalanche diode arranged on a first semiconductor substrate and detecting the reflected light reflected by the reflector, and each pixel generating a first logic signal depending on a detection timing in the single-photon avalanche diode; and

[0280] a time measuring section disposed on a second semiconductor substrate combined with the first semiconductor substrate and measuring the detection time of each of the plurality of pixels,

[0281] wherein each pixel among the plurality of pixels except a first pixel arranged at one end in the first direction generates an output signal based on an output signal of a pixel except the pixel and based on the first logic signal generated in the pixel, and

[0282] The time measurement section measures the detection timing of each of the plurality of pixels based on an output signal of a second pixel arranged at the other end in the first direction among the plurality of pixels.

[0283] (21) A time measurement unit, comprising:

[0284] a light emitting portion, the light emitting portion emitting light;

[0285] a reflector that reflects reflected light corresponding to the light;

[0286] a plurality of pixels arranged side by side in a first direction, each pixel including a light receiving element detecting the reflected light reflected by the reflecting mirror, and each pixel generating a first logic signal depending on a detection timing in the light receiving element; and

[0287] a time measuring unit that measures the detection time of each of the plurality of pixels,

[0288] wherein each pixel among the plurality of pixels except a first pixel arranged at one end in the first direction generates an output signal based on an output signal of a pixel except the pixel and based on the first logic signal generated in the pixel, and

[0289] The time measurement section measures the detection timing of each of the plurality of pixels based on an output signal of a second pixel arranged at the other end in the first direction among the plurality of pixels.

[0290] (22) A time measurement unit, comprising:

[0291] a light emitting portion, the light emitting portion emitting light;

[0292] a reflector that reflects reflected light corresponding to the light;

[0293] a first pixel, a second pixel, and a third pixel, each of which includes a single-photon avalanche diode disposed on a first semiconductor substrate and detecting the reflected light reflected by the reflector, and generating a first logic signal depending on a detection timing in the single-photon avalanche diode; and

[0294] a time measuring section disposed on a second semiconductor substrate combined with the first semiconductor substrate and measuring the detection time of each of the first pixel, the second pixel, and the third pixel,

[0295] wherein the second pixel generates an output signal based on the output signal of the first pixel and based on the first logic signal generated in the second pixel,

[0296] wherein the third pixel generates an output signal based on the output signal of the second pixel and based on the first logic signal generated in the third pixel, and

[0297] The time measurement unit measures the detection time of each of the first pixel, the second pixel, and the third pixel based on the output signal of the third pixel.

[0298] This application claims the benefit of Japanese Patent Application No. 2017-190304 filed with the Japan Patent Office on September 29, 2017, the entire contents of which are hereby incorporated by reference into this application.

[0299] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made according to design requirements or other factors without departing from the scope of the appended claims or the equivalents thereof.

Claims

1. A light detection device, comprising: A plurality of pixels arranged in rows and columns, a first pixel of the plurality of pixels comprising: a first avalanche photodiode; and an inverter coupled to an anode or a cathode of the first avalanche photodiode; a pixel control circuit configured to output a pixel control signal; and a logic circuit configured to receive the pixel control signal and a signal output by the inverter of the first pixel, The logic circuit includes a first logic circuit and a second logic circuit, the first logic circuit receives a logic signal based on a signal output by the inverter of the first pixel, and the second logic circuit receives the pixel control signal.

2. The light detection device according to claim 1, wherein: The logic circuit includes a third logic circuit, the third logic circuit is a trigger circuit, and wherein, The second logic circuit receives the signal output by the inverter of the first pixel and outputs a second logic signal, and the third logic circuit receives the second logic signal and outputs a first logic signal, wherein the first logic signal is the logic signal based on the signal output by the inverter of the first pixel.

3. The light detection device according to claim 1, wherein: The plurality of pixels further includes a second pixel that is adjacent to the first pixel in a row direction. 4 . The light detection device according to claim 3 , further comprising another logic circuit configured to receive a signal output by the inverter of the second pixel.

5. The light detection device according to claim 4, wherein: An output of the first logic circuit is coupled to an input of the further logic circuit.

6. The light detection device according to claim 1, wherein: The first avalanche photodiode is in a first substrate, and the inverter is in a second substrate.

7. The light detection device according to claim 1, wherein: The first pixels are arranged at an edge of a row.

8. A light detection device, comprising: A plurality of pixels arranged in rows and columns, the plurality of pixels including a first pixel and a second pixel, the first pixel and the second pixel being disposed adjacent to each other in a first row, the first pixel and the second pixel comprising: Avalanche photodiodes; and an inverter coupled to an anode or a cathode of the avalanche photodiode; and a pixel control circuit, the pixel control circuit being configured to output a pixel control signal, a logic circuit configured to receive the pixel control signal, the logic signal output by the first pixel, and the signal output by the inverter of the second pixel, The logic circuit includes a first logic circuit and a second logic circuit, the first logic circuit receives a logic signal output by the first pixel and receives a logic signal based on a signal output by the inverter of the second pixel, and the second logic circuit receives the pixel control signal.

9. The light detection device according to claim 8, wherein: The logic circuit further includes a third logic circuit, which is a trigger circuit, and wherein, The second logic circuit receives the signal output by the inverter of the second pixel and outputs a second logic signal, and the third logic circuit receives the second logic signal and outputs a first logic signal, wherein the first logic signal is the logic signal based on the signal output by the inverter of the second pixel.

10. The light detection device according to claim 8, wherein: The avalanche photodiode is in a first substrate and the inverter is in a second substrate.

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