Radio frequency system switching power amplifier system and method

Abstract

The present invention provides a radio frequency system switching power amplifier system and method. One embodiment describes a radio frequency system, which is configured to facilitate wireless communication of data between electronic devices, and the radio frequency system includes a first switching power amplifier and a second switching power amplifier. The first switching power amplifier includes a first output terminal and a first transistor. The first output terminal is configured to output a positive amplified analog electrical signal based at least in part on a positive input analog electrical signal and an envelope voltage. The first transistor is configured to supply electrical energy including a first leakage current to the first output terminal based at least in part on the positive input analog electrical signal in response to the envelope voltage being lower than a threshold range. The second switching power amplifier includes a second transistor. The second transistor is configured to supply electrical energy including a second leakage current to the first output terminal based at least in part on the negative input analog electrical signal in response to the envelope voltage being lower than a threshold range, so that the first leakage current and the second leakage current are substantially offset.

Description

[0001] This application is a divisional application of the invention patent application with application number 201680008043.1, application date February 24, 2016, and name “RF system switching power amplifier system and method”. Technical Field

[0002] The present disclosure relates generally to radio frequency systems, and more particularly to switching power amplifiers used in radio frequency systems. Background Art

[0003] This section is intended to introduce the reader to various aspects of the prior art that may be related to various aspects of the present disclosure that are described below and / or protected by the claims. We believe that this discussion is helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Therefore, it should be understood that these text descriptions are to be read in this sense, and not as admissions of prior art.

[0004] Many electronic devices may include a radio frequency system to facilitate wireless communication of data with another electronic device and / or a network. The radio frequency system may include a transceiver that outputs an analog representation of the data as an analog electrical signal, which may then be transmitted wirelessly via an antenna. Because electronic devices may be separated by a certain distance, the radio frequency system may include an amplifier component for controlling the output power of the radio frequency system (e.g., the strength of the analog electrical signal).

[0005] In some embodiments, the amplifier component may include a switching (e.g., Class D) power amplifier that utilizes one or more transistors as electronic switches. In some embodiments, the switching power amplifier may amplify an input analog electrical signal to a desired output power. More specifically, the switching power amplifier may amplify an input analog electrical signal at least in part based on the input analog electrical signal by connecting an output terminal to an envelope voltage (e.g., V env ) power rail or ground to generate an amplified analog electrical signal.

[0006] Ideally, a switching power amplifier should achieve high power efficiency (e.g., output power / DC power consumption), linearly regulate the output power of an amplified analog electrical signal, and maintain a constant phase shift between an input analog electrical signal and an amplified output analog electrical signal. However, in actual operation, transistors typically have parasitic capacitances, which may cause the transistors to conduct leakage current from their gates to their drains. In fact, such leakage currents may affect the power efficiency of the switching power amplifier, the linearity of the regulation of the output power, and / or the constancy of the phase shift between the input analog electrical signal and the amplified output analog electrical signal. Summary of the invention

[0007] The following describes a summary of certain embodiments disclosed herein. It should be understood that these aspects are presented only to provide the reader with a concise summary of these specific embodiments, and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may cover a number of aspects that may not be described below.

[0008] The present disclosure generally relates to improving the operation of a switching (e.g., Class D) power amplifier used in a radio frequency system. Typically, a switching power amplifier receives an input analog electrical signal and outputs an amplified analog electrical signal, which can then be wirelessly transmitted to another electronic device or network. More specifically, the switching power amplifier can connect an output terminal to an envelope voltage (e.g., V env ) power rail or ground to generate an amplified analog electrical signal.

[0009] However, each of the transistors generally has a parasitic capacitance, which enables leakage current to flow from the gate of the transistor through the transistor and to its drain. Therefore, especially when the output power of the amplified analog electrical signal is low, the leakage current may limit the minimum output power, thereby reducing the linearity of the regulation of the output power and / or making the phase shift between the input analog electrical signal and the output analog electrical signal non-constant.

[0010] Thus, the techniques described herein can improve the operation of a switching power amplifier by improving the linearity of the regulation of the output power and / or the constancy of the phase shift between the input electrical signal and the output electrical signal. In some embodiments, when the RF system utilizes a positive analog electrical signal (e.g., +V 输入 ) and negative analog electrical signals (e.g., -V 输入 ), the first switching power amplifier may be included in a first branch receiving a positive analog electrical signal, and the second switching power amplifier may be included in a second branch receiving a negative analog electrical signal.

[0011] More specifically, each switching power amplifier may include a first p-type metal oxide semiconductor (PMOS) transistor and a first n-type metal oxide semiconductor (NMOS) transistor, the first PMOS transistor having a voltage level electrically coupled to an envelope voltage (eg, V env ) power rail, a gate electrically coupled to an input analog electrical signal, and a drain electrically coupled to an output terminal of the switching power amplifier, the first NMOS transistor having a source electrically coupled to a ground portion, a gate electrically coupled to an input analog electrical signal, and a drain electrically coupled to the output terminal. In addition, each switching power amplifier may include a second NMOS transistor having a gate electrically coupled to the input electrical signal, a drain electrically coupled to the envelope voltage power rail, and a source electrically coupled to the output terminal of the switching amplifier of the opposite branch.

[0012] Thus, during operation, when the output power is low due to the voltage on the envelope voltage power rail being below a threshold range (e.g., a voltage between the magnitude of the threshold voltage of the PMOS transistor and the voltage of the input analog electrical signal (when high) minus the threshold voltage of the NMOS transistor), each switching power amplifier can be operated as a dual NMOS inverter (e.g., a first NMOS transistor coupled in parallel with a second NMOS transistor from an opposite branch). In this way, because the NMOS transistors share a common output node and input an inverted (e.g., opposite) analog electrical signal, leakage currents flowing through the NMOS transistors can be canceled out. In this way, the linearity of the regulation of the output power and / or the constancy of the phase shift between the input analog electrical signal and the output analog electrical signal (particularly at low output power) can be improved.

[0013] However, due to the higher drive voltage of NMOS transistors compared to PMOS transistors, the dual NMOS architecture may result in higher DC power consumption at high output power. Accordingly, since linearity and / or phase shift are less affected by leakage current at high output power (e.g., envelope voltage is greater than a threshold), each switching power amplifier may operate as an NMOS / PMOS inverter (e.g., a first NMOS transistor coupled in parallel with a first PMOS transistor) when the output power is high due to the voltage on the envelope voltage power rail being higher than a threshold range. In addition, when the voltage on the envelope voltage power rail is within the threshold range, each switching power amplifier may operate as a parallel dual NMOS inverter and an NMOS / PMOS inverter. In this way, the power consumption of the switching power amplifier may also be reduced, thereby improving the efficiency (e.g., output power / DC power consumption) of the RF system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various aspects of the present disclosure may be better understood by reading the following detailed description and referring to the accompanying drawings, in which:

[0015] Figure 1 is a block diagram of an electronic device having a radio frequency system according to an embodiment;

[0016] Figure 2 According to the implementation plan Figure 1 Examples of electronic devices;

[0017] Figure 3 According to the implementation plan Figure 1 Examples of electronic devices;

[0018] Figure 4 According to the implementation plan Figure 1 Examples of electronic devices;

[0019] Figure 5 According to the implementation plan Figure 1 Block diagram of the RF system;

[0020] Figure 6 According to the implementation plan Figure 5 A schematic diagram of amplifier components used in a radio frequency system;

[0021] Figure 7 According to the implementation plan Figure 6 A schematic diagram of one embodiment of a switching power amplifier used in an amplifier component of;

[0022] Fig. 8A According to the implementation plan Figure 7 Schematic diagram of a switching power amplifier when the envelope voltage is high;

[0023] Figure 8B According to the implementation plan Figure 7 Schematic diagram of a switching power amplifier when the envelope voltage is low;

[0024] Fig. 9 is a flow chart describing a process for operating a switching power amplifier according to an embodiment;

[0025] Fig.10 is a flow chart describing a process for assembling a switching power amplifier according to an embodiment;

[0026] Fig.11 According to the implementation plan Figure 6 A schematic diagram of another embodiment of a switching power amplifier used in an amplifier component of;

[0027] Fig. 12A According to the implementation plan Fig.11 Schematic diagram of a switching power amplifier when the envelope voltage is high;

[0028] Fig. 12B According to the implementation plan Fig.11 Schematic diagram of a switching power amplifier when the envelope voltage is low;

[0029] Fig.13 According to the implementation plan Fig.11 A graph of output power and phase shift as a function of envelope voltage in a switching power amplifier;

[0030] Fig.14 According to the implementation plan Fig.11 A graph of the current in a transistor in a switching power amplifier as a function of the envelope voltage;

[0031] Fig.15 is the voltage at different envelopes according to the implementation scheme. Fig.11 A graph of an amplified analog electrical signal output by a switching power amplifier;

[0032] Fig.16 According to the implementation plan Fig.11 A graph of power dissipation and efficiency as a function of envelope voltage in a switching power amplifier. DETAILED DESCRIPTION

[0033] One or more specific embodiments of the present disclosure will be described below. These described embodiments are merely examples of the presently disclosed technology. In addition, in order to provide a concise description of these embodiments, all features of the actual specific implementation may not be described in this specification. It should be recognized that in the development of any such actual implementation, as in any engineering or design project, decisions specific to many specific implementations must be made to achieve the developer's specific goals, such as compliance with system-related constraints and transaction-related constraints that may vary with the specific implementation. In addition, it should be understood that such development efforts may be complex and time-consuming, but for ordinary technicians who benefit from this disclosure, it may still be a routine task of design, manufacture and production.

[0034] When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Furthermore, it should be understood that reference to "one embodiment" or "an embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0035] As described above, an electronic device may include a radio frequency system to facilitate wireless transmission of data with another electronic device and / or a network. More specifically, the radio frequency system may modulate radio waves to enable the electronic device to communicate via a personal area network (e.g., a Bluetooth network), a local area network (e.g., an 802.11x Wi-Fi network), and / or a wide area network (e.g., a 4G or LTE cellular network). In other words, the radio frequency system may utilize various wireless communication protocols to facilitate the transmission of data.

[0036] However, regardless of the wireless communication protocol used, the radio frequency system can generally be similar in operation. For example, to transmit data, the processing circuit can generate a digital representation of the data as a digital electrical signal, and the transceiver (e.g., a transmitter and / or a receiver) can then convert the digital electrical signal into one or more analog electrical signals. Based on various factors (e.g., wireless communication protocol, power consumption, distance, etc.), the analog electrical signal can be wirelessly transmitted at different output powers. To facilitate control of the output power, the radio frequency system can include an amplifier component that receives the analog electrical signal and outputs an amplified analog electrical signal at a desired output power for transmission via an antenna.

[0037] In some embodiments, the amplifier component may include one or more switching (e.g., Class D) power amplifiers that utilize multiple transistors to generate an amplified analog electrical signal. More specifically, the switching power amplifier may generate an analog electrical signal based on an input analog electrical signal by connecting an output terminal to an envelope voltage (e.g., V env ) power rail or ground to generate an amplified analog electrical signal. For example, when the input analog electrical signal is low (e.g., zero volts), the switching power amplifier may turn on the first transistor and turn off the second transistor to connect the output to the envelope voltage power rail. On the other hand, when the input signal is high (e.g., a positive voltage), the switching amplifier may turn off the first transistor and turn on the second transistor to connect the output to the ground.

[0038] In this way, the output power of the amplified analog electrical signal can be controlled by adjusting the envelope voltage. Therefore, in order to facilitate the control of the output power, it may be desirable that the output power of the amplified analog electrical signal varies proportionally with the magnitude of the envelope voltage. In other words, it may be desirable that the output power varies linearly with the envelope voltage. In addition, it may be desirable that the phase shift between the amplified analog electrical signal and the input signal is relatively constant regardless of the output power.

[0039] In theory, the transistor will operate as an electronic switch by disconnecting the power supply when off and connecting the power supply when on. However, in real-world situations, the transistor typically has parasitic capacitance, which allows leakage current to conduct from the gate of the transistor through the transistor and flow to its drain. In other words, the operation of the transistor may deviate from the operation of an ideal switch. In fact, leakage current can affect the linearity (e.g., amplitude output / amplitude input) and phase shift of the switching power amplifier, especially at low output power (e.g., envelope voltage is below a threshold range). For example, when the switching power amplifier includes only a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor coupled in parallel, the leakage current in the transistor can impose a lower limit on the output power of the switching power amplifier, thereby reducing linearity and causing the phase shift to vary significantly with output power (e.g., 100 degrees).

[0040] Thus, the techniques described in this embodiment can improve the operation of the radio frequency system by improving the control of the output power and the constancy of the phase shift in the switching power amplifier. For example, some embodiments of the radio frequency system utilize a differential scheme. In such embodiments, the first switching power amplifier can be included in receiving a positive analog electrical signal (e.g., +V 输入 ) in the first branch, and the second switching power amplifier may be included in receiving a negative analog electrical signal (eg, -V 输入 ). More specifically, each switching power amplifier may include a first p-type metal oxide semiconductor (PMOS) transistor and a first n-type metal oxide semiconductor (NMOS) transistor, the first PMOS transistor having an envelope voltage (e.g., V env ) power rail, a gate electrically coupled to the input analog electrical signal, and a drain electrically coupled to the output terminal of the switching power amplifier, the first NMOS transistor having a source electrically coupled to the ground, a gate electrically coupled to the input analog electrical signal, and a drain electrically coupled to the output terminal. In addition, each switching power amplifier may include a second NMOS transistor having a gate electrically coupled to the input analog electrical signal, a drain electrically coupled to the envelope voltage power rail, and a source electrically coupled to the output terminal of the switching power amplifier in the opposite branch.

[0041] Therefore, during operation, when the output power is low (e.g., the envelope voltage is below the threshold range), the switching power amplifier may connect the first NMOS transistor of one branch in parallel with the second NMOS transistor of the other branch. In other words, the switching power amplifier may operate as two dual NMOS inverters. More specifically, in each dual NMOS inverter, the first NMOS transistor and the second NMOS transistor receive inverted (e.g., opposite) input analog signals at their respective gates. In this way, because the NMOS transistors share a common output node and are provided with an inverted input analog electrical signal, the leakage current flowing through the first NMOS transistor and the second NMOS transistor can be offset. In this way, the linearity of the adjustment made to the output power, the constancy of the phase shift between the input analog electrical signal and the output analog electrical signal (especially at low output power), or both can be improved.

[0042] On the other hand, during operation, when the output power is high (e.g., the envelope voltage is above a threshold range), the switching power amplifier may connect the first NMOS transistor and the first PMOS transistor of the branch in parallel. In other words, the switching power amplifier may operate as two NMOS / PMOS inverters. More specifically, since the first PMOS can use a lower driving voltage than the NMOS transistor, the power consumption of the switching power amplifier can be reduced. In addition, since the output power is high, the effect of the leakage current on the amplified analog electrical signal may be small, and therefore, the linearity and / or phase shift may not be significantly affected. In this way, the techniques described herein may improve the operation of the RF system (e.g., improving the control of the output power and the constancy of the phase shift in the switching power amplifier) ​​while also reducing power consumption (e.g., improving power efficiency).

[0043] To help illustrate, Figure 1 An electronic device 10 that may utilize a radio frequency system 12 is described in . As will be described in more detail below, the electronic device 10 may be any suitable electronic device, such as a handheld computing device, a tablet computing device, a laptop computer, or the like.

[0044] Thus, as shown, electronic device 10 includes a radio frequency system 12 , input structures 14 , memory 16 , one or more processors 18 , one or more storage devices 20 , a power source 22 , input / output ports 24 , and an electronic display 26 . Figure 1 The various components described may include hardware elements (including circuits), software elements (including computer code stored on non-transitory computer-readable media), or a combination of hardware elements and software elements. It should be noted that Figure 1 This is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device 10. Additionally, it should be noted that the various components shown may be combined into fewer components or separated into additional components. For example, memory 16 and storage device 20 may be included in a single component.

[0045] As shown, the processor 18 is operably coupled to the memory 16 and the storage device 20. More specifically, the processor 18 may execute instructions stored in the memory 16 and / or the storage device 20 to perform operations in the electronic device 10, such as directing the radio frequency system 12 to communicate with another device. As such, the processor 18 may include one or more general-purpose microprocessors, one or more application-specific processors (ASICs), one or more field programmable logic arrays (FPGAs), or any combination thereof. In addition, the memory 16 and / or the storage device 20 may be a tangible, non-transitory computer-readable medium that stores instructions that can be executed by the processor 18 and data that can be processed by the processor 18. For example, the memory 16 may include a random access memory (RAM), and the storage device 20 may include a read-only memory (ROM), a rewritable flash memory, a hard drive, an optical disk, and the like.

[0046] In addition, as shown in the figure, the processor 18 is operably coupled to a power supply 22, which provides power to various components in the electronic device 10. For example, the power supply 22 can provide direct current (DC) electricity to the radio frequency system 12. Therefore, the power supply 22 may include any suitable energy source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter. In addition, as shown in the figure, the processor 18 is operably coupled to an I / O port 24, which enables the electronic device 10 to interact with various other electronic devices, and the processor is operably coupled to an input structure 14, which enables a user to interact with the electronic device 10. Therefore, the input structure 14 may include buttons, keyboards, mice, trackpads, etc. In addition, in some embodiments, the electronic display 26 may include a touch-sensitive component.

[0047] In addition to enabling user input, the electronic display 26 can display image frames, such as, static images, video content, or a graphical user interface (GUI) application interface for an operating system. As shown, the display can be operatively coupled to the processor 18. Therefore, the image frames displayed by the electronic display 26 can be based on the display image data received from the processor 18.

[0048] As shown, the processor 18 is also operably coupled to the RF system 12, which can facilitate the communication coupling of the electronic device 10 to one or more other electronic devices and / or networks. For example, the RF system 12 can enable the electronic device 10 to be communicatively coupled to a personal area network (PAN), such as a Bluetooth network, a local area network (LAN) (such as an 802.11x Wi-Fi network), and / or a wide area network (WAN) (such as a 4G or LTE cellular network). It will be appreciated that the RF system 12 can implement communications using various communication protocols and / or varying output power (e.g., the strength of the transmitted analog electrical signal).

[0049] For each communication protocol (e.g., Bluetooth, LTE, 802.11x Wi-Fi, etc.), the operating principles of the radio frequency system 12 can be similar. More specifically, as will be described in more detail below, the radio frequency system 12 can use a transceiver to convert a digital electrical signal containing data desired to be transmitted into an analog electrical signal. The radio frequency system 12 can then use an amplifier component to amplify the analog electrical signal to a desired output and use one or more antennas to output the amplified analog signal. In other words, the techniques described herein can be applied to any suitable radio frequency system 12, which operates in any suitable manner regardless of the communication protocol used.

[0050] As mentioned above, electronic device 10 may be any suitable electronic device. To aid in illustration, Figure 2 An example of a handheld device 10A is described, which may be a portable telephone, a media player, a personal data organizer, a handheld gaming platform, or any combination of such devices. For example, the handheld device 10A may be a smartphone, such as any of the smartphones available from Apple Inc. As shown, the handheld device 10A includes a housing 28 that can protect the internal components from physical damage and shield the internal components from electromagnetic interference. The housing 28 can surround the electronic display 26, which, in the illustrated embodiment, displays a graphical user interface (GUI) 30 having an array of icons 32. For example, when an icon 32 is selected through the input structure 14 or a touch sensing component of the electronic display 26, an application can be launched.

[0051] In addition, as shown in the figure, the input structure 14 can be opened by a housing (e.g., shell) 28. As described above, the input structure 14 can enable a user to interact with the handheld device 10A. For example, the input structure 14 can activate or deactivate the handheld device 10A, navigate the user interface to the home screen, navigate the user interface to the user-configurable application screen, activate the voice recognition feature, provide volume control, and switch between a vibration mode and a ringing mode. In addition, as shown in the figure, the I / O port 24 is opened by the housing 28. In some embodiments, the I / O port 24 may include, for example, an audio jack connected to an external device. In addition, the radio frequency system 12 may also be enclosed in the housing 28 and be located inside the handheld device 10A.

[0052] To further illustrate a suitable electronic device 10, Figure 3 Tablet device 10B is described in In addition, in other embodiments, the electronic device 10 may adopt Figure 4The computer 10C may be in the form of any computer 10C available from Apple Inc. or As shown, the tablet device 10B and the computer 10C also include a display 26, an input structure 14, an I / O port 24, and a housing (e.g., a casing) 28. Similar to the handheld device 10A, the radio frequency system 12 may also be enclosed in the housing 28 and located inside the tablet device 10B and / or the computer 10C.

[0053] As described above, the radio frequency system 12 can facilitate communication with other electronic devices and / or networks by transmitting data wirelessly. To help illustrate, Figure 5 1 and 2. As shown, portion 34 includes a digital signal generator 36, a transceiver 38, an amplifier component 40, one or more filters 42, and an antenna 44. The digital signal generator 36 can generate a digital representation of data desired to be transmitted from the electronic device 10 by outputting a digital electrical signal. Thus, in some embodiments, the digital signal generator 36 may include the processor 18 and / or a separate processing circuit, such as a baseband processor or modem in the RF system 12.

[0054] The transceiver 38 can then receive the digital electrical signal and generate an analog representation of the data. In some embodiments, the transceiver 38 can generate an analog representation of the digital electrical signal by outputting an envelope voltage (e.g., V env ) to generate an analog representation to indicate the desired output power of the RF system 12 and one or more analog electrical signals (e.g., +V 输入 and -V 输入 ), thereby indicating the phase of the digital electrical signal (e.g., high or low). For example, when the desired output is 20 dBm, the transceiver 38 may output an envelope voltage of 1.2 volts. In addition, when the digital electrical signal is high (e.g., "1"), the transceiver 38 outputs an analog electrical signal with a positive voltage, and when the digital electrical signal is low (e.g., "0"), the transceiver 38 may output an analog electrical signal of zero volts.

[0055] Additionally, in some embodiments, transceiver 38 may use a differential scheme, thereby generating a positive analog electrical signal (eg, +V 输入 ) and negative analog electrical signals (e.g., -V 输入). More specifically, instead of generating a single analog electrical signal, the transceiver may generate a positive analog electrical signal and a negative analog electrical signal such that they are in antiphase with each other and their magnitudes are equal to half the magnitude of the single analog electrical signal. In other words, when the digital electrical signal is high (e.g., "1"), the positive analog electrical signal may have a positive voltage and the negative analog electrical signal may be zero volts. On the other hand, when the digital electrical signal is low (e.g., "0"), the positive analog electrical signal may have zero volts and the negative analog electrical signal may be a positive voltage.

[0056] Since the output power of the analog electrical signal may be small, the amplifier component 40 may receive and amplify the analog electrical signal by outputting the amplified analog electrical signal. For example, when receiving a positive analog electrical signal and a negative analog electrical signal, the amplifier component 40 may output the amplified positive analog electrical signal (e.g., +V 输出 ) and amplified negative analog electrical signals (e.g., -V 输出 ). It can be understood that the amplified positive analog electrical signal and the amplified negative analog signal can also be inverted to each other.

[0057] In addition, the amplifier component 40 can change the magnitude of the amplified analog electrical signal so that the output power of the RF system 12 can be adjusted. As will be described in more detail below, the amplifier component 40 may include one or more switching power amplifiers having one or more transistors. In such embodiments, the switching power amplifier can connect the output of the switching power amplifier to an envelope voltage (e.g., V) based on the input analog electrical signal received from the transceiver 38 by turning the transistor on and off. env ) power rail or ground to generate an amplified analog electrical signal, for example, when the positive analog electrical signal is high and the negative analog electrical signal is low, the amplified positive analog electrical signal may be an envelope voltage, and the amplified negative analog electrical signal may be zero volts. On the other hand, when the positive analog electrical signal is low and the negative analog electrical signal is high, the amplified positive analog electrical signal may be zero volts, and the amplified negative analog electrical signal may be an envelope voltage.

[0058] It is understood that noise, such as parasitic noise or out-of-band noise, may be introduced by the transceiver 38 and / or the amplifier component 40. Therefore, one or more filters 42 may remove the introduced noise from the amplified analog electrical signal and output a filtered analog electrical signal. The filtered analog electrical signal may then be wirelessly transmitted as a modulated radio wave via an antenna 44 to another electronic device and / or a network.

[0059] As described above, the amplifier component 40 may include one or more switching power amplifiers to facilitate controlling the magnitude of the amplified analog electrical signal and, therefore, the output power of the RF system 12. To aid in illustration, Figure 6A more detailed view of the amplifier component 40 is described in FIG. In the illustrated embodiment, the amplifier component 40 utilizes a differential scheme and includes an envelope voltage amplifier 46 that receives a positive analog electrical signal +V 输入 The first branch 48 receives the negative analog electrical signal -V 输入 The second branch 50.

[0060] As shown, the envelope voltage amplifier 46 includes a power rail 54, a transistor 56, a capacitor 58, and a capacitor 59 for receiving the envelope voltage V from the transceiver 38. env The operational amplifier 52 of FIG. 4 is connected to the envelope voltage amplifier 46. In the illustrated embodiment, the envelope voltage amplifier 46 is connected in a negative feedback loop. More specifically, the operational amplifier 52 can receive the envelope voltage at its inverting input terminal and receive the output voltage of the envelope amplifier 46 (e.g., the voltage at the output terminal 60) at its non-inverting input terminal. Therefore, the operational amplifier 52 can amplify the difference between the output voltage filtered by the capacitor 58 and the envelope voltage.

[0061] Additionally, in the illustrated embodiment, transistor 56 has a gate connected to the output of operational amplifier 52, a source connected to power rail 54, and a drain connected to output 60 of envelope voltage amplifier 46. More specifically, a power source (such as power supply 22) can supply direct current to power rail 54, such that power rail 54 has a voltage V DD Thus, transistor 56 can selectively connect output terminal 60 to power rail 54 based on the difference between the output voltage and the envelope voltage. In this manner, envelope voltage amplifier 46 can output power to first branch 48 and second branch 50 at approximately the envelope voltage.

[0062] As shown, each branch 48 or 50 includes one or more primary (e.g., driving) power amplifiers (e.g., inverters) 62 and a switching power amplifier 64. More specifically, during operation, the one or more primary power amplifiers 62 can each amplify (e.g., increase the magnitude of) the received analog electrical signal to a voltage sufficient to drive the switching power amplifier 64. The switching power amplifiers 64 can then each amplify the received analog electrical signal to a desired output power based at least in part on the power output from the envelope voltage amplifier 46. For example, in the illustrated embodiment, the first branch 48 can output an amplified positive analog electrical signal +V 输出 , and the second branch 50 can output an amplified negative analog electrical signal -V 输出 .

[0063] The amplified analog electrical signal may then be received by a load 66 (such as filter 42 and / or antenna 44) for transmission. Thus, when the RF system 12 utilizes a differential scheme, the amplified positive analog electrical signal and the amplified negative analog electrical signal may be combined into a single amplified analog electrical signal via transformer 68.

[0064] As described above, switching power amplifiers 64A and 64B can output amplified analog electrical signals at a desired output power based at least in part on the envelope voltage. To help illustrate, Figure 7 A more detailed view of the first switching power amplifier 64A in the first branch 48 and the second switching power amplifier 64B in the second branch 50 is described in FIG. As shown, the first switching power amplifier 64A receives a positive analog electrical signal (e.g., +V 输入 ), the second switching power amplifier 64B receives a negative analog electrical signal (eg, -V 输入 ), and both switching power amplifiers 64A and 64B are coupled in parallel between the envelope voltage supply rail 70 and the ground 72. More specifically, the envelope voltage amplifier 46 operates with the envelope voltage (V env ) supplies power to the envelope voltage rail.

[0065] In addition, as shown, the switching power amplifiers 64A and 64B each include a first PMOS transistor 74, a first NMOS transistor 76, a second PMOS transistor 78, a second NMOS transistor 80, and a metering (e.g., smoothing filter) component including a capacitor 82 and an inductor 84 connected in series. More specifically, the first PMOS transistor 74 and the first NMOS transistor 76 are coupled in parallel such that the source of the first PMOS transistor 74 is electrically coupled to the envelope voltage power rail 70, the source of the first NMOS transistor 76 is electrically coupled to the ground 72, the drain is electrically coupled to the metering component, and the gate is electrically coupled to the input analog electrical signal. In addition, the second NMOS transistor 80 and the second PMOS transistor 78 are coupled in parallel such that the drain of the second NMOS transistor 80 is electrically coupled to the envelope voltage power rail 70, the drain of the second PMOS transistor 78 is electrically coupled to the ground 72, the source is electrically coupled to the metering component of the opposite branch, and the gate is electrically coupled to the input analog electrical signal. Furthermore, in some embodiments, NMOS transistors 76 and 80 may have substantially the same operating characteristics (e.g., parasitic capacitance and / or leakage current), and PMOS transistors 74 and 78 may have substantially the same operating characteristics (e.g., parasitic capacitance and / or leakage current) to facilitate reducing the effects of leakage current.

[0066] During operation, the switching power amplifiers 64A and 64B can act as NMOS / PMOS inverters when the envelope voltage is above the threshold range; can act as dual NMOS inverters when the envelope voltage is below the threshold range; and can act as a combined inverter (e.g., a dual NMOS inverter coupled in parallel with an NMOS / PMOS inverter) when the envelope voltage is within the threshold range. In some embodiments, the threshold range may include a voltage between the threshold voltage of the PMOS transistors (e.g., 74 and 78) and the voltage of the input analog electrical signal (when high) (e.g., the drive voltage of the primary amplifier 62) minus the threshold voltage of the NMOS transistors (e.g., 76 and 80). To help illustrate, Fig. 8A describes the envelope voltage (e.g., V env高 ) is above the threshold range, and Figure 8B describes the envelope voltage (e.g., V env低 ) below a threshold range.

[0067] like Fig. 8A As shown, when the envelope voltage is higher than the threshold range, the second NMOS transistor 80 and the second PMOS transistor 78 may be maintained in the cut-off state. More specifically, the NMOS transistors 76 and 80 may have a voltage greater than the input analog electrical signal (eg, +V 输入 or –V 输入 ) voltage and the envelope voltage (for example, V env高 ). In other words, when the input analog electrical signal is low, the second NMOS transistor 80 can be turned off because the gate voltage is approximately zero volts. In addition, even when the input analog electrical signal is high, the second NMOS transistor 80 can be kept turned off because the difference between the gate voltage (e.g., the voltage of the input analog electrical signal) and the source voltage (e.g., the envelope voltage) is less than the threshold voltage of the second NMOS transistor 80.

[0068] In addition, PMOS transistors 74 and 78 may have a voltage greater than the envelope voltage (eg, V env高 ) and the voltage of the received analog electrical signal. In other words, when the received analog electrical signal is high, the second PMOS transistor 78 can be turned off because the gate voltage is the positive voltage of the received analog electrical signal. In addition, even if the received analog electrical signal is low, the second PMOS transistor 78 can be kept turned off because both the gate voltage and the source voltage are approximately zero volts.

[0069] Therefore, when the envelope voltage is higher than the threshold range, the switching power amplifiers 64A and 64B can operate as NMOS / PMOS inverters, wherein the first PMOS transistor 74 and the first NMOS transistor 76 are coupled in parallel. More specifically, in each of the switching power amplifiers 64A and 64B, when the analog electrical signal (e.g., +V 输入 or –V 输入 ) is high, the first PMOS transistor 74 may be turned off and the first NMOS transistor 76 may be turned on, thereby connecting the output terminal to the ground. On the other hand, when the received analog electrical signal is low, the first NMOS transistor 76 may be turned off and the first PMOS transistor 74 may be turned on, thereby connecting the output terminal to the envelope voltage supply rail 70.

[0070] In this manner, the first switching power amplifier 64A outputs an amplified positive analog electrical signal +V at a desired output power (eg, based at least in part on the envelope voltage). 输出 , and the second switching power amplifier 64B outputs the amplified negative analog electrical signal -V with the desired output power 输出 In addition, since the switching power amplifiers 64A and 64B generate amplified analog electrical signals (eg, +V 输出 and -V 输出 ), so the amplified analog electrical signals can also be inverted to each other.

[0071] On the other hand, Figure 8B As shown, when the envelope voltage is lower than the threshold range, the first PMOS transistor 74 and the second PMOS transistor 78 can be maintained in the off state. As described above, the threshold range can be a voltage between the magnitude of the threshold voltage of the first PMOS transistor 74 and the voltage of the input analog electrical signal (when high) minus the threshold voltage of the NMOS transistors 76 and 80. Therefore, when the input analog electrical signal is high, the first PMOS transistor 74 and the second PMOS transistor 78 can be turned off because the gate voltage is the positive voltage of the input analog electrical signal. In addition, even when the input analog electrical signal is low, since the difference between the source voltage (e.g., the envelope voltage) and the gate voltage (e.g., zero volts) is less than the threshold voltage of the PMOS transistors 74 and 78, the first PMOS transistor 74 and the second PMOS transistor 78 can be maintained off.

[0072] Therefore, when the envelope voltage is below the threshold range, the switching power amplifiers 64A and 64B can operate as dual NMOS inverters, where the first NMOS transistor 76 is coupled in parallel with the second NMOS transistor of the opposite branch. More specifically, when the input analog electrical signal (e.g., +V 输入 or -V 输入) is high, the first NMOS transistor 76 may be turned on, and the second NMOS transistor 80 of the opposite branch may be turned off, thereby connecting the output terminal to the ground. On the other hand, when the received analog electrical signal is low, the first NMOS transistor 76 may be turned off, and the second NMOS transistor 80 of the opposite branch may be turned on, thereby connecting the output terminal to the envelope voltage power supply rail 70.

[0073] In addition, since the switching power amplifiers 64A and 64B are operated as dual NMOS inverters, the effects of leakage current can be reduced. More specifically, as described above, each transistor typically has a parasitic capacitance that enables leakage current to flow. For example, in the illustrated embodiment, a first leakage current can flow through the first PMOS transistor 74A and the first NMOS transistor 76A in the first switching power amplifier 64A, and a second leakage current can flow through the second PMOS transistor 78B and the second NMOS transistor 80B in the second switching power amplifier 64B, both of which can be supplied to the amplified positive analog electrical signal +V 输出 .

[0074] In general, the amount of leakage current conducted by a transistor may be based at least in part on the parasitic capacitance of the transistor. Thus, since the parasitic capacitance across the first PMOS transistor 74A and the first NMOS transistor 76A is substantially the same as the parasitic capacitance across the second NMOS transistor 80B and the second PMOS transistor 78B, the magnitude of the first leakage current and the second leakage current are approximately the same. In addition, since the input analog electrical signal (e.g., +V 输入 and -V 输入 ) are in anti-phase with each other, so the phases of the first leakage current and the second leakage current may also be in anti-phase with each other (for example, opposite), so that the two cancel each other out.

[0075] Similarly, in the illustrated embodiment, the third leakage current may flow through the first PMOS transistor 74B and the first NMOS transistor 76B of the second switching power amplifier 64B, and the fourth leakage current may flow through the second PMOS transistor 78A and the second NMOS transistor 80A of the first switching power amplifier, both of which may be supplied to the amplified negative analog electrical signal -V 输出 However, due to the input analog electrical signal (for example, -V 输入 and +V 输入 ) are inverted to each other and the parasitic capacitances are approximately equal, so the third leakage current and the fourth leakage can also be offset.

[0076] In this manner, the switching power amplifiers 64A and 64B can be operated to reduce the effects of leakage current, particularly when the output power is low (e.g., below the output power threshold range), thereby improving the linearity of the output power control and the constancy of the phase shift between the input analog electrical signal and the output analog electrical signal. In addition, the switching power amplifiers 64A and 64B can be operated to reduce the DC power consumption supplied from the power supply 22, particularly when the output power is high (e.g., above the output power threshold range), thereby improving the efficiency of the RF system 12 (e.g., output power / DC power consumption).

[0077] To further illustrate, Fig. 9 One embodiment of a process 86 for operating a switching power amplifier 64 is described in . In general, the process includes determining an envelope voltage (process box 88); determining whether the envelope voltage is less than a threshold range (decision box 90); using a dual NMOS inverter when the envelope voltage is less than the threshold range (process box 92); determining whether the envelope voltage is greater than the threshold range when the envelope voltage is not less than the threshold range (decision box 94); using an NMOS / PMOS inverter when the envelope voltage is greater than the threshold range (process box 96); and using a combination of a dual NMOS inverter and an NMOS / PMOS inverter when the threshold voltage is not greater than the threshold range (process box 100). In some embodiments, process 86 may be implemented using instructions stored in memory 16 and / or another suitable tangible, non-transitory computer-readable medium and executable by processor 18 and / or another suitable processing circuit.

[0078] Thus, the RF system 12 may determine the envelope voltage (process block 88). In some embodiments, the RF system 12 may poll the transceiver 38 for an envelope voltage output that is used to generate the desired output power. Additionally or alternatively, the RF system 12 may include one or more sensors (e.g., voltage sensors) that measure the voltage output of the transceiver and / or the voltage on the envelope voltage supply rail 70.

[0079] The RF system 12 may then determine whether the envelope voltage is less than a threshold range (decision block 90). In some embodiments, the threshold range may include voltages between the threshold voltage of the PMOS transistors (e.g., 74 and 78) and the voltage of the input analog electrical signal (when high) minus the threshold voltage of the NMOS transistors (e.g., 76 and 80). Additionally, in some embodiments, the threshold range may be predetermined and stored in the memory 16 and / or storage device 20. Thus, in such embodiments, the RF system 12 may retrieve the threshold range and compare it to the envelope voltage.

[0080] When the envelope voltage is less than the threshold range, the RF system 12 may operate the switching power amplifier 64 as a dual NMOS inverter (process block 92). More specifically, the RF system 12 may maintain the first PMOS transistor 74 and the second PMOS transistor 78 in an off state. In addition, the RF system 12 may connect the first NMOS transistor 76 of one branch in parallel with the second NMOS transistor 80 of the other branch. As described above, the dual NMOS inverter may allow leakage current to be canceled, thereby improving linearity and / or phase shift constancy, especially at low output power (e.g., low envelope voltage).

[0081] On the other hand, when not less than the threshold range, the RF system 12 may determine whether the envelope voltage is greater than the threshold range (decision box 94). When the envelope voltage is greater than the threshold range, the RF system 12 may operate the switching power amplifier 64 as an NMOS / PMOS inverter (process box 96). More specifically, the RF system 12 may maintain the second PMOS transistor 78 and the second NMOS transistor 80 in an off state. In addition, the RF system 12 may connect the first PMOS transistor 74 and the first NMOS transistor 76 of each branch in parallel. As described above, the use of NMOS / PMOS inverters can reduce power consumption, thereby improving power efficiency, especially at high output power (e.g., high envelope voltage).

[0082] In addition, when not greater than and not less than a threshold range, the RF system may operate the switching power amplifier 64 as a dual NMOS inverter coupled in parallel with an NMOS / PMOS inverter (process block 100). As described above, the threshold may be a voltage range between the magnitude of the threshold voltage of the first PMOS transistor 74 and the voltage of the input analog electrical signal (when high) minus the threshold voltages of the NMOS transistors 76 and 80. Thus, when the envelope voltage is within the threshold range, the transistor may be in a region where the transistor is partially turned on.

[0083] In this way, the RF system 12 can operate the switching power amplifier 64 using a combination of the first PMOS transistor 74, the first NMOS transistor 76, and the second NMOS transistor 80. In other words, each switching power amplifier 64 can output an amplified analog electrical signal based at least in part on the current conducted by the first PMOS transistor 74 of the branch and the current conducted by the second NMOS transistor 80 of the opposite branch. In fact, as will be described in more detail below, the first PMOS transistor 74 and the second NMOS transistor 80 can be selected so that the sum of the output currents varies linearly with the envelope voltage even within the threshold range.

[0084] Thus, the techniques described herein describe a switching power amplifier 64 that may be used to improve the operation of the radio frequency system 12 . Fig.10 One embodiment of a process 102 for manufacturing a pair of switching power amplifiers (e.g., 64A and 64B) is described in . Generally, process 102 includes forming a first switching power amplifier (process block 104) and forming a second switching power amplifier (process block 106). In some embodiments, process 102 can be implemented by a manufacturer using instructions stored on any suitable tangible, non-transitory computer-readable medium and executable by any suitable processing circuit.

[0085] Thus, the manufacturer may form a first switching power amplifier (process block 104), which includes forming a first PMOS transistor (process block 108), forming a first NMOS transistor (process block 110), forming a second NMOS transistor (process block 112), and optionally forming a second PMOS transistor (process block 114). In some embodiments, the manufacturer may form a first PMOS transistor (e.g., first PMOS transistor 74A) and a first NMOS transistor (e.g., first NMOS transistor 76A) in a first switching power amplifier (e.g., switching power amplifier 64A) such that they are coupled in parallel. More specifically, the first PMOS transistor 74 may be formed such that its source may be electrically coupled to an envelope voltage (e.g., V env ) power rail 70, whose gate may be electrically coupled to an analog electrical signal (eg, +V 输入 ), and its drain can be electrically coupled to the output terminal of the first switching power amplifier (eg, +V 输出 ), and the first NMOS transistor 76 can be formed so that its source can be electrically coupled to the ground portion 72, its gate can be electrically coupled to the analog electrical signal input to the first switching power amplifier, and its drain can be electrically coupled to the output terminal of the first switching power amplifier.

[0086] In addition, a second NMOS transistor (e.g., second NMOS transistor 80A) may be formed in the first switching power amplifier so that its gate may be electrically coupled to the analog electrical signal input to the first switching power amplifier, its drain may be electrically coupled to the envelope voltage power rail 70, and its source may be electrically coupled to the output of the second switching power amplifier. In addition, a second PMOS transistor (e.g., second PMOS transistor 78A) may be formed so that it is coupled in parallel with the second NMOS transistor 80. More specifically, the second PMOS transistor 78 may be formed in the first switching power amplifier so that its gate may be electrically coupled to the analog electrical signal input to the first switching power amplifier, its drain may be electrically coupled to the ground 72, and its source may be electrically coupled to the output of the second switching power amplifier.

[0087] It should be noted that Figure 7For the embodiments of the switching power amplifiers 64A and 64B described in the above, the second PMOS transistor 78 is usually maintained in the off state. In fact, as will be described in detail below, even if the second PMOS transistor 78 is omitted, the influence of leakage current can still be reduced. In this way, the second PMOS transistor 78 can be optionally formed in the first switching power amplifier.

[0088] Similar to the first switching power amplifier, the manufacturer may form a second switching power amplifier (process block 106), which includes forming a first PMOS transistor (process block 116), forming a first NMOS transistor (process block 118), forming a second NMOS transistor (process block 120), and optionally forming a second PMOS transistor (process block 122). In some embodiments, the manufacturer may form a first PMOS transistor (e.g., first PMOS transistor 74B) and a first NMOS transistor (e.g., first NMOS transistor 76B) in the second switching power amplifier (e.g., switching power amplifier 64B) so that they are coupled in parallel. More specifically, the first PMOS transistor 74 may be formed so that its source may be electrically coupled to an envelope voltage (e.g., V env ) power rail 70, whose gate may be electrically coupled to an analog electrical signal (eg, -V 输入 ), and its drain can be electrically coupled to the output terminal of the second switching power amplifier (eg, -V 输出 ), and the first NMOS transistor 76 can be formed so that its source can be electrically coupled to the ground portion 72, its gate can be electrically coupled to the analog electrical signal input to the second switching power amplifier, and its drain can be electrically coupled to the output terminal of the second switching power amplifier.

[0089] In addition, the second NMOS transistor (e.g., the second NMOS transistor 80B) may be formed so that its gate may be electrically coupled to the analog electrical signal input to the second switching power amplifier, its drain may be electrically coupled to the envelope voltage power rail 70, and its source may be electrically coupled to the output terminal of the first switching power amplifier. In addition, the second PMOS transistor (e.g., the second PMOS transistor 78B) may be formed so that it is coupled in parallel with the second NMOS transistor 80. More specifically, the second PMOS transistor 78 may be formed so that its gate may be electrically coupled to the analog electrical signal input to the second switching power amplifier, its drain may be electrically coupled to the ground portion 72, and its source may be electrically coupled to the output terminal of the first switching power amplifier.

[0090] In addition, as in the first switching power amplifier, a second PMOS transistor 78 may be optionally formed in the second switching power amplifier while still reducing the effects of leakage current. To help illustrate, Fig.11An embodiment of the switching power amplifier 64 without the second PMOS transistor 78 is described in FIG. Figure 7 In the embodiment described, the first switching power amplifier 64C receives the positive analog electrical signal +V 输入 , the second switching power amplifier 64D receives the negative analog electrical signal -V 输入 , and both switching power amplifiers 64C and 64D are coupled in parallel between the envelope voltage supply rail 70 and the ground 72 .

[0091] In addition, as shown, the first switching power amplifier 64C and the second switching power amplifier 64D each include a first PMOS transistor 74, a first NMOS transistor 76, a second NMOS transistor 80, and a metering component (e.g., a capacitor 82 and an inductor 84 connected in series). More specifically, the first PMOS transistor 74 and the first NMOS transistor 76 are coupled in parallel so that the source of the first PMOS transistor 74 is electrically coupled to the envelope voltage power rail 70, the source of the first NMOS transistor 76 is electrically coupled to the ground 72, the drain is electrically coupled to the metering component, and the gate is electrically coupled to the input analog electrical signal. In addition, the second NMOS transistor 80 is coupled so that the drain is electrically coupled to the envelope voltage power rail 70, the source is electrically coupled to the metering component of the opposite branch, and the gate is electrically coupled to the input analog electrical signal. In addition, the NMOS transistors 76 and 80 may have substantially the same operating characteristics (e.g., parasitic capacitance and / or leakage current).

[0092] Similar to Figure 7 In the embodiment described in , during operation, the switching power amplifiers 64C and 64D can act as NMOS / PMOS inverters when the envelope voltage is above the threshold range, can act as dual NMOS inverters when the envelope voltage is below the threshold range, and can act as a combination of inverters (e.g., an NMOS / PMOS inverter coupled in parallel with a dual NMOS inverter) when the envelope voltage is within the threshold range. To help illustrate, Fig. 12A describes the envelope voltage (e.g., V env高 ) is above the threshold range, and Fig. 12B describes the envelope voltage (e.g., V env低 ) below the threshold range.

[0093] like Fig. 12A As shown, when the envelope voltage is higher than the threshold range, the threshold voltage (eg, gate-to-source voltage) of the second NMOS transistor 80 is greater than the voltage of the input analog electrical signal (eg, +V 输入 or -V 输入 ) and the envelope voltage (e.g., V env高), and thus can be maintained in a cut-off state. In other words, when the input analog electrical signal is low, since the gate voltage is approximately zero volts, the second NMOS transistor 80 can be cut off. In addition, even when the input analog electrical signal is high, since the difference between the gate voltage (e.g., the voltage of the input analog electrical signal) and the source voltage (e.g., the envelope voltage) is less than the threshold voltage of the second NMOS transistor 80, the second NMOS transistor 80 can be maintained cut off.

[0094] Therefore, when the envelope voltage is above the threshold range, the switching power amplifiers 64C and 64D can operate as NMOS / PMOS inverters, in which the first PMOS transistor 74 and the first NMOS transistor 76 are coupled in parallel. More specifically, in each of the switching power amplifiers 64C and 64D, when the analog electrical signal (e.g., +V 输入 or –V 输入 ) is high, the first PMOS transistor 74 may be turned off and the first NMOS transistor 76 may be turned on, thereby connecting the output terminal to the ground. On the other hand, when the input analog electrical signal is low, the first NMOS transistor 76 may be turned off and the first PMOS transistor 74 may be turned on, thereby connecting the output terminal to the envelope voltage power rail 70. In this way, the first switching power amplifier 64C outputs the amplified positive analog electrical signal +V with the desired output power. 输出 , and the second switching power amplifier 64D outputs the amplified negative analog electrical signal -V with the desired output power 输出 .

[0095] On the other hand, Fig. 12B As shown, when the envelope voltage is lower than the threshold range, the first PMOS transistor 74 can be maintained in the off state. As described above, the threshold range can be a voltage between the magnitude of the threshold voltage of the first PMOS transistor 74 and the voltage of the input analog electrical signal (when high) minus the threshold voltages of the NMOS transistors 76 and 80. Therefore, when the input analog electrical signal is high, the first PMOS transistor 74 can be turned off because the gate voltage is the positive voltage of the input analog electrical signal. In addition, even when the input analog electrical signal is low, the first PMOS transistor 74 can be maintained off because the difference between the source voltage (e.g., envelope voltage) and the gate voltage (e.g., zero volts) is less than the threshold voltage of the first PMOS transistor 74.

[0096] Therefore, when the envelope voltage is below the threshold range, the switching power amplifiers 64D and 64D can operate as dual NMOS inverters, where the first NMOS transistor 76 is coupled in parallel with the second NMOS transistor 80 of the opposite branch. More specifically, when the input analog electrical signal (e.g., +V 输入 or -V输入 ) is high, the first NMOS transistor 76 may be turned on, and the second NMOS transistor 80 of the opposite branch may be turned off, thereby connecting the output terminal to the ground. On the other hand, when the input analog electrical signal is low, the first NMOS transistor 76 may be turned off, and the second NMOS transistor 80 of the opposite branch may be turned on, thereby connecting the output terminal to the envelope voltage power supply rail 70.

[0097] Furthermore, even if the switching power amplifiers 64C and 64D do not include the second PMOS transistor 78, the influence of the leakage current can still be reduced. For example, in the embodiment described, the first leakage current can flow through the first PMOS transistor 74C and the first NMOS transistor 76C in the first switching power amplifier 64C, and the second leakage current can flow through the second NMOS transistor 80D of the second switching power amplifier 64D, and both leakage currents can be supplied to the amplified positive analog electrical signal +V 输出 However, because the parasitic capacitance across the first PMOS transistor 74C and the first NMOS transistor 76C may be different than the parasitic capacitance across the second NMOS transistor 80D, the magnitudes of the first leakage current and the second leakage current may vary slightly and thus may not completely cancel. However, as will be shown in more detail below, any small amount of leakage current remaining may not significantly affect the operation of the switching power amplifiers 64C and 64D.

[0098] Similarly, in the illustrated embodiment, the third leakage current may flow through the first PMOS transistor 74D and the first NMOS transistor 76D of the second switching power amplifier 64D, and the fourth leakage current may flow through the second NMOS transistor 80C of the first switching power amplifier 64C, both of which may be supplied to the amplified negative analog electrical signal -V 输出 Because the parasitic capacitance across the first PMOS transistor 74D and the first NMOS transistor 76D may be different than the parasitic capacitance across the second NMOS transistor 80C, the magnitudes of the third leakage current and the fourth leakage current may vary slightly and thus may not completely cancel each other out. However, any small amount of leakage current remaining may not significantly affect the operation of the switching power amplifiers 64C and 64D.

[0099] To help illustrate, Fig.13 The output power of the amplified analog electrical signal and the phase shift between the input analog electrical signal and the output analog electrical signal of the switching power amplifiers 64C and 64D related to the envelope voltage are described. More specifically, Fig.13 Depicted is a graph including an output power curve 124 describing the output power of the amplified analog electrical signal and a phase shift curve 126 describing the phase shift between the input analog electrical signal and the output analog electrical signal.

[0100] As depicted by phase shift curve 126, the phase shift between the input analog electrical signal and the output analog electrical signal is relatively constant. In some embodiments, the phase shift may vary by a few degrees with the envelope voltage. However, such small amounts of phase shift may be accounted for in software in the RF system 12. In other words, any effect of the leakage current on the constancy of the phase shift between the input analog electrical signal and the output analog electrical signal may not significantly affect the operation of the switching power amplifier 64.

[0101] Furthermore, as depicted by output power curve 124, the output power of switching power amplifiers 64C and 64D varies relatively linearly from a minimum output power (when the envelope voltage is at a minimum envelope voltage) to a maximum output power (when the envelope voltage is at a maximum envelope voltage). In fact, even at low envelope voltages (e.g., at a minimum envelope voltage), the linearity of the variation in output power is maintained. In other words, any leakage current present does not significantly affect the linearity of the control of the output power of the amplified analog electrical signal.

[0102] As described above, the linearity of regulation of the output power can be improved by using a dual NMOS inverter when the envelope voltage is below a threshold range, using an NMOS / PMOS inverter when the envelope voltage is above the threshold range, and using a combined inverter (e.g., a dual NMOS inverter and an NMOS / PMOS inverter in parallel) when the envelope voltage is within the threshold range. To help illustrate, Fig.14 An example of current conducted by first NMOS transistor 76 and first PMOS transistor 74 in a first switching power amplifier (e.g., switching power amplifier 64C) and current conducted by second NMOS transistor 80 in a second switching power amplifier (e.g., switching power amplifier 64D) related to an envelope voltage is described.

[0103] More specifically, Fig.14 A graph including a first NMOS current curve 128, a PMOS current curve 130, and a second NMOS current curve 132 is depicted, wherein the first NMOS current curve describes the current conducted by the first NMOS transistor 76, the PMOS current curve describes the current conducted by the first PMOS transistor 74, and the second NMOS current curve describes the current conducted by the second NMOS transistor 80. Furthermore, since the first NMOS transistor 76 is turned on whenever the switching power amplifier 64 outputs an amplified analog electrical signal, the first NMOS current curve 128 may also describe the current output to the metering component.

[0104] In the illustrated embodiment, the threshold range may be between a lower threshold voltage and an upper threshold voltage. Thus, as shown, when the envelope voltage is less than the lower threshold voltage, the second NMOS transistor 80 is turned on to provide power while the first PMOS transistor 74 is turned off, thereby operating generally as a dual NMOS inverter. Additionally, when the envelope voltage is greater than the upper threshold voltage, the first PMOS transistor 74 is turned on to provide power while the second NMOS transistor 80 is turned off, thereby operating generally as an NMOS / PMOS inverter.

[0105] In addition, when the envelope voltage is between the lower threshold voltage and the higher threshold voltage, the first PMOS transistor 74 and the second NMOS transistor 80 can both be partially turned on to supply a portion of the power, thereby operating the switching power amplifier 64 as a combined inverter (e.g., a dual NMOS inverter and an NMOS / PMOS inverter in parallel). In fact, as shown, the linearity of the output power is generally maintained even when the envelope voltage is between the lower threshold voltage and the higher threshold voltage. Therefore, the transistors can be selected to provide a smooth gradual transition between operating the switching power amplifier 64 as a dual NMOS inverter and operating the switching power amplifier 64 as an NMOS / PMOS inverter within the threshold range.

[0106] To further illustrate the improved output power linearity, Fig.15 The amplified analog electrical signal (eg, output power) output from the switching power amplifier 64 when a squared analog electrical signal and a varying envelope voltage are input is described. More specifically, Fig.15A graph including the following curves is depicted: a first output curve 134 depicting the amplified analog electrical signal when the envelope voltage is a first (e.g., minimum) envelope voltage; a second output curve 136 depicting the amplified analog electrical signal when the envelope voltage is a second envelope voltage; a third output curve 138 depicting the amplified analog electrical signal when the envelope voltage is a third envelope voltage; a fourth output curve 140 depicting the amplified analog electrical signal when the envelope voltage is a fourth envelope voltage; a fifth output curve 142 depicting the amplified analog electrical signal when the envelope voltage is a fifth envelope voltage; a fifth output curve 143 depicting the amplified analog electrical signal when the envelope voltage is a sixth envelope voltage (e.g., a lower threshold voltage); and a fifth output curve 144 depicting the amplified analog electrical signal when the envelope voltage is a sixth envelope voltage (e.g., a lower threshold voltage). voltage); describes a sixth output curve 144 of the amplified analog electrical signal when the envelope voltage is a seventh envelope voltage; describes a seventh output curve 146 of the amplified analog electrical signal when the envelope voltage is a seventh envelope voltage; describes an eighth output curve 148 of the amplified analog electrical signal when the envelope voltage is an eighth envelope voltage (e.g., a higher threshold voltage); describes a ninth output curve 150 of the amplified analog electrical signal when the envelope voltage is a ninth envelope voltage; describes a tenth output curve 152 of the amplified analog electrical signal when the envelope voltage is a tenth envelope voltage; and describes an eleventh output curve 154 of the amplified analog electrical signal when the envelope voltage is an eleventh (e.g., maximum) envelope voltage.

[0107] As shown in output curves 134-154, even when the envelope voltage is low (e.g., minimum envelope voltage), the fidelity of the input analog electrical signal is maintained by the amplified analog electrical signal. In addition, when the envelope voltage is within the threshold range (e.g., between the lower threshold voltage and the upper threshold voltage), the fidelity of the input curve of the input analog electrical signal is also maintained by the amplified analog electrical signal. Therefore, the techniques described herein can reduce the impact of leakage current on the operation of the switching power amplifier 64, thereby improving linearity and phase shift.

[0108] In addition, as described above, the efficiency (e.g., output power / DC power consumption) of the RF system can also be improved by using a combination of dual NMOS inverters and NMOS / PMOS inverters. To help illustrate, Fig.16 The following items related to the envelope voltage are described: the DC power consumption of one or more power amplifiers (e.g., inverters) 62, the DC power consumption of the switching power amplifier 64, the total DC power consumption of the one or more primary power amplifiers 62 and the switching power amplifier 64, and the efficiency of the amplifier component 40. More specifically, Fig.16A graph is depicted including the following curves: a power amplifier power consumption curve 156 describing the DC power consumption of one or more primary power amplifiers 62; a switching power amplifier power consumption curve 158 describing the DC power consumption of the switching power amplifier 64; a total power consumption curve 160 describing the total DC power consumption of the one or more primary power amplifiers 62 and the switching power amplifier 64; and an efficiency curve 162 describing the efficiency of the amplifier component 40.

[0109] As depicted by the power amplifier power consumption curve 156, the DC power consumption of the one or more primary power amplifiers 62 remains relatively constant from the minimum envelope voltage to the maximum envelope voltage. In addition, as depicted by the switching power amplifier power consumption curve 158, the DC power consumption of the switching power amplifier 64 increases relatively linearly from the minimum envelope voltage to the maximum envelope voltage. Therefore, as depicted by the total power consumption curve 160, the total DC power consumption of the switching power amplifier 64 and the one or more primary power amplifiers 62 also increases relatively linearly from the minimum envelope voltage to the maximum envelope voltage.

[0110] Furthermore, as the envelope voltage increases (e.g., the output power continues to increase), the efficiency (e.g., output power / DC power consumption) also increases. In fact, as depicted by the efficiency curve 162, when the envelope voltage is below a lower threshold voltage (e.g., below a threshold range), the efficiency can increase at a slower rate, and when the envelope voltage is above a higher threshold voltage (e.g., above a threshold range), the efficiency can increase at a faster rate. More specifically, the difference in the efficiency increase process can be attributed to operating the switching power amplifier 64 as a dual NMOS inverter when below the threshold range, and operating the switching power amplifier 64 as an NMOS / PMOS inverter when above the threshold range. In this way, when the envelope voltage is at the maximum envelope voltage, the efficiency of the amplifier component 40 can reach 50.7%.

[0111] In fact, the efficiency of amplifier component 40 may be limited to 66% due to power dissipation in envelope voltage amplifier 46 and / or metering components such as capacitor 82 and inductor 84. Thus, the techniques described herein may enable one or more primary power amplifiers 62 and switching power amplifier 64 to achieve an efficiency of 76.81% relative to the maximum achievable efficiency.

[0112] Therefore, the technical effects of the present disclosure include improving the operation of a switching power amplifier used in a radio frequency system. More specifically, the switching power amplifier can be operated as a dual NMOS inverter when the desired output power is low (e.g., the envelope voltage is less than a threshold value) to improve the linearity of the adjustment made to the output power and the constancy of the phase shift between the input analog electrical signal and the output analog electrical signal, thereby reducing the impact of leakage current. In addition, the switching power amplifier can be operated as an NMOS / PMOS inverter when the desired output power is high (e.g., the envelope voltage is higher than a threshold range) to improve the efficiency of the radio frequency system, thereby reducing the power consumption of the switching power amplifier.

[0113] Specific embodiments have been described above by way of example, but it should be understood that these embodiments are susceptible to various modifications and alternative forms. It should also be understood that the claims are not intended to be limited to the specific forms disclosed, but are intended to cover all modifications, equivalents, and alternative forms that fall within the spirit and scope of the present disclosure.

Claims

1. A radio frequency system, the radio frequency system being configured to facilitate wireless communication of data between electronic devices, the radio frequency system comprising: a first switching power amplifier configured to output a positive amplified analog electrical signal based on a positive input analog electrical signal and an envelope voltage, the first switching power amplifier comprising a first transistor configured to supply the positive amplified analog electrical signal based at least in part on the positive input analog electrical signal in response to the envelope voltage being below a threshold range, the first transistor causing a first leakage current; as well as a second switching power amplifier, the second switching power amplifier comprising a second transistor configured to supply a negative amplified analog electrical signal based at least in part on a negative input analog electrical signal in response to the envelope voltage being below the threshold range, the second transistor causing a second leakage current that substantially cancels the first leakage current.

2. The radio frequency system according to claim 1, wherein: The negatively amplified analog electrical signal is the inversion of the positively amplified analog electrical signal.

3. The radio frequency system according to claim 1, wherein: The second switching power amplifier includes a third transistor configured to supply the second leakage current to the first switching power amplifier such that the second leakage current substantially cancels the first leakage current.

4. The radio frequency system according to claim 3, wherein: The third transistor includes a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor of the second switching power amplifier.

5. The radio frequency system according to claim 1, wherein: The first transistor includes a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor in the first switching power amplifier, and the second transistor includes the NMOS transistor in the second switching power amplifier.

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