A method and device for converting bus to USB

Abstract

The present invention belongs to the field of chip technology. The present invention provides a bus and USB conversion method and device. The method includes the following steps: when the bus of the chip system sends a command to an external model, the command is converted into a USB format command, so that the external model receives the USB format command through the USB; when the external model returns a USB format status word, the USB format status word is converted into a bus format status word, so that the bus receives the bus format status word. The present invention supports connecting with other hosts outside the chip through a USB interface, and communicates with a Matlab algorithm model, a C-based algorithm model, or a SystemC-based off-chip IP model located in an off-chip host by converting the bus access in the SOC or FPGA into USB data, so as to form a heterogeneous system of SOC or FPGA+off-chip IP.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a bus and USB conversion method and device. Background Art

[0002] When developing and designing SOC chips, it is usually necessary to conduct preliminary software and hardware system verification on the FPGA platform. For newly designed IP modules in the project, they are often first modeled and simulated using high-level simulation languages, such as algorithm simulation based on Matlab, algorithm simulation based on C, and TLM transaction-level simulation based on SystemC, and finally RTL code implementation and simulation verification. This makes it impossible to integrate new IP on the FPGA platform for software and hardware verification in the early stages, which will lead to longer project development time.

[0003] With the increasing complexity of electronic systems and the emergence of new technologies, it is becoming increasingly difficult to integrate all functional IPs within a SOC system, which makes the emergence of more heterogeneous systems possible. However, there is currently no IP that can support heterogeneous systems consisting of SOC or FPGA and off-chip models. Summary of the invention

[0004] The present invention provides a bus and USB conversion method and device to solve the above problems.

[0005] The technical solution provided by the present invention is as follows:

[0006] In one aspect, the present invention provides a method for converting a bus to a USB, comprising the steps of:

[0007] When the bus of the chip system sends a command to the external model, the command is converted into a command in USB format, so that the external model receives the command in USB format through USB;

[0008] When the external model returns a status word in USB format, the status word in USB format is converted into a status word in bus format, so that the bus receives the status word in bus format.

[0009] The USB format is a format that supports sending and receiving using USB.

[0010] Further preferably, when the bus of the chip system sends a command to the external model, the command is converted into a command in USB format so that the external model receives the command in USB format through USB, which specifically includes the steps of:

[0011] When the bus reads the register of the external model, the read command packet of the bus is written into a read command word for reading the register of the external model into a USB transmission buffer;

[0012] When the bus writes into the register of the external model, the write command of the bus is packaged into a write command word for writing into the register of the external model and written into the USB sending buffer.

[0013] Further preferably, when the bus of the chip system sends a command to the external model, the command is converted into a command in USB format so that the external model receives the command in USB format through USB, which specifically includes the steps of:

[0014] When the bus reads the data of the external model, the read command packet of the bus is written into the USB transmission buffer as a read command word for reading the data of the external model;

[0015] When the bus writes the data of the external model, the write command packet of the bus is converted into a write command word for writing the data of the external model and is written into the USB sending buffer.

[0016] Further preferably, when the bus reads the register of the external model, the read command packet of the bus is written into the USB send buffer as a read command word for reading the register of the external model, which specifically includes the steps of:

[0017] When the bus reads the register of the external model, receiving a read command of the bus, the read command including a read tag, a read address, and a read type;

[0018] The read command of the bus is converted into a read command in USB format and written into the USB sending buffer.

[0019] Further preferably, when the register of the external model returns a status word in USB format, converting the status word in USB format into a status word in bus format so that the bus receives the status word in bus format specifically comprises the steps of:

[0020] When the register of the external model returns a read status word in USB format through USB, the conversion module receives the status word into a receiving buffer, and converts the read status word into a read status word in bus format, so that the bus receives the read status word in bus format;

[0021] When the register of the external model returns a write status word in USB format through USB, the conversion module receives the status word into a receiving buffer and converts the write status word into a write status word in bus format so that the bus receives the write status word in bus format.

[0022] Further preferably, the bus and USB conversion method further comprises the steps of:

[0023] When receiving an interrupt command word sent by the external model through the USB, driving the interrupt signal to be valid, so that the chip system can receive the interrupt signal of the external model;

[0024] When the bus writes the interrupt clear register of the external model, the interrupt of the external model can be cleared.

[0025] A bus and USB conversion device, comprising:

[0026] A conversion module, used for converting a command into a USB format command when the bus of the chip system sends a command to the external model, so that the external model receives the USB format command through the USB;

[0027] The conversion module is further configured to convert the status word in USB format into a status word in bus format when the external model returns the status word in USB format, so that the bus receives the status word in bus format.

[0028] Further preferably, the conversion module is further used for:

[0029] When the bus reads the register of the external model, the read command packet of the bus is written into a read command word for reading the register of the external model into a USB transmission buffer;

[0030] When the bus writes into the register of the external model, the write command of the bus is packaged into a write command word for writing into the register of the external model and written into the USB sending buffer.

[0031] When the external model returns a status word in USB format via USB, the conversion module receives the status word into a receiving buffer and converts the status word into a status word in bus format, so that the bus receives the read / write status word in the bus format.

[0032] Further preferably, the conversion module is further used for:

[0033] When the bus reads the data of the external model, the read command packet of the bus is written into the USB transmission buffer as a read command word for reading the data of the external model;

[0034] When the bus writes the data of the external model, the write command packet of the bus is converted into a write command word for writing the data of the external model and is written into the USB sending buffer.

[0035] When the external model returns a status word in USB format via USB, the conversion module receives the status word into a receiving buffer and converts the status word into a status word in bus format, so that the bus receives the read / write status word in the bus format.

[0036] Further preferably, the bus and USB conversion device further includes:

[0037] An interrupt module, used for driving an interrupt signal to be effective when receiving an interrupt command word sent by the external model through the USB, so that the chip system receives the interrupt signal of the external model through the interrupt module;

[0038] The interrupt module is further used to clear the interrupt of the external model when the bus writes the interrupt clear register of the external model.

[0039] The present invention provides a bus-to-USB conversion method and device, which has at least the following beneficial effects:

[0040] 1) The present invention supports connection with other off-chip hosts through a USB interface, and communicates with a Matlab algorithm model, a C-based algorithm model, or a SystemC-based off-chip IP model located in an off-chip host by converting bus access in the SOC or FPGA into USB data, thereby forming a heterogeneous system of SOC or FPGA+off-chip IP.

[0041] 2) By using block mode to process data, IP design is simplified and data transmission efficiency is improved.

[0042] 3) After the IP for bus-USB conversion is integrated in the SOC or FPGA system, it can be combined with the off-chip software model system, thus significantly expanding the application scope of SOC and FPGA. Compared with heterogeneous systems that are directly connected to the off-chip host via USB, there is no need to develop USB drivers in the SOC / FPGA, and the software is simpler.

[0043] 4) The off-chip model can send interrupts, interrupt status register data and data to the chip. It can support multiple off-chip models at the same time; the software in the SOC or FPGA can access the IP model in the external host just like accessing the IP on the internal bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments:

[0045] Figure 1 It is a flow chart of an embodiment of a bus-to-USB conversion method of the present invention;

[0046] Figure 2 It is a flow chart of an embodiment of a bus-to-USB conversion method of the present invention;

[0047] Figure 3It is a flow chart of an embodiment of a bus-to-USB conversion method of the present invention;

[0048] Figure 4 It is a flow chart of an embodiment of a bus-to-USB conversion method of the present invention;

[0049] Figure 5 It is a flow chart of an embodiment of a bus-to-USB conversion method of the present invention;

[0050] Figure 6 It is a flow chart of an embodiment of a bus-to-USB conversion method of the present invention;

[0051] Figure 7 It is a flow chart of an embodiment of a bus-to-USB conversion method of the present invention;

[0052] Figure 8 It is a flow chart of an embodiment of a bus and USB conversion device of the present invention;

[0053] Fig. 9 It is an application schematic diagram of a bus and USB conversion device of the present invention. DETAILED DESCRIPTION

[0054] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] In order to simplify the drawings, only the parts related to the present invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0056] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0057] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0058] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0059] It should be noted that the USB in the present invention is an Ethernet interface; SOC is System On Chip, which refers to a chip system on a chip; FPGA is a field programmable gate array; and the software model refers to modeling the module behavior by software.

[0060] Embodiment 1

[0061] like Figure 1 As shown, the present invention provides an embodiment of a method for converting a bus to a USB, comprising the following steps:

[0062] S100 When the bus of the chip system sends a command to the external model, the command is converted into a command in USB format, so that the external model receives the command in USB format through USB.

[0063] S200: When the external model returns a status word in USB format, convert the status word in USB format into a status word in bus format, so that the bus receives the status word in bus format.

[0064] Specifically, the chip system includes SOC and FPGA systems, and the external model refers to a software model located in an off-chip host.

[0065] By supporting the implementation of new heterogeneous systems by SOC or FPGA systems through USB and software models in off-chip hosts, system-level hardware and software simulation and verification can be performed at an earlier stage of SOC development.

[0066] In this embodiment, after the bus and USB conversion IP are integrated in the SOC system, it can be combined with the off-chip software model system, thereby significantly expanding the application scope of the SOC. Compared with heterogeneous systems that are directly connected to the off-chip host via USB, there is no need to develop USB drivers in the SOC / FPGA, and the software is simpler.

[0067] Embodiment 2

[0068] Based on the above embodiment, the parts in this embodiment that are the same as those in the above embodiment will not be repeated one by one. This embodiment provides an embodiment of a method for converting a bus to a USB, such as Figure 2 As shown, the following steps are included:

[0069] When the bus reads the register of the external model, preferably, when the bus of the chip system sends a command to the external model in S100, the command is converted into a command in USB format so that the external model receives the command in USB format through USB, which specifically includes the steps of:

[0070] S101: When the bus reads the register of the external model, the read command of the bus is packaged into a read command word for reading the register of the external model and written into the USB transmission buffer.

[0071] Preferably, when the bus reads the register of the external model, S101 encapsulates the read command of the bus into a read command word for reading the register of the external model and writes it into the USB send buffer, which specifically includes the steps of:

[0072] When the bus reads the register of the external model, a read command of the bus is received, where the read command includes a read tag, a read address, and a read type.

[0073] The read command of the bus is converted into a read command in USB format and written into the USB sending buffer.

[0074] Preferably, when the external model returns a status word in USB format, S200 saves the UART data to a UART receiving buffer, and converts the status word in USB format into a status word in bus format, so that the bus receives the status word in bus format, specifically comprising the steps of:

[0075] S201: When the register of the external model returns a read status word in USB format through USB, convert the read status word into a read status word in bus format, so that the bus receives the read status word in bus format.

[0076] Exemplarily, when reading the register of the external model through the Slave bus, the bus information such as the read tag, read address, and read type are packaged as a command word for reading the register of the external model and written into the USB transmit buffer. After receiving the read command word, the external model parses the command word and returns the result package as a read status word. The USB receives and parses the read status word and returns it to the Slave bus interface.

[0077] When the bus writes to the registers of the external model, such as Figure 3As shown, preferably, when the bus of the chip system sends a command to the external model, S100 converts the command into a command in USB format so that the external model receives the command in USB format through USB, which specifically includes the steps of:

[0078] S102: When the bus writes into the register of the external model, the write command of the bus is packaged into a write command word for writing into the register of the external model and written into the USB sending buffer.

[0079] Specifically, when the bus writes to the register of the external model, S102 encapsulates the write command of the bus into a write command word for writing the register of the external model and writes it into the USB send buffer, including the steps of:

[0080] Receive a data command word sent by an external model via USB, wherein the data command word includes a data write command word, a write address, a length, and USB data.

[0081] The software model in the off-chip host parses the data command word to receive the corresponding USB data and responds.

[0082] Preferably, when the external model returns a status word in USB format, S200 saves the UART data to a UART receiving buffer, and converts the status word in USB format into a status word in bus format, so that the bus receives the status word in bus format, specifically comprising the steps of:

[0083] S202: When the register of the external model returns a write status word in USB format through USB, convert the write status word into a write status word in bus format, so that the bus receives the write status word in bus format.

[0084] Exemplarily, when writing to the register of the external model through the Slave bus, the bus information such as the write tag, write address, write type, etc. is packaged into a command word for writing the register of the external model and written into the USB transmit buffer. After receiving the write command word, the external model parses the command word, performs the write operation, and returns the result package to the write status word. The USB receives and parses the write status word and returns it to the Slave bus interface.

[0085] Embodiment 3

[0086] Based on the above embodiment, the parts in this embodiment that are the same as those in the above embodiment will not be repeated one by one. This embodiment provides an embodiment of a method for converting a bus to a USB, such as Figure 4 As shown, the following steps are included:

[0087] S100, when the bus of the chip system sends a command to the external model, converts the command into a command in USB format, so that the external model receives the command in USB format through USB, specifically including the steps of:

[0088] S103: When the bus reads the data of the external model, the read command packet of the bus is written into a read command word for reading the data of the external model into the USB sending buffer.

[0089] Preferably, when the external model returns a status word in USB format, S200 converts the status word in USB format into a status word in bus format so that the bus receives the status word in bus format, specifically comprising the steps of:

[0090] S203: When the external model returns a read status word in USB format via USB, convert the read status word in USB format into a read status word in bus format, so that the bus receives the read status word in bus format.

[0091] When the bus writes data to the external model, S100, when the bus of the chip system sends a command to the external model, converting the command into a command in USB format so that the external model receives the command in USB format through USB, specifically includes the steps of:

[0092] S104: when the bus writes the data of the external model, the write command packet of the bus is converted into a write command word for writing the data of the external model and is written into the USB transmission buffer.

[0093] When writing the send data buffer through the Slave bus, first write the send data command word, which includes the data write command word, write address, length, and data.

[0094] Preferably, when the external model returns a status word in USB format, S200 converts the status word in USB format into a status word in bus format so that the bus receives the status word in bus format, specifically comprising the steps of:

[0095] S204: When the external model returns the interrupt command word and data in USB format through USB, convert the interrupt command word in USB format into an interrupt command word in bus format, so that the bus reads the data of the external model.

[0096] Specifically, after the external model receives the write command word, it receives data according to the write command word; after the external model completes receiving the data, it returns an interrupt command word to report that the write data block is completed.

[0097] Embodiment 4

[0098] Based on the above embodiment, the parts in this embodiment that are the same as those in the above embodiment will not be described one by one. This embodiment provides an embodiment of a method for converting a bus to a USB, including the following steps:

[0099] S100 When the bus of the chip system sends a command to the external model, the command is converted into a command in USB format, so that the external model receives the command in USB format through USB.

[0100] S200: When the external model returns a status word in USB format, convert the status word in USB format into a status word in bus format, so that the bus receives the status word in bus format.

[0101] Specifically, the chip system includes SOC and FPGA systems, and the external model refers to a software model located in an off-chip host.

[0102] By supporting the implementation of new heterogeneous systems by SOC or FPGA systems through USB and software models in off-chip hosts, system-level hardware and software simulation and verification can be performed at an earlier stage of SOC development.

[0103] In this embodiment, after the bus and USB conversion IP are integrated in the SOC system, it can be combined with the off-chip software model system, thereby significantly expanding the application scope of the SOC. Compared with heterogeneous systems that are directly connected to the off-chip host via USB, there is no need to develop USB drivers in the SOC / FPGA, and the software is simpler.

[0104] Preferably, the bus and USB conversion method further comprises the steps of:

[0105] When receiving the interrupt command word sent by the external model through the USB, the interrupt signal is driven to be valid, so that the chip system receives the interrupt signal of the external model through the interrupt module.

[0106] In this embodiment, the off-chip model can send interrupts, interrupt status register data and data to the chip. Multiple off-chip models can be supported at the same time; the software in the SOC or FPGA can access the IP model in the external host just like accessing the IP on the internal bus.

[0107] Embodiment 5

[0108] Based on the above embodiment, the parts in this embodiment that are the same as those in the above embodiment will not be repeated one by one. This embodiment provides an embodiment of a method for converting a bus to a USB, such as Figure 5 , 6 As shown, the following steps are included:

[0109] Write registers in the external model and read registers in the external model. Figure 5 As shown in the figure, the Slave interface writes to the external register and generates a command word for writing to the external register. After the external model receives the command word for writing to the register, it performs the write operation. The external model returns a write status word, receives and parses the write status word, and returns it to the Slave interface. The Slave interface completes the writing.

[0110] The Slave interface reads the external register and generates a command word for reading the external register. After receiving the command word for reading the register, the external model performs a write operation. The external model returns a read status word, receives and parses the read status word, and returns it to the Slave interface. The Slave interface read is completed.

[0111] Write data blocks to external models and read data blocks from external models. Figure 6 As shown, the Slave interface writes external data, generates a write external data command word and data, and after the external model receives the write data command word and data, it performs a write operation. The external model returns a write completion interrupt status word, receives and parses the write completion interrupt status word, and returns it to the Slave interface, and the Slave interface completes writing data. The Slave interface reads external data, generates a read external data command word, and after the external model receives the read data command word, it performs a read operation. The external model returns a read completion interrupt status word, receives and parses the write completion interrupt status word, and returns it to the Slave interface, and the Slave interface completes reading.

[0112] The external model generates an interrupt and clears the external model interrupt. Figure 7 As shown in the figure, the external model generates an interrupt and generates an interrupt command word, receives and parses the interrupt command word, sets the interrupt status Shadow register, drives the interrupt information, and the CPU responds to the interrupt. Clear the external model interrupt, write the interrupt status Shadow register through the Slave interface, write the external register through the Slave interface, and clear the interrupt.

[0113] In this embodiment, by processing data in a block manner, IP design is simplified and data transmission efficiency is improved.

[0114] Embodiment 6

[0115] On the other hand, the present invention provides an embodiment of a bus and USB conversion device, comprising the steps of:

[0116] The conversion module is used to convert the command into a USB format command when the bus of the chip system sends a command to the external model, so that the external model receives the USB format command through the USB.

[0117] The conversion module is further configured to convert the status word in USB format into a status word in bus format when the register of the external model returns the status word in USB format, so that the bus receives the status word in bus format.

[0118] For example, Figure 8 As shown, the bus and USB conversion device includes a control module, a bus interface, a register, an interrupt module, a USB receive data buffer, and a USB send data buffer.

[0119] The bus interface includes Slave and Master, of which the Slave interface is mandatory and the Master interface is optional. The bus interface supports AHB and AXI type buses; the data read or written by the Slave is distinguished by the address and mapped to the internal register, external register, USB send buffer, and USB send buffer respectively.

[0120] Registers include internal registers and external registers; internal registers are used to control the operation and status of the entire IP; external registers are used to read or write registers of external IP; when reading external registers through the Slave bus, bus information such as read tags, read addresses, and read types are packaged into command words for reading external registers and written into the USB send buffer; after the external model receives the read command word, it parses the command word and returns the result package as a read status word; the USB receives and parses the read status word and returns it to the Slave bus interface.

[0121] When writing to an external register via the Slave bus, the bus information such as write tag, write address, write type, etc. is packaged into a command word for writing to an external register and written into the USB send buffer; after receiving the write command word, the external model parses the command word, performs the write operation, and returns the result package as a write status word; the USB receives and parses the write status word and returns it to the Slave bus interface;

[0122] Control the module's enable / disable, reset / release; control clock frequency generation, and establish one-input and one-output USB endpoint transmission.

[0123] The interrupt module is used to send the interrupt command word, interrupt register value and address information to USB after the external IP generates an interrupt. The conversion IP receives and analyzes the interrupt command word and drives the interrupt signal to be valid according to the internal information.

[0124] Data packaging and transmission, including:

[0125] To simplify IP design and improve transmission efficiency, data is processed in a block manner.

[0126] When writing the send data cache through the Slave bus, first write the send data command word, which includes the data write command word, write address, length, and data; after the external model receives the write command word, it receives data according to the write command word; after the external model completes receiving the data, it returns the interrupt command word to report that the write data block is completed.

[0127] Data reception and analysis, including:

[0128] To simplify IP design and improve transmission efficiency, data is processed in a block manner.

[0129] When the external model needs to send data, it will send a data command word, including a data write command word, a write address, a length, and data; the conversion IP receives and parses it and finds it to be a data command word, receives the data according to the internal information and puts it into the receive data cache; after the external model completes sending the data, it generates a data interrupt, packages the interrupt command word, interrupt register value, and address information, and sends it to the USB; the conversion IP receives and parses it and finds it to be an interrupt command word, and drives the interrupt signal to be valid according to the internal information; after receiving the interrupt, the CPU in the SOC or FPGA reads the data.

[0130] Preferably, the conversion module is further used for:

[0131] When the bus reads the register of the external model, the read command of the bus is packaged into a read command word for reading the register of the external model and written into the USB sending buffer.

[0132] When the bus writes into the register of the external model, the write command of the bus is packaged into a write command word for writing into the register of the external model and written into the USB sending buffer.

[0133] Preferably, the conversion module is further used for:

[0134] When the bus reads the register of the external model, a read command of the bus is received, where the read command includes a read tag, a read address, and a read type.

[0135] The read command of the bus is converted into a read command in USB format and written into the USB sending buffer.

[0136] Preferably, the conversion module is further used for:

[0137] When the register of the external model returns a read status word in the USB format through the USB, the read status word is converted into a read status word in the bus format, so that the bus receives the read status word in the bus format.

[0138] When the register of the external model returns a write status word in the USB format through the USB, the write status word is converted into a write status word in the bus format, so that the bus receives the write status word in the bus format.

[0139] Preferably, the bus and USB conversion device further comprises:

[0140] The interrupt module is used to drive the interrupt signal to be valid when receiving the interrupt command word sent by the external model through the USB, so that the chip system receives the interrupt signal of the external model through the interrupt module.

[0141] For example, Fig. 9 As shown, the bus and USB conversion IP and method implemented by the present invention support the implementation of a new heterogeneous system by a SOC or FPGA system through a USB and a software model in an off-chip host, thereby enabling system-level software and hardware simulation and verification at an earlier stage of SOC development.

[0142] The SOC / FPGA platform integrates CPU, other existing IP, bus and USB conversion IP, and USB interface; the off-chip host integrates off-chip IP model, interface programming library and USB interface. The communication between the SOC / FPGA platform and the off-chip host is realized through this bus and USB conversion IP.

[0143] Among them, the bus and USB conversion device can be a bus and USB conversion IP to achieve transaction-level modeling support for registers, interrupts, and data of external IP. It mainly includes bus interface, registers, control module, interrupt module, data packaging and sending, data reception and analysis, etc.

[0144] In this embodiment, the off-chip model can send interrupts, interrupt status register data and data to the chip; it can support multiple off-chip models at the same time. The software in the SOC or FPGA can access the IP model in the external host just like accessing the IP on the internal bus; after the bus and the USB conversion IP are integrated in the FPGA system, it can be combined with the off-chip software model system, thereby supporting earlier system-level verification based on off-chip software IP.

[0145] After the IP for bus and USB conversion is integrated into the SOC system, it can be combined with an off-chip software model system, thereby significantly expanding the application scope of the SOC; compared with heterogeneous systems that are directly connected to the chip via USB, there is no need to develop USB drivers in the SOC / FPGA, and the software is simpler.

[0146] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed with hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0147] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. Exemplarily, the system embodiments described above are merely schematic. Exemplarily, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation. Exemplarily, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0148] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0149] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0150] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A method for converting bus to USB, characterized in that: Includes steps: Integrate the IP for bus and USB conversion in a chip system, wherein the chip system includes a SOC and an FPGA system; When the bus of the chip system sends a command to the external model, the command is converted into a command in USB format, so that the external model receives the command in USB format through USB, wherein the command conversion process occurs within the chip system; When the external model returns a status word in USB format, converting the status word in USB format into a status word in bus format, so that the bus receives the status word in bus format, wherein the status word conversion process occurs within the chip system; When receiving the interrupt command word sent by the external model through the USB, driving the interrupt signal to be valid, so that the chip system receives the interrupt signal of the external model; The USB format is a format that supports sending and receiving using USB, and the external model includes a Matlab algorithm model, a C-based algorithm model, or a SystemC-based off-chip IP model.

2. The method for converting bus to USB according to claim 1, characterized in that: When the bus of the chip system sends a command to the external model, the command is converted into a command in USB format so that the external model receives the command in USB format through USB, which specifically includes the steps of: When the bus reads the register of the external model, the read command packet of the bus is written into a read command word for reading the register of the external model into a USB transmission buffer; When the bus writes into the register of the external model, the write command of the bus is packaged into a write command word for writing into the register of the external model and written into the USB sending buffer.

3. The method for converting bus to USB according to claim 1, characterized in that: When the bus of the chip system sends a command to the external model, the command is converted into a command in USB format so that the external model receives the command in USB format through USB, which specifically includes the steps of: When the bus reads the data of the external model, the read command packet of the bus is written into the USB transmission buffer as a read command word for reading the data of the external model; When the bus writes the data of the external model, the write command packet of the bus is converted into a write command word for writing the data of the external model and is written into the USB sending buffer.

4. The method for converting bus to USB according to claim 2, characterized in that: When the bus reads the register of the external model, the read command packet of the bus is written into the read command word of the register of the external model into the USB sending buffer, which specifically includes the steps of: When the bus reads the register of the external model, receiving a read command of the bus, the read command including a read tag, a read address, and a read type; The read command of the bus is converted into a read command in USB format and written into the USB sending buffer.

5. The method for converting bus to USB according to claim 2, characterized in that: When the register of the external model returns a status word in USB format, converting the status word in USB format into a status word in bus format so that the bus receives the status word in bus format specifically comprises the steps of: When the register of the external model returns a read status word in USB format through USB, the conversion module receives the status word into a receiving buffer, and converts the read status word into a read status word in bus format, so that the bus receives the read status word in bus format; When the register of the external model returns a write status word in USB format through USB, the conversion module receives the status word into a receiving buffer and converts the write status word into a write status word in bus format so that the bus receives the write status word in bus format.

6. The method for converting bus to USB according to any one of claims 1 to 5, characterized in that: Also includes the steps: When the bus writes the interrupt clear register of the external model, the interrupt of the external model is cleared.

7. A bus and USB conversion device, characterized in that: include: A conversion module, used for converting a command into a USB format command when the bus of the chip system sends a command to the external model, so that the external model receives the USB format command through the USB; The conversion module is further used for, when the external model returns a status word in USB format, converting the status word in USB format into a status word in bus format, so that the bus receives the status word in bus format; An interrupt module, used for driving an interrupt signal to be effective when receiving an interrupt command word sent by the external model through the USB, so that the chip system receives the interrupt signal of the external model through the interrupt module; The conversion module is located in the chip system, and the external model includes a Matlab algorithm model, a C-based algorithm model or a SystemC-based off-chip IP model.

8. The bus and USB conversion device according to claim 7, characterized in that: The conversion module is further used for: When the bus reads the register of the external model, the read command packet of the bus is written into a read command word for reading the register of the external model into a USB transmission buffer; When the bus writes into the register of the external model, the write command packet of the bus is written into the write command word of the register of the external model and written into the USB transmission buffer; When the external model returns a status word in USB format via USB, the conversion module receives the status word into a receiving buffer and converts the status word into a status word in bus format, so that the bus receives the read / write status word in the bus format.

9. The bus and USB conversion device according to claim 7, characterized in that: The conversion module is further used for: When the bus reads the data of the external model, the read command packet of the bus is written into the USB transmission buffer as a read command word for reading the data of the external model; When the bus writes the data of the external model, the write command packet of the bus is written into the write command word of the data of the external model and is written into the USB sending buffer; When the external model returns a status word in USB format via USB, the conversion module receives the status word into a receiving buffer and converts the status word into a status word in bus format, so that the bus receives the read / write status word in the bus format.

10. The bus-to-USB conversion device according to any one of claims 7 to 9, characterized in that: The interrupt module is also used to clear the interrupt of the external model when the bus writes the interrupt clear register of the external model.

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