A multi-rate LDPC coding method with variable frame length suitable for deep space communication

Abstract

The present invention relates to a multi-rate LDPC encoding method with a variable frame length suitable for deep space communication, comprising the following steps: step 1, caching received data frames; step 2, setting the value of the encoding code length L; step 3, designing an LDPC code with a coding parameter of (4088, 1784); step 4, starting the corresponding LDPC encoding process for the received data frame according to the value of the encoding code length L; step 5, caching the encoded data, and then outputting the encoded data. The data frame lengths before and after encoding in this method are both matched with traditional deep space detectors, and the data frame length can be set by the user by sending instructions according to needs. A multi-rate output scheduling mechanism is adopted to solve the problem of multi-rate switching of output data after encoding. In the present invention, long frame encoding and short frame encoding share an LDPC encoding module, a scrambling module, and a synchronization header insertion module, thereby saving hardware resources and greatly reducing the complexity of implementation.

Description

Technical Field

[0001] The present invention relates to the field of spacecraft measurement and control data transmission technology, and in particular to a multi-rate LDPC coding method with a variable frame length suitable for deep space communication. Background Art

[0002] In the design of deep space probes, due to the long communication distance, large transmission delay, and extremely low received signal-to-noise ratio, it is necessary to design a high-performance channel coding method to provide reliable communication. In the design of traditional deep space communication systems, a single RS+convolutional cascade code is often used, with a coding gain of 6 to 7 dB. In recent years, Low Density Parity Check (LDPC) codes have received extensive attention in the field of deep space communication due to their advantages such as high coding gain, moderate complexity, and parallel encoding and decoding.

[0003] The LDPC code recommended by the CCSDS standard for telemetry and data transmission channels in deep space communication is a type of system LDPC code with a quasi-cyclic structure, including three information lengths (128, 512, 2048 bytes, before encoding) and three code rates (1 / 2, 2 / 3, 4 / 5), with a coding gain of no less than 9dB. In current deep space exploration missions, the coding method generally used for telemetry and data transmission channels is (223, 255) RS coding + (1 / 2) convolution coding. The data frame length before coding is 220 bytes or 892 bytes, and the corresponding frame length after coding is 512 bytes or 2048 bytes. Due to the complex channel conditions of the ground and relay links of deep space detectors, different channel environments have different requirements for coding methods and rates. Therefore, telemetry and data transmission channels need to be compatible with multiple coding methods and can be switched on-orbit through instructions. The LDPC coding recommended by the CCSDS standard is not compatible with the existing RS+convolution cascade coding method.

[0004] In view of the above situation, the present invention designs a multi-rate LDPC encoding method with variable frame length suitable for deep space communication. The data frame length before and after encoding matches the traditional deep space detector, and the data frame length can be set by the user by sending instructions according to needs. At the same time, a multi-rate output scheduling mechanism is adopted to solve the problem of multi-rate switching of output data after encoding. In the present invention, the long frame encoding process and the short frame encoding process share the LDPC encoding module, the scrambling module, and the synchronization header insertion module, thereby saving hardware resources and greatly reducing the complexity of implementation. Summary of the invention

[0005] The purpose of the present invention is to design a multi-rate LDPC coding method with variable frame length in view of the high requirements on coding gain, the coexistence of multiple frame lengths and the need to support on-orbit multi-rate switching in deep space communications.

[0006] In order to solve the problems in the prior art, the present invention proposes a multi-rate LDPC coding method with a variable frame length suitable for deep space communication. The present invention comprises the following steps:

[0007] Step 1: Cache the received data frame;

[0008] Step 2: Set the value of the encoding code length L;

[0009] Step 3: Design an LDPC code with coding parameters of (4088, 1784);

[0010] Step 4: according to the value of the encoding code length L, start the corresponding LDPC encoding process for the received data frame;

[0011] Step 5: Cache the encoded data frame, and then output the encoded data frame.

[0012] Furthermore, in the step one, caching the received data frames is achieved through two cache modules, namely a short frame data frame cache module and a long frame data frame cache module; the short frame data frame cache module is used to cache the received short frame data frames; the long frame data frame cache module is used to cache the received long frame data frames; the cache adopts a ping-pong operation mechanism, and the cache module can generate a storage status flag.

[0013] Furthermore, in the step 2, the encoding code length is set according to the long-short frame switching instruction sent by the user according to the current task requirements, L='0' represents a short frame; L='1' represents a long frame.

[0014] Furthermore, when the value of the encoding code length L is '0', the LDPC encoding process is as follows:

[0015] (1) When the data in the short frame data frame buffer module is not empty, read the 1760-bit data frame H S ;

[0016] (2) In data frame H S The header is filled with 24 bits of 0, and the filled data frame M S The frame length is 1784 bits;

[0017] (3) In the LDPC encoding module, the LDPC code of the data frame M is encoded according to step 3. S Perform (4088, 1784) LDPC encoding to obtain data frame N S .

[0018] (4) Remove data frame N S The initial 24 bits of padding data give 4064 bits of data P S ;

[0019] (5) In the scrambling module, P S The scrambled data sequence is called Q S ;

[0020] (6) When inserting the synchronization header module, S Insert a 32-bit synchronization header into the header to obtain the final encoded data frame R S , R S The frame length is 32+4064=4096 bits, or 512 bytes.

[0021] Furthermore, when the value of the encoding code length L is '1', the LDPC encoding process is as follows:

[0022] (1) When the data in the long frame data frame buffer module is not empty, read the 7136-bit data frame H L ;

[0023] (2) Data frame H L Split into four 1784-bit data blocks, marked as M LA 、M LB 、M LC 、M LD ;

[0024] (3) In the LDPC encoding module, the LDPC code described in step 3 is used to encode the data block M LA 、M LB 、M LC 、M LD Perform (4088, 1784) LDPC encoding to obtain 4 encoded data blocks N LA 、N LB 、N LC 、N LD , the length of the four encoded data blocks is 4088 bits;

[0025] (4) Data block N LA 、N LB 、N LC 、N LD Merge into a 16352-bit data sequence P L ;

[0026] (5) In the scrambling module, P L The scrambled data sequence is called Q L ;

[0027] (6) When inserting the synchronization header module, L Insert a 32-bit synchronization header into the header to obtain the final encoded data frame R L , R LThe frame length is 32+16352=16384 bits, or 2048 bytes.

[0028] Furthermore, in different LDPC encoding processes, the LDPC encoding module, scrambling module, and synchronization header insertion module used have the same design status, and the modules can be shared.

[0029] Furthermore, in the step five, caching the encoded data frames is achieved through two cache modules, namely a short frame encoded data frame cache module and a long frame encoded data frame cache module; the short frame encoded data frame cache module is used to cache the encoded short frame data frames; the long frame encoded data frame cache module is used to cache the encoded long frame data frames.

[0030] Furthermore, before outputting the encoded data frame, the following steps are also included:

[0031] (1) Divide the local clock frequency according to the rate switching instruction to generate an equally spaced pulse signal;

[0032] (2) counting the pulse signal and generating a scheduling flag according to the value of the pulse signal;

[0033] (3) when the scheduling flag is valid, querying the status of the short frame coded data frame buffer module or the long frame coded data frame buffer module;

[0034] (4) When the short frame coded data frame buffer module or the long frame coded data frame buffer module is not empty, the coded data is read bit by bit and output.

[0035] Further, when L='0', a scheduling flag is generated for every 4096 pulse signals; when L='1', a scheduling flag is generated for every 16384 pulse signals.

[0036] Compared with the prior art, the beneficial effects of the present invention are:

[0037] 1. The present invention designs a multi-rate LDPC encoding method with variable frame length suitable for deep space communication. The data frame lengths before and after encoding are matched with the current traditional deep space detectors. The data frame length can be set by the user by sending a long-short frame switching instruction according to demand.

[0038] 2. The present invention solves the problem of multi-rate switching of output data after encoding.

[0039] 3. In the present invention, the long frame coding process and the short frame coding process share the LDPC coding module, the scrambling module, and the synchronization header insertion module, thereby saving hardware resources and greatly reducing the complexity of implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1A block diagram of an implementation method of a variable frame length multi-rate LDPC encoding method provided by an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of a short frame encoding process provided by an embodiment of the present invention;

[0042] Figure 3 A schematic diagram of a long frame encoding process provided by an embodiment of the present invention;

[0043] Figure 4 An example of a short frame format provided by an embodiment of the present invention;

[0044] Figure 5 An example of a long frame format provided for an embodiment of the present invention; DETAILED DESCRIPTION

[0045] In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0046] A deep space probe uses LDPC coding for its ground link, requiring the coding gain to be no less than 9dB. At the same time, the coding method is required to be able to adapt to short frames (220 bytes, see the attached frame format). Figure 4 ) and long frames (892 bytes, see the attached Figure 5 ), the encoded data frames are 512 bytes and 2048 bytes respectively, which are switched by long and short frame switching instructions. The data rate output to the transponder after encoding is adjustable from 32bps to 2048kbps. The specific processing steps are as follows:

[0047] Step 1: Cache the received data frame;

[0048] like Figure 1 As shown in the figure, two receiving buffers are designed at the interface between the encoding module and the combining module. The receiving buffer is implemented by the BLOCKRAM inside the FPGA. The storage depth of BLOCKRAM is 2048 and the bit width is 8 bits. The short frame data is stored in BLOCKRAM1, the 2n-1 (n=1,2,3...) frame 220 bytes are stored at address 0 to address 219, and the 2n frame 220 bytes are stored at address 1024 to address 1243. The long frame data is stored in BLOCKRAM2, the 2n-1 frame 892 bytes are stored at address 0 to address 891, and the 2n frame 892 bytes are stored at address 1024 to address 1915.

[0049] 1. When the data in BLOCKRAM1 is not full, the shunt module can continue to write short frame data, otherwise it continues to wait;

[0050] 2. When the data in BLOCKRAM2 is not full, the branch module can continue to write long frame data, otherwise it continues to wait.

[0051] 3. When the data in BLOCKRAM1 is not empty, the LDPC encoding module can start the short frame encoding process, otherwise it continues to wait;

[0052] 4. When the data in BLOCKRAM2 is not empty, the LDPC encoding module can start the long frame encoding process, otherwise continue to wait.

[0053] Step 2: According to the long and short frame switching instruction sent by the user according to the current task requirements, set the encoding code length L, L = '0' for short frame; L = '1' for long frame

[0054] Step 3: Design an LDPC code with coding parameters of (4088, 1784).

[0055] 1. Construct an LDPC code with coding parameters of (4096, 1792).

[0056] The dimension of the base matrix of the check matrix H is 18×32, and the dimension of the extended matrix is ​​128×128. Therefore, the dimension of the check matrix H is 2304×4096. H can be decomposed into H1 and H2, where H1 represents the part corresponding to the information bit and H2 represents the part corresponding to the check bit.

[0057] H=[H1 H2]

[0058]

[0059]

[0060] In formula (1), H1 is composed of m b ×k b I×I all-zero sub-matrices or non-zero sub-matrices, E L represents the I×I identity matrix, m b =18, k b =14, I=128.

[0061] The row and column weight distribution of the LDPC check matrix is:

[0062] Row weight distribution:

[0063]

[0064] Column weight distribution:

[0065]

[0066] The information bit length of the LDPC code is 1792 bits, the check bit length is 2304 bits, and the coding parameters are (4096, 1792).

[0067] 2. Perform 8-bit deletion on the (4096, 1792) code, delete the last 8 bits of the information bit, and obtain an LDPC code with coding parameters of (4088, 1784).

[0068] Step 4: according to the value of the encoding code length L, start the corresponding LDPC encoding process for the received data frame;

[0069] 1. As Figure 2 As shown, the short frame encoding process is as follows:

[0070] (1) When the data in BLOCKRAM1 is not empty, read the 1760-bit data frame H S .

[0071] (2) In data frame H S The header is filled with 24 bits of 0, and the filled data frame M S The frame length is 1784 bits.

[0072] (3) In the LDPC encoding module, the LDPC code pair M described in step 3 is S Perform (4088, 1784) LDPC encoding. The encoding process is as follows: the state variable enc_state is set in the encoder, and the value range is 0 to 4095. When 0≤enc_state≤1783, the encoder outputs a 1784-bit information sequence; when 1784≤enc_state≤1791, the encoder does not output; when 1792≤enc_state≤4095, the encoder outputs a 2304-bit check sequence. A total of 4088 bits of data are output in one cycle of enc_state, which is called an encoding codeword N S .

[0073] (4) Remove N S The initial 24 bits of padding data give 4064 bits of data P S .

[0074] (5) In the scrambling module, P S The scrambled data sequence is called Q S The pseudo-random sequence generator polynomial used in the scrambling operation is h(x)=x 8 +x 7 +x 5 +x 3 +1. For every P S, the initial state of scrambling is all 1.

[0075] (6) When inserting the synchronization header module, S Insert a 32-bit synchronization header into the header to obtain the final encoded data frame R S , R S The frame length is 32+4064=4096 bits (512 bytes).

[0076] 2. If Figure 3 As shown, the long frame encoding process is as follows:

[0077] (1) When the data in BLOCKRAM2 is not empty, read the 7136-bit data frame H L .

[0078] (2) Put H L Split into four 1784-bit data blocks, marked as M LA 、M LB 、M LC 、M LD .

[0079] (3) In the LDPC encoding module, for the data block M LA 、M LB 、M LC 、M LD Perform (4088, 1784) LDPC encoding respectively, the encoding process is the same as the short frame encoding process step (3). Get 4 encoded data blocks N LA 、N LB 、N LC 、N LD , with a length of 4088 bits.

[0080] (4) Data block N LA 、N LB 、N LC 、N LD Merge into a 16352-bit data sequence P L .

[0081] (5) In the scrambling module, P L The scrambled data sequence is called Q L The pseudo-random sequence generator polynomial used in the scrambling operation is h(x)=x 8 +x 7 +x 5 +x 3 +1. For every P L , the initial state of scrambling is all 1.

[0082] (6) When inserting the synchronization header module, LThe header inserts a 32-bit (0x1ACFFC1D) synchronization header to obtain the data frame R L . R L The frame length is 32+16352=16384 bits (2048 bytes).

[0083] In the short frame coding process and the long frame coding process, the LDPC coding module, scrambling module, and synchronization header insertion module used have the same design status and can be shared.

[0084] Step 5: Cache the encoded data frame, and then output the encoded data frame.

[0085] 1. The output interface sets the output buffer to store the encoded data frame. The output buffer is implemented by the BLOCKRAM inside the FPGA. The encoded short frame data is stored in BLOCKRAM3, and the encoded long frame data is stored in BLOCKRAM4.

[0086] 2. Set up the clock generation module, divide the local clock according to the rate switching instruction, generate equally spaced pulse signals, count the pulse signals at the same time, and generate a scheduling flag.

[0087] (1) In short frame mode, a scheduling flag is generated for every 4096 pulse signals;

[0088] (2) In long frame mode, a scheduling flag is generated for every 16384 pulse signals.

[0089] 3. When the dispatch flag is valid, query the output buffer status. When the output buffer is not empty, output the encoded data bit by bit to the transponder.

[0090] (1) In short frame mode, query and read BLOCKRAM3;

[0091] (2) In long frame mode, query and read BLOCKRAM4.

[0092] Although the present invention has been described in detail above by means of general description, specific implementation methods and tests, it is obvious to those skilled in the art that some modifications or improvements may be made to the present invention. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of protection claimed by the present invention.

Claims

1. A variable frame length multi-rate LDPC coding method suitable for deep space communication, characterized in that: The steps include: Step 1: Cache the received data frame; Step 2: Set the value of the encoding code length L; The encoding code length is set according to the long and short frame switching instruction sent by the user according to the current task requirements, L = '0' represents a short frame; L = '1' represents a long frame; Step 3: Design an LDPC code with coding parameters of (4088, 1784); Step 4: according to the value of the encoding code length L, start the corresponding LDPC encoding process for the received data frame; Step 5: caching the encoded data frame, and then outputting the encoded data frame; In the step 4, when the value of the encoding code length L is '0', the LDPC encoding process is as follows: (1) When the data in the short frame data frame buffer module is not empty, read the 1760-bit data frame H S ; (2) In data frame H S The header is filled with 24 bits of 0, and the filled data frame M S The frame length is 1784 bits; (3) In the LDPC encoding module, the LDPC code of the data frame M is encoded according to step 3. S Perform (4088, 1784) LDPC encoding to obtain data frame N S ; (4) Remove data frame N S The initial 24 bits of padding data give 4064 bits of data P S ; (5) In the scrambling module, P S The scrambled data sequence is called Q S ; (6) When inserting the synchronization header module, S Insert a 32-bit synchronization header into the header to obtain the final encoded data frame R S , R S The frame length is 32+4064=4096 bits, or 512 bytes. In the step 4, when the value of the encoding code length L is '1', the LDPC encoding process is as follows: (1) When the data in the long frame data frame buffer module is not empty, read the 7136-bit data frame H L ; (2) Data frame H L Split into four 1784-bit data blocks, marked as M LA 、M LB 、M LC 、M LD ; (3) In the LDPC encoding module, the LDPC code described in step 3 is used to encode the data block M LA 、M LB 、M LC 、M LD Perform (4088, 1784) LDPC encoding to obtain 4 encoded data blocks N LA 、N LB 、N LC 、N LD , the length of the four encoded data blocks is 4088 bits; (4) Data block N LA 、N LB 、N LC 、N LD Merge into a 16352-bit data sequence P L ; (5) In the scrambling module, P L The scrambled data sequence is called Q L ; (6) When inserting the synchronization header module, L Insert a 32-bit synchronization header into the header to obtain the final encoded data frame R L , R L The frame length is 32+16352=16384 bits, or 2048 bytes.

2. The method according to claim 1, characterized in that In the step 1, caching the received data frames is implemented by two cache modules, namely a short frame data frame cache module and a long frame data frame cache module; The short frame data frame buffer module is used to buffer the received short frame data frames; The long frame data frame buffer module is used for buffering received long frame data frames.

3. The method according to claim 1, characterized in that In different LDPC encoding processes, the LDPC encoding module, scrambling module, and synchronization header insertion module used have the same design status and can be shared.

4. The method according to claim 1, characterized in that: In the step 5, caching the encoded data frames is achieved through two cache modules, namely a short frame encoded data frame cache module and a long frame encoded data frame cache module; the short frame encoded data frame cache module is used to cache the encoded short frame data frames; the long frame encoded data frame cache module is used to cache the encoded long frame data frames.

5. The method according to claim 4, characterized in that In the step 5, before outputting the encoded data frame, the following steps are also included: (1) Divide the local clock frequency according to the rate switching instruction to generate an equally spaced pulse signal; (2) counting the pulse signal and generating a scheduling flag according to the value of the pulse signal; (3) when the scheduling flag is valid, querying the status of the short frame coded data frame buffer module or the long frame coded data frame buffer module; (4) When the short frame coded data frame buffer module or the long frame coded data frame buffer module is not empty, the coded data is read bit by bit and output.

6. The method according to claim 5, characterized in that In the step 5, when L='0', a scheduling flag is generated for every 4096 pulse signals; when L='1', a scheduling flag is generated for every 16384 pulse signals.

Images