Method, system, control method and control system for managing and storing BMP images in module signal generator using FPGA
By storing and calculating the starting address in the FPGA, the problems of FPGA management Bmp image complexity and resource consumption in the prior art are solved, and efficient picture refresh, movement and split screen functions are realized, meeting the high-resolution needs under different conditions.
Patent Information
- Application Number
- CN202110052052.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-01-15
- Publication Date
- 2025-03-07
- Estimated Expiration
- 2041-01-15
AI Technical Summary
The existing FPGAs have complex methods to manage Bmp pictures in module signal generators, making it difficult to achieve efficient picture refresh, movement and split screen functions with different resolutions, color depths and refresh rates. The logical code consumes a lot of resources, and Fmax cannot meet the requirements.
By storing and adjusting steps in the FPGA, each pixel of the Bmp picture is filled and stored according to the set value, so that the storage size of each row of pixels is an integer multiple of the FPGA memory interface, and the starting address of each row of pixels in memory is calculated to simplify the implementation of mobile and split screen functions.
The requirements for high-resolution picture refresh bandwidth, movement and split screen functions under different resolutions, color depths, and refresh rates are realized, simplifying the FPGA logic code and reducing logical resource consumption.
Smart Images
Figure CN112767234B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the fields of liquid crystal module testing equipment and image processing technology, and in particular to a method and system for managing and storing BMP images in a module signal generator using an FPGA, and a control method and control system. Background Art
[0002] In the field of LCD module testing, customers require module signal generators to support different screen resolutions, color depths, refresh rates, and other screen requirements; they need to implement special screen functions such as flipping, horizontal movement, and vertical movement; and they need to support multiple split-screen modes such as horizontal split-screen, vertical split-screen, and square split-screen.
[0003] There are two typical options for the main control chip of the module signal generator in the field of LCD module testing equipment: ARM and FPGA.
[0004] The ARM implementation has a fatal flaw: large-resolution screens cannot meet the requirements of screen refresh rate bandwidth.
[0005] FPGAs are the mainstream choice in the market. FPGAs typically store BMP image data directly in memory without any processing. However, their limitations include the complexity of the logic code required to implement image movement and split-screen functionality at various color depths and resolutions, such as 6, 8, and 10-bit. This consumes significant logic resources, making it difficult to easily implement complex special functions like movement and split-screen functionality. Furthermore, the Fmax (Frequency Max) may not meet required specifications. Summary of the Invention
[0006] In order to solve the problems in the prior art, the present invention provides a method for storing BMP images in the memory of the main control chip FPGA of the module signal generator in the field of liquid crystal module testing equipment. Its purpose is to provide a simple, low-cost and easy-to-implement method while meeting all the functional requirements of customers.
[0007] The present invention provides a method for managing and storing BMP images in a module signal generator using an FPGA, comprising the following steps:
[0008] Storage adjustment step: filling and storing each pixel in the BMP image according to the first set value, and filling and storing the number of pixels in each row of the BMP image according to an integer multiple of the second set value, so that the pixel storage size of each row of the BMP image is an integer multiple of the FPGA memory interface;
[0009] Calculation steps: Calculate the starting address of each row of pixels of the BMP image stored in the memory.
[0010] As a further improvement of the present invention, the first set value is 32 bits.
[0011] As a further improvement of the present invention, the second set value is an integer multiple of 2 pixels, temporarily taken as 16 pixels.
[0012] As a further improvement of the present invention, the method can simultaneously store three types of pixels: RGB 6-bit, 8-bit, and 10-bit.
[0013] As a further improvement of the present invention, for the bitmap RGB 6-bit single pixel storage, each pixel is stored in the memory as 32 bits, where R[5:0], G[5:0], B[5:0] are the RGB component values of the BMP image. RGB has a total of 18 bits, and 14 bits of data need to be filled to form 32 bits;
[0014] For bitmap RGB 8-bit single pixel storage, each pixel is stored in memory as 32 bits, where R[7:0], G[7:0], B[7:0] are the RGB component values of the BMP image. RGB has a total of 24 bits, and 8 bits of data need to be filled to form 32 bits;
[0015] For bitmap RGB 10-bit single pixel storage, each pixel is stored in memory as 32 bits, where R[9:0], G[9:0], and B[9:0] are the RGB component values of the BMP image. RGB has a total of 30 bits, and 2 bits of data need to be filled to form 32 bits.
[0016] As a further improvement of the present invention, in the calculation step, the calculation formula for the starting address of each row of pixels of the BMP image stored in the memory is as follows: if H / the second set value is an integer, then: R*(H / the second set value)*the first set value / the memory bit width; if H / the second set value is not an integer, then: R*(H / the second set value+1)*the first set value / the memory bit width; wherein H represents the number of row pixels, R represents the row number of pixels, and R=0, 1, 2,...
[0017] The present invention also provides a system for managing and storing BMP images in a module signal generator using an FPGA, comprising:
[0018] Storage adjustment module: used to fill each pixel in the BMP image with a first set value and fill each row of the BMP image with an integer multiple of a second set value, so that the pixel storage size of each row of the BMP image is an integer multiple of the FPGA memory interface;
[0019] Calculation module: used to calculate the starting address of each row of pixels of the BMP image stored in the memory.
[0020] As a further improvement of the present invention, the first setting value is 32 bits, and the second setting value is an integer multiple of 2 pixels, and the temporary value is 16.
[0021] As a further improvement of the present invention, the system can simultaneously store three types of pixels: RGB 6-bit, 8-bit, and 10-bit.
[0022] As a further improvement of the present invention, in the calculation module, the calculation formula for the starting address of each row of pixels of the BMP image stored in the memory is as follows: if H / the second set value is an integer, then: R*(H / the second set value)*the first set value / the memory bit width; if H / the second set value is not an integer, then: R*(H / the second set value+1)*the first set value / the memory bit width; wherein H represents the number of row pixels, R represents the row number of pixels, and R=0, 1, 2,...
[0023] The present invention also provides a method for controlling BMP images using FPGA in a module signal generator. After using the method for storing BMP images in memory using FPGA of the present invention to calculate the starting address of each row of pixels of the BMP image stored in the memory, the FPGA realizes the movement and splitting of the BMP image according to the obtained starting address.
[0024] The present invention also provides a system for controlling BMP images using FPGA in a module signal generator. The system for storing BMP images in a memory using the FPGA of the present invention calculates the starting address of each row of pixels of the BMP image stored in the memory, and then, based on the obtained starting address, the FPGA realizes the movement and splitting of the BMP image.
[0025] The beneficial effects of the present invention are: the present invention can simultaneously meet different functional requirements such as high-resolution picture refresh bandwidth, movement, split screen, etc. under different resolutions, color depths, and refresh rates; through the present invention, the FPGA logic code is simple to implement and consumes less logic resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 This is a schematic diagram of the bitmap RGB 6-bit single pixel storage style;
[0027] Figure 2 This is a schematic diagram of the bitmap RGB 8bit single pixel storage style;
[0028] Figure 3 This is a schematic diagram of the bitmap RGB 10-bit single pixel storage style;
[0029] Figure 4 It is a schematic diagram of the storage style of each row of pixels;
[0030] Figure 5 This is a schematic diagram of the storage style of the entire frame image;
[0031] Figure 6 It is a flow chart of the method of the present invention. DETAILED DESCRIPTION
[0032] like Figure 6 As shown, the present invention discloses a method for managing and storing BMP (Bitmap) images in a module signal generator using an FPGA, comprising the following steps:
[0033] Storage adjustment steps: fill and store each pixel in the BMP image according to the first set value (the first set value is 32 bits), and fill and store the number of pixels in each row according to an integer multiple of the second set value (the second set value can be 16 pixels or 32 pixels, temporarily selected as 16 pixels). The FPGA operation memory interface is generally 256 or 512 bits. In this way, the pixel storage size of each row of the BMP image is an integer multiple of the FPGA memory interface.
[0034] Calculation steps: Make the starting position of each row of pixels of the BMP image an exact address (that is, calculate the starting address of each row of pixels of the BMP image stored in the memory). Knowing the starting address of each row of pixels can easily complete the functions of moving and splitting the screen.
[0035] In the calculation step, the calculation formula for the starting address of each row of pixels of the BMP image stored in the memory is as follows: if H / the second set value is an integer, then: R*(H / the second set value)*the first set value / the memory bit width; if H / the second set value is not an integer, then: R*(H / the second set value+1)*the first set value / the memory bit width; where H represents the number of row pixels, R represents the row number of pixels, and R=0, 1, 2,...
[0036] Specifically, the first setting value is 32, the second setting value is 16; R represents the row number of pixels, and R starts from 0.
[0037] This method can store RGB 6-bit, 8-bit, and 10-bit pixels at the same time. The following is a detailed description:
[0038] Figure 1 This invention uses a 6-bit RGB pixel storage format for bitmaps. Each pixel is stored in memory as 32 bits. R[5:0], G[5:0], and B[5:0] represent the RGB component values of the BMP image. RGB has a total of 18 bits, so 14 bits of data are needed to fill the 32 bits. The padding position and content can be filled in the same manner as described above, or adjusted to other positions and contents.
[0039] Figure 2 This invention stores 8-bit RGB single-pixel bitmaps in memory, each pixel being stored as 32 bits. R[7:0], G[7:0], and B[7:0] represent the RGB component values of the BMP image. RGB has a total of 24 bits, so 8 bits of data are needed to fill the 32-bit space. The padding position and content can be based on the pattern shown in the image, or adjusted to other positions and content.
[0040] Figure 3 This invention uses a 10-bit RGB single-pixel storage format for bitmaps. Each pixel is stored in memory as 32 bits. R[9:0], G[9:0], and B[9:0] represent the RGB component values of the BMP image. RGB has a total of 30 bits, so 2 bits of data are required to fill the 32 bits. The padding position and content can be filled in the same manner as described above, or adjusted to other positions and contents.
[0041] Figure 4 Each row of pixels is stored in a way that the number of pixels in each row is padded and stored as an integer multiple of 16. For example, the pixel value in the row is 1366, and 1366 needs to be supplemented with 10 pixels. 1376 is divisible by 16. Figure 4 1 in the middle means that pixels 1360-1365 are real pixels, and pixels 1366-1375 are Dummy filling pixels. The filling position and content can be adjusted by Figure 4 The styles shown can also be adjusted to other positions and contents.
[0042] Figure 5 The entire image is stored in memory. The figure shows how a 1366x768 resolution image is stored in memory. If 1366 is not divisible by 16, 10 pixels are added. This storage method makes it easy to find the starting position of each row of pixels in memory, making it easier to implement functions such as moving and splitting the screen.
[0043] The present invention also discloses a system for managing and storing BMP images in a module signal generator using FPGA, comprising:
[0044] Storage adjustment module: used to fill and store each pixel in the BMP image according to the first set value, and fill and store the number of pixels in each row of the BMP image according to the integer multiple of the second set value, so that the pixel storage size of each row of the BMP image is an integer multiple of the FPGA memory interface.
[0045] Calculation module: used to calculate the starting address of each row of pixels of the BMP image stored in the memory.
[0046] The first setting value is 32 bits, and the second setting value is 16 pixels.
[0047] The system can simultaneously store three types of pixels: RGB 6-bit, 8-bit, and 10-bit.
[0048] For bitmap RGB 6-bit single pixel storage, each pixel is stored in memory as 32 bits, where R[5:0], G[5:0], and B[5:0] are the RGB component values of the BMP image. RGB has a total of 18 bits, and 14 bits of data need to be filled to form 32 bits.
[0049] For bitmap RGB 8-bit single pixel storage, each pixel is stored in memory as 32 bits, where R[7:0], G[7:0], and B[7:0] are the RGB component values of the BMP image. RGB has a total of 24 bits, and 8 bits of data need to be filled to form 32 bits.
[0050] For bitmap RGB 10-bit single pixel storage, each pixel is stored in memory as 32 bits, where R[9:0], G[9:0], and B[9:0] are the RGB component values of the BMP image. RGB has a total of 30 bits, and 2 bits of data need to be filled to form 32 bits.
[0051] In the calculation module, if H / the second set value is an integer, then: R*(H / the second set value)*the first set value / the memory bit width; if H / the second set value is not an integer, then: R*(H / the second set value+1)*the first set value / the memory bit width; wherein H represents the number of row pixels, R represents the row number of pixels, R=0,1,2,...
[0052] The present invention also discloses a method for controlling a BMP image using an FPGA in a module signal generator. Using the method for storing BMP images in memory using the present invention, the FPGA calculates the starting address of each row of pixels in the BMP image stored in memory. Based on the obtained starting address, the FPGA implements movement and screen splitting of the BMP image. Movement includes flipping, horizontal movement, and vertical movement, while screen splitting includes various modes, including horizontal, vertical, and square-shaped splits.
[0053] For example, after calculating the starting address of each row of pixels in a BMP image stored in memory, the FPGA can easily implement the functions of moving and splitting the screen. For example, the image can be moved vertically (up / down). The current frame starts refreshing from row 0, the next frame starts refreshing from row x, and the next frame starts refreshing from row 2x, where x represents the step of movement per frame.
[0054] For example, after calculating the starting address of each row of pixels in the BMP image stored in the memory, the FPGA can realize the effect of moving the image, splitting the image into two vertical screens, the first split screen from row 0 to row r / 2-1, and the second split screen from row r / 2 to row r-1 (where r is the number of rows of the entire image). The split-screen operation can be completed based on a simple calculation of the starting address of each row of pixels stored in the memory.
[0055] The present invention also discloses a system for controlling BMP images using FPGA in a module signal generator. The system for storing BMP images in a memory using the FPGA of the present invention calculates the starting address of each row of pixels of the BMP image stored in the memory, and then, based on the obtained starting address, the FPGA realizes the movement and splitting of the BMP image.
[0056] The present invention can simultaneously meet different functional requirements such as high-resolution picture refresh bandwidth, movement, split screen, etc. under different resolutions, color depths, and refresh rates; through the present invention, FPGA logic code is simple to implement and consumes less logic resources.
[0057] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.
Claims
1. A method for managing and storing BMP pictures in a module signal generator using FPGA, characterized in that: The steps include: Storage adjustment step: fill and store each pixel in the BMP image according to the first set value, and fill and store the number of pixels in each row of the BMP image according to an integer multiple of the second set value, so that the pixel storage size of each row of the BMP image is an integer multiple of the FPGA memory interface; Calculation steps: Calculate the starting address of each row of pixels of the BMP image stored in the memory; the first setting value is 32 bits, and the second setting value is an integer multiple of 2 pixels; In the calculation step, the calculation formula for the starting address of each row of pixels of the Bmp picture stored in the memory is as follows: if H / the second set value is an integer, then: R*(H / the second set value)*the first set value / the memory bit width; if H / the second set value is not an integer, then: R*(H / the second set value+1)*the first set value / the memory bit width; wherein H represents the number of row pixels, R represents the row number of pixels, R=0,1,2,...; the method can simultaneously satisfy the storage of three types of pixels: RGB 6bit, 8bit, and 10bit; for the storage of a single pixel of RGB 6bit in the bitmap, each pixel is stored in the memory as 32bit, wherein R[5:0], G[5:0], and B[5:0] are the RGB component values of the Bmp picture, RGB has a total of 18bits, and 14bits of data need to be filled to form 32bits; For bitmap RGB 8-bit single pixel storage, each pixel is stored in memory as 32 bits, where R[7:0], G[7:0], B[7:0] are the RGB component values of the BMP image. RGB has a total of 24 bits, and 8 bits of data need to be filled to form 32 bits; For the bitmap RGB 10-bit single pixel storage, each pixel is stored in the memory as 32 bits, where R[9:0], G[9:0], and B[9:0] are the RGB component values of the BMP image. RGB has a total of 30 bits, and 2 bits of data need to be filled to form 32 bits.
2. A system for managing and storing BMP images in a module signal generator using FPGA, characterized in that: include: Storage adjustment module: used to fill and store each pixel in the BMP picture according to the first set value, and fill and store the number of pixels in each row of the BMP picture according to the integer multiple of the second set value, so that the pixel storage size of each row of the BMP picture is an integer multiple of the FPGA memory interface; Calculation module: used to calculate the starting address of each row of pixels of the BMP picture stored in the memory; the first setting value is 32 bits, and the second setting value is an integer multiple of 2 pixels; In the calculation module, the calculation formula for the starting address of each row of pixels of the BMP image stored in the memory is as follows: if H / the second set value is an integer, then: R*(H / the second set value)*the first set value / the memory bit width; if H / the second set value is not an integer, then: R*(H / the second set value+1)*the first set value / the memory bit width; wherein H represents the number of row pixels, R represents the row of pixels, R=0,1,2,...; the system can simultaneously satisfy the storage of three types of pixels: RGB 6bit, 8bit, and 10bit.
3. A method for controlling a BMP image using FPGA in a module signal generator, characterized in that: After calculating the starting address of each row of pixels of the BMP picture stored in the memory using the method described in claim 1, the FPGA realizes the movement and screen splitting of the BMP picture according to the obtained starting address.
4. A FPGA control system for BMP images in a module signal generator, characterized in that: After using the system described in claim 2 to calculate the starting address of each row of pixels of the BMP picture stored in the memory, the FPGA realizes the movement and screen splitting of the BMP picture according to the obtained starting address.