Solid-state imaging devices

Abstract

The solid-state imaging device includes a photoelectric conversion part configured to generate photocharges and a transmission gate that transmits the photocharges to a semiconductor region. The method for driving a unit pixel includes a step of accumulating photocharges in the photoelectric conversion part and a step of accumulating photocharges in the semiconductor region. The method for forming the solid-state imaging device includes injecting ions into a well layer through an opening in a mask, injecting additional ions into the well layer through an opening in another mask, and injecting other ions into the well layer through an opening in yet another mask. The electronic device includes a solid-state imaging device.

Description

[0001] This case is a divisional case of application number 201710400555.9, application date July 5, 2012, and titled “Solid-state imaging device, method for driving the same, and method for manufacturing the same”. Technical Field

[0002] The present technology relates to a solid-state imaging device, a method for driving a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an electronic device, and specifically to a solid-state imaging device that performs global exposure, a method for driving a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an electronic device. Background Art

[0003] In a solid-state imaging device, for example, a CMOS image sensor which is an XY address type solid-state imaging device, an operation of continuously scanning and reading out the photoelectric charge generated by the photoelectric conversion part and accumulated in the photoelectric conversion part is performed pixel by pixel or row by row. In the case of continuous scanning, in other words, if a rolling shutter is adopted as an electronic shutter, it is impossible to adapt the start time and end time of exposure for accumulating photoelectric charges in all pixels. Therefore, there is a problem that various distortions appear in the imaged image when imaging a moving subject with continuous scanning.

[0004] For sensing applications that require imaging of a subject moving at high speed and simultaneity of the imaged images (which cannot tolerate such image distortion), a global shutter that performs the start and end of exposure at the same time for all pixels in the pixel array section is adopted as an electronic shutter. In order to realize the global shutter, an embedded MOS capacitor, for example, is provided separately from a photodiode as a photoelectric conversion section as a region for accumulating photocharges, that is, a photocharge accumulation section (for example, refer to Patent Document 1).

[0005] However, in order for the embedded MOS capacitor to receive all the photoelectric charges generated by the photoelectric conversion in the photodiode and accumulated therein when the global shutter is operated, the embedded MOS capacitor needs to have a saturation charge amount equal to or greater than the saturation charge amount of the photodiode. On the contrary, considering them with the same unit pixel size, the area of ​​the photodiode is significantly reduced because of the presence of the embedded MOS capacitor in the unit pixel. Therefore, there is a problem of a reduction in the saturation charge amount of the photodiode.

[0006] As a measure against this problem, a technology for accumulating photoelectric charges generated by photoelectric conversion in a photodiode in both a photodiode and an embedded MOS capacitor has been proposed (for example, refer to Patent Document 2). According to the prior art, the saturation charge amount is the sum of the saturation charge amounts of the photodiode and the embedded MOS capacitor.

[0007] Citation List

[0008] Patent Documents

[0009] Patent Document 1: Japanese Patent No.3874135

[0010] Patent Document 2: Japanese Patent Application Laid-Open No. 2009-268083 Summary of the invention

[0011] Technical issues

[0012] However, even the prior art disclosed in Patent Document 2 is significantly worse in terms of saturation charge amount than a CMOS image sensor without a global shutter function. This is because it is necessary not only to add a photocharge accumulation part (an embedded MOS capacitor in the case of the prior art) but also to further add a transistor in a unit pixel to achieve global exposure. This results in a reduction in the dynamic range of the image.

[0013] In addition, in addition to the prior art for realizing the above-mentioned global exposure, it is easy to assume that a capacitor having a higher capacitance per unit area is used as a charge accumulation portion instead of an embedded MOS capacitor. However, a large amount of leakage current usually flows out of a capacitor having a high capacitance per unit area, and there is a problem that deterioration of characteristics in darkness, such as dark current or white spots, becomes significant.

[0014] In addition, if there is a change in the potential barrier of the overflow path of the pixel included in the solid-state imaging device in the above-mentioned pixel structure in which the photodiode and the memory part are integrated via the overflow path, the quality of the imaged image is reduced. Therefore, it is necessary to suppress the influence of the change in the potential barrier of the overflow path of the pixel included in the solid-state imaging device and improve the quality of the imaged image.

[0015] Therefore, the present technology can obtain an image with a wide dynamic range and low noise by utilizing global exposure.

[0016] Technical Effects

[0017] According to the first or second aspect of the present technology, an image with a wide dynamic range and low noise can be obtained by utilizing global exposure.

[0018] According to the third, fifth, and sixth aspects of the present technology, a high-quality image can be obtained. In addition, according to the fourth aspect of the present technology, a solid-state imaging device that obtains a high-quality image can be manufactured. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 : is a system block diagram showing an overview of the configuration of a CMOS image sensor to which the present technology is applied.

[0020] Figure 2: is a (first) system block diagram showing another system configuration of a CMOS image sensor to which the present technology is applied.

[0021] Figure 3 is a (second) system block diagram showing another system configuration of a CMOS image sensor to which the present technology is applied.

[0022] Figure 4 A and Figure 4 B is an explanatory diagram of an embedded MOS capacitor and a surface-side MOS capacitor.

[0023] Figure 5 A and Figure 5 B is an explanatory diagram of a combination of multiple capacitor structures.

[0024] Figure 6 A and Figure 6 B is a (first) cross-sectional view showing other configuration examples of the second charge accumulation portion.

[0025] Figure 7 A and Figure 7 B is a (second) cross-sectional view showing other configuration example of the second charge accumulation portion.

[0026] Figure 8 is a circuit diagram showing a circuit configuration of a unit pixel.

[0027] Fig. 9 is a schematic diagram showing a pixel structure of a unit pixel.

[0028] Fig.10 It is a timing diagram provided for the description of the circuit operation of a unit pixel.

[0029] Fig.11 is a (first) potential diagram provided for the description of the circuit operation of a unit pixel.

[0030] Fig.12 is a (second) potential diagram provided for the description of the circuit operation of a unit pixel.

[0031] Fig.13 is a (third) potential diagram provided for the description of the circuit operation of a unit pixel.

[0032] Fig.14 is a (fourth) potential diagram provided for the description of the circuit operation of a unit pixel.

[0033] Fig.15 is a (fifth) potential diagram provided for the description of the circuit operation of the unit pixel.

[0034] Fig.16 is a (sixth) potential diagram provided for the description of the circuit operation of a unit pixel.

[0035] Fig.17 is a (seventh) potential diagram provided for the description of the circuit operation of the unit pixel.

[0036] Fig.18 is an (eighth) potential diagram provided for the description of the circuit operation of a unit pixel.

[0037] Fig.19 is a circuit diagram showing a circuit configuration of Modification 1 of the unit pixel.

[0038] Fig. 20 is a circuit diagram showing a circuit configuration of Modification Example 2 of the unit pixel.

[0039] Fig.21 It is a timing chart provided for the description of the circuit operation of Modification Example 2 of the unit pixel.

[0040] Fig. 22 is a circuit diagram showing a circuit configuration according to specific example 1 of pixel sharing.

[0041] Fig.23 is a circuit diagram showing a circuit configuration according to specific example 2 of pixel sharing.

[0042] Fig.24 It is a potential diagram in the substrate depth direction provided for description of the requirement for the FD portion, the first charge accumulating portion, and the second charge accumulating portion to pin the substrate surface and couple potential.

[0043] Fig.25 It is a timing chart provided for the description of signal processing in the case of Processing Example 1 and Processing Example 2 in the signal processing unit.

[0044] Fig.26 is a (first) characteristic curve diagram of incident light amount-output provided for the description of signal processing in the case of Processing Example 3.

[0045] Fig. 27 27A and 27B are (second) characteristic curve graphs of incident light amount-output provided for the description of the case of Processing Example 3.

[0046] Fig.28 is a timing chart provided for the description of the circuit operation of the unit pixel according to the modification example.

[0047] Fig.29 A and Fig.29 B is a diagram for explaining the operation of a unit pixel according to a reference example.

[0048] Fig.30A configuration example of peripheral devices of a column processing unit, a signal processing unit, and a data storage unit for realizing a circuit operation of a long-time exposure is shown.

[0049] Fig.31 is a (first) timing diagram provided for the description of the circuit operation of a unit pixel with a long exposure time.

[0050] Fig.32 is a (second) timing diagram provided for the description of the circuit operation of the unit pixel with long-time exposure.

[0051] Fig.33 is a (first) potential diagram provided for the description of the circuit operation of a unit pixel with a long exposure time.

[0052] Fig.34 is a (second) potential diagram provided for the description of the circuit operation of a unit pixel with a long exposure time.

[0053] Fig.35 is a (third) potential diagram provided for the description of the circuit operation of a unit pixel with a long exposure time.

[0054] Fig.36 is a (fourth) potential diagram provided for the description of the circuit operation of a unit pixel with a long exposure time.

[0055] Fig.37 is a modification example of a timing chart provided for the description of the circuit operation of a unit pixel with long exposure time.

[0056] Fig.38 1 is a (first) timing chart provided for description of the circuit operation of Modification Example 2 of the unit pixel with long-time exposure.

[0057] Fig.39 is a (second) timing chart provided for description of the circuit operation of Modification Example 2 of the unit pixel with long-time exposure.

[0058] Fig.40 is a circuit diagram showing a circuit configuration of a unit pixel in which the second charge accumulation portion is omitted.

[0059] Fig.41 is a schematic diagram showing a pixel structure of a unit pixel in which the second charge accumulation portion is omitted.

[0060] Fig.42 It is a timing chart provided for the description of the circuit operation of the unit pixel in which the second electric charge accumulation portion is omitted.

[0061] Fig.43is a (first) potential diagram provided for the description of the circuit operation of the unit pixel in which the second electric charge accumulation portion is omitted.

[0062] Fig.44 is a (second) potential diagram provided for the description of the circuit operation of the unit pixel in which the second electric charge accumulation portion is omitted.

[0063] Fig.45 is a (third) potential diagram provided for the description of the circuit operation of the unit pixel in which the second electric charge accumulation portion is omitted.

[0064] Fig.46 is a (fourth) potential diagram provided for the description of the circuit operation of the unit pixel in which the second electric charge accumulation portion is omitted.

[0065] Fig.47 is a (fifth) potential diagram provided for the description of the circuit operation of the unit pixel in which the second electric charge accumulation portion is omitted.

[0066] Fig.48 is a (sixth) potential diagram provided for the description of the circuit operation of the unit pixel in which the second electric charge accumulation portion is omitted.

[0067] Fig.49 is a (seventh) potential diagram provided for the description of the circuit operation of the unit pixel in which the second electric charge accumulation portion is omitted.

[0068] Fig.50 is an (eighth) potential diagram provided for the description of the circuit operation of the unit pixel in which the second electric charge accumulation portion is omitted.

[0069] Fig.51 is a (first) timing chart provided for omitting the description of the circuit operation in which the unit pixel of the second charge accumulation portion is exposed for a long time.

[0070] Fig.52 is a (second) timing chart provided for omitting the description of the circuit operation in which the unit pixel of the second charge accumulation portion is exposed for a long time.

[0071] Fig.53 1 is a (first) potential diagram provided for the purpose of omitting the description of the circuit operation in which the unit pixel of the second charge accumulation portion is exposed for a long time.

[0072] Fig.54 1 is a (second) potential diagram provided for omitting the description of the circuit operation in which the unit pixel of the second charge accumulation portion is exposed for a long time.

[0073] Fig.551 is a (third) potential diagram provided for omitting the description of the circuit operation of the unit pixel of the third charge accumulation portion with long-time exposure.

[0074] Fig.56 1 is a (fourth) potential diagram provided for omitting the description of the circuit operation of the unit pixel of the fourth charge accumulation portion with long-time exposure.

[0075] Fig.57 is a diagram showing the structure of a known unit pixel.

[0076] Fig.58 is Fig.57 Potential diagram in the X direction.

[0077] Fig.59 (1) to Fig.59 (5) is a simplified diagram for explaining the exposure operation.

[0078] Fig.60 (1) to Fig.60 (5) is a simplified diagram for explaining the exposure operation.

[0079] Fig.61 is a timing diagram showing a method for driving a unit pixel.

[0080] Fig.62 A to Fig.62 C is a simple diagram explaining the problem to be solved.

[0081] Fig.63 Is a simple diagram that explains the problem to be solved.

[0082] Fig.64 A and Fig.64 B is shown Figure 1 A simplified diagram of the structure of a unit pixel used in a CMOS image sensor.

[0083] Fig.65 A and Fig.65 B is a diagram for explaining considerations for a unit pixel in the embodiment.

[0084] Fig.66 A to Fig.66 C is a simplified diagram for explaining considerations for a unit pixel in the embodiment.

[0085] Fig.67 is a potential diagram of a unit pixel in the embodiment.

[0086] Fig.68 A to Fig.68 C is a diagram for explaining the operation of accumulating photocharges in a unit pixel in the embodiment.

[0087] Fig.69is a diagram for explaining specific example 1 of a unit pixel.

[0088] Fig.70 is a diagram for explaining specific example 2 of a unit pixel.

[0089] Fig.71 is a simplified diagram explaining a method of manufacturing a unit pixel.

[0090] Fig.72 is a simplified diagram explaining a method of manufacturing a unit pixel.

[0091] Fig.73 is a schematic diagram showing another structure of a unit pixel.

[0092] Fig.74 A and Fig.74 B is a diagram showing another structure of a unit pixel.

[0093] Fig.75 is a schematic diagram showing another structure of a unit pixel.

[0094] Fig.76 is a diagram showing another configuration example of a unit pixel.

[0095] Fig.77 is a schematic block diagram of an electronic device according to an embodiment to which the present technology is applied. DETAILED DESCRIPTION

[0096] <1. Solid-state imaging devices to which this technology is applied>

[0097] [1-1. Basic system configuration]

[0098] Figure 1 This is a system block diagram showing an overview of the configuration of a solid-state imaging device to which the present technology is applied, for example, a CMOS image sensor as a type of XY address type solid-state imaging device. Here, the CMOS image sensor indicates an image sensor manufactured by applying or partially using a CMOS process.

[0099] The CMOS image sensor 10 according to the application example includes a pixel array unit 11 formed on a semiconductor substrate (chip) not shown, and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit 11. The peripheral circuit unit is configured by, for example, a vertical driving unit 12, a column processing unit 13, a horizontal driving unit 14, and a system control unit 15.

[0100] The CMOS image sensor 10 further includes a signal processing unit 18 and a data storage unit 19. The signal processing unit 18 and the data storage unit 19 may be mounted on the same substrate as the CMOS image sensor 10 or may be provided on a substrate different from the CMOS image sensor 10. In addition, the processing of the signal processing unit 18 and the data storage unit 19 may be performed by an external signal processing unit provided on a substrate different from the substrate of the CMOS image sensor 10, for example, a DSP (digital signal processor) circuit or software.

[0101] The pixel array unit 11 is configured so that unit pixels (hereinafter also referred to as "pixels") are arranged two-dimensionally in a row direction and a column direction, that is, in a matrix, wherein each unit pixel has a photoelectric conversion part for generating and accumulating photocharges according to the amount of light received. Here, the row direction indicates the arrangement direction of pixels on pixel rows (that is, the horizontal direction), and the column direction indicates the arrangement direction of pixels on pixel columns (that is, the vertical direction). The specific circuit configuration of the unit pixel and the details of the pixel structure will be described later.

[0102] In the pixel array unit 11, the pixel drive line 16 is wired along the row direction for each pixel row of the matrix pixel array, and the vertical signal line 17 is wired along the column direction for each pixel column. The pixel drive line 16 transmits a drive signal for driving when reading a signal from a pixel. Figure 1 , the pixel driving line 16 is shown as one line; however, the number of lines is not limited to one. One end of the pixel driving line 16 is connected to an output end corresponding to each row of the vertical driving unit 12.

[0103] The vertical driving unit 12 is configured by a shift register, an address decoder, etc. and drives all pixels of the pixel array unit 11 at the same time, or drives pixels in each row at a time, etc. In other words, the vertical driving unit 12 is configured as a driving unit that drives the pixels of the pixel array unit 11 together with the system control unit 15 that controls the vertical driving unit 12. Although illustration of a specific configuration of the vertical driving unit 12 is omitted, the vertical driving unit 12 generally includes two scanning systems, i.e., a reading scanning system and a sweep scanning system.

[0104] The read scanning system selectively scans the unit pixels of the pixel array unit 11 row by row in sequence to read signals from the unit pixels. The signals read from the unit pixels are analog signals. The sweeping scanning system performs a sweeping scan on the row to be read (on which the read scanning system is to perform a read scan) only for the time of the shutter speed before the read scanning.

[0105] By the sweeping scanning of the sweeping scanning system, unnecessary charges are swept away from the photoelectric conversion part of the unit pixel in the row to be read, and thus the photoelectric conversion part is reset. The unnecessary charges are swept away (reset) by the sweeping scanning system to perform the so-called electronic shutter operation. Here, the electronic shutter operation indicates an operation of discarding the photoelectric conversion part's photoelectric charges and newly starting exposure (starting accumulation of photoelectric charges).

[0106] The signal read by the reading operation of the reading scanning system corresponds to the amount of light received after the immediately preceding reading operation or the electronic shutter operation. The exposure time of the photocharge in the unit pixel is defined by the period from the reading timing of the immediately preceding reading operation or the sweeping timing of the electronic shutter operation to the reading timing of the current reading operation.

[0107] Signals output from unit pixels in a pixel row selectively scanned by the vertical drive unit 12 are input to the column processing unit 13 one pixel column at a time through each vertical signal line 17. The column processing unit 13 performs designated signal processing on signals output from pixels in the selected row through the vertical signal line 17 for each pixel column of the pixel array unit 11, and temporarily stores the pixel signals after the signal processing.

[0108] Specifically, the column processing unit 13 performs at least noise removal processing, for example, CDS (correlated double sampling) processing as signal processing. Reset noise unique to a pixel and fixed pattern noise such as a change in the threshold of an amplifier transistor in a pixel are removed by the CDS processing of the column processing unit 13. In addition to the noise removal processing, the column processing unit 13 may also have an AD (analog / digital) conversion function, for example, converting an analog pixel signal into a digital signal and outputting the digital signal.

[0109] The horizontal driving unit 14 is configured by a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns of the column processing unit 13. Through selective scanning by the horizontal driving unit 14, pixel signals for which signal processing has been performed by the column processing unit 13 for each unit circuit are sequentially output.

[0110] The system control unit 15 is configured by a timing generator that generates various timing signals and the like, and performs drive control of the vertical driving unit 12 , the column processing unit 13 , the horizontal driving unit 14 and the like based on the various timings generated by the timing generator.

[0111] The signal processing unit 18 has at least a calculation processing function and performs various signal processing such as calculation processing on the pixel signal output from the column processing unit 13. At the time of signal processing by the signal processing unit 18, the data storage unit 19 temporarily stores data necessary for the processing.

[0112] The CMOS image sensor 10 having the above configuration adopts global exposure that performs the start and end of exposure at the same timing with respect to all pixels in the pixel array unit 11. In other words, the CMOS image sensor 10 is capable of simultaneously exposing all pixels. This global exposure is performed by driving by a drive unit including a vertical drive unit 12 and a system control unit 15. The global shutter function that realizes global exposure is a shutter operation suitable for sensing applications that require imaging of a subject moving at high speed and simultaneity of the imaged images.

[0113] [1-2. Other system configuration]

[0114] The CMOS image sensor 10 to which the present technology is applied is not limited to the CMOS image sensor having the above-described system configuration. The following system configurations can be cited as other system configurations.

[0115] For example, Figure 2 As shown, a CMOS image sensor 10A having a system configuration in which a data storage unit 19 is placed in a subsequent stage of a column processing unit 13 to supply a pixel signal output from the column processing unit 13 to a signal processing unit 18 through the data storage unit 19 may be cited.

[0116] In addition, if Figure 3 As shown, a CMOS image sensor 10B having the following system configuration can be cited, in which the column processing unit 13 has an AD conversion function of performing AD conversion on each column or each plurality of columns of the pixel array unit 11, and a data storage unit 19 and a signal processing unit 18 are provided in parallel with the column processing unit 13.

[0117] <2. Description of Embodiment>

[0118] In order to realize global exposure, the solid-state imaging device (e.g., CMOS image sensor) according to the embodiment includes both the first and second charge accumulation parts in the unit pixel to ensure a larger saturation charge amount in darkness or under low light conditions without deteriorating the quality of the imaged image compared to the prior art realizing global exposure. In addition, an embedded MOS capacitor is used as the first charge accumulation part, and a capacitor having a higher unit area capacitance value than the first charge accumulation part is used as the second charge accumulation part.

[0119] It is preferable that the magnitude relationship of the saturation charge amounts should be set in the following manner for the first and second charge accumulation portions. In other words, it is preferable that the first charge accumulation portion should have a saturation charge amount smaller than the saturation charge amount of the photoelectric conversion portion.

[0120] When the saturation charge amount of the first charge accumulation part is set to be smaller than the saturation charge amount of the photoelectric conversion part, the difference is compensated by the second charge accumulation part. Therefore, when the saturation charge amount of the first charge accumulation part is added to the second charge accumulation part, it is necessary for the second charge accumulation part to have a saturation charge amount that is equal to or greater than the saturation charge amount of the photoelectric conversion part.

[0121] As described above, both the first and second charge accumulation parts are provided in a unit pixel, and an embedded MOS capacitor is used as the first charge accumulation part, while a capacitor having a higher unit area capacitance value than the first charge accumulation part is used as the second charge accumulation part; therefore, the following operations and effects can be obtained.

[0122] In other words, the capacitance value that can accumulate photocharges can be significantly increased, in other words, a larger saturation charge amount can be ensured compared to the case where an embedded MOS capacitor is formed over the same area as the total area of ​​the first and second charge accumulation parts. In addition, the embedded MOS capacitor is used for signals under low light conditions and is resistant to the influence of interface states, defects, etc. Compared with the prior art that realizes global exposure, the properties in the dark do not deteriorate. Therefore, the quality of the image imaged under low light conditions does not deteriorate.

[0123] As a result, a CMOS image sensor with a global shutter function that exhibits characteristics equivalent to those of a CMOS image sensor with the same unit pixel size but without a global shutter function can be realized. In addition, a CMOS image sensor that facilitates a significant expansion of the dynamic range compared to a known CMOS image sensor with the same unit pixel size and a global shutter function can be realized.

[0124] [2-1. Why can the total capacitance value of the charge accumulation part be increased by dividing the charge accumulation part]

[0125] In this way, an embedded MOS capacitor is used as the first charge accumulation part, and a capacitor having a higher capacitance per unit area than the first charge accumulation part is used as the second charge accumulation part; therefore, the total capacitance value of the charge accumulation part can be increased. Here, a description of the reason why the total capacitance value of the charge accumulation part can be increased will be given using a numerical example.

[0126] For example, consider forming a 1 μm 2 Assume that the capacitance per unit area of ​​the first charge accumulation portion is 1fF / μm 2 , the unit area capacitance value of the second charge accumulation part is 10fF / μm 2 , and has 1μm 2 The area of ​​the entire capacitor formed by the first charge accumulation portion has 1μm2 The capacitance value of the capacitor with an area of ​​1fF is 1fF.

[0127] At this time, if 1μm 2 If half of the area is replaced by the second charge accumulation portion, then the 2 The capacitance of a capacitor with an area of ​​5.5fF (=1 / 2μm 2 ×1fF+1 / 2μm 2 ×10fF). In other words, if half of the area is replaced by the second charge accumulation portion, a 1 μm 2 The capacitance value of the capacitor with the area of ​​​​the replacement is 5.5 times higher than that in the unreplaced case.

[0128] In addition, if 1μm 2 Three quarters of the area is replaced by the second charge accumulation portion, then the 1 μm 2 The capacitance value of the capacitor with the area of ​​​​1μm is 7.75fF, which is 7.75 times higher than that in the unreplaced case. 2 Half of the area is replaced by the second charge accumulation portion, assuming that the unit area capacitance value of the second charge accumulation portion is 20fF / μm 2 , then with 1μm 2 The capacitance value of the capacitor of the area is 10.5fF, which is 10.5 times higher than that of the unreplaced case.

[0129] On the other hand, a large amount of leakage current usually flows out from a capacitor having a high capacitance value per unit area, and there is a problem that the deterioration of characteristics in the dark, such as dark current or white spots, becomes noticeable for the second charge accumulation part. Therefore, when the photocharges of all pixels are transferred from the photoelectric conversion part at the same time, the photocharges under low light conditions are accumulated in the first charge accumulation part. Here, "photocharges under low light conditions" indicates photocharges that are equal to or less than the saturation charge amount of the first charge accumulation part. The first charge accumulation part is formed by an embedded capacitor, and therefore tolerates the influence of interface states, defects, etc., and has better properties in the dark than the second charge accumulation part.

[0130] In addition, photocharges under high light conditions are accumulated in both the first charge accumulation portion and the second accumulation capacitor. Here, "photocharges under high light conditions" indicates photocharges that exceed the saturation charge amount of the first charge accumulation portion. Under high light conditions with a large amount of charge, a high S / N can be guaranteed, so properties in the dark such as dark current or white spots are unlikely to have an impact. Therefore, even if photocharges under high light conditions are accumulated in the second charge accumulation portion from which a large amount of leakage current flows, the impact on image quality is minimal.

[0131] As is clear from the above description, by using an embedded MOS capacitor as the first charge accumulation portion and using a capacitor having a higher capacitance per unit area than the first charge accumulation portion as the second charge accumulation portion, a larger saturation charge amount can be ensured. Conversely, if an equal saturation charge amount is acceptable, a reduction in the unit pixel size can be promoted by the amount of space saved.

[0132] In addition, by accumulating photocharges under low-light conditions in a first charge accumulation portion, which has good properties in darkness such as dark current or white spots, and accumulating photocharges under high-light conditions in a second charge accumulation portion, which has poor properties in darkness, when all pixels are read out at the same time, the quality of images imaged in darkness or under low-light conditions does not deteriorate compared to the existing technology for achieving global exposure.

[0133] Examples of the capacitor having a higher capacitance value per unit area than the first charge accumulation portion, in other words, a capacitor having a higher capacitance value per unit area than the embedded MOS capacitor include a surface type MOS capacitor.

[0134] [2-2. Description of capacitor having high capacitance value per unit area]

[0135] Here, a description will be given of the difference between the embedded MOS capacitor configuring the first charge accumulation portion and, for example, the surface side MOS capacitor configuring the second charge accumulation portion.

[0136] Figure 4 A and Figure 4 B shows the embedded MOS capacitor A and the surface side MOS capacitor B. In addition, Figure 4 A and Figure 4 In B, (a) and (b) show the cross-sectional structure of each MOS capacitor and the equivalent circuit, respectively.

[0137] like Figure 4 A and Figure 4 As shown in FIG. 2B , a gate electrode 23 is provided on a semiconductor substrate 21 via a gate oxide film 22 in any MOS capacitor. In the case of an embedded MOS capacitor A, a charge accumulation region 24 for accumulating signal charges is formed deep in the semiconductor substrate 21, and in the case of a surface type MOS capacitor B, a charge accumulation region 25 is formed in the substrate surface of the semiconductor substrate 21.

[0138] exist Figure 4 A and Figure 4 In (b) of B, Cox represents the capacitance value of the gate oxide film 22, Cch represents the capacitance value between the substrate surface and the charge accumulation region, and Csi represents the capacitance value between the charge accumulation region and the substrate.

[0139] (In the case of an embedded capacitor)

[0140] Assuming that the capacitance value per unit area of the charge accumulation region 24 is Cb, the capacitance value Cb is represented by the following expression (1):

[0141] Cb = Cox·Cch / (Cox + Cch) + Csi = Cox·{1 / (1 + Cox / Cch)} + Csi...(1)

[0142] Here, assuming that the capacitance value Csi between the charge accumulation region and the substrate is sufficiently low, expression (1) can be approximated by the following expression (2):

[0143] Cb ≈ Cox·{1 / (1 + Cox / Cch)}...(2)

[0144] (In the case of a surface capacitor)

[0145] Assuming that the capacitance value per unit area of the charge accumulation region is Cs, the capacitance value Cs is represented by the following expression (3):

[0146] Cs = Cox + Csi...(3)

[0147] Here, assuming that the capacitance value Csi between the charge accumulation region and the substrate is sufficiently low, the capacitance value Cs can be approximated by the capacitance value Cox of the gate oxide film 22, as represented by the following expression (4):

[0148] Cs ≈ Cox...(4)

[0149] In other words, the numerical relationship between the capacitance value per unit area Cb of the charge accumulation region 24 and the capacitance value per unit area Cs of the charge accumulation region 25 is Cb < Cs, and the capacitance value decreases by burying the charge accumulation region in the substrate instead of the substrate surface. Conversely, the capacitance value increases by bringing the charge accumulation region from the inside of the substrate to the surface of the substrate.

[0150] (Description of a method for increasing the capacitance value per unit area from a material perspective)

[0151] The capacitance value Cox per unit area of the gate oxide film 22 is represented by the following expression (5):

[0152] Cox = εox / tox...(5)

[0153] where εox is the permittivity of the gate oxide film 22, and tox is the film thickness of the gate oxide film 22.

[0154] Although the film thickness tox of the gate oxide film 22 is important from the viewpoint of withstand voltage and leakage, even if the film thickness is equal, the capacitance value Cox per unit area can be increased by using a material having a high permittivity. Materials having a high permittivity include, for example, the following materials:

[0155] Si3N4: relative permittivity 7

[0156] Ta2O5: relative permittivity 26

[0157] HfO2: relative permittivity 25

[0158] ZrO2: relative permittivity 25

[0159] Since the product of the vacuum permittivity and the relative permittivity is the permittivity of each material, if the ratio of the relative permittivity to SiO2 (relative permittivity 3.9) is considered, the increase in the capacitance per unit area can be estimated. For example, if a surface MOS capacitor is assumed and Si3N4 having the same film thickness is used instead of SiO2, the capacitance per unit area increases by 1.8 times, and if Ta2O5 is used, the capacitance per unit area increases by 6.7 times.

[0160] (Description of a method for increasing capacitance per unit area from a structural perspective)

[0161] In addition, from a structural perspective, the capacitance per unit area can be increased by combining multiple capacitor structures. Examples of combined structures include Figure 5 A and Figure 5 The structure shown in B, in other words, the structure A in which a planar MOS capacitor and a junction capacitor are combined and the structure B in which a planar MOS capacitor and a stacked capacitor are combined.

[0162] First, a description of the combined structure A will be given. For example, a P-type well 52 is formed on an N-type semiconductor substrate 51. An N+ type semiconductor region 41 serving as an intermediate electrode is formed on a surface layer portion of the P-type well 52 to form a junction MOS capacitor between the P-type well 52 serving as a lower electrode. In addition, an upper electrode 42 is provided on the substrate surface via an insulating film 53 to form a planar MOS capacitor in parallel with the junction MOS capacitor. In short, the second charge accumulation portion 40 is formed in parallel connection between the planar MOS capacitor and the junction capacitor.

[0163] Next, a description will be given of the combined structure B. The first charge accumulation portion 30 is a planar MOS capacitor as in the case of the combined structure A. The second charge accumulation portion 40 includes a planar MOS capacitor formed in a region partitioned by the element isolation insulating films 55 and 56 and a stacked capacitor formed in parallel connection in a further upper layer.

[0164] Specifically, a P+ (or N+) type semiconductor region 43 serving as a lower electrode is formed in the surface layer portion of the P-type well 52, and an intermediate electrode 45 is formed on the semiconductor region 43 via a capacitor insulating film 44. This structure is a structure of a planar MOS capacitor. In addition, an upper electrode 47 is formed on the intermediate electrode 45 via a capacitor insulating film 46. This structure is a structure of a stacked capacitor. The intermediate electrode 45 is electrically connected to the N+ type semiconductor region 41 by wiring 57.

[0165] According to the combined structure B, in other words, according to the combined structure of the planar MOS capacitor and the stacked capacitor, a capacitor having a higher capacitance value per unit area can be formed.

[0166] (Other Structural Examples of Second Charge Accumulating Section)

[0167] Figure 6 A. Figure 6 B. Figure 7 A and Figure 7 B shows another structural example of the second charge accumulation portion 40. Figure 6 A. Figure 6 B. Figure 7 A and Figure 7 B, the same reference numerals are assigned to indicate Figure 5 A and Figure 5 The same part as in B.

[0168] Figure 6 A is a cross-sectional view showing the structure of a planar MOS capacitor. The planar MOS capacitor configuring the second charge accumulation portion 40 has a structure in which a P+ (or N+) type semiconductor region 43 serving as a lower electrode is formed in a surface layer portion of a P-type well 52 and an upper electrode 45 is formed on the semiconductor region 43 via a capacitor insulating film 44.

[0169] Figure 6 B is a cross-sectional view showing the structure of the stacked capacitor 1. The stacked capacitor 1 configuring the second charge accumulation portion 40 has a structure in which a lower electrode 45 is formed on an element isolation insulating film 55 and an upper electrode 47 is formed on the lower electrode 45 via a capacitor insulating film 46.

[0170] Figure 7A is a cross-sectional view showing the structure of the stacked capacitor 2. The stacked capacitor 2 configuring the second charge accumulation portion 40 has a structure in which a lower electrode 45 having a U-shaped cross section is electrically connected to the N+ type semiconductor region 41 and an upper electrode 47 is inserted inside the lower electrode 45 via a capacitor insulating film 46.

[0171] In the case of the structure of the stacked capacitor 2, a power supply voltage is applied to the upper electrode 47, or the upper electrode 47 is grounded. According to the stacked capacitor 2 including the lower electrode 45 having a U-shaped cross section and the upper electrode 47 embedded inside the intermediate electrode 45, it is advantageous to have a larger relative area to contribute to the capacitance value than a conventional stacked capacitor such as the stacked capacitor 1.

[0172] Figure 7 B is a cross-sectional view showing the structure of a trench capacitor. The trench capacitor configuring the second charge accumulation portion 40 is formed such that a trench 48 is formed in such a manner as to pass through the P-type well 52 up to the substrate 51 and a capacitor is formed in the trench 48.

[0173] Specifically, the trench capacitor has the following structure: an N+ (or P+) type semiconductor region 43 serving as a lower electrode is formed in the inner wall of a trench 48, the inner wall of the semiconductor region 43 is covered by a capacitor insulating film 44, and an upper electrode 45 is embedded via the capacitor insulating film 44.

[0174] In addition, the second charge accumulation portion 40 is configured by a planar MOS capacitor, a junction capacitor, a stacked capacitor or a trench capacitor, wherein a part or all of the capacitor insulating film is configured by a material having a higher permittivity than a silicon dioxide film or a combination thereof. The material having a higher permittivity than a silicon dioxide film (SiO2) includes Si3N4, Ta2O5, HfO2, and ZrO2.

[0175] As mentioned above, based on Figure 6 A. Figure 6 B. Figure 7 A and Figure 7 B gives a description of examples of the structure of the second charge accumulation portion 40. However, the structure of the second charge accumulation portion 40 is not limited to these structural examples, and various methods developed until now to increase the capacitance for the storage capacitor of the DRAM may be adopted.

[0176] <3. Example 1>

[0177] A description will be given below of a specific example of a unit pixel including the first charge accumulation portion 30 and the second charge accumulation portion 40 in the pixel.

[0178] Throughout the specification, the first charge accumulation portion 66 corresponds to the above-described first charge accumulation portion 30 and the second charge accumulation portion 67 corresponds to the above-described second charge accumulation portion 40 .

[0179] (Circuit Configuration of Unit Pixel 60A)

[0180] Figure 8 is a circuit diagram showing a circuit configuration of a unit pixel 60A to which the present technology is applied. Figure 8 As shown, the unit pixel 60A includes, for example, a photodiode 61 having a pn junction as a photoelectric conversion portion that receives light to generate and accumulate photocharges. The photodiode 61 generates and accumulates photocharges according to the amount of received light.

[0181] The unit pixel 60A further includes, for example, a first transfer gate section 62, a second transfer gate section 63, a third transfer gate section 64, a reset gate section 65, a first charge accumulation section 66, a second charge accumulation section 67, an amplification transistor 68, a selection transistor 69 and a charge drain gate section 70.

[0182] In the unit pixel 60A having the above-described configuration, the first and second charge accumulation portions 66 and 67 correspond to the above-described first and second charge accumulation portions 30 and 40. In other words, from the perspective of the circuit, the first charge accumulation portion 66 is provided as an embedded MOS capacitor between the first transfer gate portion 62 and the second transfer gate portion 63. A drive signal SG (hereinafter also referred to as a transfer signal SG) is applied to the gate electrode of the first charge accumulation portion 66. The second charge accumulation portion 67 is configured by a capacitor having a higher capacitance per unit area than the first charge accumulation portion 66. Details of the layout and cross-sectional structure of the first and second charge accumulation portions 66 and 67 will be described later.

[0183] As Figure 1 The pixel drive lines 16 in the embodiment, for example, a plurality of drive lines are connected to the unit pixels 60A in each pixel row. Figure 1 The vertical driving unit 12 in the embodiment provides various driving signals TG, SG, FG, CG, RST, SEL and PG via a plurality of driving lines of the pixel driving line 16. In the above configuration, the transistors are NMOS transistors, so these driving signals TG, SG, FG, CG, RST, SEL and PG are pulse signals that are at a high level (e.g., the power supply voltage V DD ) becomes active at a low level (e.g., a negative potential) and becomes inactive at a low level (e.g., a negative potential).

[0184] The drive signal TG is applied as a transfer signal to the gate electrode of the first transfer gate portion 62. From the viewpoint of the circuit, the first transfer gate portion 62 is connected between the photodiode 61 and the first charge accumulation portion 66. When the drive signal TG (hereinafter also referred to as the transfer signal TG) becomes active, then the first transfer gate portion 62 establishes electrical continuity in response thereto, thereby transferring the photocharge accumulated in the photodiode 61 to the first charge accumulation portion 66. The photocharge transferred by the first transfer gate portion 62 is temporarily accumulated in the first charge accumulation portion 66.

[0185] The drive signal FG is applied as a transfer signal to the gate electrode of the second transfer gate portion 63. From the perspective of the circuit, the second transfer gate portion 63 is connected between the first charge accumulation portion 66 and the floating diffusion portion (hereinafter described as "FD portion") 71 to which the gate electrode of the amplification transistor 68 is connected. The FD portion 71 converts the photocharge into an electrical signal, for example, a voltage signal, and outputs the signal. When the drive signal FG (hereinafter also referred to as the transfer signal FG) becomes active, the second transfer gate portion 63 then establishes electrical continuity in response thereto, thereby transferring the photocharge accumulated in the first charge accumulation portion 66 to the FD portion 71.

[0186] The drive signal CG is applied as a transfer signal to the gate electrode of the third transfer gate portion 64. From the perspective of the circuit, the third transfer gate portion 64 is connected between the first charge accumulation portion 66 and the second charge accumulation portion 67. When the drive signal CG (hereinafter also referred to as the transfer signal CG) becomes active, the third transfer gate portion 64 then establishes electrical continuity in response thereto, thereby coupling the potentials of the first charge accumulation portion 66 and the second charge accumulation portion 67.

[0187] The driving signal RST is applied as a reset signal to the gate electrode of the reset gate portion 65. From the circuit point of view, one source / drain region of the reset gate portion 65 is connected to the reset voltage V DR , and the other source / drain region is connected to the FD portion 71. When the drive signal RST (hereinafter also referred to as the reset signal RST) becomes active, the reset gate portion 65 then establishes electrical continuity in response thereto, thereby resetting the potential of the FD portion 71 to the reset voltage V DR level.

[0188] From the circuit point of view, the gate electrode of the amplifying transistor 68 is connected to the FD portion 71, and the drain electrode thereof is connected to the power supply voltage V DD, and the amplifier transistor 68 is used as an input part of a reading circuit (referred to as a source follower circuit) that reads the photocharge obtained by the photoelectric conversion of the photodiode 61. In other words, the source electrode of the amplifier transistor 68 is connected to the vertical signal line 17 via the selection transistor 69, and the amplifier transistor 68 configures the source follower circuit with the constant current source 80 connected to one end of the vertical signal line 17.

[0189] The drive signal SEL is applied as a selection signal to the gate electrode of the selection transistor 69. From the perspective of the circuit, the selection transistor 69 is connected between the source electrode of the amplification transistor 68 and the vertical signal line 17. When the drive signal SEL (hereinafter also referred to as the selection signal SEL) becomes active, the selection transistor 69 then establishes electrical continuity in response thereto, thereby making the unit pixel 60A a selected state and connecting the pixel signal output from the amplification transistor 68 to the vertical signal line 17.

[0190] The driving signal PG is applied as a charge drain control signal to the gate electrode of the charge drain gate portion 70. From the circuit point of view, the charge drain gate portion 70 is connected between the photodiode 61 and the charge drain portion (for example, the power supply voltage V DD ). When the driving signal PG (hereinafter also referred to as the charge drain control signal PG) becomes active, the charge drain gate portion 70 then establishes electrical continuity in response thereto, thereby selectively draining a preset specified amount or all of the photocharges accumulated in the photodiode 61 from the photodiode 61 to the charge drain portion.

[0191] The charge leakage gate portion 70 is provided for the following purpose. In other words, the purpose is to prevent the photodiode 61 from being saturated with photocharges and photocharges exceeding the saturated charge amount from overflowing to the first and second charge accumulation portions 66 and 67 and surrounding pixels, which is caused by turning on the charge leakage gate portion 70 during a period during which photocharges are not accumulated.

[0192] (Pixel Structure of Unit Pixel 60A)

[0193] Fig. 9 is a schematic diagram showing a pixel structure of a unit pixel 60A, and Fig. 9 The same reference numerals are assigned to indicate Figure 8 The same part. Fig. 9 A plane pattern of a pixel layout and cross-sectional portions of the plane pattern taken along arrow AA' and arrow BB', respectively, are shown.

[0194] exist Fig. 9, as is clearly seen from the cross-sectional view taken along arrow BB', the photodiode (PD) 61 has a structure of a diode including a pn junction in which an N-type semiconductor region 611 is formed in a P-type well 52 of a semiconductor substrate 51. The photodiode 61 includes a P-type semiconductor region 612 formed in a surface layer portion thereof, and is therefore an embedded photodiode in which a depletion end is separated from an interface (a so-called HAD (hole accumulation diode) sensor structure).

[0195] The first transfer gate portion 62 includes a gate electrode 621 provided on the surface of the substrate via a gate insulating film (not shown) and a P-type semiconductor region 622 formed in a surface layer portion of the substrate. The P-type semiconductor region 622 has a potential slightly deeper under the gate electrode 621 than in the case where the semiconductor region 622 is not formed. Therefore, as is clear from the cross-sectional view taken along arrow BB', the P-type semiconductor region 622 forms an overflow path that transfers photocharges equal to or greater than a specified amount, or specifically, photocharges exceeding the saturation charge amount of the photodiode 61, overflowing from the photodiode 61, to the first charge accumulation portion 66.

[0196] The first charge accumulation portion 66 includes a gate electrode 661 provided on the surface of the substrate via a gate insulating film (not shown), and is formed as an embedded MOS capacitor under the gate electrode 661. In other words, the first charge accumulation portion 66 is configured by an embedded MOS capacitor including an N-type semiconductor region 662 formed in the P-type well 52 under the gate electrode 661 and a P-type semiconductor region 663 formed in a surface layer portion thereof.

[0197] The second transfer gate portion 63 includes a gate electrode 631 provided on the substrate surface via a gate insulating film (not shown). The second transfer gate portion 63 has the N-type semiconductor region 662 of the first charge accumulation portion 66 as one source / drain region, and the N+ type semiconductor region 711 used as the FD portion 71 as another source / drain region.

[0198] Therefore, the unit pixel 60A has a pixel structure in which the first charge accumulation portion 66 is formed as an embedded MOS capacitor under the gate electrode 661 formed adjacent to the first and second transfer gate portions 62 and 63 .

[0199] The third transfer gate portion 64 includes a gate electrode 641 provided on the substrate surface via a gate insulating film (not shown). The third transfer gate portion 64 has the N-type semiconductor region 662 of the first charge accumulation portion 66 as one source / drain region, and the N+ type semiconductor region 642 formed in the substrate surface layer portion as another source / drain region.

[0200] The N+ type semiconductor region 642 of the third transfer gate portion 64 is electrically connected to one end of the second charge accumulation portion 67. The other end of the second charge accumulation portion 67 is connected to a negative side power source (eg, ground).

[0201] The second transfer gate portion 63 , the gate electrode 661 of the first charge accumulation portion 66 , and the third transfer gate portion 64 operate to couple or divide the potentials of the FD portion 71 , the first charge accumulation portion 66 , and the second charge accumulation portion 67 .

[0202] In addition, the third transfer gate portion 64 has a structure in which an N-type semiconductor region 643 is formed in a surface layer portion of the channel portion. The N-type semiconductor region 643 has a potential slightly deeper than that in the case where the semiconductor region 643 is not formed under the gate electrode 641. Therefore, as is clearly seen from the cross-sectional view taken along the arrow A-A', the N-type semiconductor region 643 forms an overflow path for transferring the photocharge exceeding the saturation charge amount of the first charge accumulation portion 66 to the second charge accumulation portion 67.

[0203] Here, it is important that the overflow path formed under the first and third transfer gate portions 62 and 64 should be formed so that the photocharges accumulated in the first charge accumulation portion 66 do not leak to the photodiode 61 but are transferred to the second charge accumulation portion 67 .

[0204] In this manner, the unit pixel 60A has an overflow path below the gate electrode 641 of the third transfer gate portion 64; therefore, the photocharges overflowing from the photodiode 61 under the high light condition can be accumulated also in the second charge accumulation portion 67. Specifically, even if the third transfer gate portion 64 is not turned on, the photocharges equal to or greater than a specified amount overflowing from the first charge accumulation portion 66 can be transferred to the second charge accumulation portion 67 and accumulated in the second charge accumulation portion 67. Therefore, the saturation charge amount of the first charge accumulation portion can be set to be smaller than the saturation charge amount of the photodiode 61.

[0205] (Circuit Operation of Unit Pixel 60A)

[0206] Next, we will refer to Fig.10 The timing diagram and Figures 11 to 18 A description is given of the circuit operation of the unit pixel 60A by means of a potential diagram.

[0207] Fig.10 1 shows a timing diagram of the selection signal SEL, the reset signal RST, the transfer signal TG, the charge drain control signal PG, the transfer signal CG, the transfer signal SG, and the transfer signal FG of the unit pixel 60A. Figures 11 to 18 Shown in Fig.10 The timing diagram shows the state of the potential of the unit pixel 60A in the Nth row from time ta to th.

[0208] First, at time t1, while the charge drain control signal PG remains active, the selection signal SEL, the reset signal RST, the transfer signal CG, the transfer signal SG, and the transfer signal FG become active simultaneously in all pixels. Therefore, the selection transistor 69, the reset gate portion 65, the third transfer gate portion 64, the gate electrode 661 of the first charge accumulation portion 66, the second transfer gate portion 63, and the charge drain gate portion 70 establish electrical continuity.

[0209] Fig.11 The state of the potential of the unit pixel 60A at time ta between time t1 and time t2 is shown. In this way, the potentials of the FD portion 71, the first charge accumulation portion 66, and the second charge accumulation portion 67 are coupled, and the coupled regions are reset.

[0210] Subsequently, the reset signal RST, the selection signal SEL, the transfer signal FG, the transfer signal SG and the transfer signal CG become inactive in all pixels simultaneously in this order. At time t2, the charge drain control signal PG then becomes inactive in all pixels simultaneously. Thus, an exposure period common to all pixels begins.

[0211] Fig.12 The state of the potential of the unit pixel 60A at time tb between time t2 and time t3 is shown. In this way, although the photocharge is accumulated in the photodiode 61, if it is under high light conditions, the photocharge overflowing from the photodiode 61 is also accumulated in the first charge accumulation portion 66 via the overflow path of the first transfer gate portion 62. In addition, if the first charge accumulation portion 66 is saturated, the photocharge overflowing from the first charge accumulation portion 66 is accumulated in the second charge accumulation portion 67 via the overflow path of the third transfer gate portion 64. If it is under low light conditions, the photocharge is accumulated only in the photodiode 61.

[0212] Next, at time t3 , the transfer signal TG and the transfer signal SG become active and the first transfer gate portion 62 and the gate electrode 661 of the first charge accumulation portion 66 establish electrical continuity.

[0213] Fig.13 The state of the potential of the unit pixel 60A at time tc between time t3 and time t4 is shown. In this way, the light charges accumulated in the photodiode 61 are transferred to the first charge accumulation portion 66 and accumulated in the first charge accumulation portion 66.

[0214] Next, at time t4, in all pixels, the transfer signal TG becomes inactive and simultaneously the charge drain control signal PG becomes active. The first transfer gate portion 62 then breaks electrical continuity and simultaneously the charge drain gate portion 70 establishes electrical continuity. Thus, the exposure period common to all pixels ends.

[0215] Subsequently, the transfer signal SG also becomes inactive, and the gate electrode 661 of the first charge accumulation portion 66 breaks the electrical continuity, so the potential of the first charge accumulation portion 66 is restored to its initial level. At this time, if the accumulated charge amount of the first charge accumulation portion 66 exceeds the saturation charge amount, the photocharge overflowed from the first charge accumulation portion 66 is transferred to the second charge accumulation portion 67 via the overflow path of the third transfer gate portion 64.

[0216] After the exposure time common to all pixels ends, the accumulated photocharges are read out sequentially row by row.

[0217] Specifically, at time t5, the selection signal SEL in the Nth row becomes active, and the selection transistor 69 in the Nth row establishes electrical continuity, thereby making the unit pixel 60A in the Nth row a selected state. At the same time, the reset signal RST becomes active and the reset gate portion 65 establishes electrical continuity, thereby resetting the FD portion 71. At time t6, the reset signal RST then becomes inactive.

[0218] Fig.14 The state of the potential of the unit pixel 60A at time td between time t6 and time t7 is shown. The potential of the FD portion 71 in this state is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as the first reset level N1.

[0219] Next, at time t7 , the transfer signal FG becomes active, and thus the second transmission gate portion 63 establishes electrical continuity.

[0220] Fig.15 The state of the potential of the unit pixel 60A at time te between time t7 and time t8 is shown. In this way, the light charges accumulated in the first charge accumulation portion 66 are transferred to the FD portion 71.

[0221] Next, at time t8, the transfer signal FG becomes inactive, and the second transmission gate portion 63 breaks the electrical continuity.

[0222] Fig.16 The potential of the FD portion 71 in this state is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as a first signal level S1 according to the accumulated charge amount of the first charge accumulation portion 66.

[0223] Next, at time t9, the transfer signals CG, SG, and FG become active at the same time, and the third transfer gate portion 64, the gate electrode 661 of the first charge accumulation portion 66, and the second transfer gate portion 63 establish electrical continuity together.

[0224] Fig.17 The state of the potential of the unit pixel 60A at time tg between time t9 and time t10 is shown. In this way, the potentials of the FD portion 71, the first charge accumulation portion 66, and the second charge accumulation portion 67 are coupled, and light charges are accumulated over the entire coupled region. The light charges are output to the vertical signal line 17 as a second signal level S2 through the amplification transistor 68 and the selection transistor 69.

[0225] Next, at time t10, the reset signal RST becomes active, and electrical continuity is established with the reset gate portion 65. Thus, the region in which the potentials of the FD portion 71, the first charge accumulation portion 66, and the second charge accumulation portion 67 are coupled is reset.

[0226] Next, at time t11 , the reset signal becomes inactive, and the reset gate portion 65 breaks the electrical continuity.

[0227] Fig.18 The state of the potential of the unit pixel 60A at time th between time t11 and time t12 is shown. In this state, the potential of the potential coupling region is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as the second reset level N2.

[0228] Next, at time t12, the selection signal SEL in the Nth row becomes inactive, and the selection transistor 69 in the Nth row breaks the electrical continuity, thus making the unit pixel 60A in the Nth row a non-selected state.

[0229] Subsequently, the transfer signal FG, the transfer signal SG, and the transfer signal CG are made inactive in this order, and the second transfer gate portion 63, the gate electrode 661 of the first charge accumulation portion 66, and the third transfer gate portion 64 break electrical continuity.

[0230] The reason why the transfer signal FG, the transfer signal SG, and the transfer signal CG are made inactive in this order is that the channel charges accumulated in the substrate surface in the state where the gate electrode 661 of the first charge accumulation portion 66 is turned on are accumulated in the second charge accumulation portion 67. Unlike the FD portion 71, the second charge accumulation portion 67 is not reset separately; therefore, there is no concern such as an offset occurring in the pixel signal by resetting the channel charges.

[0231] Through the above series of circuit operations, the first reset level N1, the first signal level S1, the second signal level S2, and the second reset level N2 are sequentially output from the unit pixel 60A to the vertical signal line 17. A designated signal processing is performed in a signal processing unit at a later stage with respect to the first reset level N1, the first signal level S1, the second signal level S2, and the second reset level N2 sequentially output in this manner. The details of the signal processing will be described later.

[0232] As described above, according to the unit pixel 60A, a larger saturation charge amount can be ensured by using an embedded MOS capacitor as the first charge accumulation portion 66 and using a capacitor having a higher capacitance per unit area than the first charge accumulation portion 66 as the second charge accumulation portion 67. Conversely, if an equal saturation charge amount is acceptable, a reduction in the size of the unit pixel can be promoted by the amount of space saved.

[0233] In addition, when all pixels are read out at the same time, photocharges under low light conditions are accumulated in the first charge accumulation portion 66 having good properties in the dark, and photocharges under high light conditions are accumulated in the second charge accumulation portion 67 having poor properties in the dark. Therefore, compared with the prior art for achieving global exposure, the quality of an image imaged in the dark or under low light conditions is not deteriorated.

[0234] (Revision 1)

[0235] Fig.19 1 is a circuit diagram showing a circuit configuration of a unit pixel 60A1 according to a modification example 1 of the unit pixel 60A, and the same reference numerals are assigned in the figure to indicate the circuit configuration of the unit pixel 60A1 according to the modification example 1 of the unit pixel 60A. Figure 8 The same part.

[0236] The unit pixel 60A1 according to Modification 1 is different from the unit pixel 60A in that the charge drain gate portion 70 is omitted.

[0237] For example, if, during a period in which photocharges are not accumulated, saturation of the photodiode 61 is prevented in another way or there is no possibility that the photodiode 61 is saturated with photocharges, the charge leakage gate portion 70 may be omitted in this manner.

[0238] (Revision 2)

[0239] Fig. 20 60A2 according to Modification Example 2 of the unit pixel 60A, and the same reference numerals are assigned in the figure to indicate the circuit configuration of the unit pixel 60A2 according to Modification Example 2 of the unit pixel 60A. Figure 8 The same part.

[0240] The unit pixel 60A2 according to the modification 2 is different from the unit pixel 60A in that the selection transistor 69 is omitted. In addition, the unit pixel 60A2 realizes a function of selecting a pixel with the selection transistor 69 by making the drain voltage DRN to be applied to the drain electrode of the reset gate portion 65 variable.

[0241] Specifically, a high voltage is applied as a drain voltage DRN to the drain electrode of the reset gate portion 65; therefore, the amplifying transistor 68 becomes active to perform an operation of outputting a signal. In other words, the amplifying transistor 68 operates as a selection transistor in cooperation with the switching operation of the drain voltage DRN. By omitting the selection transistor 69, there is an advantage that the number of circuit elements configuring the unit pixel 60 can be reduced by one element per pixel.

[0242] Fig.21 is shown similar to Fig.10 A timing diagram of the states of signals with respect to the circuit operation of the unit pixel 60A2.

[0243] The circuit operation is basically the same as that of the unit pixel 60A, and only the timing of the reset signal RST is different.

[0244] (Pixel Sharing)

[0245] In the unit pixels 60A, 60A1, and 60A2, circuit elements configuring the pixel may be shared among a plurality of pixels.

[0246] Fig. 22 is a circuit diagram showing a circuit configuration according to a specific example 1 of pixel sharing. Here, as an example, a case where a part of a pixel constituent element is shared between four pixels 60A-1 to 60A-4 adjacent to each other is cited. However, the number of shared pixels is not limited to four pixels. In addition, as a relationship of four adjacent pixels 60A-1 to 60A-4, for example, sharing can be performed between four pixels including two pixels in the row direction and two pixels in the column direction, or four pixels in the column direction.

[0247] In the specific example 1, the pixel sharing of the pixel configuration of the unit pixel 60A is cited as an example. The circuit elements after the FD portion 71 including the reset gate portion 65, in other words, the three circuit elements of the reset gate portion 65, the amplification transistor 68 and the selection transistor 69 are shared among four pixels.

[0248] Fig.23is a circuit diagram showing a circuit configuration according to a specific example 2 of pixel sharing. Also here, cited as an example is a case where a part of a pixel constituent element is provided between four pixels 60A-1 to 60A-4 adjacent to each other. However, the number of shared pixels is not limited to four pixels. In addition, as a relationship of the adjacent four pixels 60A-1 to 60A-4, for example, sharing can be performed between four pixels including two pixels in the row direction and two pixels in the column direction, or four pixels in the column direction.

[0249] In Specific Example 2, pixel sharing in the case of the pixel configuration of the unit pixel 60A2 according to Modification 2 is cited as an example. The circuit elements after the FD portion 71 including the reset gate portion 65, in other words, two circuit elements of the reset gate portion 65 and the amplification transistor 68 are shared among four pixels.

[0250] In this way, the use of technology for sharing circuit elements between multiple pixels makes it possible to promote space saving of unit pixel size in addition to obtaining operations and effects similar to unit pixel 60A. In addition, due to the space saving, a larger saturation charge amount can be guaranteed. Conversely, if equal saturation charge amounts are acceptable, the reduction of unit pixel size can be promoted by the amount of space saved.

[0251] Here, a description will be given of the potentials of the first to third transfer gate portions 62 to 64 and the gate electrode 661 of the first charge accumulation portion 66. Fig.24 It is a potential diagram in the substrate depth direction provided for description of requirements for setting and coupling the potentials of the FD portion 71, the first charge accumulation portion 66, and the second charge accumulation portion 67 at the pins on the substrate surface.

[0252] The potentials of the gate electrodes in the non-conductive state of the first to third transfer gate portions 62 to 64 and the gate electrode 661 of the first charge accumulation portion 66 are set to a potential that makes the substrate surface pinned (for example, negative potential) regardless of the conductive layer immediately below the gate oxide film. The substrate surface is pinned in this manner, and the effect of improving properties in the dark such as dark current or white spots can be obtained.

[0253] Ratio of reset voltage V DR A higher potential, in other words, a potential applied to the drain of the reset gate portion 65 is set in such a manner that the potential of the substrate surface and the gate electrode 661 of the first charge accumulation portion 66 are in the on-state of the second and third transfer gate portions 63 and 64. This makes it possible to couple the potentials of the FD portion 71, the first charge accumulation portion 66, and the second charge accumulation portion 67.

[0254] <4. Description of Noise Removal Processing and Calculation Processing>

[0255] The first reset level N1, the first signal level S1, the second signal level S2, and the second reset level N2 are output in this order from the unit pixel 60A and the unit pixel according to the modification thereof as described above to the vertical signal line 17. In the signal processing unit at the subsequent stage, for example, Figures 1 to 3 In the column processing unit 13 and the signal processing unit 18 shown in FIG. 1 , the specified noise removal processing and signal processing are performed with respect to the first reset level N1, the first signal level S1, the second signal level S2, and the second reset level N2. A description will be given below of the noise removal processing in the column processing unit 13 and the calculation processing in the signal processing unit 18 as a unit in the later stage.

[0256] First, for example, a description will be given of processing in a CDS circuit embedded as noise removing means in the column processing unit 13. A CDS circuit having a known circuit configuration can be used, and the circuit configuration thereof does not matter.

[0257] Fig.25 Timing charts provided for the description of the noise removal processing in the column processing unit 13 of the cases of Processing Example 1 and Processing Example 2 are shown.

[0258] (Processing Example 1)

[0259] First, a difference is obtained between a voltage signal S1 based on photocharges transferred to the FD portion 71 when a signal is read out and a voltage signal N1 based on a reset level before the photocharges are transferred to the FD portion 71. Furthermore, a difference is obtained between a voltage signal S2 based on photocharges accumulated in the FD portion 71, the charge accumulation portion 66, and the second charge accumulation portion 67 and a voltage signal N2 based on a reset level after resetting the FD portion 71, the first charge accumulation portion 66, and the second charge accumulation portion 67. Assuming that the first difference is SN1 and the second difference is SN2, SN1=S1-N1 and SN2=S2-N2.

[0260] In this way, in Processing Example 1, CDS processing is performed on the signals S1 and N1 output first to remove reset noise and fixed pattern noise unique to the pixel, such as changes in the threshold value of the amplifier transistor in the pixel. CDS processing is performed on the signals S2 and N2 output later to remove fixed pattern noise unique to the pixel, such as changes in the threshold value of the amplifier transistor in the pixel, but reset noise is not removed. However, this is a calculation process that does not require the use of a frame memory; therefore, there is an advantage of promoting simplification of circuit configuration and cost reduction.

[0261] (Processing Example 2)

[0262] In processing example 2, a storage device, for example, a frame memory needs to use information of a previous frame. Therefore, for example, the calculation processing of processing example 2 is performed by using the data storage unit 19 as a storage device in the signal processing unit 18 or using a frame memory in an external DSP circuit.

[0263] Specifically, first, a difference is obtained between a voltage signal S1 based on the photocharge transferred to the FD portion 71 when the signal is read out and a voltage signal N1 based on a reset level before the photocharge is transferred to the FD portion 71. Next, a difference is obtained between a voltage signal S2 based on the photocharge accumulated in the FD portion 71, the first charge accumulation portion 66, and the second charge accumulation portion 67 and a voltage signal N2A of the previous frame. The voltage signal N2A is a signal based on a reset level after the photocharge accumulated in the FD portion 71, the first charge accumulation portion 66, and the second charge accumulation portion 67 for the previous frame is reset. Assuming that the first difference is SN1, and the second difference is SN2, SN1=S1-N1 and SN2=S2-N2A.

[0264] In this way, in Processing Example 2, CDS processing for removing reset noise and fixed pattern noise unique to pixels, such as changes in the threshold value of the amplifier transistor in the pixel, is also performed on the signals S2 and N2 outputted thereafter. In the case of Processing Example 2, although a storage device such as a frame memory is required, there is an advantage that reset noise can be significantly suppressed compared to Processing Example 1.

[0265] (Processing Example 3)

[0266] Next, a description will be given of the calculation processing in the signal processing unit 18. First, if the first difference value falls within the specified range, a ratio of the first difference value to the second difference value is calculated as a gain of each pixel for each of a plurality of pixels, for each color, for each specific pixel in a shared pixel unit, or uniformly for all pixels to create a gain table. A product of the second difference value and the gain table is calculated as a calculated value of the second difference value.

[0267] Here, assuming that the first difference is SN1, the second difference is SN2, the gain is G, and the calculated value of the second difference SN2 is SN2′, the gain G and the calculated value SN2′ of the second difference SN2 can be obtained based on the following expressions (6) and (7):

[0268] G=SN1 / SN2=(Cfd+Cgs+Ccap) / Cfd...(6)

[0269] SN2'=G×SN2...(7)

[0270] Where Cfd is the capacitance value of the FD portion 71, Cgs is the capacitance value of the first charge accumulation portion 66, and Ccap is the capacitance value of the second charge accumulation portion 67, and the gain G is equivalent to the capacitance ratio.

[0271] Fig.26 Shows the relationship of the first difference SN1, the second difference SN2, and the calculated value SN2' of the second difference SN2 with respect to the incident light amount.

[0272] Next, as Fig. 27 shown in A, a preset specified threshold Vt is used. The specified threshold Vt is preset in the region where the first difference SN1 in the light response characteristic is linear before saturation.

[0273] If the first difference SN1 does not exceed the specified threshold Vt, the first difference SN1 is output as the pixel signal SN of the pixel to be processed. In other words, if SN1 < Vt, then SN = SN1 (SN1 replaces SN). If the first difference SN1 exceeds the specified threshold Vt, the calculated value SN2' of the second difference SN2 is output as the pixel signal SN of the pixel to be processed. In other words, if Vt ≤ SN1, then SN = SN2' (SN2' replaces SN).

[0274] (Processing Example 4)

[0275] In the following calculation process, as Fig. 27 shown in B, the values of the first difference SN1 and the calculated value SN2' of the second difference SN2 are combined at a preset ratio within a specified range where the first difference SN1 decreases, and output as the pixel signal SN.

[0276] For example, as shown below, the combination ratio of the first difference SN1 and the calculated value SN2' of the second difference SN2 changes stepwise within a range around the specified threshold Vt set as a reference. As described above, the specified threshold Vt is a preset value in the region where the first difference SN1 in the light response characteristic is linear before saturation.

[0277] If SN1 < SN1 × 0.90, then SN = SN1.

[0278] If Vt × 0.90 ≤ SN1 < Vt × 0.94, then SN = 0.9 × SN1 + 0.1 × SN2'.

[0279] If Vt × 0.94 ≤ SN1 < Vt × 0.98, then SN = 0.7 × SN1 + 0.3 × SN2'.

[0280] If Vt × 0.98 ≤ SN1 < Vt × 1.02, then SN = 0.5 × SN1 + 0.5 × SN2'.

[0281] If Vt × 1.02 ≤ SN1 < Vt × 1.06, then SN = 0.3 × SN1 + 0.7 × SN2'.

[0282] If Vt × 1.06 ≤ SN1 < Vt × 1.10, then SN = 0.1 × SN1 + 0.9 × SN2'.

[0283] If Vt × 1.10 ≤ SN1, then SN = SN2'.

[0284] This calculation process is performed so that the signal can be switched more smoothly from the low-light condition to the high-light condition.

[0285] <5. Reference>[[]]

[0286] The features of the embodiments described above mainly lie in that two charge accumulation parts 66 and 67 are provided in the unit pixel, and the second charge accumulation part 67 is formed by a capacitor having a higher unit area capacitance value than the first charge accumulation part 66. However, even if the unit area capacitance values of the two charge accumulation parts 66 and 67 are equal, the effect of being able to expand the dynamic range can be obtained. This will be referred to[[]] Fig.28 Fig.28 for description.

[0287] During the exposure period of the photodiode 61, the second transfer gate part 63 is made to conduct during a period set at a specified ratio of the exposure period of the photodiode 61, so that the optical charges equal to or greater than a specified amount overflowing from the photodiode 61 leak out.

[0288] Here, it is assumed that the exposure period of the photodiode 61 is Tpd, and the period during which the optical charges overflowing from the photodiode 61 are accumulated in the second charge accumulation part 67 is Tcap. According to[[]] Fig.28 Fig.28 the unit pixel is operated according to the shown timing diagram, and the exposure period Tcap of the second charge accumulation part 67 is limited. This operation enables the compression of the information on the high-light side and at least extends the dynamic range because the capacitance value of the second charge accumulation part 67 is substantially equal to the capacitance value of the first charge accumulation part 66.

[0289] After reading the noise component and the signal component under the low-light condition, the FD part 71 is reset once, and the optical charges overflowing from the photodiode 61 and accumulated in the second accumulation part 67 are read as the signal on the high-light side. Different from other examples, since the FD part 71 is reset once, the signal on the high-light side does not include the optical charges accumulated in the first charge accumulation part 66.

[0290] Assume that when reading out a signal, the voltage signal based on the optical charge transmitted to the FD section 71 is S1, the voltage signal based on the reset level before the optical charge is transmitted to the FD section 71 is N1, and the first difference is SN1. Further assume that the voltage signal based on the optical charge accumulated in the FD section 71, the first charge accumulation section 66, and the second charge accumulation section 67 when the FD section 71 is reset immediately before reading out is S3. Additionally, assume that the voltage signal at the reset level or at a level corresponding to the reset of the FD section 71, the first charge accumulation section 66, and the second charge accumulation section 67 is N2, the third difference is SN3, the gain is G, and the calculated value of the third difference SN3 is SN3'. Thus, the following calculations can be made:

[0291] SN1 = S1 - N1

[0292] SN3 = S3 - N2

[0293] G = SN1 / SN3 = (Cfd + Csg + Ccap) / Cfd

[0294] SN3' = G × SN3 × Tpd / Tcap

[0295] Assume that the specified threshold preset in the region where the first difference SN1 in the light response characteristic is before saturation and the light response characteristic is linear is Vt, and the pixel signal of the target pixel to be processed is SN. Then, the pixel signal SN is output as follows:

[0296] If SN1 < Vt, then SN = SN1 (SN1 replaces SN).

[0297] If Vt ≤ SN1, then SN = SN3' (SN3' replaces SN).

[0298] <6. Modified Example>

[0299] [6 - 1. Example of Accumulating Optical Charge Only in the Photodiode 61]

[0300] In the above example and modified example, the optical charge overflowing from the photodiode 61 under high - light conditions accumulates in the first charge accumulation section 66 via the overflow path of the first transfer gate section 62 and further accumulates in the second charge accumulation section 67 via the overflow path of the third transfer gate section 64. In other words, the feature of this embodiment is that the optical charge overflowing from the photodiode 61 under high - light conditions accumulates in the photodiode 61 and also accumulates in the first and second charge accumulation sections 66 and 67 in addition to the photodiode 61.

[0301] However, as can be seen from Fig.29As is clear from the operation explanation diagram of A, exposure cannot be performed during the reading period of the photocharge in the above-mentioned pixel structure. Therefore, a pixel structure in which the photocharge is accumulated only in the photodiode 61 is proposed as a modification example.

[0302] And in this case, the essence of the present technology, that is, accumulating the photocharges after reading from the photodiode 61, selectively using the first charge accumulation portion 66 and the second charge accumulation portion 67 is unchanged. In other words, after reading the photocharges from the photodiode 61, the photocharges overflowing from the first charge accumulation portion 66 are accumulated in the second charge accumulation portion 67. In order to do this, an overflow path between the first charge accumulation portion 66 and the second charge accumulation portion 67 is naturally required.

[0303] In this way, if Fig.29 As shown in the operation explanation diagram of FIG. 1B, the use of a pixel structure that accumulates photocharges only in the photodiode 61 enables exposure during the reading period of the photocharges; therefore, seamless operation can be achieved without interruption of the exposure period when imaging a moving image. However, because the photocharges are accumulated only in the photodiode 61, the dynamic range is limited by the saturation charge amount of the photodiode 61. Therefore, a significant expansion of the dynamic range cannot be expected.

[0304] However, as the essence of the present technology, the photocharge is accumulated, and the first charge accumulation part 66 and the second charge accumulation part 67 are selectively used, so the total area of ​​the charge accumulation part for accumulating the photocharge can be reduced. Therefore, the area of ​​the photodiode 61 can be expanded by reducing the total area; therefore, the dynamic range can be indirectly extended.

[0305] [6-2. Example of Switching Circuit Operation Between Short-Time Exposure and Long-Time Exposure]

[0306] As described above, on the one hand, the second charge accumulation portion 67 is high in area efficiency of the capacitor, but on the other hand, a large amount of leakage current flows out therefrom. In addition, light charges are also accumulated in the second charge accumulation portion 67 during the exposure period; therefore, the longer the exposure period, the more the image quality is deteriorated by the leakage current.

[0307] Therefore, for example, the circuit operation of the unit pixel can be switched between the case where the exposure time is short and the case where the exposure time is long. Specifically, the above circuit operation is performed in the case of short exposure. On the other hand, in the case of long exposure, for example, the accumulated photocharges can be regularly read during the exposure period so as not to accumulate the photocharges in the second charge accumulation portion 67 but to accumulate the photocharges only in the photodiode 61 and the first charge accumulation portion 66.

[0308] (Configuration example for realizing circuit operation at long exposure)

[0309] Fig.30 A configuration example of peripheral devices of the column processing unit 13 , the signal processing unit 18 , and the data storage unit 19 for realizing a circuit operation in long-time exposure is shown.

[0310] The switch 101 is provided between the column processing unit 13 and the signal processing unit 18 and the data storage unit 19. Switching of the state of the switch 101 makes it possible to switch the destination to supply the pixel signal output from the column processing unit 13 to any one of the signal processing unit 18 and the data storage unit 19.

[0311] Furthermore, the signal processing unit 18 includes memories 111 a and 111 b , an adding unit 112 , and another signal processing unit 113 .

[0312] The memory 111a stores a pixel signal supplied from the data storage unit 19, and the memory 111b stores a pixel signal supplied from the column processing unit 13 via the switch 101. The adding unit 112 adds the pixel signal stored in the memory 111a and the pixel signal stored in the memory 111b, and supplies the added pixel signal to the data storage unit 19.

[0313] The memories 111 a and 111 b each have a capacitance that can hold a pixel signal equal to at least one pixel, and, for example, their capacitance values ​​are set to capacitance that can hold a pixel signal equal to one line.

[0314] The other signal processing unit 113 performs other various signal processing on the pixel signal stored in the data storage unit 19 .

[0315] (Example of Circuit Operation of Unit Pixel 60A in Long-Time Exposure)

[0316] Next, we will refer to Fig.31 and Fig.32 The timing diagram and Figure 33 to Figure 36 A description is given of an example of the circuit operation of the unit pixel 60A in long-time exposure with reference to a potential diagram.

[0317] Fig.31 The timing diagram of the selection signal SEL, the reset signal RST, the transfer signal TG, the charge drain control signal PG, the transfer signal CG, the transfer signal SG and the transfer signal FG of the unit pixel 60A under long-time exposure is shown. Fig.32 Shown by Fig.31 The alternating dot-dash box surrounds the detailed timing diagram of the time period. In addition, Figure 33 to Figure 36 Shown respectively in Fig.32 The state of the potential of the unit pixel 60A in the Nth row during the time Ta to Td1.

[0318] In by Fig.31 and Fig.32 The period surrounded by the alternate dot-dash line frame in , in other words, the circuit operation during the period from time t2 to time t3 is different between the short exposure and the long exposure. A description of the circuit operation during this period will be given below.

[0319] Fig.33 The state of the potential of the unit pixel 60A at time Ta between time t2 and time T11 is shown. In this way, photocharges are accumulated in the photodiode 61. In addition, if it is under high light conditions, the photocharges overflowing from the photodiode 61 are accumulated in the first charge accumulation portion 66 via the overflow path of the first transfer gate portion 62. If it is under low light conditions, the photocharges are accumulated only in the photodiode 61.

[0320] At time T11, the selection signal SEL in the Nth row becomes active, and the selection transistor 69 in the Nth row establishes electrical continuity; therefore, the unit pixel 60A in the Nth row is made a selected state. At the same time, the reset signal RST becomes active and the reset gate portion 65 establishes electrical continuity, so the FD portion 71 is reset. At time T21, the reset signal RST then becomes inactive.

[0321] At a time between time T21 and time T31 , the potential of the FD portion 71 is output as a reset level NL1 to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 .

[0322] Next, at time T31 , the transfer signal TG, the transfer signal SG, and the transfer signal FG become active, and the first transfer gate portion 62 , the gate electrode 661 of the first charge accumulation portion 66 , and the second transfer gate portion 63 establish electrical continuity.

[0323] Fig.34 is a diagram showing the state of the potential of the unit pixel 60A at time Tb1 between time T31 and time T41. In this way, the potentials of the coupling FD portion 71 and the first charge accumulation portion 66 are coupled and the photocharge accumulated in the photodiode 61 during the period from time t2 to time T31 is transferred to the coupled region. In addition, the photocharge generated in the photodiode 61 between time T31 and time T41 is also transferred to the coupled region.

[0324] For the time from time t2 to time T31, the accumulated charge amount is set in such a manner as not to exceed the total of the saturated charge amounts of the photodiode 61 and the first charge accumulation portion 66. Therefore, during this period, the photocharge may overflow from the photodiode 61 to be accumulated in the first charge accumulation portion 66 via the overflow path of the first transfer gate portion 62; however, the photocharge does not further overflow from the first charge accumulation portion 66 to be accumulated in the second charge accumulation portion 67 via the overflow path of the third transfer gate portion 64.

[0325] Next, at time T41, the transfer signal TG and the transfer signal SG become inactive, and the first transfer gate portion 62 and the gate electrode 661 of the first charge accumulation portion 66 break electrical continuity. The first transfer gate portion 62 then breaks electrical continuity; therefore, the photocharges resume being accumulated in the photodiode 61.

[0326] Fig.35 6A at time Tc1 between time T41 and time T51. In this way, all the photocharges transferred from the photodiode 61 to the potential coupling region of the FD portion 71 and the first charge accumulation portion 66 are transferred to the FD portion 71.

[0327] Next, at time T51, the transfer signal FG becomes inactive, and the second transmission gate portion 63 breaks the electrical continuity.

[0328] Fig.36 1 is a diagram showing the state of the potential of the unit pixel 60A at time Td1 between time T51 and time T61. The potential of the FD portion 71 in this state is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as a signal level SL1 according to the accumulated charge amount of the photodiode 61 and the first charge accumulation portion 66 in the period from time t2 to time T41.

[0329] The column processing unit 13 obtains the difference between the signal level SL1 and the signal level NL1. The difference SNL1 (= SL1 - NL1) is then provided by the column processing unit 13 to the data storage unit 19 via the switch 101 to be stored therein.

[0330] Next, at time T61, the selection signal SEL becomes inactive, and the selection transistors 69 in the Nth row break the electrical continuity; thus, the unit pixels 60A in the Nth row are made to be in a non-selected state.

[0331] These processes are performed line by line, and as a result, image data composed of the difference value SNL1 for each pixel is stored in the data storage unit 19 .

[0332] Next, at time T12 to T62, operations similar to those at time T11 to T61 are performed, and the reset level NL2 and the signal level SL2 are output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 in this order.

[0333] For the time from time T41 to time T32 during which photocharges are accumulated in the photodiode 61, similarly to the time from time t2 to time T31, the accumulated charge amount is set in such a manner as not to exceed the total of the saturation charge amounts of the photodiode 61 and the first charge accumulation portion 66.

[0334] The column processing unit 13 obtains the difference between the signal level SL2 and the signal level NL2. The difference SNL2 (= SL2 - NL2) is then supplied by the column processing unit 13 to the memory 111b via the switch 101 to be stored therein.

[0335] On the other hand, the difference value SNL1 of the corresponding unit pixel 60A is supplied to the memory 111a by the data storage unit 19 to be stored therein. The adding unit 112 adds the difference value SNL1 stored in the memory 111a and the difference value SNL2 stored in the memory 111b, and causes the data storage unit 19 to store the combined value SNLa.

[0336] These processes are performed line by line, and as a result, image data composed of the combined value SNLa of each pixel is stored in the data storage unit 19.

[0337] Next, at time T13 to T63, operations similar to those at time T11 to T61 are performed, and the reset level NL3 and the signal level SL3 are output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 in this order.

[0338] For the time from T42 to T33 during which photocharges are accumulated in the photodiode 61 , similarly to the time from time t2 to time T31 , the accumulated charge amount is set so as not to exceed the total of the saturated charge amounts of the photodiode 61 and the first charge accumulation portion 66 .

[0339] The column processing unit 13 obtains the difference between the signal level SL3 and the signal level NL3. The difference SNL3 (= SL3 - NL3) is then supplied by the column processing unit 13 to the memory 111b via the switch 101 to be stored therein.

[0340] On the other hand, the combined value SNLa of the corresponding unit pixel 60A is provided to the memory 111a by the data storage unit 19 to be stored therein. The adding unit 112 adds the combined value SNLa stored in the memory 111a to the difference value SNL3 stored in the memory 111b, and causes the data storage unit 19 to store the combined value SNLa.

[0341] These processes are performed line by line, and as a result, image data composed of the combined value SNLa of each pixel is stored in the data storage unit 19.

[0342] Then, at time T14 to T6 n In other words, the intermediate reading of the amount of photocharge accumulated in the output unit pixel 60A as an electric signal (pixel signal) is performed n times while maintaining exposure at a time interval when the accumulated charge amount does not exceed the total of the photodiode 61 and the first charge accumulation portion 66 during the exposure period for all pixels, and a combined value SNLa according to the accumulated charge amount of each pixel is obtained.

[0343] Furthermore, at time t3 to t12, a process similar to exposure with a short time is performed. As a result, reset level N1, first signal level S1, second signal level S2, and reset level N2 are output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 in this order.

[0344] A pixel signal for each pixel is then generated based on the combined value SNLa stored in the data storage unit 19 , the signal levels S1 and S2 , and the reset levels N1 and N2 .

[0345] (Modification of Circuit Operation of Unit Pixel 60A in Long-Time Exposure)

[0346] Fig.37 Shown by Fig.31 A modified example of the detailed timing diagram of the time period surrounded by a box of alternating dot-dash lines.

[0347] In terms of the transmit signal SG not becoming active but remaining inactive during the time from time t2 to t3, Fig.37 The timing diagram is different from the above Fig.32 In other words, when the light charges accumulated in the photodiode 61 are transferred to the FD portion 71 via the first charge accumulation portion 66, the gate electrode 661 of the first charge accumulation portion 66 is maintained in a non-conductive state.

[0348] This operation can be performed if the potential of the photodiode 61 at the time of depletion is sufficiently shallower than the potential of the first charge accumulation portion 66 at the time of depletion.

[0349] (Example of Circuit Configuration of Unit Pixel 60A with Long-Time Exposure)

[0350] Fig.38 and Fig.39 2 is a diagram showing a unit pixel 60A2 ( Fig. 20 ) with a timing diagram of the circuit operation with a long exposure. Fig.39 Shown by Fig.38 A detailed timing diagram of the time periods surrounded by alternating dot-dashed boxes.

[0351] Similar to Fig.37 In the timing diagram of FIG. 1 , the transfer signal SG does not become active but remains inactive during the exposure period common to all pixels, Fig.39 The timing diagram is different from Fig.32 Timing diagram of .

[0352] (Timing for Switching Between Circuit Operation with Short Exposure Time and Circuit Operation with Long Exposure Time)

[0353] Here, the timing for switching between the circuit operation with a short exposure time and the circuit operation with a long exposure time will be discussed.

[0354] In order to prevent the dynamic range from being reduced due to the circuit operation with long exposure, it is necessary to set the number n (natural number) of intermediate readings during the exposure period in such a manner as to satisfy the following conditional expression (8):

[0355] Qs≤Qm×n...(8)

[0356] Here, Qs represents the saturation charge amount of the unit pixel 60A in the circuit operation with short exposure, and Qm represents the maximum charge amount that can be read from the unit pixel 60A by one intermediate reading. In other words, the number n of intermediate readings needs to be set so that the intermediate reading is repeated n times and the amount of photocharge that can be read from the unit pixel 60A becomes equal to or greater than the saturation charge amount Qs of the unit pixel 60A.

[0357] The following expression (9) is a modification of the expression (8):

[0358] n≥Qs / Qm...(9)

[0359] Both the saturation charge amount Qs and the maximum charge amount Qm are determined by the device characteristics of the CMOS image sensor 10 including the unit pixel 60A. As a result, the condition of the number n of intermediate readings is determined by Expression (9), and the number n of intermediate readings can be set in advance within the range of the obtained condition.

[0360] On the other hand, assuming that the exposure time of the imaging device including the CMOS image sensor 10 is Te, and the time required for intermediate reading for one frame is Tm, it is necessary that the exposure time Te, the required time Tm, and the number n of intermediate readings satisfy the following conditional expression (10):

[0361] Tm≤Te / n ... (10)

[0362] Therefore, if the exposure time Te satisfies the following expression (11), it is possible to switch to the circuit operation with long exposure.

[0363] Te≥n×Tm...(11)

[0364] For example, the driving unit of the CMOS image sensor 10 may automatically switch the circuit operation between exposure with a short time and exposure with a long time based on whether the exposure time Te satisfies the conditional expression (11). Otherwise, if the exposure time Te satisfies the conditional expression (11), the circuit operation may be fixed to the circuit operation with a short time exposure, and if the exposure time Te satisfies the conditional expression (11), the circuit operation may be switched by the user's operation.

[0365] As described above, in the circuit operation of long-time exposure, photocharges are accumulated and read without accumulating photocharges in the second charge accumulation portion 67 from which a large amount of leakage current flows and without overflowing the photocharges. Therefore, for example, the circuit operation of switching the unit pixel according to the exposure time makes it possible to obtain an image with a wide dynamic range and low noise regardless of the exposure period.

[0366] A case where the dynamic range is reduced is assumed; however, the circuit operation with a short exposure time and the circuit operation with a long exposure time may be set to be switchable by a user's operation regardless of the exposure time Te.

[0367] [6-3. Example of Omitting the Second Charge Accumulation Section 67]

[0368] Furthermore, the second charge accumulation portion 67 may be deleted from the unit pixel and the FD portion 71 may be used as the second charge accumulation portion. In other words, the optical charges overflowing from the first charge accumulation portion 66 may also be transferred to the FD portion 71 and accumulated therein.

[0369] (Circuit Structure of Unit Pixel 60B)

[0370] Fig.40 60B is a circuit diagram showing a circuit configuration of a unit pixel 60B in which the second charge accumulation portion 67 is omitted. Fig.40As shown, similar to the unit pixel 60A, the unit pixel 60B includes, for example, a photodiode 61 having a pn junction as a photoelectric conversion portion that receives light to generate and accumulate photocharges. The photodiode 61 generates and accumulates photocharges according to the amount of received light.

[0371] This unit pixel 60B further includes, for example, a first transfer gate portion 62 , a second transfer gate portion 63 , a reset gate portion 65 , a first charge accumulation portion 66 , an amplification transistor 68 , a selection transistor 69 , and a charge drain gate portion 70 .

[0372] In the unit pixel 60B having the above configuration, the first charge accumulation portion 66 corresponds to the above-mentioned first charge accumulation portion. In other words, the first charge accumulation portion 66 is configured by an embedded MOS capacitor.

[0373] like Figure 1 For example, a plurality of drive lines are connected to the unit pixels 60B in each pixel row, just like the pixel drive lines 16 in FIG. Figure 1 The vertical driving unit 12 in the pixel driving line 16 provides various driving signals TG / SG, FG, RST, SEL and PG through a plurality of driving lines of the pixel driving line 16. In the above configuration, the transistors are NMOS transistors, and thus these driving signals TG / SG, FG, RST, SEL and PG are pulse signals that become active at a high level (e.g., the power supply voltage VDD) and become inactive at a low level (e.g., a negative potential).

[0374] The drive signal TG / SG is applied as a transfer signal to the gate electrode of the first transfer gate portion 62. From the perspective of the circuit, one source / drain region of the first transfer gate portion 62 is connected to the photodiode 61. When the drive signal TG / SG becomes active, the first transfer gate portion 62 then establishes electrical continuity in response thereto, thereby transferring the photocharge accumulated in the photodiode 61 to the first charge accumulation portion 66. The photocharge transferred by the first transfer gate portion 62 is temporarily accumulated in the first charge accumulation portion 66.

[0375] The drive signal FG is applied as a transfer signal to the gate electrode of the second transfer gate portion 63. From the perspective of the circuit, the second transfer gate portion 63 is connected between the first charge accumulation portion 66 and the FD portion 71 to which the gate electrode of the amplification transistor 68 is connected. The FD portion 71 converts the photocharge into an electrical signal, for example, a voltage signal and outputs the signal. When the drive signal FG becomes active, the second transfer gate portion 63 then establishes electrical continuity in response thereto and thus transfers the photocharge accumulated in the first charge accumulation portion 66 to the FD portion 71.

[0376] The driving signal RST is applied as a reset signal to the gate electrode of the reset gate portion 65. From a circuit perspective, one source / drain region of the reset gate portion 65 is connected to the reset voltage V DR , and its other source / drain region is connected to the FD portion 71. When the drive signal RST becomes active, the reset gate portion 65 then establishes electrical continuity in response thereto, and thus resets the potential of the FD portion 71 to the reset voltage V DR level.

[0377] From the circuit point of view, the gate electrode of the amplifying transistor 68 is connected to the FD portion 71, and the drain electrode thereof is connected to the power supply voltage V DD , and the amplifier transistor 68 is used as an input part of a reading circuit (so-called source follower circuit) that reads the photocharge obtained by the photoelectric conversion of the photodiode 61. In other words, the source electrode of the amplifier transistor 68 is connected to the vertical signal line 17 via the selection transistor 69, and the amplifier transistor 68 configures the source follower circuit with the constant current source 80 connected to one end of the vertical signal line 17.

[0378] The drive signal SEL is applied as a selection signal to the gate electrode of the selection transistor 69. From the perspective of the circuit, the selection transistor 69 is connected between the source electrode of the amplification transistor 68 and the vertical signal line 17. When the drive signal SEL becomes active, the selection transistor 69 then establishes electrical continuity in response thereto, and thus makes the unit pixel 60A a selected state and connects the pixel signal output from the amplification transistor 68 to the vertical signal line 17.

[0379] The driving signal PG is applied as a charge leakage control signal to the gate electrode of the charge leakage gate portion 70. From the circuit point of view, the charge leakage gate portion 70 is connected between the photodiode 61 and the charge leakage portion (for example, the power supply voltage V DD When the drive signal PG becomes active, the charge drain gate portion 70 then establishes electrical continuity in response thereto, and thus selectively drains a preset specified amount or all of the photocharges accumulated in the photodiode 61 from the photodiode 61 to the charge drain portion.

[0380] The charge leakage gate portion 70 is provided for the following purpose. In other words, the purpose is to prevent the photodiode 61 from being saturated with photocharges and photocharges exceeding the saturated charge amount from overflowing to the first charge accumulation portion 66, the FD portion 71, and the surrounding pixels, which is caused by turning on the charge leakage gate portion 70 during a period during which photocharges are not accumulated.

[0381] (Pixel Structure of Unit Pixel 60B)

[0382] Fig.4160B, and the same reference numerals are assigned to indicate the same pixel structure as the unit pixel 60B. Fig.40 The same part. Fig.41 A plane pattern of a pixel layout and cross-sectional portions of the plane pattern taken along arrow AA' and arrow BB', respectively, are shown.

[0383] exist Fig.41 , as is clearly seen from the cross-sectional view taken along arrow BB', the photodiode (PD) 61 has a structure of a diode including a pn junction in which an N-type semiconductor region 611 is formed in a P-type well 52 on a semiconductor substrate 51. The photodiode 61 includes a P-type semiconductor region 612 formed in a surface layer portion thereof, and is therefore an embedded photodiode in which a depletion end is separated from an interface (a so-called HAD (hole accumulation diode) sensor structure).

[0384] The first transfer gate portion 62 includes a gate electrode 621 provided on the surface of the substrate via a gate insulating film (not shown) and a P-type semiconductor region 622 formed in a surface layer portion of the substrate. The P-type semiconductor region 622 has a potential slightly deeper under the gate electrode 621 than in the case where the semiconductor region 622 is not formed. Therefore, as is clear from the cross-sectional view taken along arrow BB', the P-type semiconductor region 622 forms an overflow path that transfers photocharges equal to or greater than a specified amount, or specifically, photocharges exceeding the saturation charge amount of the photodiode 61, which overflow from the photodiode 61, to the first charge accumulation portion 66.

[0385] Furthermore, the gate electrode 621 of the first transfer gate portion 62 also serves as the gate electrode 661 of the first charge accumulation portion 66. In another way, the gate electrode 621 of the first transfer gate portion 62 and the gate electrode 661 of the first charge accumulation portion 66 are integrally formed.

[0386] The first charge accumulation portion 66 includes a gate electrode 661 which also serves as the gate electrode 621 of the first transfer gate portion 62 and is formed as an embedded MOS capacitor under the gate electrode 661. In other words, the first charge accumulation portion 66 is configured by an embedded MOS capacitor including an N-type semiconductor region 662 formed in the P-type well 52 under the gate electrode 661 and a P-type semiconductor region 623 formed in a surface layer portion thereof.

[0387] The second transfer gate portion 63 includes a gate electrode 631 provided on the substrate surface via a gate insulating film (not shown). The second transfer gate portion 63 has the N-type semiconductor region 662 of the first charge accumulation portion 66 as one source / drain region, and the N+ type semiconductor region 711 used as the FD portion 71 as another source / drain region.

[0388] The second transfer gate portion 63 and the gate electrode 661 of the first charge accumulation portion 66 operate to couple or divide the potentials of the FD portion 71 and the first charge accumulation portion 66 .

[0389] In addition, the second transfer gate portion 63 has a structure in which an N-type semiconductor region 632 is formed in the surface layer portion of the channel portion. The N-type semiconductor region 632 has a potential slightly deeper under the gate electrode 631 than in the case where the semiconductor region 632 is not formed. Therefore, as is clear from the cross-sectional view taken along the arrow A-A', the N-type semiconductor region 632 forms an overflow path that transfers the photocharges equal to or greater than a specified amount, or specifically, equal to or greater than the saturation charge amount of the first charge accumulation portion 66, which overflow from the first charge accumulation portion 66, to the FD portion 71.

[0390] Here, it is important that the overflow path formed under the first and second transfer gate portions 62 and 63 should be formed so that the photocharges accumulated in the first charge accumulation portion 66 are not leaked to the photodiode 61 but transferred to the FD portion 71 .

[0391] In this manner, the unit pixel 60B has an overflow path below the gate electrode 631 of the second transfer gate portion 63; therefore, photocharges overflowing from the photodiode 61 under high light conditions can also be accumulated in the FD portion 71. Specifically, even if the second transfer gate portion 63 is not turned on, photocharges equal to or greater than a specified amount overflowing from the first charge accumulation portion 66 can be transferred to the FD portion 71 and accumulated in the FD portion 71. Therefore, the saturation charge amount of the first charge accumulation portion can be set to be smaller than the saturation charge amount of the photodiode 61.

[0392] (Circuit Operation of Unit Pixel 60B)

[0393] Next, we will refer to Fig.42 The timing diagram and Figure 43 to Figure 50 A description is given of the circuit operation of the unit pixel 60B by means of a potential diagram.

[0394] Fig.42 1 shows a timing diagram of the selection signal SEL, the reset signal RST, the transfer signal TG / SG, the charge drain control signal PG and the transfer signal FG of the unit pixel 60B. Figures 43 to 50 Shown in Fig.42 The state of the potential of the unit pixel 60B in the Nth row from time ta to time tg in the timing chart of FIG.

[0395] First, at time t61, while the charge drain control signal PG remains active, the selection signal SEL, the reset signal RST and the transfer signal FG become active in all pixels simultaneously. Therefore, the selection transistor 69, the reset gate portion 65, the second transfer gate portion 63 and the charge drain gate portion 70 establish electrical continuity.

[0396] Fig.43 The state of the potential of the unit pixel 60B at time ta between time t61 and time t62 is shown. In this way, the potentials of the coupling FD portion 71 and the first charge accumulation portion 66 are coupled and the coupled region is reset.

[0397] Subsequently, the transfer signal FG, the reset signal RST and the selection signal SEL become inactive in this order simultaneously in all pixels. At time t62, the charge drain control signal PG then becomes inactive simultaneously in all pixels. Thus, an exposure period common to all pixels begins.

[0398] Fig.44 The state of the potential of the unit pixel 60B at time t62 is shown. At this time, the light charges are not accumulated in the photodiode 61 and the first charge accumulation portion 66.

[0399] Fig.45 The state of the potential of the unit pixel 60B at time tb between time t62 and time t63 is shown. In this way, although the photocharge is accumulated in the photodiode 61, if it is under high light conditions, the photocharge overflowing from the photodiode 61 is accumulated in the first charge accumulation portion 66 via the overflow path of the first transfer gate portion 62. In addition, if the first charge accumulation portion 66 is saturated, the photocharge overflowing from the first charge accumulation portion 66 is accumulated in the FD portion 71 via the overflow path of the second transfer gate portion 63. If it is under low light conditions, the photocharge is accumulated only in the photodiode 61.

[0400] Next, at time t63 , the transfer signal TG / SG becomes active and the first transfer gate portion 62 and the gate electrode 661 of the first charge accumulation portion 66 establish electrical continuity.

[0401] Fig.46 The state of the potential of the unit pixel 60B at time tc between time t63 and time t64 is shown. In this way, the light charges accumulated in the photodiode 61 are transferred to the first charge accumulation portion 66 and accumulated in the first charge accumulation portion 66.

[0402] Next, at time t64, in all pixels, the transfer signal TG / SG becomes inactive at the same time and the charge drain control signal PG becomes active. The first transfer gate portion 62 and the gate electrode 661 of the first charge accumulation portion 66 then break electrical continuity, and the potential of the first charge accumulation portion 66 is restored to its initial level and the charge drain gate portion 70 establishes electrical continuity. Thus, the exposure period common to all pixels ends. In addition, if the accumulated charge amount of the first charge accumulation portion 66 exceeds the saturation charge amount, the photocharge overflowing from the first charge accumulation portion 66 is accumulated in the FD portion 71 via the overflow path of the second transfer gate portion 63.

[0403] After the exposure period common to all pixels ends, the accumulated photocharges are sequentially read row by row.

[0404] Specifically, at time t65, the selection signal SEL in the Nth row becomes active, and the selection transistors 69 in the Nth row establish electrical continuity, thereby making the unit pixels 60A in the Nth row a selected state.

[0405] Fig.47 The state of the potential of the unit pixel 60B at time td between time t65 and time t66 is shown. In this state, the potential of the FD portion 71 is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as a first signal level S1 according to the charge amount exceeding the saturation charge amount of the first charge accumulation portion 66.

[0406] Next, at time t66, the reset signal RST becomes active, and the reset gate portion 65 establishes electrical continuity. Thus, the FD portion 71 is reset. At time t67, the reset signal RST becomes inactive, and the reset gate portion 65 breaks electrical continuity.

[0407] Fig.48 The state of the potential of the unit pixel 60B at time te between time t67 and time t68 is shown. The potential of the FD portion 71 in this state is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as a reset level N1.

[0408] Next, at time t68 , the transfer signal FG becomes active, and the second transmission gate portion 63 establishes electrical continuity.

[0409] Fig.49 The state of the potential of the unit pixel 60B at time tf between time t68 and time t69 is shown. In this way, the potentials of the FD portion 71 and the first charge accumulation portion 66 are coupled to transfer the photocharge from the first charge accumulation portion 66 to the FD portion 71.

[0410] Next, at time t69, the transfer signal FG becomes inactive, and the second transmission gate portion 63 breaks the electrical continuity.

[0411] Fig.50 The state of the potential of the unit pixel 60B at time tg between time t69 and time t70 is shown. In this state, the potential of the FD portion 71 is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as a second signal level S2 according to the accumulated charge amount of the first charge accumulation portion 66.

[0412] Next, at time t70 , the selection signal SEL in the Nth row becomes inactive, and the selection transistor 69 in the Nth row breaks the electrical continuity, thus making the unit pixel 60A in the Nth row a non-selected state.

[0413] Through the above-described series of circuit operations, the first signal level S1 , the reset level N1 , and the second signal level S2 are sequentially output from the unit pixel 60B to the vertical signal line 17 .

[0414] For example, in the column processing unit 13, noise removal processing is then performed by taking the difference between the first signal level S1 and the reset level N1 and the difference between the reset level N1 and the second signal level S2. At this time, for example, if the difference between the first signal level S1 and the reset level N1 is taken, the reset level N1 of the previous frame can be used.

[0415] In this manner, according to the unit pixel 60B, omitting the second charge accumulation portion 67 makes it possible to expand the area of ​​the photodiode 61 and to ensure a larger saturation charge amount of the photodiode 61. Otherwise, it is possible to expand the area of ​​the first charge accumulation portion 66 and to ensure a larger saturation charge amount of the first charge accumulation portion 66. Conversely, if an equal saturation charge amount is acceptable, it is possible to promote a reduction in the size of the unit pixel by the amount of space saved.

[0416] In addition, when all pixels are read out at the same time, photocharges under low light conditions are accumulated in the first charge accumulation portion 66 having good properties in the dark, and photocharges under high light conditions are accumulated in the FD portion 71 having poor properties in the dark. Therefore, compared with the prior art that realizes global exposure, the quality of an image imaged in the dark or under low light conditions is not deteriorated.

[0417] (Circuit Operation of Unit Pixel 60B with Long-Time Exposure)

[0418] Similar to the unit pixel 60A, the circuit operation with long exposure can also be implemented in the unit pixel 60B. In other words, with long exposure, the accumulated photocharge is regularly read during the exposure period, and thus the photocharge can be accumulated only in the photodiode 61 and the first charge accumulation portion 66 without accumulating the photocharge in the FD portion 71.

[0419] Here, we will refer to Fig.51 and Fig.52 The timing diagram and Figure 53 to Figure 56 A description is given of the circuit operation of the unit pixel 60B with long-time exposure.

[0420] Fig.51 1 shows a timing diagram of the selection signal SEL, the reset signal RST, the transfer signal TG / SG, the charge drain control signal PG and the transfer signal FG of the unit pixel 60B. Fig.52 Shown by Fig.51 The alternating dot-dash box surrounds the detailed timing diagram of the time period. In addition, Figure 53 to Figure 56 Shown respectively in Fig.52 The state of the potential of the unit pixel 60B from the time Ta to Td1.

[0421] In by Fig.51 and Fig.52 During the period surrounded by the alternate dot-dash frame in , in other words, the circuit operation during the period from time t62 to time t63 differs between exposure with a short time and exposure with a long time. A description of the circuit operation during this period will be given below.

[0422] Fig.52 The state of the potential of the unit pixel 60B at the time Ta between the time t62 and the time T611 is shown.

[0423] At time T611, the selection signal SEL in the Nth row becomes active, and the selection transistor 69 in the Nth row establishes electrical continuity; therefore, the unit pixel 60A in the Nth row is in a selected state. At the same time, the reset signal RST becomes active and the reset gate portion 65 establishes electrical continuity, so the FD portion 71 is reset. At time t621, the reset signal RST becomes inactive.

[0424] At a time between time T621 and time T631 , the potential of the FD portion 71 is output as a reset level NL1 to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 .

[0425] Next, at time T631 , the transfer signal TG / SG and the transfer signal FG become active, and the first transfer gate portion 62 , the gate electrode 661 of the first charge accumulation portion 66 , and the second transfer gate portion 63 establish electrical continuity.

[0426] Fig.54 60B at time Tb1 between time T631 and time T641. In this way, the potentials of the FD portion 71 and the first charge accumulation portion 66 are coupled and the photocharge accumulated in the photodiode 61 is transferred to the coupled region. In addition, the photocharge generated in the photodiode 61 between time T631 and time T641 is also transferred to the coupled region.

[0427] For the time from time t62 to time T631, the accumulated charge amount is set in such a manner as not to exceed the total of the saturated charge amounts of the photodiode 61 and the first charge accumulation portion 66. Therefore, during this period, the photocharge may overflow from the photodiode 61 to be accumulated in the first charge accumulation portion 66 via the overflow path of the first transfer gate portion 62; however, the photocharge does not further overflow from the first charge accumulation portion 66 to be accumulated in the FD portion 71 via the overflow path of the second transfer gate portion 63.

[0428] Next, at time T641, the transfer signal TG / SG becomes inactive, and the first transfer gate portion 62 and the gate electrode 661 of the first charge accumulation portion 66 break electrical continuity. The first transfer gate portion 62 then breaks electrical continuity; therefore, the photocharges resume being accumulated in the photodiode 61.

[0429] Fig.55 60A at time Tc1 between time T641 and time T651. In this way, all the photocharges transferred to the region where the potentials of the FD portion 71 and the first charge accumulation portion 66 are coupled are transferred to the FD portion 71.

[0430] Next, at time T651, the transfer signal FG becomes inactive, and the second transmission gate portion 63 breaks the electrical continuity.

[0431] Fig.56 1 is a diagram showing the state of the potential of the unit pixel 60B at time Td1 between time T651 and time T661. The potential of the FD portion 71 in this state is output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 as a second signal level SL2 according to the accumulated charge amount of the photodiode 61.

[0432] Next, at time T661, the selection signal SEL becomes inactive, and the selection transistors 69 in the Nth row break the electrical continuity; thus, the unit pixels 60A in the Nth row are made to be in a non-selected state.

[0433] Then, at time T612 to T66n Processing similar to that at time T611 to T661 is repeated n-1 times. As a result, reset level NL2, third signal level SL2, . . . , reset level NLn and signal level SLn are output to the vertical signal line 17 through the amplification transistor 68 and the selection transistor 69 in this order.

[0434] Similar to the case of the unit pixel 60A, whenever intermediate reading is performed, a combined value corresponding to the accumulated charge amount of each pixel is calculated.

[0435] As described above, in the circuit operation of long-time exposure, similarly to the unit pixel 60A, photocharges are accumulated and read in the unit pixel 60B without accumulating photocharges in the FD portion 71 from which a large amount of leakage current flows out and without overflowing photocharges. Therefore, for example, switching the circuit operation of the unit pixel according to the exposure time makes it possible to obtain an image with a wide dynamic range and low noise regardless of the exposure period.

[0436] [6-4. Other Modifications]

[0437] In addition, although the present technology is applied to a CMOS image sensor in which unit pixels are arranged in a matrix as an example, the description has been given in the above embodiment, but the present technology is not limited to application to CMOS image sensors. In other words, the present technology can be applied to a general solid-state imaging device of an XY address type in which unit pixels are arranged two-dimensionally in a matrix.

[0438] In addition, the present technology can be applied not only to solid-state imaging devices that detect the distribution of the amount of incident visible light and image the distribution as an image, but also to general solid-state imaging devices that image the distribution of the amount of incident infrared rays, X-rays, particles, etc.

[0439] The solid-state imaging device may be formed into one chip or may be formed into a module in which an imaging unit and a signal processing unit or an optical system are packaged together, the module having an imaging function.

[0440] In addition, all pixels in the present technology indicate all pixels of a portion appearing on an image and exclude pseudo pixels, etc. In addition, in the present technology, as long as the time lag and distortion of the image are small to the extent that they do not cause problems, it is also possible to perform scanning at high speed for each multiple rows (for example, several tens of rows) instead of operating all pixels simultaneously. In addition, in the present technology, it is also possible to apply the global shutter operation not only to all pixels appearing in an image but also to a specified multiple rows.

[0441] In addition, the conduction type of the device structure of the unit pixel described above is only an example, and N-type and P-type may be opposite aspects. Depending on whether the majority carriers moving in the unit pixel are holes or electrons, the potential of the above unit or the magnitude relationship of the potential may be opposite.

[0442] Furthermore, for example, the present technology can take the following structures.

[0443] The solid-state imaging device includes a photoelectric conversion part configured to generate photocharges and a transmission gate that transmits the photocharges to a semiconductor region. The method for driving a unit pixel includes a step of accumulating photocharges in the photoelectric conversion part and a step of accumulating photocharges in the semiconductor region. The method for forming the solid-state imaging device includes injecting ions into a well layer through an opening in a mask, injecting additional ions into the well layer through an opening in another mask, and injecting other ions into the well layer through an opening in yet another mask. The electronic device includes a solid-state imaging device.

[0444] <7. Example 2>

[0445] [7-1. Known unit pixel structure]

[0446] In giving Figure 1 Prior to describing the structure of the unit pixel 320 adopted by the CMOS image sensor 10 , a description of the structure of the unit pixel 220 disclosed in Patent Document 1 (Japanese Patent Application Laid-Open No. 2009-268083) will be given to easily understand the problem to be solved by the CMOS image sensor 10 .

[0447] (Structure of Unit Pixel 220)

[0448] Fig.57 is a diagram showing the structure of a unit pixel 220 described in Patent Document 1.

[0449] The unit pixel 220 has a structure in which a charge holding region (hereinafter described as a "memory portion") for storing (accumulating) photocharges to be transferred from a photoelectric conversion element away from a floating diffusion region (capacitor) is installed. A detailed description of the unit pixel 220 will be given below.

[0450] The unit pixel 220 includes a photodiode (PD) 221 as a photoelectric conversion element. The photodiode 221 is an embedded photodiode formed by forming a P-type layer 233 on the substrate surface side in a P-type well layer 232 formed on an N-type substrate 231 and burying an N-type buried layer 234.

[0451] In addition to the embedded photodiode 221, the unit pixel 220 includes a first transfer gate 222, a memory portion (MEM) 223, a second transfer gate 224, and a floating diffusion region (FD: floating diffusion) 225. The memory portion 223 and the floating diffusion region 225 are shielded from light. The floating diffusion region 225 may also be referred to as the FD portion 225 below.

[0452] The first transfer gate 222 transfers the charge photoelectrically converted in the embedded photodiode 221 and accumulated therein to the gate electrode 222A by applying a transfer pulse TRX. The memory portion 223 is formed by an N-type buried trench 235 formed under the gate electrode 222A, and accumulates the charge transferred from the photodiode 221 by the first transfer gate 222. Since the memory portion 223 is formed by the buried trench 235, the occurrence of dark current at the Si-SiO2 interface can be suppressed, and thus it can contribute to the improvement of image quality.

[0453] In the memory portion 223, a gate electrode 222A is provided thereon and a transmission pulse TRX is applied to the gate electrode 222A; therefore, modulation can be performed on the memory portion 223. In other words, the transmission pulse TRX is applied to the gate electrode 222A to deepen the potential of the memory portion 223. Therefore, the saturation charge amount of the memory portion 223 can be increased more than the case where modulation is not performed.

[0454] In addition, an N-impurity diffusion region (OFB) 239 is provided under the gate electrode 222A in the boundary region between the photodiode 221 and the memory portion 223. The N-impurity diffusion region 239 forms a potential barrier φTRX that allows the photocharge generated in the photodiode 221 to overflow to the memory portion 223 even in a state where a sufficient voltage is applied to turn off the first charge transfer gate 222 if a charge equal to or greater than a specified amount is accumulated in the photodiode 221. In another way, an overflow path (intermediate transfer path) 230 that allows the photocharge generated in the photodiode 221 to overflow to the memory portion 223 even in a state where a sufficient voltage is applied to turn off the first transfer gate 222 is formed. In addition, the gate electrode 222A also includes a function as a complete transfer path that transfers all the charges accumulated in the photodiode 221 to the memory portion 223 by applying a transfer pulse TRX. Here, the sufficient voltage to turn off the first transfer gate 222 is a voltage having a magnitude of forming an inversion layer on the Si surface. A P-impurity diffusion region 239 may be provided instead of the N-impurity diffusion region 239.

[0455] The second transfer gate 224 transfers the charge accumulated in the memory portion 223 by applying a transfer pulse TRG to the gate electrode 224A. The FD portion 225 is a charge voltage conversion portion formed of an N-type layer, and converts the charge transferred from the memory portion 223 by the second transfer gate 224 into a voltage.

[0456] The unit pixel 220 further includes a reset transistor 226, an amplifying transistor 227, and a selecting transistor 228. Here, N-channel MOS transistors are used for the reset transistor 226 to the selecting transistor 228, for example. However, the combination of conductivity types of the reset transistor 226 to the selecting transistor 228 illustrated here is only an example, and the combination is not limited to these.

[0457] The reset transistor 226 is connected between the power supply VDB and the FD portion 225, and resets the FD portion 225 by a reset pulse RST applied to the gate electrode of the reset transistor 226. The amplifier transistor 227 has a drain electrode connected to the power supply VDO, a gate electrode connected to the FD portion 225, and reads the voltage across the FD portion 225.

[0458] For example, the drain electrode of the selection transistor 228 is connected to the source electrode of the amplifier transistor 227, the source electrode of which is connected to the vertical signal line 217, and the selection transistor 228 selects the unit pixel 220 from which the signal is to be read by selecting the pulse SEL applied to the gate electrode thereof. A configuration in which the selection transistor 228 is connected between the power supply VDO and the drain electrode of the amplifier transistor 227 may also be adopted.

[0459] As for the reset transistor 226 to the selection transistor 228, one or more of them may also be omitted or shared among a plurality of pixels depending on a method of reading out a signal.

[0460] The unit pixel 220 further includes a charge draining portion 229 for draining the accumulated charge of the photodiode 221. The charge draining portion 229 drains the charge of the photodiode 221 to the draining portion 236 of the N-type layer by the control pulse ABG applied to the gate electrode 229A at the beginning of exposure. The charge draining portion 229 further operates to prevent the saturation of the photodiode 221 and the overflow of the charge during the reading period after the end of exposure. A specified voltage VDA is applied to the draining portion 236.

[0461] (Potential of the gate electrode of the memory portion 223)

[0462] Here, a description will be given of the potential of the gate electrode 222A of the memory portion 223 which is a charge holding region.

[0463] exist Fig.57In the embodiment, the potential of the gate electrode of the memory portion 223 as the charge holding region is set to a potential that brings about a clamped state during a period for which at least any one of the first transfer gate 222 and the second transfer gate 224, for example, the first transfer gate 222 is made non-conductive. More specifically, when the first transfer gate 222 or the second transfer gate 224 or both are made non-conductive, the voltage applied to the gate electrodes 222A and 224A is set to bring about a clamped state in which carriers can be accumulated in the Si surface directly under the gate electrodes.

[0464] As in this example, if the transistor forming the transmission gate is an N-type, when the first transmission gate 222 is made non-conductive, the voltage to be applied to the gate electrode 222A is set to a voltage that makes the potential of the P-type well layer 232 more negative than the ground GND. Although not shown, if the transistor forming the transmission gate is a P-type, the P-type well layer becomes an N-type well layer, and a voltage is set so that the potential of the N-type well layer is higher than the power supply voltage VDD.

[0465] The reason why the voltage to be applied to the gate electrode 222A when the first transfer gate 222 is made non-conductive is set to a voltage that brings about a clamped state in which carriers can be accumulated in the Si surface immediately below the gate electrode is as follows:

[0466] exist Fig.57 In FIG. 2 , assuming that the potential of the gate electrode 222A of the first transfer gate 222 is equal to the potential of the P-type well layer 232 (e.g., 0 V), carriers generated from crystal defects in the Si surface may accumulate in the memory portion 223 to generate dark current, and thus image quality may deteriorate. Fig.57 In the embodiment, the OFF potential of the gate electrode 222A formed on the memory portion 223 is set to a potential more negative than the potential of the P-type well layer 232, for example, -2.0 V. Therefore, in this embodiment, holes (holes: Hole) can be generated in the Si surface of the memory portion 223 during the charge retention period and electrons (electrons: Electron) generated in the Si surface can be coupled again. As a result, dark current can be reduced.

[0467] exist Fig.57 In the embodiment, since the gate electrode 224A of the second transfer gate 224 exists at the end of the memory portion 223, the dark current generated at the end of the memory portion 223 can be suppressed similarly by also setting the gate electrode 224A to a negative potential.

[0468] Fig.57The unit pixel 220 is characterized in that an overflow path 230 formed in a boundary area between the photodiode 221 and the memory portion 223 is used as a way of preferentially accumulating charges generated under low-light conditions in the photodiode 221.

[0469] Fig.58 Shown in Fig.57 Potential diagram in the X direction.

[0470] As from Fig.58 As is clear from the potential diagram in the X direction of FIG. 2 , an N- impurity diffusion region 239 is provided in the boundary region between the photodiode 221 and the memory portion 223 to reduce the potential of the boundary region. The portion where the potential is reduced serves as the overflow path 230. The charge generated in the photodiode 221 and exceeding the potential of the overflow path 230 automatically leaks to the memory portion 223 to be accumulated in the memory portion 223. In another manner, the generated charge equal to or less than the potential of the overflow path 230 is accumulated in the photodiode 221.

[0471] Here, the overflow path 230 has a function as an intermediate charge transfer section. In other words, in an exposure period during which all of the plurality of pixels simultaneously perform imaging operations, the overflow path 230 as the intermediate charge transfer section transfers charges generated by photoelectric conversion in the photodiode 221 and exceeding a specified charge amount determined by the potential of the overflow path 230 to the memory section 223.

[0472] (Photocharge accumulation operation)

[0473] Reference Fig.59 (1) to Fig.59 (5) and Fig.60 (1) to Fig.60 (5) A description is given of the operation from the start of exposure (start of accumulation) to the end of exposure (end of accumulation). Fig.59 (1) to Fig.59 (5) shows the movement of the transfer of photocharges when the luminance of incident light is equal to or higher than a specified luminance and the accumulation amount of photocharges is large, in other words, when the incident light is bright.

[0474] First, (1) a control pulse ABG is applied to the gate electrode 229A to open the charge drain portion 229 and drain the charge of the photodiode 221 .

[0475] (2) The charge drain section 229 is closed again, and the photocharge generated in the photodiode 221 according to the brightness of the incident light is accumulated in the photodiode 221 to start exposure. The charge accumulated in the photodiode 221 (via the overflow path 230) crosses the potential barrier φTRX of the transfer path between the photodiode 221 and the memory section 223 to be accumulated in the memory section 223.

[0476] (3) Photoelectric charges according to the intensity of incident light are accumulated in the photodiode 221 and the memory portion 223. At the end of exposure, the reset transistor 226 is turned on, and the charges of the FD portion 225 flow away (reset operation).

[0477] (4) The transfer pulse TRG is applied to turn on the second transfer gate 224 , and the charges accumulated in the memory portion 223 are transferred to the FD portion 225 .

[0478] (5) Next, a transfer pulse TRX is applied to turn on the first transfer gate 222 , and the charge accumulated in the photodiode 221 is transferred to the memory portion 223 .

[0479] Next Fig.60 (1) to Fig.60 (5) shows the movement of the transfer of photocharge when the brightness of incident light is lower than a specified brightness and the accumulated amount of photocharge is small, in other words, when the incident light is dark.

[0480] The driving in the case of dark incident light is similar to Fig.59 (1) to Fig.59 (5) driver. Fig.60 (1) to Fig.60 (5) Fig.59 (1) to Fig.59 The difference of (5) is that because the incident light is dim, the photocharge according to the intensity of the incident light is accumulated only in the photodiode 221, as shown in FIG. Fig.59 (2) and Fig.59 (3) is shown. In another way, if the incident light is dark, the accumulated charge does not cross the potential barrier φTRX of the transfer circuit. Therefore, (4) the application of the transfer pulse TRG does not cause the charge to be transferred from the second transfer gate 224 to the FD portion 225, but (5) the application of the transfer pulse TRX causes all the charge to be stored in the memory portion 223 by the first transfer gate 222.

[0481] Fig.61 is shown for driving Fig.57 A timing diagram of the method of the unit pixel 220. Fig.61 In this case, (1) to (5) are the same as those described above. Fig.59 (1) to Fig.59 (5) and Fig.60 (1) to Fig.60 (5) corresponds to the operation; therefore, the description will be omitted.

[0482] For the transfer operation until (5) at the end of exposure, the charge is held in the memory portion 223 and the FD portion 225. As described above, no charge is held in the FD portion 225 in the dark pixel.

[0483] (6) In the DH period, the charge accumulated in the FD portion 225 is read as the first signal voltage via the amplification transistor 227 .

[0484] (7) The reset transistor 226 turns on, and the charge of the FD portion 225 flows away.

[0485] (8) In the P period, the reset level of the FD portion 225 is read.

[0486] (9) The transfer pulse TRG is applied to turn on the second transfer gate 224 , and the charge held in the memory portion 223 is transferred to the FD portion 225 .

[0487] (10) In the DL period, the charge of the FD portion 225 is read via the amplification transistor 227 as the second signal voltage.

[0488] The first and second signal voltages can obtain the effect of noise removal by calculating the difference from the reset voltage read in the P period. At this time, the kTC noise by the reset operation is superimposed on the signal voltage stored in the FD part 225; however, the kTC noise is removed from the signal voltage stored in the memory part 223. The signal is stored in the FD part 225 only when the incident light is bright, and because a large amount of signal charge is obtained, the light shot noise becomes the main noise component, and the deterioration of the image quality due to the kTC noise can be ignored. For example: the light shot noise generated in a signal charge of 10,000e- is 100e-rms, and the signal-to-noise ratio is 40.00dB. The kTC noise can be obtained by √(kT / C) and is 25.4e-rms. Assume that k is the Boltzmann coefficient, 1.38×10 -23 (J / K), T is a temperature of 300 (K), and C is a general capacitance value, for example, 4 fF, of the FD portion 225. The sum of the optical shot noise and the kTC noise is 103.2 e-rms, and the signal-to-noise ratio is 39.73 dB, and the difference is small.

[0489] On the other hand, if the incident light is dark and the amount of signal charge is small, all the charges are held in the memory portion 223, and the kTC noise can be removed by calculating the difference from the reset signal.

[0490] In addition, as is clear from using both the photodiode 221 and the memory portion 223 to accumulate during the exposure period, the maximum accumulable charge amount is equal to the maximum accumulable charge amount of the pixel structure without installing the memory portion 223. Therefore, due to the ktc noise, Fig.57 The unit pixel 220 can solve the significant deterioration of image quality and further enable simultaneous global exposure operation with respect to all pixels without reducing the maximum accumulable charge amount.

[0491] (A prerequisite to avoid corruption of output images)

[0492] Here, we will give Fig.57 A description of the prerequisites for avoiding damage to the output image in the unit pixel 220.

[0493] Assuming that the signal charge accumulated according to the intensity of the incident light is Qsig, the charge transferred to the FD portion 225 by the second transfer gate 224 is Qh, and the charge transferred to the memory portion 223 by the first transfer gate 222 is Ql, the signal charge Qsig=charge Qh+charge Ql. Fig.60 (1) to Fig.60 As described in (5), if the incident light is dark and the accumulated charge does not cross the potential barrier φTRX between the photodiode 221 and the memory portion 223, Qh=0.

[0494] In addition, assuming that the maximum value of the charge Ql determined by the potential barrier φTRX is Qp, if the incident light is bright and the accumulated charge of Qsig>Qp is obtained, the charge Qh obtained by Qh=Qsig-Qp is transferred to the FD part 225 by the second transfer gate 224 to be stored. At this time, it is assumed that the potential barrier φTRX changes, and there is a pixel of φTRX+ΔφTRX. Assuming that the change amount of the charge Qp of the difference passing through the potential barrier ΔφTRX is ΔQp, if the accumulated charge Qsig exceeds Qp+ΔQp, the accumulation in the memory part 223 starts and the charge Qh becomes the charge Qh>0 and is stored in the FD part 225.

[0495] In other words, if the signal charge Qsig ≤ charge Qp + change ΔQp, then charge Ql = signal charge Qsig, and charge Qh = 0. The two outputs are added to have charge Qh + charge Ql = signal charge Qsig and obtain a correct signal. On the other hand, if the signal charge Qsig> charge Qp + change ΔQp, the charges Qh and Ql are charge Qh = signal charge Qsig-(charge Qp + change ΔQp), and are read as charge Ql = charge Qp + change ΔQp, and the two outputs are added. Therefore, similarly, charge Qh + charge Ql = signal charge Qsig to obtain a correct signal. In particular, if the output of charge Ql is sufficiently smaller than charge Qp, noise superposition by adding charge Qh can be avoided.

[0496] In this way, if Ql (≤Qp) accumulated in the photodiode 221 after the charge Qh is transferred by the second transfer gate 224 has a charge amount that the memory portion 223 can hold after being transferred to the memory portion 223 by the first transfer gate 222, the change in the potential barrier φTRX does not damage the output image.

[0497] Here, if the maximum charge that the memory portion 223 can store is Qm, the condition is that the maximum charge Qm ≥ charge Qp to obtain an output image without damage. If the area of ​​the memory portion 223 is expanded and the area of ​​the photodiode 221 is reduced, it is easy to have a relationship of the barrier φTRX ≥ charge Qp of the maximum charge Qm. However, in reality, the area of ​​the opening is increased by increasing the area of ​​the photodiode 221 to make the sensitivity better, or the range of the signal with low noise on which the kTC noise is not superimposed can be extended by increasing the charge Qp, etc. Therefore, it is important to achieve higher image quality by maximizing the charge Qp while maintaining the relationship of the maximum charge Qm ≥ charge Qp.

[0498] In particular, if the signal charge Qsig ≤ charge Qp, it is preferred that the charge Qh should not be added to the charge Ql and output to prevent superimposed noise; however, if the charge Qh≈0, addition is necessary and therefore it is necessary to judge whether to add the minimum value of the charge Qp as a threshold. In other words, if there is a pixel having the charge Qp-change amount ΔQp as the minimum value due to the large change in the potential barrier φTRX, there is a problem of narrowing the signal area with low noise in which the noise of the charge Qh is not superimposed. In addition, since it is necessary to satisfy the charge Qm≥charge Qp, if there is a pixel in which the charge Qp+change amount ΔQp is the maximum value, it is necessary to increase the charge Qm, and there is a problem of reducing the charge Qp due to the expansion of the memory part 223 and the reduction of the photodiode 221.

[0499] Therefore, reduction in variation of the potential barrier φTRX is required to improve sensitivity while maximizing the area of ​​the photodiode 221 and to achieve higher quality of the output image while maximizing the low-noise signal range.

[0500] [7-2. Problems to be solved]

[0501] However, as in Fig.57 In the unit pixel 220, if the potential barrier φTRX is formed by the transfer path of the first transfer gate 222 between the photodiode 221 and the memory portion 223, there is a limit to reducing the variation of the potential barrier φTRX for the following reason.

[0502] It is preferable to design the impurity diffusion region (OFB) 239 forming the potential barrier φTRX Fig.62 The interval L shown in A (hereinafter appropriately referred to as L length) is as narrow as possible to maximize the accumulated charge Qp of the photodiode 221 and the maximum charge amount Qm of the memory portion 223 .

[0503] However, if Fig.62 As shown in FIG. 1B, the L length of the impurity diffusion region 239 is designed to be narrow; therefore, the change ΔφTRX of the potential barrier φTRX is significantly affected by the change Δd in the width of the resist of the resist mask 360 provided at the time of ion implantation. In other words, if the L length of the impurity diffusion region 239 is designed to be narrow to ensure the area of ​​the photodiode 221 and the memory portion 223, the density of the impurities of the impurity diffusion region 239 is significantly changed due to the change Δd in the width of the resist, and this also causes a large change in the change ΔφTRX of the potential barrier φTRX.

[0504] On the contrary, Fig.62 As shown in FIG. 3 , if the L length of the impurity diffusion region 239 is designed to be wide, the variation ΔφTRX of the potential barrier φTRX can be suppressed; however, the area of ​​the photodiode 221 and the memory portion 223 is significantly reduced. Therefore, from the perspective of maximizing the accumulated charge Qp of the photodiode 221 and the maximum charge amount Qm of the memory portion 223, it is difficult to extend the length (L length) of the transfer path in a structure in which the first transfer gate 222 is used as both an intermediate transfer path (overflow path 230) and a complete transfer path.

[0505] Furthermore, the impurity diffusion region (OFB) 239 forming the overflow path 230 designed to fall in a depleted state before charge accumulation is modulated by charge accumulation of the photodiode 221 .

[0506] For example, Fig.63As shown, assuming that the capacitance between the photodiode 221 and the barrier φTRX is C1, the other capacitance value of the photodiode 221 is Cg, and the capacitance between the memory portion 223 and the barrier φTRX is C2, the capacitance Cp of the accumulated charge is expressed as Cp=Cg+C1·C2 / (C1+C2). In this case, if the charge of ΔQsig is accumulated in the photodiode 221, the potential φp of the photodiode 221 changes by Δφp=ΔQsig / Cp. At this time, the barrier φTRX is modulated by ΔφTRX(p)=(C1 / (C1+C2))·Δφp. In other words, ΔφTRX(p) represents the modulation of the barrier φTRX by the change in the potential of the photodiode due to the accumulation of the charge of the photodiode 221.

[0507] It is more preferable that the change ΔφTRX(p) of the potential barrier φTRX caused by the barrier modulation of the charge accumulation of the photodiode 221 is also reduced. However, it is necessary to make the deepest point of the potential of the photodiode 221 close to the complete transmission path to increase the transmission efficiency of the complete transmission path. Therefore, Fig.57 The unit pixel 220 has a structure in which it is difficult to obtain the effect of reducing the modulation amount ΔφTRX(p) of the potential barrier φTRX due to the reduction of the capacitance C1 between the photodiode 221 and the potential barrier φTRX.

[0508] In this way, in Fig.57 The modulation amount ΔφTRX(p) of the charge accumulation reduction barrier φTRX which is difficult to pass through the photodiode 221 in the unit pixel 220 is increased. Therefore, the change amount ΔQp among (charge Qp+change amount ΔQp) which should be considered as the maximum value of the charge Qp when the maximum charge Qm≥charge Qp is satisfied increases. As a result, it becomes necessary to increase the maximum charge Qm additionally.

[0509] [7-3. Unit Pixel of Embodiment]

[0510] (Structure of Unit Pixel 320)

[0511] Therefore, in order to improve Fig.57 In other words, in order to promote the reduction of the variation of the potential barrier φTRX and the reduction of the modulation amount ΔφTRX(p) of the potential barrier φTRX, the CMOS image sensor 10 in this embodiment adopts Fig.64 A and Fig.64 B shows the structure that makes the intermediate transmission path robust.

[0512] in other words, Fig.64 A and Fig.64 B shows the structure of a unit pixel 320 employed in the CMOS image sensor 10 . Fig.64 A is along Fig.64B is a cross-sectional view of the unit pixel 320 taken along the arrow ZZ', and Fig.64 B is a plan view showing the configuration of the unit pixel 320 .

[0513] In the unit pixel 320, the N-type buried layer 334 of the photodiode 221 is formed in such a manner as to extend under the memory portion 223 (on the deeper side of the substrate). Fig.64 The N-type buried layer 334 is formed in an L shape in the cross section shown in FIG. 64B , the region of the N-type buried layer 334 of the photodiode 221 extending to the memory portion 223 side substantially overlaps with the gate electrode 222A of the memory portion 223 .

[0514] In the unit pixel 320, an impurity diffusion region 342 is formed in a boundary region between the lower surface of the buried trench 235 of the memory portion 223 and the upper surface of the N-type buried layer 334 extending under the memory portion 223; thus, an intermediate transfer path 340 is provided. Therefore, the intermediate transfer path 340 is not controlled (modulated) by the first transfer gate 222.

[0515] In this way, an impurity diffusion region 342 is formed in the boundary region between the lower surface of the buried trench 235 and the upper surface of the N-type buried layer 334; therefore, for example, compared to a case where the impurity diffusion region 342 is formed in the boundary region between the side of the buried trench 235 and the N-type buried layer 334, leakage of incident light into the impurity diffusion region 342 can be suppressed.

[0516] Furthermore, the intermediate transfer path 340 is formed only by the distribution of the impurities in the depth direction; therefore, variations caused by the row width and the lamination of masks are reduced, and thus variations in the potential barrier φTRX can be reduced.

[0517] In another way, due to the density of the impurities of the impurity diffusion region 342 forming the intermediate transfer path 340 , the potential barrier φ TRX that determines a specified charge amount by which the accumulated charges of the photodiode 221 overflow into the memory portion 223 can be stably formed.

[0518] As described above, in the unit pixel 320, variations in the potential barrier φTRX caused by misalignment of the mask, variations in the width of the resist, diffusion of impurities from the high-density impurity diffusion region, the position and potential of the electrode of the first transfer gate 222, and the accumulated charge amount of the photodiode 221 can be reduced.

[0519] On the other hand, similar to Fig.57 In the unit pixel 220 of FIG. 2 , the complete transfer path 350 is formed on the surface side. Therefore, the transfer pulse TRX is applied to the first transfer gate 222 to perform complete transfer via the complete transfer path 350 .

[0520] Because the intermediate transmission path 340 and the complete transmission path 350 are isolated and the density of impurities in the impurity diffusion region 342 can form a stable potential barrier φTRX, sensitivity improvement can be achieved by maximizing the area of ​​the photodiode 221, and higher quality of the output image can be achieved by maximizing the low-noise signal range without reducing the transmission efficiency of the complete transmission.

[0521] like Fig.64 B, from a planar viewpoint, in addition to being disposed near the center of the memory portion 223, the impurity diffusion region 342 may also be disposed at a position farther away from the photodiode 221 than the position shown in the figure or may be disposed in a manner away from the deepest point of the potential of the photodiode 221. The impurity diffusion region 342 used as the intermediate transfer path 340 is disposed at a position away from the photodiode 221 in this manner; therefore, the leakage of incident light can be further reduced.

[0522] (Considerations for designing unit pixels of 320)

[0523] However, it is necessary to give Fig.64 A and Fig.64 The unit pixel 320 shown in B having a structure that makes the intermediate transmission path robust is considered below.

[0524] Reference Fig.65 A and Fig.65 B and Fig.66 A to Fig.66 C gives a description of problems that may occur in the unit pixel 320 having a structure that makes the intermediate transfer path robust.

[0525] Fig.65 A and Fig.65 B shows that when Fig.57 The potential diagram of the intermediate transfer path and the complete transfer path when the overflow path 230 of the intermediate transfer path of the unit pixel 220 is simply rearranged below the memory portion 223 (in the depth direction) is shown. Fig.65 A shows that along Fig.64 The potential diagram of the complete transmission path in the cross section taken by the arrow X-X' of A, and Fig.65 B shows that along Fig.64 Potential diagram of the intermediate transmission path in the cross section taken by arrow YY' in A.

[0526] if Fig.65 It is sufficient for the complete transmission path of A to completely deplete the photodiode 221 when the first transmission gate 222 is turned on. Fig.57 The overflow path 230 of the unit pixel 220 is shown, and thus a potential barrier between the photodiode 221 and the memory portion 223 is formed to be higher than a potential barrier when the overflow path 230 is provided.

[0527] on the other hand, Fig.65 The potential barrier φTRX of the intermediate transmission path of B corresponds to Fig.57 The overflow path 230 of the unit pixel 220 shown is thus formed to be lower than the complete transfer path when the first transfer gate 222 is turned off. However, the intermediate transfer path is not controlled by the first transfer gate 222; therefore, the potential barrier φTRX does not change even when the first transfer gate 222 is turned on. In addition, the deepest point of the potential of the photodiode 221 is formed in a region close to the complete transfer path to increase the transfer efficiency of the complete transfer; therefore, the distance to the intermediate transfer path naturally becomes farther. Therefore, the modulation amount ΔφTRX(p) of the potential barrier φTRX depending on the accumulated charge amount of the photodiode 221 can be reduced.

[0528] As described above, the structure that makes the intermediate transfer path robust extends the distance between the deepest point of the potential of the photodiode 221 and the intermediate transfer path becomes farther; therefore, the modulation amount ΔφTRX(p) of the potential barrier φTRX caused by the charge accumulation of the photodiode 221 can be reduced. However, on the contrary, the intermediate transfer path becomes close to the deepest point of the potential of the memory part 223; therefore, the modulation amount ΔφTRX(m) of the potential barrier φTRX with respect to the charge accumulation of the memory part 223 may become relatively large. In this case, the charge Qh to be transferred to the FD part 225 by the second transfer gate 224 is reduced (compared with the amount expected from the area of ​​the pixel).

[0529] Reference Fig.66 A to Fig.66 C gives a more detailed description.

[0530] Fig.66 A shows a depletion state in which charge is not accumulated in any of the photodiode 221 and the memory portion 223, and is Fig.65 A and Fig.65 The state shown in B is the same state.

[0531] In a depletion state in which electric charge is not accumulated in any of the photodiode 221 and the memory portion 223 , the height (potential barrier) of the intermediate transfer path is φTRX.

[0532] Fig.66 B shows a state in which charges photoelectrically converted from incident light are accumulated (only) in the photodiode 221 .

[0533] The intermediate transfer path is modulated by the charge accumulation 221 of the photodiode, and its height is φTRX+ΔφTRX(p). Assuming that the modulation amount ΔφTRX(p) changes the amount of charge accumulated in the photodiode 221, and Fig.66ΔφTRX(p) shown in B is the modulation amount in a state where charges are accumulated until the maximum amount is only in the photodiode 221. As viewed from the photodiode 221, φTRX+ΔφTRX(p) is sufficiently lower than the height of the potential barrier of the (small) other paths; therefore, Fig.66 Photoelectric conversion is further performed in the photodiode 221 in the state of B, and if charges are generated, all the generated charges overflow to the memory portion 223 side. Therefore, if the charge Ql and the charge Qh are added at the end, the linearity of the signal with respect to the light amount is maintained.

[0534] Fig.66 C shows that Fig.66 In the state B, the charge generated by further photoelectric conversion in the photodiode 221 overflows into the memory portion 223.

[0535] The charge overflowing from the photodiode 221 is accumulated in the memory portion 223. The height φTRX of the intermediate transfer path is further modulated by the accumulated charge in the memory portion 223, and the result is φTRX+ΔφTRX(p)+ΔφTRX(m). Here, ΔφTRX(m) is the modulation amount of the potential barrier φTRX with respect to the charge accumulation of the memory portion 223. The problem at this time is that the modulation amount ΔφTRX(m) of the potential barrier φTRX with respect to the charge accumulation of the memory portion 223 is large. In other words, since the intermediate transfer path is formed on the deeper side in the depth direction with respect to the memory portion 223, the distance between the intermediate transfer path and the deepest point of the potential of the memory portion 223 is close. In addition, since the intermediate transfer path is floating, the potential change caused by the charge accumulation of the memory portion 223 is easily modulated. Therefore, the height of the potential barrier becomes as high as φTRX+ΔφTRX(p)+ΔφTRX(m), and the potential difference with other potential barriers becomes smaller when viewed from the photodiode 221. As a result, the accumulated charge amount of the memory portion 223 begins to overflow into other portions outside the memory portion 223 before reaching the charge amount that can be inherently accumulated in the memory portion 223. Here, the charge amount that can be inherently accumulated in the memory portion 223 indicates Fig.66 The region shown in C includes an empty region of the memory portion 223 above the charges accumulated in the memory portion 223. If an overflow path from the photodiode 221 to other portions outside the memory portion 223 is generated in a state where the empty region exists, it is impossible to fully utilize the accumulation performance that the memory portion 223 essentially has. As a result, the linearity of the signal with respect to the light amount collapses, and the signal range that can be actually used (saturated signal amount) becomes narrower.

[0536] In order to simply solve this problem, it is considered to increase the potential difference between the intermediate transfer path and other paths by any of the following methods: (1) making the potential barriers of other paths other than the intermediate transfer path viewed from the photodiode 221 still high and (2) lowering the intermediate transfer path. However, these two measures are not available for the following reasons. Considering (1), because the signal is initially prevented from overflowing (sprouting) between adjacent pixels, the potential barriers of other buses are formed sufficiently high; therefore, it is generally impossible to further increase their height. In addition, considering (2), because only the charge Ql accumulated in the photodiode 221 is reduced, the FD part 225 (charge Qh) is used from the area where the signal amount is small; therefore, the S / N deteriorates and therefore its selection cannot be simply performed.

[0537] Therefore, the unit pixel 320 of the CMOS image sensor 10 adopts Fig.67 The structure shown.

[0538] Fig.67 As shown in the unit pixel 320 of the CMOS image sensor 10, Fig.64 The complete transport path 350 (first transport path) on the cross section taken along arrow XX' of A and Fig.64 A potential diagram of the intermediate transfer path 340 (second transfer path) on a cross section taken along arrow YY'.

[0539] like Fig.67 As shown, the height of the potential barrier of the complete transfer path 350, in other words, the height of the potential barrier φTRX1 is higher than the height of the potential barrier of the intermediate transfer path 340, in other words, the height of the potential barrier φTRX2. However, the height of the potential barrier of the complete transfer path 350 is lower than the height of the potential barrier of the path other than the transfer path from the photodiode 221 to the memory section 223. Therefore, if the intermediate transfer path 340 does not exist, all the charges accumulated in the photodiode 221 overflow into the memory section 223 via the complete transfer path 350. Conversely, if the intermediate transfer path 340 does not exist, the height of the potential barrier of the complete transfer path 350 (the height of the potential barrier φTRX1) is formed so that all the charges accumulated in the photodiode 221 overflow into the memory section 223 via the complete transfer path 350.

[0540] If the barrier heights of the complete transfer path 350 and the intermediate transfer path 340 are expressed by potential, the potential of the complete transfer path 350 is formed to be lower than the potential of the intermediate transfer path 340 and higher than the potential of the barriers of paths other than the transfer path from the photodiode 221 to the memory part 223.

[0541] The complete transfer path 350 has a structure to be sandwiched between the photodiode 221 and the memory part 223; therefore, when the intermediate transfer path 340 is formed, the density difference between the density of impurities of the memory part 223 as the charge transfer destination and the density of impurities of the impurity diffusion region 342 for forming the potential barrier φTRX2 is reduced, and the potential barrier in the impurity diffusion region 342 is not weakened by the controllability of the impurity diffusion of the memory part 223.

[0542] The potential barriers of the paths other than the transfer path from the photodiode 221 to the memory portion 223 include, for example, the potential barriers of the path from the photodiode 221 to the charge drain portion 229, which is Fig.67 The potential barrier on the left side of the photodiode 221.

[0543] (Operation of Accumulating Photocharges in Unit Pixel 320)

[0544] Reference Fig.68 A to Fig.68 C is given in Fig.67 A description of the operation of accumulating photocharges in the unit pixel 320 formed as shown. Fig.68 A to Fig.68 The state shown in C corresponds to Fig.66 A to Fig.66 The status of C.

[0545] Fig.68 A shows a depletion state in which charge is not accumulated in any of the photodiode 221 and the memory portion 223, and is Fig.67 The status shown is the same as the status.

[0546] Fig.68 B shows a state in which charges photoelectrically converted from incident light are accumulated (only) in the photodiode 221 .

[0547] By the charge accumulation of the photodiode 221, the complete transfer path 350 and the intermediate transfer path 340 are modulated, and the results of their heights are φTRX1+ΔφTRX1(p) and φTRX2+ΔφTRX2(p), respectively. The height φTRX2+ΔφTRX2(p) of the potential barrier of the intermediate transfer path 340 is formed to be lower than the height φTRX1+ΔφTRX1(p) of the potential barrier of the complete transfer path 350. Therefore, if a charge equal to or greater than a specified amount is generated in the photodiode 221, the charge first overflows from the photodiode 221 to the memory portion 223 via the intermediate transfer path 340.

[0548] The charge Q1 accumulated in the photodiode 221 is limited to the height φTRX2 of the potential barrier of the intermediate transfer path 340. The height φTRX2 of the potential barrier of the intermediate transfer path 340 can be formed in a manner that blocks the modulation of the accumulation through the photodiode 221 and is robust from a processing point of view (not affected by variations in mask line width and stacking). Therefore, it is possible to design a sufficient charge Q1 for the need.

[0549] Fig.68 C shows a state in which the charges overflowing from the photodiode 221 are accumulated in the memory portion 223 .

[0550] If the charge overflowed from the photodiode 221 is accumulated in the memory portion 223, the height φTRX2 of the potential barrier of the intermediate transfer path 340, which is sensitive to the modulation with respect to the accumulation of the memory portion 223, gradually increases. In other words, the height of the potential barrier of the intermediate transfer path 340 increases by the modulation amount ΔφTRX2(m) with respect to the accumulation of the memory portion 223, resulting in φTRX2+ΔφTRX2(p)+ΔφTRX2(m).

[0551] However, the potential barrier 350 of the complete transfer path blocks the modulation of the accumulation with respect to the memory portion 223, compared with the potential barrier of the intermediate transfer path 340. Therefore, even if the intermediate transfer path 340 is modulated and its height increases to φTRX2+ΔφTRX2(p)+ΔφTRX2(m), the complete transfer path 350 serves as an overflow path. In other words, after a certain amount of charge is accumulated in the memory portion 223, the height φTRX1+ΔφTRX1(p)+ΔφTRX1(m) of the potential barrier of the complete transfer path 350 becomes lower than the height φTRX2+ΔφTRX2(p)+ΔφTRX2(m) of the potential barrier of the intermediate transfer path 340. Therefore, after a certain amount of charge is accumulated in the memory portion 223, all the charges generated in the photodiode 221 overflow into the memory portion 223 via the complete transfer path 350.

[0552] Therefore, since the modulation amount φTRX1(m) of the potential barrier φTRX1 for charge accumulation of the memory portion 223 is large, Fig.67 The unit pixel 320 can prevent overflow from the photodiode 221 to portions other than the memory portion 223 before the memory portion 223 is saturated.

[0553] As described above, even if charges are accumulated in the memory portion 223, the charges are overflowed (transferred) through the full transfer path 350 that blocks modulation compared to the intermediate transfer path 340; therefore, the charges can be saved, fully utilizing the memory portion 223. Therefore, high quality of the output image can be achieved by maximizing the saturation signal amount and by extending the extension of the signal range.

[0554] The reason why the potential barrier of the full transmission path 350 blocks the modulation regarding the accumulation of the memory portion 223 compared to the potential barrier of the intermediate transmission path 340 is because it is biased via the first transmission gate 222 and close to the P-type layer 233 which is a dense P-type impurity formed in the surface of the photodiode 221; therefore, the capacitance component of the memory portion 223 among all the capacitors remains lower than the potential barrier of the intermediate transmission path 340.

[0555] Furthermore, it is sufficient if the potential barrier of the complete transmission path 350 is formed to be higher than the potential barrier of the intermediate transmission path 340 and lower than the potential barrier of the paths other than the intermediate transmission path 340; Fig.57 Compared with the unit pixel 220, it is beneficial that there is a Fig.67 There are fewer restrictions on the design of the unit pixel 320.

[0556] (accomplish Fig.67 Specific example of a bit barrier 1)

[0557] Reference Fig.69 Given the form Fig.67 A description of a specific example 1 of the heights of the potential barriers of the complete transfer path 350 and the intermediate transfer path 340 is shown.

[0558] exist Fig.69 In the structure of the unit pixel 320 shown, the distance (interval) between the impurity diffusion regions is adjusted to adjust the heights of the potential barriers of the complete transfer path 350 and the intermediate transfer path 340 .

[0559] For example, the buried trench 235 of the memory portion 223 is formed with a depth of about 0.2 to 0.6 μm from the substrate surface (interface), and the impurity diffusion region 342 as the intermediate transfer path 340 is formed with a depth of about 0.1 to 0.4 μm from the lower surface of the buried trench 235. Therefore, the distance between the upper surface of the N-type buried layer 334 formed under the buried trench 235 of the memory portion 223 and the substrate surface (interface) is about 0.3 to 1.0 μm. In addition, it is formed so that the distance in the horizontal direction between the buried trench 235 of the memory portion 223 and the N-type buried layer 334 of the photodiode 221 is about 0.1 to 0.4 μm.

[0560] (accomplish Fig.67 Specific example of a bit barrier 2)

[0561] Reference Fig.70 Given the form Fig.67 A description of specific example 2 of the heights of the potential barriers of the complete transfer path 350 and the intermediate transfer path 340 is shown.

[0562] Fig.70The structure of a unit pixel 320B which is a modified example of the unit pixel 320 is shown.

[0563] exist Fig.70 In the unit pixel 320B, an impurity diffusion region 341 is newly formed in the substrate surface between the N-type buried layer 334 and the buried trench 235. As a result, the height of the potential barrier of the complete transfer path 350 is formed to be lower than the height of the potential barrier of the path other than the transfer path from the photodiode 221 to the memory portion 223.

[0564] A description will be given of the density of each impurity diffusion region that determines the height of the potential barrier of the complete transfer path 350 and the intermediate transfer path 340 of the unit pixel 320B.

[0565] The photodiode 221 and the memory portion 223 are formed at an impurity density that brings about a depletion state when leaking charges, and the FD portion 225 is formed at an impurity density that allows a wiring for extracting a voltage to be electrically connected thereto.

[0566] More specifically, assuming that the density of the P-type impurities in the P-type well layer 232 formed on the N-type substrate 231 is, for example, 10 15 / cm 3 In this case, the N-type buried layer 334 of the photodiode 221 and the buried trench 235 of the memory portion 223 have an N-type impurity density that causes a depletion state when the charge is drained, for example, 1×10 16 to 1×10 17 / cm 3 form.

[0567] The impurity diffusion region 342 used as the intermediate transfer path 340 becomes depleted when the charge is leaked, and has an impurity density that can form a potential barrier φTRX2. Depending on the height of the potential barrier φTRX2 determined according to the specified charge amount, the impurity density of the impurity diffusion region 342 is set between the density of the P-type impurity and the density of the N-type impurity lower than the impurity density of the N-type buried layer 334 of the photodiode 221 and the buried trench 235 of the memory portion 223.

[0568] The impurity diffusion region 341 formed on the substrate surface side for the complete transfer path 350 is formed with a P-type impurity density higher than that of the impurity diffusion region 342 of the intermediate transfer path 340, and is set to, for example, 1×10 18 to 1×10 19 / cm 3 The impurity diffusion region 341 may be formed with an N-type impurity density still lower than that of the impurity diffusion region 342 of the intermediate transfer path 340 .

[0569] The FD portion 225 is formed with, for example, 1×10 19to 1×10 20 / cm 3 The density of N-type impurities.

[0570] As described above, at least one of the distances in the horizontal direction and the depth direction between the N-type buried layer 334, the buried trench 235 and the impurity diffusion region 342 and their impurity densities are appropriately adjusted; therefore, the potential barrier of the complete transmission path 350 is formed to be higher than the potential barrier of the intermediate transmission path 340 and lower than the potential barrier of the path other than the intermediate transmission path 340.

[0571] (Method of Manufacturing Unit Pixel 320)

[0572] Next, we will refer to Fig.71 Give manufacturing Fig.64 A( Fig.69 )'s unit pixel 320 method.

[0573] In the first step, N-type ions are implanted using the resist 360-1 formed on the surface of the substrate to form a portion 334' of the N-type buried layer 334. Fig.64 As shown in the cross-sectional view of FIG. 4A , the resist 360 - 1 is used to form an N-type buried layer 334 extending below the buried trench 335 and an opening in a region corresponding to a portion 334 ′ of the N-type buried layer 334 .

[0574] In the second step, a resist 360 - 2 is formed on the surface of the substrate. The resist 360 - 2 is used to form the impurity diffusion region 342 and an opening in a region corresponding to the impurity diffusion 342 .

[0575] In the third step, the impurity diffusion region 342 is formed by implanting N type ions using the resist 360 - 2 so as to be in contact with the upper surface of the portion 334 ′ of the N type buried layer 334 .

[0576] In the fourth step, N-type ions are implanted to form a buried trench 335 using a resist 360-3 formed on the surface of the substrate, and then the memory portion 223 is provided. The resist 360-3 is used to form the buried trench 335 and an opening in a region corresponding to the buried trench 335.

[0577] Next, after removing the resist 360-3, in the fifth step, a polysilicon layer 222A' serving as a gate electrode 222A is formed on the substrate surface. In the sixth step, a resist 360-4 is formed in a region corresponding to the gate electrode 222A on the surface of the polysilicon layer 222A', and in the seventh step, etching is performed to remove unnecessary portions of the polysilicon layer 222A' and form the gate electrode 222A.

[0578] In the eighth step, N type ions are implanted to form a portion other than the portion 334 ′ formed in the first step, and thus, the N type buried layer 334 is formed.

[0579] The above steps can be used to manufacture Fig.64 A( Fig.69 ) unit pixel 320.

[0580] If manufacturing Fig.70 In other words, if an impurity diffusion region 341 is formed in the substrate surface between the N-type buried layer 334 and the buried trench 235, then Fig.71 Add between the fourth and fifth steps Fig.72 Steps shown.

[0581] In other words, Fig.72 As shown, after applying the resist 360-5, a portion corresponding to the impurity diffusion region 341 is opened. Subsequently, N-type ions are implanted to reduce the density of the P-type impurities, and a step of forming the impurity diffusion region 341 in the substrate surface is added.

[0582] (Another structural example of the unit pixel 320)

[0583] Fig.73 A structure of a unit pixel 320C as another example of the unit pixel 320 is shown.

[0584] It is desirable that the photodiode 221 should be formed symmetrically with respect to the center of the opening into which the light is incident. This is because the sensitivity to the incident light angle of the photodiode 221 is equal without bias from any direction. Fig.73 In the unit pixel 320C shown, although it is formed in a shape extending under the memory portion 223 in a manner overlapping with a part of the memory portion 223 from a planar viewpoint, the photodiode 221 is formed in a shape symmetrical with the center of the opening (opening center) into which light is incident. An intermediate transmission path 340 is formed in the overlapping portion of the photodiode 221 and the memory portion 223. Therefore, the photodiode 221 can receive light equally from any direction.

[0585] (Another structural example of the unit pixel 320)

[0586] Fig.74 A and Fig.74 B and Fig.75 As another example of the unit pixel 320 , a structure of a unit pixel 320D is shown.

[0587] Fig.74 A is a plan view showing the structure of a unit pixel 320D, and Fig.74 B is along Fig.74A is a cross-sectional view of the unit pixel 320D taken along the arrow ZZ′.

[0588] From a planar viewpoint, the N-type buried layer 334 and the buried trench 235 are formed so that a portion of the N-type buried layer 334 of the photodiode 221 and a portion of the buried trench 235 of the memory portion 223 of the unit pixel 320D are located in the width direction ( Fig.74 The impurity diffusion region 342 is formed in the isolation region in the depth direction to provide the intermediate transfer path 340.

[0589] On the other hand, with respect to the complete transmission path 350, similar to the above-described Fig.64 A and Fig.64 In the unit pixel 320 of B, the distance between the N-type buried layer 334 and the buried trench 235 is adjusted to adjust the height of the potential barrier of the complete transmission path 350 .

[0590] Fig.75 Show Fig.74 A and Fig.74 B is a modification of the unit pixel 320D.

[0591] exist Fig.75 In the unit pixel 320D-1, the overlapping portion of the N-type buried layer 334 of the photodiode 221 and the buried trench 235 of the memory portion 223 in the boundary region between the photodiode 221 and the memory portion 223 has an area smaller than 100 μm when viewed from a planar perspective. Fig.74 A and Fig.74 Case B. The impurity diffusion region 342 is formed small by making the overlapping region small in this way, and a phenomenon in which photocharges generated by light incident on the photodiode 221 being incident on the impurity diffusion region 342 of the intermediate transfer path 340 leak to the memory portion 223 can be suppressed.

[0592] (Method for driving unit pixel 320)

[0593] A description will be given of a method for driving the unit pixel 320 .

[0594] The method for driving the unit pixel 320 is basically the same as Fig.61 The driving method is the same as shown. However, although Fig.61 Not shown in Fig.61In the exposure period of (1) to (3) in FIG. 1 , the photocharge generated in the photodiode 221 according to the brightness of the incident light is initially transferred to the memory portion 223 via the intermediate transfer path 340, and then transferred to the memory portion 223 via the complete transfer path 350 after a certain period of time. In other words, when the charge accumulated in the photodiode 221 reaches a first charge amount or more, the overflowing charge is transferred to the memory portion 223 via the intermediate transfer path 340, and when the charge accumulated in the photodiode 221 and the memory portion 223 reaches a second charge amount or more (the second charge amount is greater than the first charge amount), the transfer path of the charge is changed from the intermediate transfer path 340 to the complete transfer path 350.

[0595] (Configuration example of another unit pixel)

[0596] The unit pixel 320 of the above-described embodiment has a structure in which photocharges generated in the photodiode 221 are stored in two charge storage portions, the memory portion 223 and the FD portion 225 , and under their memory portion 223 , an intermediate transfer path 340 from the photodiode 221 is formed.

[0597] However, the present technology can be similarly applied to e.g. Fig.76 The unit pixel 330 shown in FIG. 3 is a unit pixel 330 in which the first transfer gate 222 and the memory portion 223 in the unit pixel 320 are omitted and the photocharge is stored only in the FD portion 225. In this case, an N-type buried layer 334 is formed to extend under a portion of the FD portion 225 or the entire FD portion 225. An impurity diffusion region 342 is formed in a boundary region between the lower surface of the FD portion 225 and the upper surface of the N-type buried layer 334 extending under the FD portion 225; thus, an intermediate transfer path 340 is provided. On the other hand, similar to the unit pixel 320, a complete transfer path 350 is formed on the surface side between the photodiode 221 and the FD portion 225.

[0598] <8. Electronic devices>

[0599] (Block diagram of electronic device)

[0600] Fig.77 is a schematic block diagram of an electronic device 500 according to an embodiment to which the present technology is applied.

[0601] Fig.77The electronic device 500 includes an optical unit 501 including a lens group, a solid-state imaging device (imaging device) 502 of the above-described configuration in which the unit pixel 320 is adopted, and a DSP (digital signal processor) circuit 503 as a camera signal processing circuit. In addition, the electronic device 500 also includes a frame memory 504, a display unit 505, a recording unit 506, an operation unit 507, and a power supply unit 508. The DSP circuit 503, the frame memory 504, the display unit 505, the recording unit 506, the operation unit 507, and the power supply unit 508 are connected to each other via a bus 509.

[0602] The optical unit 501 captures incident light (image light) from the subject and forms an image on the image plane of the solid-state imaging device 502. The solid-state imaging device 502 converts the amount of incident light that forms an image on the image plane through the optical unit 501 into an electrical signal for each pixel and outputs the electrical signal as a pixel signal. A solid-state imaging device of the CMOS image sensor 10, in other words, a solid-state imaging device that can realize imaging without distortion due to global exposure and can suppress the leakage signal suppression ratio for each pixel of RGB can be used as the solid-state imaging device 502.

[0603] The display unit 505 includes, for example, a panel type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image imaged by the solid-state imaging device 502. The recording unit 506 records the moving image or the still image imaged by the solid-state imaging device 502 in a recording medium such as a video tape or a DVD (Digital Versatile Disk).

[0604] The operation unit 507 issues operation instructions for various functions of the electronic device 500 under the operation of the user. The power supply unit 508 appropriately supplies various power sources as operation power sources of the DSP circuit 503, the frame memory 504, the display unit 505, the recording unit 506, and the operation unit 507 to these supply targets.

[0605] As described above, using the CMOS image sensor 10 according to the above-described embodiment as the solid-state imaging device 502 makes it possible to achieve imaging without distortion due to global exposure and to suppress the leakage signal suppression ratio for each pixel of RGB. Therefore, higher quality of imaged images can be promoted in the electronic device 500 such as a video camera and a digital camera, and also a camera module for a mobile device including a mobile phone.

[0606] In addition, in the above-mentioned embodiment, the description has been given by taking as an example the case where the present technology is applied to a CMOS image sensor in which unit pixels that detect signal charges according to the amount of visible light as a physical quantity are arranged in a matrix. However, the present technology is not limited to application to a CMOS image sensor, but can be applied to a general solid-state imaging device of a column type in which a column processing unit is provided for each pixel row of a pixel array unit.

[0607] In addition, the present technology can be applied not only to solid-state imaging devices that detect the distribution of the amount of incident visible light and image the distribution as an image, but also to solid-state imaging devices that image the distribution of the amount of incident infrared rays, X-rays, particles, etc. as an image, and in a broad sense, to general solid-state imaging devices (physical quantity distribution detection devices) that detect the distribution of another physical quantity such as pressure and capacitance and image the distribution as an image, such as fingerprint detection sensors.

[0608] The solid-state imaging device may be formed as one chip or may be formed as a module in which an imaging unit and a signal processing unit or an optical system are packaged together, the module having an imaging function.

[0609] The embodiments of the present technology are not limited to the above-described embodiments, but various modifications can be made without departing from the essence of the present technology.

[0610] This technology may take the following structure:

[0611] (1) A solid-state imaging device comprising:

[0612] a first channel portion of the first conductivity type located between the charge accumulation region of the second conductivity type and the photodiode; and

[0613] An overflow path of the second conductivity type is located between the intermediate electrode of the second conductivity type and the charge accumulation region.

[0614] (2) The solid-state imaging device according to claim 1, wherein the intermediate electrode is electrically connected to the charge accumulation portion.

[0615] (3) The solid-state imaging device according to claim 1, further comprising:

[0616] A semiconductor region of a first conductivity type in a surface layer portion of the charge accumulation region, the first conductivity type semiconductor region being located between the first channel portion and the overflow path.

[0617] (4) The solid-state imaging device according to claim 1, further comprising:

[0618] A semiconductor region of the first conductivity type in a surface layer portion of the first channel portion.

[0619] (5) The solid-state imaging device according to claim 1, further comprising:

[0620] A semiconductor region of a first conductivity type in a surface layer portion of the photodiode.

[0621] (6) The solid-state imaging device according to claim 1, wherein the intermediate electrode is an electrode of a capacitor.

[0622] (7) The solid-state imaging device according to claim 1, wherein the charge accumulation portion is a capacitor.

[0623] (8) The solid-state imaging device according to claim 1, wherein the charge accumulation portion has a higher capacitance value per unit area than that of the charge accumulation region.

[0624] (9) The solid-state imaging device according to claim 1, wherein the overflow path of the second conductivity type is in physical contact with the charge accumulation region and the intermediate electrode.

[0625] (10) The solid-state imaging device according to claim 1, further comprising:

[0626] A second channel portion of the first conductivity type is located between the semiconductor region of the second conductivity type and the charge accumulation region.

[0627] (11) The solid-state imaging device according to claim 10, wherein a concentration of an impurity of the second conductivity type in the semiconductor region is greater than a concentration of the impurity of the second conductivity type in the charge accumulation region.

[0628] (12) The solid-state imaging device according to claim 1, wherein a concentration of an impurity of the second conductivity type in the intermediate electrode is greater than a concentration of an impurity of the second conductivity type in the charge accumulation region.

[0629] (13) The solid-state imaging device according to claim 12, wherein a concentration of an impurity of the second conductivity type in the charge accumulation region is greater than a concentration of an impurity of the second conductivity type in the overflow path.

[0630] (14) The solid-state imaging device according to claim 1, wherein the first channel portion is in physical contact with the charge accumulation region and the photodiode.

[0631] (15) The solid-state imaging device according to claim 1, wherein the overflow path is in physical contact with the intermediate electrode and the charge accumulation region.

[0632] (16) The solid-state imaging device according to claim 1, wherein the first conductivity type is a P type.

[0633] (17) The solid-state imaging device according to claim 1, wherein the second conductivity type is an N type.

[0634] (18) An electronic device comprising:

[0635] The solid-state imaging device according to claim 1; and

[0636] An optical unit is configured to capture incident light from a subject and form an image of the subject on an image plane of the solid-state imaging device.

[0637] (19) A solid-state imaging device comprising:

[0638] a photoelectric conversion portion configured to generate photoelectric charges, the photoelectric charges accumulable in the photoelectric conversion portion being equal to or less than a saturation charge amount of the photoelectric conversion portion;

[0639] a first transmission gate portion overflow path configured to overflow excess photocharge from within the photoelectric conversion portion, the excess photocharge from within the photoelectric conversion portion being photocharge exceeding the saturation charge amount of the photoelectric conversion portion;

[0640] a first charge accumulation region configured to accumulate the photoelectric charge accumulable in the photoelectric conversion portion and the excess photoelectric charge from within the photoelectric conversion portion, the photoelectric charge accumulable in the first charge accumulation region being equal to or smaller than a saturation charge amount of the first charge accumulation region;

[0641] a semiconductor region overflow path configured to overflow excess photocharges from within the first charge accumulation region, the excess photocharges from within the first charge accumulation region being photocharges exceeding the saturation charge amount of the first charge accumulation region; and

[0642] A semiconductor region is configured to accumulate the excess photocharges from within the first charge accumulation region.

[0643] (20) The solid-state imaging device according to claim 19, wherein the saturation charge amount of the photoelectric conversion portion is a total amount of photocharges that can be held by the photoelectric conversion portion.

[0644] (21) The solid-state imaging device according to claim 19, wherein a saturation charge amount of the first charge accumulation region is a total amount of photocharges that can be held by the first charge accumulation region.

[0645] (22) The solid-state imaging device according to claim 19, wherein the first transfer gate portion overflow path is located between the photoelectric conversion portion and the first charge accumulation region.

[0646] (23) The solid-state imaging device according to claim 19, wherein the first transfer gate portion overflow path is of a first conductivity type.

[0647] (24) The solid-state imaging device according to claim 23, wherein the first conductivity type is a P type.

[0648] (25) The solid-state imaging device according to claim 23, wherein the first charge accumulation region, the semiconductor region, and the semiconductor region overflow path are of the second conductivity type.

[0649] (26) The solid-state imaging device according to claim 25, wherein the second conductivity type is an N type.

[0650] (27) The solid-state imaging device according to claim 25, wherein a concentration of an impurity of the second conductivity type in the semiconductor region is greater than a concentration of the impurity of the second conductivity type in the first charge accumulation region.

[0651] (28) A solid-state imaging device according to claim 27, wherein a concentration of an impurity of the second conductivity type in the first charge accumulation region is greater than a concentration of an impurity of the second conductivity type in an overflow path of the semiconductor region.

[0652] (29) The solid-state imaging device according to claim 19, wherein the semiconductor region overflow path is located between the first charge accumulation region and the semiconductor region.

[0653] (30) The solid-state imaging device according to claim 19, wherein the semiconductor region is an intermediate electrode.

[0654] (31) The solid-state imaging device according to claim 30, wherein the intermediate electrode is an electrode of a capacitor.

[0655] (32) The solid-state imaging device according to claim 30, wherein the intermediate electrode is electrically connected to the charge accumulation portion.

[0656] (33) The solid-state imaging device according to claim 32, wherein the charge accumulation portion is a capacitor.

[0657] (34) A solid-state imaging device according to claim 32, wherein the charge accumulation portion has a higher capacitance value per unit area than the first charge accumulation region.

[0658] (35) An electronic device comprising:

[0659] A solid-state imaging device according to claim 19; and

[0660] An optical unit is configured to capture incident light from a subject and form an image of the subject on an image plane of the solid-state imaging device.

[0661] (36) A method for driving a solid-state imaging device, the method comprising:

[0662] a step of accumulating photocharges in a photoelectric conversion portion that generates an amount of photocharges in accordance with an amount of light received by the photoelectric conversion portion;

[0663] a step of overflowing the photoelectric charges from the photoelectric conversion portion to a first charge accumulation portion when the amount of the photoelectric charges in the photoelectric conversion portion exceeds a saturation charge amount of the photoelectric conversion portion;

[0664] a step of accumulating the photocharges in a first charge accumulation portion which receives the photocharges from the photoelectric conversion portion;

[0665] a step of transferring the photocharge accumulated in the first charge accumulation portion to a floating diffusion portion, the floating diffusion portion converting the photocharge into an electric signal.

[0666] (37) The method according to claim 36, wherein the photoelectric conversion portion saturation charge amount is a total amount of photocharge that can be held by the photoelectric conversion portion.

[0667] (38) A method according to claim 36, wherein the saturation charge amount of the first charge accumulating portion is a total amount of photocharges that can be held by the first charge accumulating portion.

[0668] (39) The method according to claim 36, further comprising:

[0669] A step of overflowing the photocharges from the first charge accumulation portion to the second charge accumulation portion when the amount of the photocharges in the first charge accumulation portion exceeds the saturation charge amount of the first charge accumulation portion.

[0670] (40) A method according to claim 39, wherein a saturation charge amount of the first charge accumulating portion is a total amount of photocharges that can be held by the first charge accumulating portion.

[0671] (41) A method according to claim 39, wherein a total amount of photocharges that can be held by the second charge accumulating portion is larger than a saturation charge amount of the first charge accumulating portion.

[0672] (42) The method according to claim 36, wherein the transferring step includes electrically coupling the photoelectric conversion portion to the floating diffusion portion through the first charge accumulation portion.

[0673] (43) The method according to claim 36, further comprising:

[0674] A step of overflowing the photocharges from the first charge accumulation portion to the floating diffusion portion when the amount of the photocharges in the first charge accumulation portion exceeds a first charge accumulation portion saturation charge amount.

[0675] (44) A method according to claim 43, wherein the saturation charge amount of the first charge accumulating portion is a total amount of photocharges that can be held by the first charge accumulating portion.

[0676] (45) A solid-state imaging device comprising:

[0677] a well layer of a first conductivity type, a surface layer of the first conductivity type on a substrate surface side of the well layer; and

[0678] The second conductivity type impurity diffusion region is located between the second conductivity type buried layer and the second conductivity type buried trench,

[0679] The impurity diffusion region is in physical contact with the buried layer and the buried trench, and the buried trench is in physical contact with the surface layer.

[0680] (46) A solid-state imaging device according to claim 45, wherein a part of the well layer is between the surface layer and the buried trench.

[0681] (47) The solid-state imaging device according to claim 45, wherein a part of the well layer is between the floating diffusion region of the second conductivity type and the buried trench.

[0682] (48) The solid-state imaging device according to claim 45, wherein the buried channel is between the impurity diffusion region and the gate electrode.

[0683] (49) The solid-state imaging device according to claim 45, wherein the buried groove is on the substrate surface side in the well layer.

[0684] (50) The solid-state imaging device according to claim 45, wherein the first conductivity type is a P type.

[0685] (51) The solid-state imaging device according to claim 45, wherein the second conductivity type is an N type.

[0686] (52) An electronic device comprising:

[0687] A solid-state imaging device according to claim 45; and

[0688] An optical unit is configured to capture incident light from a subject and form an image of the subject on an image plane of the solid-state imaging device.

[0689] (53) A method of forming a solid-state imaging device, the method comprising:

[0690] forming a portion of the buried layer by implanting buried ions of the second conductivity type into the well layer of the first conductivity type, the buried ions being implanted through an opening in a buried layer resist mask;

[0691] forming an impurity diffusion region by implanting impurity diffusion region ions of a second conductivity type into the well layer, the impurity diffusion region ions being implanted through openings in an impurity diffusion region resist mask; and

[0692] forming a buried channel by implanting buried channel ions of a second conductivity type into the well layer, the buried channel ions being implanted through openings in a buried channel resist mask,

[0693] The impurity diffusion region is between the buried trench and a portion of the buried layer, and the impurity diffusion region is in physical contact with the buried trench and a portion of the buried layer.

[0694] (54) The method of claim 53, wherein the opening in the impurity diffusion region resist mask is narrower than the opening in the buried trench resist mask, and the opening in the buried trench resist mask is narrower than the opening in the buried layer resist mask.

[0695] (55) The method of claim 53, wherein a portion of the well layer is between a floating diffusion region of the second conductivity type and the buried trench.

[0696] (56) The method according to claim 53, wherein the buried channel is between the impurity diffusion region and the gate electrode.

[0697] (57) The method of claim 53, wherein the first conductivity type is P-type.

[0698] (58) The method of claim 53, wherein the second conductivity type is N-type.

[0699] (59) The method according to claim 53, further comprising:

[0700] Different portions of the buried layer are formed by implanting other buried layer ions of the second conductivity type into the well layer, the different portions of the buried layer extending from a surface of the well layer to a portion of the buried layer.

[0701] (60) The method of claim 59, wherein a surface layer of the first conductivity type extends from a surface of the well layer into a different portion of the buried layer.

[0702] (61) The method according to claim 59, wherein a portion of the well layer is between the surface layer and the buried trench.

[0703] Reference numerals list

[0704] 10, 10A, 10B CMOS image sensors

[0705] 11 pixel array unit

[0706] 12 vertical drive units

[0707] 13 columns of processing units

[0708] 14 horizontal drive units

[0709] 15 System control unit

[0710] 16 pixel drive lines

[0711] 17 vertical signal lines

[0712] 18 signal processing units

[0713] 19 Data storage unit

[0714] 30, 66 first charge accumulation portion

[0715] 40, 67 second charge accumulation portion

[0716] 60A to 60A2, 60B unit pixels

[0717] 61 Photodiode

[0718] 62 First transmission gate part

[0719] 63 Second transmission gate part

[0720] 64 Third transmission gate part

[0721] 65 reset door part

[0722] 68 amplifier transistor

[0723] 69 Select transistor

[0724] 70 Charge leakage gate part

[0725] 71FD part (floating diffusion part)

[0726] 111a, 111b memory

[0727] 112 Addition unit

[0728] 221 Photodiode

[0729] 222 First transmission gate

[0730] 223 memory section

[0731] 224 Second transmission gate

[0732] 225 floating diffusion area (FD part)

[0733] 320 pixels per unit

[0734] 340 intermediate transmission path

[0735] 341, 342 Impurity diffusion region

[0736] 350 Full Transmission Path

[0737] 500 Imaging Equipment

[0738] 502 Imaging Device

Claims

1. A solid-state imaging device include: a well layer of a first conductivity type, a surface layer of the first conductivity type on a substrate surface side of the well layer; a first impurity diffusion region of the second conductivity type, located between an upper surface of the buried layer of the second conductivity type and a lower surface of the buried trench of the second conductivity type; as well as a second impurity diffusion region of the first conductivity type formed in the surface of the substrate between the buried layer and the buried trench, The first impurity diffusion region is in physical contact with the buried layer and the buried trench, and the buried layer is in physical contact with the surface layer.

Images