A power supply protection circuit for a depletion-type negative voltage device

Abstract

The present invention discloses a power supply protection circuit for a depletion-type negative voltage device, used for power-on and power-off protection of negative voltage devices such as GaN HEMTs and GaAs PHEMTs. The protection circuit includes: a negative voltage device gate switch timing circuit, used to control the timing of powering on and off the negative voltage device's gate; a negative voltage device drain switch timing circuit, used to control the timing of powering on and off the negative voltage device's drain; and a negative voltage device gate bias temperature compensation constant current circuit, used to temperature-compensate the negative voltage device's gate bias voltage to maintain a constant gate current at different operating temperatures. The present invention can achieve power supply timing protection for negative voltage devices, preventing device damage caused by power-on and power-off timing issues, and provides a dynamic gate voltage to ensure a constant current state at different operating temperatures, such as high, normal, and low temperatures. The present invention has a simple structure, low cost, and wide applicability, making it suitable for commercialization.

Description

Technical Field

[0001] The present invention relates to the field of solid-state amplifier bias circuits, and in particular to a power supply protection circuit for a depletion-type negative voltage device. Background Art

[0002] Semiconductor technology continues to advance, and end devices are placing increasingly higher demands on semiconductor device performance, efficiency, and miniaturization. GaN HEMTs and GaAs PHEMTs belong to the third generation of semiconductor devices. The advent of 5G is further driving the rapid development of third-generation semiconductor materials, represented by GaN HEMTs. GaN HEMTs are primarily used in power amplifiers (PAs), while GaAs PHEMTs are primarily used in low-noise amplifiers (LNAs).

[0003] Power amplifiers (PAs) and low-noise amplifiers (LNAs) are core components of mobile communication systems. The high-frequency characteristics of 5G place higher demands on materials, processes, and design. As communication frequencies shift toward higher frequencies, base stations and communication equipment will require RF devices that support high-frequency performance. GaN HEMTs and GaAs PHEMTs will clearly demonstrate their advantages. In short, GaN HEMT and GaAs PHEMT technologies have become an emerging force in the RF microwave industry. Their role will further expand as communication frequencies increase.

[0004] GaN HEMT and GaAs pHEMT are depletion-mode negative voltage devices. Their power-on and power-off must meet the following timing requirements:

[0005] Power-on sequence: 1. Set the gate voltage to negative; 2. Connect the drain power supply; 3. Adjust the gate voltage to obtain the appropriate bias current.

[0006] Power-off sequence: 1. Turn off the drain power supply; 2. Turn off the gate voltage.

[0007] Therefore, it is necessary to control the timing of powering on and off the bias circuit of the negative voltage device.

[0008] In addition, due to the process characteristics and temperature characteristics of the negative pressure device itself, temperature compensation needs to be aligned to ensure the stability of the device's operating point. Summary of the Invention

[0009] The purpose of the present invention is to provide a power supply protection circuit for a depletion-type negative voltage device, realize switching timing control of depletion-type negative voltage devices such as GaN HEMT, and keep the device in a constant current state through temperature compensation.

[0010] The technical solution of the present invention is:

[0011] A power supply protection circuit for a depletion-type negative voltage device, characterized by comprising: a gate switch timing circuit; a drain switch timing circuit; a gate bias temperature compensation constant current circuit;

[0012] The gate switch timing circuit is used to control the timing of powering on and off the gate of the negative voltage device; when it is detected that the drain of the negative voltage device is powered, the gate is not allowed to be powered off; when it is detected that the drain of the negative voltage device is not powered, the gate is allowed to be powered on and off;

[0013] The drain switch timing circuit is used to control the timing of powering on and off the drain of the negative voltage device; when a negative voltage is detected on the gate of the negative voltage device, the drain is allowed to be powered on and off; when no negative voltage is detected on the gate of the negative voltage device, the drain is not allowed to be powered on;

[0014] The gate bias temperature compensation constant current circuit is used to perform temperature compensation on the gate bias voltage of the negative voltage device, so that the gate current of the negative voltage device is constant at different operating temperatures.

[0015] Preferably, the gate switch timing circuit includes: a control signal VC, an OR gate G1, a voltage inverter Q1 and a drain sampling module;

[0016] Among them, the drain sampling module is connected to collect the drain voltage of the negative voltage device, the output end of the drain sampling module and the control signal VC are respectively connected to the two input ends of the OR gate G1, and the output end of the OR gate G1 is connected to the power supply end of the gate bias temperature compensation constant current circuit through the voltage inverter Q1.

[0017] Preferably, the drain sampling module includes resistors R4 and R5, one end of the resistor R4 is connected to the drain of the negative voltage device, and the other end is connected to the resistor R5, and the other end of the resistor R5 is grounded; the common node of the resistors R4 and R5 is the output end of the drain sampling module.

[0018] Preferably, the drain switch timing circuit includes: a control signal VC, an AND gate G2, a voltage inverter Q2, a drain switch Q4 and a drain power supply VDD;

[0019] Among them, the input end of the voltage inverter Q2 is connected to the gate of the negative voltage device, the output end of the voltage inverter Q2 and the control signal VC are respectively connected to the two input ends of the AND gate G2, the output end of the AND gate G2 is connected to the control end of the drain switch Q4, and the two ends of the drain switch Q4 are respectively connected to the drain power supply VDD and the drain of the negative voltage device.

[0020] Preferably, the drain switch Q4 is an NMOS tube, the gate of the NMOS tube is connected to the output end of the AND gate G2 through the resistor R3, and the source and drain of the NMOS tube are respectively negative voltage device drain and drain power supply VDD.

[0021] Preferably, the gate bias temperature compensation constant current circuit includes: a bias voltage Vr, an operational amplifier Q3, a resistor R1, a thermistor Rt, a resistor R2, an adjustable resistor Ra, and a resistor Rg;

[0022] The non-inverting input terminal of the operational amplifier Q3 is grounded, the inverting input terminal of Q3 is connected to the bias voltage Vr through the resistor R1, and the output terminal of Q3 is connected to the gate of the negative voltage device through the resistor Rg; the output terminal of Q3 is also connected to the inverting input terminal of Q3 through the adjustable resistor Ra and the resistor R2 connected in series, and the thermistor Rt is connected in parallel with the resistor R2;

[0023] The positive power supply pin of the operational amplifier Q3 is connected to the bias voltage Vr, and the negative power supply pin is connected to the output end of the voltage inverter Q1 in the gate switch timing circuit.

[0024] Preferably, the gate bias temperature compensation constant current circuit selects a gate voltage Vg suitable for the negative voltage device by adjusting Ra; when the operating temperature decreases, the resistance of the thermistor Rt increases, and the output gate voltage Vg of the operational amplifier Q3 increases; when the operating temperature increases, the resistance of the thermistor Rt decreases, and the output gate voltage Vg of the operational amplifier Q3 decreases; the bias current of the depletion-type negative voltage device decreases at low temperatures and increases at high temperatures, and the gate current of the negative voltage device is maintained in a constant state through the temperature compensation circuit.

[0025] The advantages of the present invention are:

[0026] 1. The power supply protection circuit for a depletion-type negative voltage device of the present invention enables Vr, Vc, and VDD to be turned on in any order when the negative voltage device needs to be turned on. The gate switching timing circuit and the drain switching timing circuit ensure that the gate of the negative voltage device is first in a negative voltage state before power is supplied to the drain of the negative voltage device. This effectively prevents damage to the negative voltage device due to incorrect power-on sequencing.

[0027] 2. The power supply protection circuit for a depletion-type negative voltage device of the present invention can shut down Vr, Vc, and VDD in any order when the negative voltage device needs to be shut down. The gate switching timing circuit and the drain switching timing circuit ensure that the negative voltage device first stops the drain power supply and then shuts off the gate power supply, effectively preventing damage to the negative voltage device due to incorrect power-down sequence.

[0028] 3. The gate bias temperature compensation constant current circuit of the depletion-mode negative voltage device power supply protection circuit of the present invention utilizes the characteristics of the thermistor and the depletion-mode negative voltage device under different temperature conditions to maintain the gate current of the negative voltage device at a constant state, thereby ensuring stable operation of the negative voltage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0030] Figure 1 This is a schematic diagram of the power supply protection circuit of the depletion-type negative voltage device of the present invention. DETAILED DESCRIPTION

[0031] like Figure 1 As shown, the power supply protection circuit of the depletion-type negative voltage device of the embodiment of the present invention is used for power-on and power-off protection of negative voltage devices such as GaN HEMT and GaAs PHEMT, and includes three functional modules. Functional module ①: Gate switch timing circuit, used to control the timing of powering on and off of the gate of the negative voltage device; when it is detected that the drain of the negative voltage device is powered, the gate is not allowed to be powered off; when it is detected that the drain of the negative voltage device is not powered, the gate is allowed to be powered on and off. Functional module ②: Drain switch timing circuit, used to control the timing of powering on and off of the drain of the negative voltage device; when it is detected that the gate of the negative voltage device is negative, the drain is allowed to be powered on and off; when it is detected that the gate of the negative voltage device is not negative, the drain is not allowed to be powered on. Functional module ③: Gate bias temperature compensation constant current circuit, used to temperature compensate the gate bias voltage of the negative voltage device so that the gate current of the negative voltage device is constant under different operating temperatures.

[0032] For functional module ①, the gate switch timing circuit includes: a control signal VC, an OR gate G1, a voltage inverter Q1 and a drain sampling module; the drain sampling module includes resistors R4 and R5, one end of the resistor R4 is connected to the drain of the negative voltage device, and the other end is connected to the resistor R5, and the other end of the resistor R5 is grounded; the common node of the resistors R4 and R5 is the output end of the drain sampling module, and the output end of the drain sampling module and the control signal VC are respectively connected to the two input ends of the OR gate G1, and the output end of the OR gate G1 is connected to the power supply end of the gate bias temperature compensation constant current circuit through the voltage inverter Q1.

[0033] The control signal Vc is connected to the input end of the OR gate G1. The other input end of G1 is the voltage VQ that represents the drain power supply state of the negative voltage device. VQ=VDS*R5 / (R4+R5). The drain voltage VDS of the negative voltage device is divided by resistors R4 and R5 to obtain a voltage VQ that represents the drain state of the negative voltage device. When the drain power supply of the negative voltage device is turned on, VQ>0. When the drain power supply of the negative voltage device is turned off, VQ=0.

[0034] The output end of the OR gate G1 is connected to the voltage inverter Q1, and Q1 inverts the output signal of G1 and outputs it.

[0035] Through the operation of OR gate G1, when and only when the control signal Vc and the voltage VQ are both 0, the output of G1 is 0, and the output of Q1 is also 0. That is, only when Vc=0 and the drain power supply of the negative voltage device is turned off, the output of G1 is 0, and the output of Q1 is 0; in other cases, G1 outputs a high level (5V or 3.3V) and Q1 outputs a negative voltage (-5V or -3.3V).

[0036] For functional module ②, the drain switch timing circuit includes: a control signal VC, an AND gate G2, a voltage inverter Q2, a drain switch Q4, and a drain power supply VDD. The drain switch Q4 uses an NMOS transistor. The input end of the voltage inverter Q2 is connected to the gate of the negative voltage device. The output end of the voltage inverter Q2 and the control signal VC are respectively connected to the two input ends of the AND gate G2. The output end of the AND gate G2 is connected to the gate of the NMOS transistor through a resistor R3. The source and drain of the NMOS transistor are respectively connected to the drain of the negative voltage device and the drain power supply VDD.

[0037] The control signal Vc is connected to the input of the AND gate G2, and the other input of G2 is the voltage representing the gate power supply state of the negative voltage device. , =-Vg. The input of voltage inverter Q2 is Vg, and the output is .

[0038] Through the operation of AND gate G2, if and only if the control signal Vc and voltage The output of G2 is high only when both Vc and the gate power supply of the negative voltage device are high. That is, only when Vc is high and the gate power supply of the negative voltage device is negative, the output of the voltage inverter Q2 is high, and the output of G2 is also high. In other cases, the output of G2 is low.

[0039] The output of AND gate G2 is connected to resistor R3, the other end of which is connected to the gate of NMOS Q4. When the output of G2 is high, the NMOS channel opens, and VDD passes through the NMOS and enters the drain of the negative voltage device. When the output of G2 is low, the NMOS channel is pinched off, and the drain voltage of the negative voltage device, VDS, is 0.

[0040] For functional module ③, the gate bias temperature compensation constant current circuit includes: bias voltage Vr, operational amplifier Q3, resistor R1, thermistor Rt, resistor R2, adjustable resistor Ra, and resistor Rg; the non-inverting input terminal of the operational amplifier Q3 is grounded, the inverting input terminal of Q3 is connected to the bias voltage Vr through resistor R1, and the output terminal of Q3 is connected to the gate of the negative voltage device through resistor Rg; the output terminal of Q3 is also connected to the inverting input terminal of Q3 through the adjustable resistor Ra and resistor R2 connected in series, and the thermistor Rt is connected in parallel with resistor R2; the positive power supply pin of the operational amplifier Q3 is connected to the bias voltage Vr, and the negative power supply pin is connected to the output terminal of the voltage inverter Q1 in the gate switch timing circuit.

[0041] Here, Vg = -(Rt / / R2+Ra)*Vr / R1. By adjusting the value of Ra, the appropriate gate voltage for the negative voltage device is selected. Furthermore, as the temperature rises, the resistance of thermistor Rt decreases, and Vg decreases; as the temperature drops, the resistance of thermistor Rt increases, and Vg increases. When the temperature of the negative voltage device rises, the threshold voltage Vth decreases, and the bias current increases; when the temperature drops, the threshold voltage Vth increases, and the bias current decreases. By adjusting the values ​​of Rt, R1, and R2 to compensate for changes in the bias current of the negative voltage device, the negative voltage device maintains a constant bias current at high and low temperatures, maintaining stable performance.

[0042] Specifically, when the negative voltage device needs to be turned on, Vr, Vc and VDD can be turned on in any order. The gate switch timing circuit and the drain switch timing circuit will ensure that the gate of the negative voltage device is first in a negative voltage state, and then the NMOS channel is turned on. VDD supplies power to the drain of the negative voltage device, which can effectively prevent the negative voltage device from being damaged due to incorrect power-on sequence.

[0043] Specifically, when the negative voltage device needs to be turned off, Vr, Vc and VDD can be turned off in any order. The gate switch timing circuit and the drain switch timing circuit will ensure that the negative voltage device first turns off the NMOS channel, stops the drain power supply, and then turns off the gate power supply, which can effectively prevent the negative voltage device from being damaged due to incorrect power-off sequence.

[0044] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any modifications made based on the spirit of the main technical solution of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A power supply protection circuit for a depletion-type negative voltage device, characterized in that: include: Gate switch timing circuit; Drain switch timing circuit; Gate bias temperature compensation constant current circuit; The gate switch timing circuit is used to control the timing of powering on and off the gate of the negative voltage device; when it is detected that the drain of the negative voltage device is powered, the gate is not allowed to be powered off; when it is detected that the drain of the negative voltage device is not powered, the gate is allowed to be powered on and off; The drain switch timing circuit is used to control the timing of powering on and off the drain of the negative voltage device; when a negative voltage is detected on the gate of the negative voltage device, the drain is allowed to be powered on and off; when no negative voltage is detected on the gate of the negative voltage device, the drain is not allowed to be powered on; The gate bias temperature compensation constant current circuit is used to perform temperature compensation on the gate bias voltage of the negative voltage device so that the gate current of the negative voltage device is constant at different operating temperatures; The gate bias temperature compensation constant current circuit includes: a bias voltage Vr, an operational amplifier Q3, a resistor R1, a thermistor Rt, a resistor R2, an adjustable resistor Ra, and a resistor Rg; wherein the non-inverting input terminal of the operational amplifier Q3 is grounded, the inverting input terminal of Q3 is connected to the bias voltage Vr through the resistor R1, and the output terminal of Q3 is connected to the gate of the negative voltage device through the resistor Rg; the output terminal of Q3 is also connected to the inverting input terminal of Q3 through the adjustable resistor Ra and the resistor R2 connected in series, and the thermistor Rt is connected in parallel with the resistor R2; the positive power supply pin of the operational amplifier Q3 is connected to the bias voltage Vr, and the negative power supply pin is connected to the output terminal of the voltage inverter Q1 in the gate switch timing circuit; The gate bias temperature compensation constant current circuit selects a gate voltage Vg suitable for the negative voltage device by adjusting Ra; when the operating temperature decreases, the resistance of the thermistor Rt increases, and the output gate voltage Vg of the operational amplifier Q3 increases; when the operating temperature increases, the resistance of the thermistor Rt decreases, and the output gate voltage Vg of the operational amplifier Q3 decreases; the bias current of the depletion-type negative voltage device decreases at low temperatures and increases at high temperatures. The gate current of the negative voltage device is maintained at a constant state through the temperature compensation circuit.

2. The power supply protection circuit of the depletion-type negative voltage device according to claim 1, characterized in that: The gate switch timing circuit includes: a control signal VC, an OR gate G1, a voltage inverter Q1 and a drain sampling module; Among them, the drain sampling module is connected to collect the drain voltage of the negative voltage device, the output end of the drain sampling module and the control signal VC are respectively connected to the two input ends of the OR gate G1, and the output end of the OR gate G1 is connected to the power supply end of the gate bias temperature compensation constant current circuit through the voltage inverter Q1.

3. The power supply protection circuit of the depletion-type negative voltage device according to claim 2, characterized in that: The drain sampling module includes resistors R4 and R5. One end of the resistor R4 is connected to the drain of the negative voltage device, and the other end is connected to the resistor R5. The other end of the resistor R5 is grounded. The common node of the resistors R4 and R5 is the output end of the drain sampling module.

4. The power supply protection circuit of the depletion-type negative voltage device according to claim 2, characterized in that: The drain switch timing circuit includes: a control signal VC, an AND gate G2, a voltage inverter Q2, a drain switch Q4 and a drain power supply VDD; Among them, the input end of the voltage inverter Q2 is connected to the gate of the negative voltage device, the output end of the voltage inverter Q2 and the control signal VC are respectively connected to the two input ends of the AND gate G2, the output end of the AND gate G2 is connected to the control end of the drain switch Q4, and the two ends of the drain switch Q4 are respectively connected to the drain power supply VDD and the drain of the negative voltage device.

5. The power supply protection circuit of the depletion-type negative voltage device according to claim 4, characterized in that: The drain switch Q4 is an NMOS tube, the gate of the NMOS tube is connected to the output end of the AND gate G2 through the resistor R3, and the source and drain of the NMOS tube are respectively connected to the drain of the negative voltage device and the drain power supply VDD.

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