Interrupt controller and inter-core communication system

Abstract

The invention discloses an interrupt controller and an inter-core communication system. The interrupt controller comprises a counting unit and an interrupt signal generating unit connected to the counting unit; the counting unit is used to count when the interrupt controller receives an interrupt request signal; the interrupt signal generating unit is used to obtain the calculation of the counting unit and generate an interrupt signal when the count value of the counting unit changes from 0 to 1. The counting unit counts the number of interrupt request signals, and the interrupt signal generating unit generates an interrupt signal when the count value of the counting unit changes from 0 to 1, so that the interrupt signal generating unit only generates an interrupt signal once when the counting unit receives multiple interrupt request signals, thereby reducing the number and frequency of interrupt signal generation, thereby reducing the waiting of multiple interrupt request signals at the sending end, and at the same time reducing the number and frequency of interrupt signals interrupting the receiving end, thereby increasing the throughput of the receiving end in processing the interrupt request signal, and improving the efficiency of the receiving end in processing the interrupt request signal.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communication technology, and in particular to an interrupt controller and an inter-core communication system. Background Art

[0002] Inter-core interrupt requests generally include two main steps: data transmission and message notification. Figure 1 A schematic diagram of the structure of inter-core communication of a communication system provided by the prior art. Figure 1 As shown in FIG. 1 , when kernel A sends an interrupt request to kernel B, during the data transmission process, kernel A sending data can store the data to be sent in shared memory (SM). When the data is completed, kernel A sending data sends an inter-processor interrupt (IPI) request to kernel B receiving data, notifying kernel B receiving data to receive the data. Kernel B receiving data saves interrupt related information, obtains data from shared memory SM, and notifies the post-processing module of kernel B to process the data. Generally, there are relatively few interrupt resources in the communication system, especially inter-core interrupt resources, and usually only one set of interrupts is reserved for inter-core communication. When kernel A includes multiple users and multiple users need to make communication requests in parallel, when a large number of communication requests are sent, different users have to wait for each other and occupy limited resources, which leads to certain delays and communication system overhead when sending communication requests. Moreover, a large number of communication requests will cause kernel B receiving data to generate a large number of interrupts, which will interrupt the normal operation of kernel B, resulting in low efficiency of data processing by kernel B. Exemplarily, when the communication system can support a maximum of 16 video streams for parallel processing, and a single video stream is 30fps, that is, a single channel has a demand for sending an interrupt request every 33ms, then the 16-channel video data transmission has 480 interrupt requests per second. According to the design requirements of the Software Development Kit (SDK), each video stream has three additional parallel channels for transmitting control commands, neural network data, system information query and other tasks, that is, there are 48 channels, and the communication system may have 64 interrupt requests at the same time. In the prior art, multiple frames of data can be combined into a large data for transmission, thereby reducing the number of data transmissions, that is, reducing the number of interrupt requests of kernel A. For example, when there are 480 interrupt requests per second for 16-channel video data transmission, by combining two frames of data and sending them at one time, the interrupt request can be halved to 240 times. When multiple frames of data are combined into a large data for transmission, the data processing delay will increase, and the complexity of data processing will increase, which will cause the performance of kernel B to decrease during data processing. Summary of the invention

[0003] The present invention provides an interrupt controller and an inter-core communication system to reduce the number and frequency of interrupt signals and improve the data processing efficiency of an interrupt signal receiving end.

[0004] In a first aspect, an embodiment of the present invention provides an interrupt controller, comprising a counting unit and an interrupt signal generating unit connected to the counting unit;

[0005] The counting unit is used for counting when the interrupt controller receives an interrupt request signal; the interrupt signal generating unit is used for obtaining the count of the counting unit and generating an interrupt signal when the count value of the counting unit changes from 0 to 1.

[0006] Optionally, the interrupt signal generating unit includes a status register and an interrupt signal generator;

[0007] The status register is connected to the counting unit, and the interrupt signal generator is connected to the status register. The status register includes an enabled state and a disabled state. When the status register is in the enabled state, the status register generates a first trigger signal to trigger the interrupt signal generator when the counting unit is increased by 1, and automatically sets the status register to the disabled state. When the status register is in the disabled state, the status register does not act when the counting unit is increased by 1; the interrupt signal generator is used to generate an interrupt signal when receiving the first trigger signal.

[0008] Optionally, the interrupt controller further comprises a write register;

[0009] The write register is used to receive the interrupt request signal and form a second trigger signal according to the interrupt request signal; the counting unit is connected to the write register and is used to count by adding 1 according to the second trigger signal.

[0010] Optionally, the interrupt controller further comprises a read register;

[0011] The read register is connected to the counting unit, and the read register is used for the interrupt signal receiving end to read the current value of the counting unit after receiving the interrupt signal, and return the current value to the counting unit; the counting unit is also used to determine whether the current value is greater than 0 when receiving the returned current value, and if the current value is greater than 0, the count is reduced by 1.

[0012] Optionally, when the interrupt signal generating unit includes a status register and an interrupt signal generator, the status register is further used to set the counting unit to an enabled state when the current value of the counting unit is reduced to 0.

[0013] Optionally, the interrupt controller further includes a first timer;

[0014] The first timer is connected to the read register, and the first timer is used to start timing to a first preset time when the current value of the counting unit read by the read register changes from 1 to 0;

[0015] During the first preset time, the interrupt signal receiving end is further used to continuously receive the interrupt signal, the write register is further used to continuously receive the interrupt request signal, and the counting unit is used to continuously count the interrupt request signal;

[0016] When the interrupt signal generating unit includes a status register and an interrupt signal generator, when the timing reaches the first preset time, the read register is also used to read the current value of the counting unit again. If the current value of the counting unit is 0, the status register is set to the enabled state.

[0017] Optionally, the first timer is further configured to restart timing when the write register receives the interrupt request signal within the first preset time.

[0018] Optionally, the interrupt controller further includes a second timer;

[0019] The second timer is connected to the interrupt signal generating unit, and the second timer is used to start timing to a second preset time when the interrupt signal generating unit generates an interrupt signal. The read register is connected to the second timer, and the read register is also used to read the current value of the counting unit after the second preset time.

[0020] Optionally, the counting unit communicates with the write register, and the counting unit communicates with the read register in parallel.

[0021] Optionally, the interrupt controller further includes a storage unit; the storage unit is used to store the to-be-processed interrupt request information corresponding to the current value of the counting unit.

[0022] Optionally, the storage unit stores data in a first-in-first-out queue.

[0023] In a second aspect, an embodiment of the present invention further provides an inter-core communication system, including a first core, a second core, and an interrupt controller provided by any embodiment of the present invention;

[0024] The first core is connected to the interrupt controller and is used to provide an interrupt request signal to the interrupt controller; the interrupt controller is used to count according to the interrupt request signal and generate an interrupt signal when the count value changes from 0 to 1; the second core is connected to the interrupt controller and is used to process the interrupt request signal according to the interrupt signal.

[0025] Optionally, the inter-core communication system further includes a storage module;

[0026] The storage module is connected to the first core and is used to store data corresponding to the interrupt request signal. The second core is also connected to the storage module and is used to read the data corresponding to the interrupt request signal according to the interrupt signal.

[0027] Optionally, the interrupt controller includes a storage unit, which is used to store the to-be-processed interrupt request information corresponding to the current value of the counting unit; and the storage unit is integrated in the storage module.

[0028] Optionally, the interrupt controller also includes a read register; the read register is connected to the counting unit, the read register is used to read the current value of the counting unit and return the current value to the counting unit, and the counting unit subtracts 1 when the current value is greater than 0; the second core is also used to call the data corresponding to the interrupt request signal according to the interrupt signal and the current value of the counting unit.

[0029] The technical solution of the embodiment of the present invention is to set an interrupt controller including a counting unit and an interrupt signal generating unit. The counting unit counts the number of interrupt request signals, and the interrupt signal generating unit generates an interrupt signal when the count value of the counting unit changes from 0 to 1, so that the interrupt signal generating unit only generates an interrupt signal once when the counting unit receives multiple interrupt request signals, thereby reducing the number and frequency of interrupt signal generation, thereby reducing the waiting time of multiple interrupt request signals at the sending end that sends the interrupt request signal, and at the same time reducing the number and frequency of interrupt signals interrupting the receiving end that receives the interrupt signal, thereby increasing the throughput of the receiving end in processing the interrupt request signal, and improving the efficiency of the receiving end in processing the interrupt request signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the structure of inter-core communication of a communication system provided by the prior art;

[0031] Figure 2 A schematic diagram of the structure of an interrupt controller provided by an embodiment of the present invention;

[0032] Figure 3 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention;

[0033] Figure 4 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention;

[0035] Figure 6 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention;

[0036] Figure 7 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention;

[0037] Figure 8 It is a flowchart of interrupt process processing when the status register is in manual mode;

[0038] Fig. 9 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention;

[0039] Fig.10 A schematic diagram of the structure of an inter-core communication system provided by an embodiment of the present invention;

[0040] Fig.11 A schematic diagram of the structure of another inter-core communication system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0042] Figure 2 A schematic diagram of the structure of an interrupt controller provided by an embodiment of the present invention. Figure 2 As shown, the interrupt controller includes a counting unit 110 and an interrupt signal generating unit 120 connected to the counting unit 110; the counting unit 110 is used to count when the interrupt controller receives an interrupt request signal, and the interrupt signal generating unit 120 is used to obtain the count of the counting unit 110 and generate an interrupt signal when the count value of the counting unit 110 changes from 0 to 1.

[0043] Specifically, the interrupt controller can be used for inter-core communication of the communication system to control inter-core interrupts. In inter-core communication, the communication system may include an interrupt signal sending end and an interrupt signal receiving end, and the interrupt controller is connected between the interrupt signal sending end and the interrupt signal receiving end. When the interrupt signal sending end and the interrupt signal receiving end communicate, the interrupt signal sending end sends an interrupt request signal, the counting unit 110 in the interrupt controller receives the interrupt request signal, and counts the number of interrupt request signals from 0, and the interrupt signal generating unit 120 generates an interrupt signal when the value of the counting unit 110 changes from 0 to 1, and the interrupt signal receiving end processes the interrupt request signal according to the interrupt signal, executes the corresponding interrupt program, and realizes the communication between the interrupt signal sending end and the interrupt signal receiving end. When the interrupt signal sending end sends multiple interrupt request signals, the value of the counting unit 110 is equal to the number of interrupt request signals. The interrupt signal generating unit 120 generates an interrupt signal only when the value of the counting unit 110 changes from 0 to 1. The interrupt signal receiving end processes all pending interrupt request signals at one time according to the value of the counting unit 110, thereby reducing the waiting time for multiple interrupt request signals at the interrupt signal sending end, reducing the number and frequency of interrupt signals generated, avoiding multiple interruptions of the execution program of the interrupt signal receiving end by the interrupt signal, and improving the efficiency of the interrupt signal receiving end in processing interrupt request signals.

[0044] It should be noted that the interrupt signal sending end and the interrupt signal receiving end may be a core. The interrupt signal sending end may include multiple users. When multiple users need to make parallel communication requests, the interrupt signal sending end may generate multiple interrupt request signals. When the interrupt signal sending end and the interrupt signal receiving end are located on the same chip, the interrupt signal sending end and the interrupt signal receiving end may be isomorphic processors. When the interrupt signal sending end and the interrupt signal receiving end are located in different chips, the interrupt signal sending end and the interrupt signal receiving end may be heterogeneous processors.

[0045] Exemplarily, the counting unit 110 includes a counter 111 ; the counter 111 is used for counting according to the number of interrupt request signals.

[0046] Specifically, the counter 111 can realize counting. Before the counter 111 receives the interrupt request signal, the counter 111 is initialized to 0. When the counter 111 receives the interrupt request signal, the counter 111 starts counting from 0, and each time the counter 111 receives an interrupt request signal, the counter 111 adds 1, thereby realizing that the counter 111 counts the number of interrupt request signals. Moreover, when the value of the counter 111 changes from 0 to 1, the interrupt signal generating unit 120 generates an interrupt signal, and the interrupt signal receiving end starts to process the interrupt request signal according to the interrupt signal, and processes all the interrupt request signals counted by the counter 111 at one time, thereby reducing the waiting of multiple interrupt request signals at the interrupt signal sending end, reducing the number and frequency of interrupt signals generated, avoiding the interrupt signal from interrupting the execution program of the interrupt signal receiving end multiple times, and improving the efficiency of the interrupt signal receiving end in processing the interrupt request signal.

[0047] Figure 3 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention. Figure 3 As shown, the interrupt signal generating unit 120 includes a status register 121 and an interrupt signal generator 122; the status register 121 is connected to the counting unit 110, and the interrupt signal generator 122 is connected to the status register 121. The status register 121 includes an enabled state and a disabled state. When the status register 121 is in the enabled state, the status register 121 generates a first trigger signal to trigger the interrupt signal generator 122 when the counting unit 110 is increased by 1, and automatically sets the status register 121 to a disabled state; when the status register 121 is in the disabled state, the status register 121 does not act when the counting unit 110 is increased by 1; the interrupt signal generator 122 is used to generate an interrupt signal when receiving the first trigger signal.

[0048] Specifically, the status register 121 has an enabled state and a disabled state. When the status register 121 is in the enabled state and the counting unit 110 adds 1, the status register 121 generates a first trigger signal according to the adding action of the counting unit 110, and the first trigger signal triggers the interrupt signal generator 122 to generate an interrupt signal, and the interrupt signal receiving end starts to process the interrupt request signal to be processed according to the interrupt signal. After the status register 121 generates the first trigger signal, it is automatically set to the disabled state. In the failure state, when the counting unit 110 continues to count and add 1 according to the interrupt request signal, the status register 121 will not generate a first trigger signal for triggering the interrupt signal generator 122 to generate an interrupt signal, so that the interrupt signal generator 122 only generates an interrupt signal when the value of the counting unit 110 changes from 0 to 1. When the counting unit 110 counts multiple interrupt request signals, it can avoid the interrupt signal generator 122 generating interrupt signals multiple times according to the adding 1 action of the counting unit 110, thereby reducing the number of interrupt signals, thereby reducing the waiting of multiple interrupt request signals at the interrupt signal sending end, reducing the number and frequency of interrupt signals generated, avoiding interrupt signals interrupting the execution program of the interrupt signal receiving end multiple times, and improving the efficiency of the interrupt signal receiving end in processing interrupt request signals.

[0049] It should be noted that the above process may be a working process when the state register 121 is in the automatic control mode. During initialization, the state register 121 is in the automatic control mode and is in the enabled state. When the counting unit 110 starts counting, the state register 121 may generate a first trigger signal only when the count value of the counting unit 110 changes from 0 to 1, triggering the interrupt signal generator 122 to generate an interrupt signal. The state register 121 may also be in the manual control mode.

[0050] Figure 4 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention. Figure 4 As shown, the interrupt controller also includes a write register 130; the write register 130 is used to receive an interrupt request signal and form a second trigger signal according to the interrupt request signal; the counting unit 110 is connected to the write register 130 and is used to count by adding 1 according to the second trigger signal.

[0051] Specifically, the write register 130 can be connected to the interrupt signal sending end, and is used to receive the interrupt request signal of the interrupt signal sending end. When the write register 130 receives the interrupt request signal, the write register 130 will form a second trigger signal, and the second trigger signal is output to the counting unit 110, and the counting unit 110 counts according to the second trigger signal plus 1. The write register 130 has an automatic clearing function. When the write register 130 writes the interrupt request signal to form the second trigger signal, the write register 130 automatically clears. Therefore, each time the write register 130 receives the interrupt request signal, the write register 130 will form a second trigger signal and output it to the counting unit 110. The counting unit 110 counts according to the second trigger signal plus 1, thereby realizing the counting of the interrupt request signal.

[0052] Figure 5 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention. Figure 5 As shown, the interrupt controller also includes a read register 140; the read register 140 is connected to the counting unit 110, and the read register 140 is used to read the current value of the counting unit 110 after the interrupt signal receiving end receives the interrupt signal, and return the current value to the counting unit 110. The counting unit 110 is also used to determine whether the current value is greater than 0 when receiving the returned current value. If the current value is greater than 0, the count is reduced by 1.

[0053] Specifically, the read register 140 is connected to the counting unit 110, and the read register 140 is also connected to the interrupt signal receiving end. When the interrupt signal generating unit 120 generates an interrupt signal, the interrupt signal receiving end receives and processes the interrupt request signal according to the interrupt signal. At this time, the read register 140 can read the count value in the counting unit 110 after the interrupt signal receiving end receives the interrupt signal. In addition, the current value of the counting unit 110 read by the read register 140 will be returned to the counting unit 110. When the counting unit 110 receives the returned current value, it determines whether the current value is greater than 0. When the current value is greater than 0, the number of unprocessed interrupt request signals can be determined according to the current value, and the interrupt signal receiving end continues to process the unprocessed interrupt request signals. Each time the read register 140 reads the count value of the counting unit 110 and returns it to the counting unit 110, the counting unit 110 determines whether the current value is greater than 0, and the interrupt signal receiving end processes the unprocessed interrupt request signal when the count value is greater than 0. Each time the read register 140 reads the count value in the counting unit 110, it sends a read signal to the counting unit 110. And after reading the count value of the counting unit 110, the count value is returned. When the current value of the counting unit 110 is greater than 0, the counting unit 110 subtracts 1 from the current count value, thereby realizing that each time the reading register 140 reads the count value of the counting unit 110, the interrupt signal receiving end processes an interrupt request signal when the count value is greater than 0, and at the same time, the count value of the counting unit 110 subtracts 1 from the current count value until the count value of the counting unit 110 is 0, and the interrupt signal receiving end processes all interrupt request signals. And the counting unit 110 can count when the interrupt signal sending end sends an interrupt request signal next time.

[0054] It should be noted that the counting unit 110 may include a counter, and the counter may be a bidirectional counter that can implement both plus-1 counting and minus-1 counting.

[0055] Continue to refer Figure 5 When the interrupt signal generating unit 120 includes a status register 121 and an interrupt signal generator 122, the status register 121 is further used to set the status to an enabled state when the current value of the counting unit 110 is reduced to 0.

[0056] Specifically, when the current value of the counting unit 110 is 0, the interrupt signal receiving end processes all interrupt request signals. The interrupt signal receiving end exits the interrupt, and the status register 121 is automatically set to the enabled state so that the interrupt controller prepares for the next interrupt, thus realizing the automatic control mode of the interrupt controller.

[0057] Figure 6 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention. Figure 6As shown, the interrupt controller further includes a first timer 150; the first timer 150 is connected to the read register 140, and the first timer 150 is used to start timing to a first preset time when the current value of the counting unit 110 read by the read register 140 changes from 1 to 0;

[0058] During the first preset time, the interrupt signal receiving end is further used to continuously receive the interrupt signal, the write register 130 is further used to continuously receive the interrupt request signal, and the counting unit 110 is used to continuously count the interrupt request signal;

[0059] When the interrupt signal generating unit 120 includes a status register and an interrupt signal generator, when the timing reaches the first preset time, the reading register 140 is also used to read the current value of the counting unit 110 again. If the current value of the counting unit 110 is 0, the status register is set to an enabled state.

[0060] Specifically, the first timer 150 is used for timing. The read register 140 reads the current value of the counting unit 110 after the interrupt signal generating unit 120 generates an interrupt signal. When the current value of the counting unit 110 read by the read register 140 changes from 1 to 0, the interrupt request signals sent by the interrupt signal sending end are all processed, and the first timer 150 starts timing at this time. When the first timer 150 counts within the first preset time, the interrupt signal receiving end continues to receive the interrupt signal, that is, it is in the state of processing the interrupt request. The write register 130 continues to receive the interrupt request signal. If the write register 130 does not receive a new interrupt request signal within the first preset time, and the current value of the interrupt request signal counted by the counting unit 110 is still 0, the read register 140 reads the current value of the counting unit 110 again as 0, that is, there is no interrupt request signal to be processed. The interrupt signal receiving end can exit the state of processing the interrupt request. If the write register 130 receives a new interrupt request signal within the first preset time, and the current value of the interrupt request signal counted by the counting unit 110 is greater than 0, the read register 140 reads the current value of the counting unit 110 again and is greater than 0, and the interrupt signal receiving end can continue to process the new interrupt request signal, so that when the interrupt signal sending end intensively sends interrupt request signals at a certain moment, the interrupt signal generating unit 120 only generates an interrupt signal once, further reducing the number of interrupt signals generated by the interrupt signal generating unit 120, thereby further reducing the waiting of multiple interrupt request signals at the interrupt signal sending end, reducing the number and frequency of interrupt signals generated, avoiding interrupt signals interrupting the execution program of the interrupt signal receiving end multiple times, and improving the efficiency of the interrupt signal receiving end in processing interrupt request signals.

[0061] On the basis of the above technical solution, the first timer 150 is further configured to restart timing when the write register 130 receives an interrupt request signal within the first preset time.

[0062] Specifically, if the write register 130 receives a new interrupt request signal within the first preset time, and the current value of the interrupt request signal counted by the counting unit 110 is greater than 0, the read register 140 reads the current value of the counting unit 110 again and is greater than 0, and the interrupt signal receiving end can continue to process the new interrupt request signal. At this time, the first timer 150 restarts the timing, and repeats the above process within the first preset time, and further reduces the number of interrupt signals generated by the interrupt signal generating unit 120 when the interrupt signal sending end sends interrupt request signals intensively at a certain moment.

[0063] Figure 7 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention. Figure 7 As shown, the interrupt controller also includes a second timer 160; the second timer 160 is connected to the interrupt signal generating unit 120, and the second timer 160 is used to start timing to a second preset time when the interrupt signal generating unit 120 generates an interrupt signal, and the reading register 140 is connected to the second timer 160, and the reading register 140 is also used to read the current value of the counting unit 110 after the second preset time.

[0064] Specifically, the second timer 160 is used for timing. When the interrupt signal generating unit 120 generates an interrupt signal, the second timer 160 starts timing. When the second timer 160 times to the second preset time, the read register 140 starts to read the current value of the counting unit 110, and the interrupt signal receiving end processes the unprocessed interrupt request signal according to the signal output by the read register 140. When the interrupt request signal received by the interrupt controller is not dense, the second timer 160 can be used to delay the second preset time, and the read register 140 can start to read the current value of the counting unit 110, and the interrupt signal receiving end processes the unprocessed interrupt request signal at the same time, which can extend the time for the counting unit 110 to receive the interrupt request signal after the interrupt signal generating unit 120 generates the interrupt signal, extend the period of the interrupt signal receiving end polling and processing the interrupt request signal, and reduce the number of interrupt signals generated by the interrupt signal generating unit 120 as a whole, thereby further reducing the waiting of multiple interrupt request signals at the interrupt signal sending end, reducing the number and frequency of interrupt signal generation, avoiding the interrupt signal from interrupting the execution program of the interrupt signal receiving end multiple times, and improving the efficiency of the interrupt signal receiving end in processing the interrupt request signal.

[0065] In other embodiments, when the interrupt signal generating unit includes a status register and an interrupt signal generator, the specific connection relationship is as follows: Figure 3 The status register can also work in manual mode. Figure 8 The following is a flowchart of interrupt processing when the status register is in manual mode. Figure 8 As shown, after the interrupt signal generator generates an interrupt signal, when the status register is in manual control mode, the second timer is first used to count to the second preset time, and then the register is read to read the current value of the counting unit. When the current value of the counting unit is greater than 0, the interrupt signal receiving end processes an interrupt request signal, that is, processes a pending data. When the current value of the counting unit is equal to 0, the first timer is started to count to the first preset time. Within the first preset time, if the reading register reads the current value of the counting unit again and is greater than 0, the interrupt controller receives a new interrupt request signal, and the interrupt signal receiving end continues to process the new interrupt request signal, thereby reducing the number of interrupt signals generated by the interrupt signal generating unit. If the reading register 140 reads the current value of the counting unit again and is equal to 0, the interrupt controller does not receive a new interrupt request signal, the interrupt signal receiving end exits the interrupt, and sets the status register to the automatic control mode and enables it, so that the status register is prepared for the next interrupt program, and the interrupt signal receiving end exits the interrupt.

[0066] Optionally, the counting unit 110 and the write register 130 , and the counting unit 110 and the read register 140 communicate in parallel.

[0067] Specifically, the counting unit 110 may have a hardware lock function. When the counting unit 110 performs write communication with the write register 130 and the counting unit 110 performs read communication with the read register 140, the counting unit 110 may first execute a step and latch another step to implement hardware waiting. When the counting unit 110 completes one step, it executes another step. For example, when the counting unit 110 performs write communication with the write register 130 and the counting unit 110 performs read communication with the read register 140, the counting unit 110 may first perform write communication with the write register 130 and latch the read function between the counting unit 110 and the read register 140. When the counting unit 110 completes the write communication and the count value of the counting unit 110 is increased by 1, the counting unit 110 performs read communication with the read register 140 again, and after the read communication is completed, the count value of the counting unit 110 is reduced by 1 when it is greater than 0.

[0068] Fig. 9 A schematic diagram of the structure of another interrupt controller provided by an embodiment of the present invention. Fig. 9 As shown, the interrupt controller further includes a storage unit 170 ; the storage unit 170 is used to store the pending interrupt request information corresponding to the current value of the counting unit 110 .

[0069] Specifically, the storage unit 170 is connected to the interrupt signal sending end. When the interrupt signal sending end outputs an interrupt request signal, the storage unit 170 can record the interrupt request information corresponding to the interrupt request signal to be processed. For example, the interrupt request information can include the hardware driver information of the interrupt signal receiving end corresponding to the interrupt request signal. The hardware driver of the interrupt signal receiving end can be a subroutine in the interrupt signal receiving end. The storage unit 170 is also connected to the interrupt signal receiving end. When the interrupt signal receiving end processes the interrupt request signal in sequence, the interrupt signal receiving end sequentially obtains the interrupt request information corresponding to the interrupt request signal from the storage unit 170, so that the hardware driver corresponding to the interrupt signal receiving end processes the corresponding interrupt request signal.

[0070] Optionally, the storage unit 170 stores data in a first-in-first-out queue.

[0071] Specifically, the First Input First Output (FIFO) queue is a traditional sequential execution method. The FIFO queue can realize that the first instruction to enter is completed and retired first, and then the second instruction is executed. When the storage unit 170 stores the interrupt request information, the storage unit 170 stores the corresponding interrupt request information in sequence according to the sequence of the interrupt request signals. When the interrupt signal receiving end processes the interrupt request signal in sequence, the interrupt signal receiving end can sequentially obtain the interrupt request information corresponding to the interrupt request signal to be processed according to the first-in-first-out queue storage method of the storage unit 170, so that the interrupt signal receiving end can process the interrupt request signal according to the interrupt request information corresponding to the interrupt request signal to be processed.

[0072] An embodiment of the present invention also provides an inter-core communication system. Fig.10 A schematic diagram of the structure of an inter-core communication system provided by an embodiment of the present invention. Fig.10 As shown, the inter-core communication system includes a first core 200, a second core 300 and an interrupt controller 100 provided by any embodiment of the present invention; the first core 200 is connected to the interrupt controller 100, and is used to provide an interrupt request signal to the interrupt controller 100; the interrupt controller 100 is used to count according to the interrupt request signal, and generate an interrupt signal when the count value changes from 0 to 1; the second core 300 is connected to the interrupt controller 100, and is used to process the interrupt request signal according to the interrupt signal.

[0073] Specifically, the first core 200 may be an interrupt signal sending end, used to send an interrupt request signal. The second core 300 may be an interrupt signal receiving end, used to receive an interrupt signal generated by the interrupt controller 100, and process the interrupt request signal according to the interrupt signal. The interrupt controller 100 includes a counting unit 110 and an interrupt signal generating unit 120. When the first core 200 outputs an interrupt request signal, the counting unit 110 counts according to the interrupt request signal to determine the number of interrupt request signals. When the value of the counting unit 110 changes from 0 to 1, the interrupt signal generating unit 120 generates an interrupt signal, and the second core 300 processes the interrupt request signal output by the first core 200 according to the interrupt signal, thereby realizing interrupt communication between the first core 200 and the second core 300. When the first core 200 sends multiple interrupt request signals, the value of the counting unit 110 is equal to the number of interrupt request signals. When the value of the counting unit 110 changes from 0 to 1, after the interrupt signal generating unit 120 generates an interrupt signal, the second core 300 processes all pending interrupt request signals at one time according to the value of the counting unit 110, thereby reducing the waiting time of multiple interrupt request signals of the first core 200, reducing the number and frequency of interrupt signals generated, avoiding interrupt signals from interrupting the execution program of the second core 300 multiple times, and improving the efficiency of the second core 300 in processing interrupt request signals.

[0074] In addition, continue to refer to Fig.10 The interrupt signal output by the interrupt signal generating unit 120 can be output to the control unit 400, and the control unit 400 controls the second core 300 to process the interrupt request signal according to the interrupt signal output control signal. Exemplarily, the control unit 400 can be a central processing unit (CPU).

[0075] Fig.11 FIG. 1 is a schematic diagram of another inter-core communication system provided by an embodiment of the present invention. Fig.11 As shown, the inter-core communication system also includes a storage module 500; the storage module 500 is connected to the first core 200 and is used to store data corresponding to the interrupt request signal. The second core 300 is also connected to the storage module 500 and is used to read the data corresponding to the interrupt request signal according to the interrupt signal.

[0076] Specifically, the storage module 500 may be a shared memory. When the first core 200 sends an interrupt request to the second core 300, the first core 200 sends the data corresponding to the interrupt request to the storage module 500 for storage. After the data storage is completed, the first core 200 sends an interrupt request signal to the interrupt controller 100, and the interrupt controller 100 generates an interrupt signal according to the interrupt request signal, controls the second core 300 to obtain data from the storage module 500, processes the data, and executes the corresponding interrupt program to realize the interrupt communication between the first core 200 and the second core 300.

[0077] Continue to refer Fig.11 The interrupt controller 100 includes a storage unit 170 , which is used to store pending interrupt request information corresponding to the current value of the counting unit 110 ; the storage unit 170 is integrated in the storage module 500 .

[0078] Specifically, the storage unit 170 can record the interrupt request information corresponding to the interrupt request signal to be processed. When the second core 300 processes the interrupt request signal in sequence, the second core 300 sequentially obtains the interrupt request information corresponding to the interrupt request signal from the storage unit 170, so that the hardware driver corresponding to the second core 300 processes the corresponding interrupt request signal. The storage unit 170 can be integrated into the storage module 500, that is, a part of the storage area is set in the storage module 500 for storing the interrupt request information to be processed corresponding to the current value of the counting unit 110, as the storage unit 170 of the interrupt controller 100, thereby avoiding the need to set up an additional storage unit 170, simplifying the structure of the inter-core communication system.

[0079] Continue to refer Fig.11 The interrupt controller also includes a read register 140; the read register 140 is connected to the counting unit 110, and the read register 140 is used to read the current value of the counting unit 110 and return the current value to the counting unit 110, and the counting unit 110 subtracts 1 when the current value is greater than 0; the second core 300 is also used to call the data corresponding to the interrupt request signal according to the interrupt signal and the current value of the counting unit 110.

[0080] Specifically, the read register 140 can read the current value of the counting unit 110 and output it to the second core 300. The second core 300 retrieves the data corresponding to the interrupt request signal in the storage module 500 according to the current value of the counting unit 110, and processes the data corresponding to the interrupt request signal to respond to the interrupt request signal of the first core 200.

[0081] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An interrupt controller, characterized in that: It includes a counting unit and an interrupt signal generating unit connected to the counting unit; The counting unit is used for counting when the interrupt controller receives an interrupt request signal; The interrupt signal generating unit is used to obtain the count of the counting unit and generate an interrupt signal when the count value of the counting unit changes from 0 to 1; Wherein, the interrupt controller further includes a write register; the write register is used to receive the interrupt request signal and form a second trigger signal according to the interrupt request signal; the counting unit is connected to the write register and is used to count by adding 1 according to the second trigger signal; The interrupt controller further includes a read register; the read register is connected to the counting unit, and the read register is used to read the current value of the counting unit after the interrupt signal receiving end receives the interrupt signal, and return the current value to the counting unit; the counting unit is also used to determine whether the current value is greater than 0 when receiving the returned current value, and if the current value is greater than 0, the count is reduced by 1; The interrupt controller further includes a first timer; the first timer is connected to the read register, and the first timer is used to start timing to a first preset time when the current value of the counting unit read by the read register changes from 1 to 0; During the first preset time, the interrupt signal receiving end is further used to continuously receive the interrupt signal, the write register is further used to continuously receive the interrupt request signal, and the counting unit is used to continuously count the interrupt request signal; When the interrupt signal generating unit includes a status register and an interrupt signal generator, when the timing reaches the first preset time, the read register is also used to read the current value of the counting unit again. If the current value of the counting unit is 0, the status register is set to an enabled state.

2. The interrupt controller according to claim 1, characterized in that: The interrupt signal generating unit includes a status register and an interrupt signal generator; The status register is connected to the counting unit, and the interrupt signal generator is connected to the status register; the status register includes an enabled state and a disabled state. When the status register is in the enabled state, the status register generates a first trigger signal to trigger the interrupt signal generator when the counting unit is incremented by 1, and automatically sets the status register to the disabled state. When the status register is in the disabled state, the status register does not act when the counting unit is incremented by 1; The interrupt signal generator is used for generating an interrupt signal when receiving the first trigger signal.

3. The interrupt controller according to claim 1, characterized in that: When the interrupt signal generating unit includes a status register and an interrupt signal generator, the status register is further used to set the counting unit to an enabled state when the current value of the counting unit is reduced to 0.

4. The interrupt controller according to claim 1, characterized in that: The first timer is further configured to restart timing when the write register receives the interrupt request signal within the first preset time.

5. The interrupt controller according to claim 1, characterized in that: Also included is a second timer; The second timer is connected to the interrupt signal generating unit, and the second timer is used to start timing to a second preset time when the interrupt signal generating unit generates an interrupt signal. The read register is connected to the second timer, and the read register is also used to read the current value of the counting unit after the second preset time.

6. The interrupt controller according to claim 1, characterized in that: The counting unit communicates with the write register in parallel, and the counting unit communicates with the read register in parallel.

7. The interrupt controller according to claim 1, characterized in that: It also includes a storage unit; the storage unit is used to store the pending interrupt request information corresponding to the current value of the counting unit.

8. The interrupt controller according to claim 7, characterized in that: The storage unit stores data in a first-in-first-out queue.

9. An inter-core communication system, characterized in that: comprising a first core, a second core and an interrupt controller according to any one of claims 1 to 8; The first core is connected to the interrupt controller and is used to provide an interrupt request signal to the interrupt controller; The interrupt controller is used to count according to the interrupt request signal and generate an interrupt signal when the count value changes from 0 to 1; the second core is connected to the interrupt controller and is used to process the interrupt request signal according to the interrupt signal.

10. The inter-core communication system according to claim 9, characterized in that: Also included is a storage module; The storage module is connected to the first core and is used to store data corresponding to the interrupt request signal. The second core is also connected to the storage module and is used to read the data corresponding to the interrupt request signal according to the interrupt signal.

11. The inter-core communication system according to claim 10, characterized in that: The interrupt controller comprises a storage unit, and the storage unit is used to store the pending interrupt request information corresponding to the current value of the counting unit; the storage unit is integrated in the storage module.

12. The inter-core communication system according to claim 10, characterized in that: The interrupt controller also includes a read register; the read register is connected to the counting unit, the read register is used to read the current value of the counting unit and return the current value to the counting unit, and the counting unit subtracts 1 when the current value is greater than 0; the second core is also used to call the data corresponding to the interrupt request signal according to the interrupt signal and the current value of the counting unit.

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