A fully dynamic comparator with programmable working mode

Abstract

The present invention relates to a fully dynamic comparator with programmable working mode. The fully dynamic comparator Comparator is respectively provided with clock signal interfaces CLK and CLKB, input voltage interfaces VIP and VIN, working mode control signals VN and VNB, and output signal interfaces OUTP and OUTN. The Comparator is composed of a pre-amplifier Pre_AmpSA and a dynamic latch SA-Latch. One end of Pre_AmpSA is respectively connected to VIP, VIN, VN, VNB, and CLK, and the other end is respectively connected to SA-Latch through signal interfaces op and on. SA-Latch is respectively connected to CLKB, OUTP, and OUTN. The working mode of the present invention is programmable and can flexibly select the working mode of the present invention to be low noise mode or low power consumption mode, low power consumption, and low noise.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment, and in particular to a fully dynamic comparator with programmable working modes, which can flexibly select working in a low noise mode or a low power consumption mode, or a programmable working mode of low power consumption and low noise. Background Art

[0002] With the rapid development of modern society, one of the important indicators to measure a country's comprehensive national strength is the development level of a country's information technology industry. The core of the information technology industry is integrated circuit technology, and analog integrated circuits play a vital role in integrated circuit technology. Compared with analog signals, digital signals are binary, easy to process and store, and have the characteristics of strong anti-interference ability, high precision, and high stability. Therefore, digital circuits are widely used in circuit systems. However, the development of circuit digitization has only replaced part of the analog circuit, and analog circuits are still an indispensable unit module in integrated circuits. Because the signals in nature are all analog signals, a circuit is needed to convert analog signals into digital signals for subsequent processing. As a bridge between analog signals and digital signals, this is the analog-to-digital converter (ADC).

[0003] The performance requirements for analog-to-digital converters (ADCs) vary in different application contexts. The current mainstream ADCs are classified into the following categories: Flash ADC, Pipeline ADC, sigma-delta ADC, and SAR ADC. Flash ADC is the simplest ADC, which uses a large number of comparators in the circuit structure to make it work at the fastest speed, but the resolution is relatively low, and it is usually used in high-speed and low-precision applications. SAR ADC is a representative of low power consumption, medium precision, and medium speed, and has stronger adaptability in today's popular biomedical and wearable portable devices.

[0004] As integrated circuit technology develops rapidly towards deep submicron, the power supply voltage of CMOS technology is constantly decreasing, and power consumption issues are emerging along with noise and short channel effects. However, the use of high-power chip systems in wearable portable devices (such as sports bracelets, smart phones, smart watches, etc.) will inevitably reduce the battery life and service time. This poses a huge challenge to the design of mixed-signal integrated circuits, making them move towards low voltage and low power consumption.

[0005] The comparator is one of the most important modules in all analog-to-digital converter (ADC) circuits. Its equivalent input noise, power consumption, comparison speed, etc. have a significant impact on the performance indicators of ADC (such as resolution, power consumption, etc.). At present, comparators can be divided into two categories: static comparators and dynamic comparators. Compared with dynamic comparators, static comparators have leakage current, static power consumption, and static comparators have a larger area. Therefore, dynamic comparators are usually used in low-power design scenarios. Although dynamic comparators have the advantages of fast speed and low power consumption, their kickback noise and equivalent input offset voltage are large, which limits their use in high-precision applications. Therefore, the design of low-power and low-noise comparators is of extremely important research significance in the design of analog-to-digital converters (ADCs).

[0006] A fully dynamic comparator with programmable working mode, flexible selection of working in low noise mode or low power mode, and programmable working mode of low power consumption and low noise is needed. Summary of the invention

[0007] The object of the present invention is to provide a fully dynamic comparator with programmable working mode, flexible selection of working in low noise mode or low power consumption mode, and programmable working mode of low power consumption and low noise.

[0008] A fully dynamic comparator with programmable operating modes, including:

[0009] A fully dynamic comparator Comparator is provided with clock signal interfaces CLK and CLKB, input voltage interfaces VIP and VIN, working mode control signals VN and VNB, and output signal interfaces OUTP and OUTN. The Comparator is composed of a pre-amplifier Pre_AmpSA and a dynamic latch SA-Latch. One end of the Pre_AmpSA is respectively connected to VIP, VIN, VN, VNB, and CLK, and the other end is respectively connected to SA-Latch through signal interfaces op and on. The SA-Latch is respectively connected to CLKB, OUTP, and OUTN.

[0010] One end of the OR gate A1 of the Pre_AmpSA is connected to CLK and VNB respectively, and the other end is connected to the gate of the field effect tube M5, the source of the M5 is connected to the source of the field effect tube M6, and the gate of the M6 ​​is connected to CLK. After the M5 and M6 are connected, they are connected to the sources of the field effect tube M1 and the field effect tube M2 respectively, the gate of the M1 is connected to VIP, the gate of the M2 is connected to VIN, the drain of the M1 is connected to the drain of the field effect tube M3 one way, and is connected to on, the capacitor C1, and the drain of the field effect tube M7 in sequence one way, the gate of the M7 is connected to VN, the drain of the M2 is connected to the drain of the field effect tube M4 one way, and is connected to op, the capacitor C2, and the drain of the field effect tube M8 in sequence one way, the gate of the M8 is connected to VN, the gate of the M3 and the gate of the M4 are connected through CLK, and the source of the M3, the source of the M4, the source of the M7, and the source of the M8 are connected.

[0011] The source of M3 is connected to the ground potential, and the source of M5 is connected to the power supply potential.

[0012] The source of the field effect transistor M15 of the SA-Latch, the source of the field effect transistor M13, the source of the field effect transistor M14, and the source of the field effect transistor M16 are connected, the gate of the M15 is connected to CLKB, the drain of the M15 is connected to the drain of the field effect transistor M11, one is connected to OUTN, one is respectively connected to the gate of M14 and the gate of the field effect transistor M10, the gate of the M11 is connected to on, the source of the M11 is connected to the drain of the field effect transistor M9, the source of the M9 is connected to the source of the field effect transistor M10, the gate of the M9 is connected to the gate of M13, one is connected to OUTP, one is respectively connected to the drains of M14 and M16, one is connected to the drain of the field effect transistor M12, the gate of the M16 is connected to CLKB, the gate of the M12 is connected to op, and the source of the M12 is connected to the drain of the field effect transistor M10.

[0013] The source of M10 is connected to the ground potential, and the source of M15 is connected to the power supply potential.

[0014] The source of M10 is connected to the source of M3 , and the source of M5 is connected to the source of M15 .

[0015] The VN and VNB are a pair of two-phase non-overlapping working mode control signal interfaces.

[0016] The CLK and CLKB are a pair of two-phase non-overlapping clock signal interfaces.

[0017] The present invention is a fully dynamic comparator with programmable working mode. It includes two circuit modules, a preamplifier with a working mode control terminal and an SA dynamic latch. Compared with the traditional comparator, the fully dynamic comparator has no static power consumption and only dynamic power consumption, which greatly reduces the power consumption of the comparator. The preamplifier with a working mode control terminal is used to make the working mode of the comparator programmable, so that the comparator can have two working modes: low power consumption and low noise. In different working modes, the performance of low power consumption and low noise of the overall comparator can be achieved respectively, and at the same time, it is ensured that the comparison time of the comparator is approximately equal under the two working modes. Various performance indicators of the comparator such as equivalent input noise, power consumption, resolution, linearity, etc. are considered in compromise, and a fully dynamic comparator with programmable working mode is realized, and its working mode can be flexibly adjusted under different application backgrounds. The invention has broad application prospects in low-power and low-noise ADCs, especially successive approximation register (SAR) ADCs.

[0018] The full dynamic comparator of the present invention is provided with clock signal interfaces CLK and CLKB, input voltage interfaces VIP and VIN, working mode control signals VN and VNB, and output signal interfaces OUTP and OUTN. The comparator is composed of a pre-amplifier Pre_AmpSA and a dynamic latch SA-Latch. One end of Pre_AmpSA is connected to VIP, VIN, VN, VNB, and CLK respectively, and the other end is connected to SA-Latch through signal interfaces op and on respectively. SA-Latch is connected to CLKB, OUTP, and OUTN respectively. The working mode of the present invention is programmable and can be flexibly selected to work in a low noise mode or a low power consumption mode, low power consumption, and low noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The overall block diagram of the fully dynamic comparator with programmable working mode of the present invention;

[0020] Figure 2 A block diagram of a fully dynamic comparator system with programmable working modes of the present invention;

[0021] Figure 3 This is a circuit diagram of the pre-amplifier of the present invention;

[0022] Figure 4 The dynamic latch circuit diagram of the present invention;

[0023] Figure 5 The overall circuit diagram of the fully dynamic comparator with programmable working mode of the present invention. DETAILED DESCRIPTION

[0024] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0025] A full-dynamic comparator with programmable working mode includes: a full-dynamic comparator Comparator, wherein the Comparator is respectively provided with clock signal interfaces CLK and CLKB, input voltage interfaces VIP and VIN, working mode control signals VN and VNB, and output signal interfaces OUTP and OUTN; the Comparator is composed of a pre-amplifier Pre_AmpSA and a dynamic latch SA-Latch; one end of Pre_AmpSA is respectively connected to VIP, VIN, VN, VNB, and CLK, and the other end is respectively connected to SA-Latch through signal interfaces op and on; and SA-Latch is respectively connected to CLKB, OUTP, and OUTN.

[0026] One end of the OR gate A1 of Pre_AmpSA is connected to CLK and VNB respectively, and the other end is connected to the gate of the field effect tube M5. The source of M5 is connected to the source of the field effect tube M6, and the gate of M6 is connected to CLK. After M5 and M6 are connected, they are connected to the sources of the field effect tube M1 and the field effect tube M2 respectively. The gate of M1 is connected to VIP, and the gate of M2 is connected to VIN. The drain of M1 is connected to the drain of the field effect tube M3, and is connected to on, capacitor C1, and the drain of the field effect tube M7 in sequence. The gate of M7 is connected to VN. The drain of M2 is connected to the drain of the field effect tube M4, and is connected to op, capacitor C2, and the drain of the field effect tube M8 in sequence. The gate of M8 is connected to VN. The gate of M3 and the gate of M4 are connected through CLK. The source of M3, the source of M4, the source of M7, and the source of M8 are connected. The source of M3 is connected to the ground potential, and the source of M5 is connected to the power supply potential.

[0027] The source of the field effect transistor M15 of the SA-Latch, the source of the field effect transistor M13, the source of the field effect transistor M14, and the source of the field effect transistor M16 are connected, the gate of M15 is connected to CLKB, the drain of M15 is connected to the drain of the field effect transistor M11, one is connected to OUTN, one is connected to the gate of M14 and the gate of the field effect transistor M10, the gate of M11 is connected to on, the source of M11 is connected to the drain of the field effect transistor M9, the source of M9 is connected to the source of the field effect transistor M10, the gate of M9 is connected to the gate of M13, one is connected to OUTP, one is connected to the drain of M14 and M16, one is connected to the drain of the field effect transistor M12, the gate of M16 is connected to CLKB, the gate of M12 is connected to op, and the source of M12 is connected to the drain of the field effect transistor M10. The source of M10 is grounded, and the source of M15 is connected to the power supply potential. The source of M10 is connected to the source of M3 , and the source of M5 is connected to the source of M15 .

[0028] VN and VNB are a pair of two-phase non-overlapping working mode control signal interfaces. CLK and CLKB are a pair of two-phase non-overlapping clock signal interfaces.

[0029] In order to make the application of comparators in low-power, high-precision analog-to-digital converters (ADCs) more flexible. The fully dynamic comparator Comparator includes two input voltages VIP and VIN, a pair of two-phase non-overlapping clock signals CLK and CLKB, a pair of two-phase non-overlapping working mode control signals VN and VNB, and a pair of output signals OUTP and OUTN. It includes two parts: a first-stage preamplifier Pre_Amp with a working mode control terminal and a second-stage SA dynamic latch SA-Latch, wherein the input signal is connected to the first-stage preamplifier, the working mode control signal is connected to the first-stage preamplifier, and a pair of output signal interfaces (on, op) of the first-stage preamplifier are connected to it as the input terminal of the second-stage SA latch. In addition, the clock input signal CLK is connected to the first-stage preamplifier, and the inverted signal CLKB of CLK is connected to the SA latch.

[0030] Field effect transistors M1, M2, M3, M4, M5, M6, M7, M8, capacitors C1, C2 and an OR gate A1 are formed. The source electrodes of M1 and M2 are connected to each other and to the drain electrodes of M5 and M6, which serve as differential input pairs, and the gate electrodes are connected to the comparator input signal. The drain electrodes of M1 and M2 are connected to the drain electrodes of M3 and M4, and are respectively connected to the upper plates of capacitors C1 and C2 as the first-level output signal interfaces (on, op), the source electrodes of M3 and M4 are both connected to the ground potential, and the gate electrodes are connected and controlled by the clock signal CLK. The gate electrode of M6 is controlled by the clock signal CLK, and the source electrode of M6 is connected to the power supply potential. Transistors M5, M7 and M8 jointly control the working mode of the full dynamic comparator, wherein the drain electrodes of M7 and M8 are respectively connected to the lower plates of capacitors C1 and C2, the gate electrodes are both connected to the working mode control signal VN, and the source electrodes are both connected to the ground potential. The clock signal CLK and the operation mode control signal VNB are connected to the gate of the transistor M5 after passing through an OR gate A1, and the source of M5 is connected to the power supply potential.

[0031] The specific structure of the SA dynamic latch is composed of field effect tubes M9, M10, M11, M12, M13, M14, M15, and M16. The output signal (on, op) of the first stage pre-amplifier is connected to the gates of M11 and M12 as input signals, and the sources of M11 and M12 are connected to the drains of M9 and M10 respectively. The gates of M9 and M13 are connected to the drains of M12, M14, and M16. Similarly, the gates of M10 and M14 are connected to the drains of M11, M13, and M15, and are used as output signals (OUTP, OUTN), respectively, thus forming a positive feedback latching latch structure. The sources of M13 to M16 are all connected to the power supply potential, and the sources of M9 and M10 are connected to the ground potential. The clock signal CLKB controls the gates of M15 and M16 to control their conduction and closure. When CLKB is at a high level, the circuit performs normal comparison work. Due to the positive feedback latch, the output signal is pulled to the power supply and ground potential respectively, and the comparison result is stored by the latch.

[0032] When the working mode control signal VN is high and VNB is low, the comparator works in low noise mode; when the working mode control signal VN is low and VNB is high, the comparator works in low power mode. And under a given frequency clock signal, the comparator compares the two analog input signals and outputs a normal comparison result.

[0033] When the comparator works in low power consumption mode, the working mode control signal VN is low level and VNB is high level. Transistors M7 and M8 are cut off, the lower plates of capacitors C1 and C2 are suspended, and since the clock signal CLK and the working mode control signal VNB are connected to the gate of transistor M5 after passing through an OR gate A1, the gate of M5 is equivalent to being connected to the power supply potential at this time, that is, M5 is cut off. When CLK is high level and CLKB is low level, the comparator works in reset state, otherwise it is in normal comparison state. In reset state, M3 and M4 in the first stage preamplifier are turned on, the drains of M1 and M2 (i.e., op, on) are reset to ground potential, and since M6 is cut off, the DC path from the power supply to the ground is cut off, so that the static power consumption of the comparator is zero, and the first stage circuit does not work at this time. Since the clock signal CLKB is at a low level, M15 and M16 in the second-stage SA dynamic latch are turned on, and the output signals (OUTP, OUTN) are at the power supply potential, causing M13 and M14 to be turned off. At the same time, M9 and M10 are turned on, and the drain voltage of M9 and M10 is pulled to the ground potential.

[0034] In the normal comparison state, M3 and M4 in the first-stage preamplifier are cut off, and M6 is conducting. Under the action of the input signals VIP and VIN, M1 and M2 are saturated and conducting. Since there is a voltage difference between the input terminal voltages (VIP, VIN), the leakage currents on both sides are different, resulting in different charging speeds of the parasitic capacitances at nodes on and op, that is, different rising speeds of the drain potentials of M1 and M2. The MOS transistor with a larger overdrive voltage has a faster rising speed of the drain potential. Therefore, the instantaneous potentials of the output signals (on, op) of the first-stage preamplifier are different. Taking the case where the rising speed of the on potential is greater than that of the op potential (i.e., VIP < VIN) as an example for illustration. In the second-stage SA dynamic latch, the gate potential of M11 (i.e., the on potential) rises faster. Therefore, M11 reaches the conduction condition earlier than M12, the OUTN potential drops first, and the OUTP potential drops later. Once OUTN drops to the potential that causes M14 to conduct, M14 conducts and pulls OUTN to the ground potential and OUTP to the power supply potential. Therefore, the comparator outputs the correct comparison result for the output signals (OUTP, OUTN).

[0035] In summary, when VIN > VIP, the comparator output OUTP > OUTN, and the comparison result is correct. On the contrary, when VIP > VIN, the working analysis process of the comparator is the same as described above.

[0036] Since the working mode control signal VN is at a low level and VNB is at a high level at this time, the transistor M5 is cut off, the lower plates of the capacitors C1 and C2 are floating, and the node capacitances at the drains of the differential input transistors M1 and M2 of the first-stage preamplifier (i.e., at nodes on and op) are smaller than those when the comparator operates in the low-noise mode. The node capacitances discharge faster, and the sum of the drain currents of the differential input transistors M1 and M2 of the first-stage preamplifier is only equal to the drain current of the transistor M6. The overall dynamic working current of the circuit decreases, and the dynamic power consumption drops.

[0037] When the comparator operates in the low-noise mode, the operating mode control signal VN is at a high level and VNB is at a low level. Transistors M7 and M8 are turned on, and the potentials of the lower plates of capacitors C1 and C2 are pulled to the ground potential. Since the clock signal CLK and the operating mode control signal VNB are connected to the gate of transistor M5 after passing through an OR gate A1, the gate of M5 is effectively controlled by the clock signal CLK at this time. When CLK is at a high level and CLKB is at a low level, the comparator operates in the reset state; otherwise, it is in the normal comparison state. In the reset state, M5 and M6 in the first-stage preamplifier are cut off, M3 and M4 are turned on, and the drains of M1 and M2 (i.e., op and on) are reset to the ground potential. Since M5 and M6 are cut off, the DC conduction path from the power supply to the ground is cut off, making the static power consumption of this comparator zero, and the first-stage circuit does not work at this time. Since the clock signal CLKB is at a low level, M15 and M16 in the second-stage SA dynamic latch are turned on, and the output signals (OUTP, OUTN) are at the power supply potential, causing M13 and M14 to be cut off. At the same time, M9 and M10 are turned on, and the drain voltages of M9 and M10 are pulled to the ground potential.

[0038] In the normal comparison state, M3 and M4 in the first-stage preamplifier are cut off, and M5 and M6 are turned on. Under the action of the input signals VIP and VIN, M1 and M2 are saturated and turned on. Since there is a voltage difference between the input terminal voltages (VIP, VIN), the leakage currents on both sides are different, resulting in different charging speeds of capacitors C1 and C2, that is, the rising speeds of the drain potentials of M1 and M2 are different. The MOS transistor with a larger overdrive voltage has a faster rising speed of the drain potential. Therefore, the instantaneous potentials of the output signals (on, op) of the first-stage preamplifier are different. Taking the case where the rising speed of the on potential is greater than the rising speed of the op potential (i.e., VIP < VIN) as an example for illustration. In the second-stage SA dynamic latch, the gate potential of M11 (i.e., the on potential) rises faster. Therefore, M11 reaches the conduction condition earlier than M12, the OUTN potential drops first, and the OUTP potential drops later. Once OUTN drops to the potential that causes M14 to conduct, M14 conducts and pulls OUTN to the ground potential and OUTP to the power supply potential. Therefore, the comparator output signals (OUTP, OUTN) output the correct comparison result.

[0039] In summary, when VIN > VIP, the comparator output OUTP > OUTN, and the comparison result is correct. Conversely, when VIP > VIN, the working analysis process of the comparator is the same as described above.

[0040] The equivalent input noise of the comparator is related to the node capacitance at the drain of transistors M1 and M2 (i.e., on, op). The higher the value, the smaller the equivalent input noise. At the same time, when the comparator works in low noise mode, the sum of the drain currents of the differential input tubes M1 and M2 of the first stage pre-amplifier is equal to the sum of the drain currents of transistors M5 and M6. Compared with the comparator working in low power mode, the drain current increases, which speeds up the charging speed of capacitors C1 and C2, ensuring that the comparison time of the comparator working in low noise mode is approximately equal to the comparison time when working in low power mode.

[0041] The present invention is a fully dynamic comparator with programmable working mode. It includes two circuit modules, a preamplifier with a working mode control terminal and an SA dynamic latch. The comparator has two working states: reset and comparison. When the clock signal CLK is at a low level, it is in a reset state, otherwise it is in a comparison state. At the same time, the working mode control signal VN is used to control the working mode of the comparator, and there are two working modes: low noise and low power consumption. When the working mode control signal VN is at a high level and VNB is at a low level, the comparator works in a low noise mode. In the preamplifier, by introducing the discharge of capacitors C1 and C2 and the conduction of transistor M5, the equivalent input noise of the circuit is reduced, and at the same time, the comparison time is ensured to be approximately equal to that when working in a low power consumption mode. When the working mode control signal VN is at a low level and VNB is at a high level, the comparator works in a low power consumption mode. In the first stage preamplifier, the signal VN makes the lower plates of capacitors C1 and C2 suspended, the transistor M5 is turned off, the overall dynamic current of the circuit is reduced, and the power consumption of the comparator is greatly reduced. In addition, the present invention adopts a fully dynamic circuit structure, so that the circuit has no static power consumption when the comparator works in low noise and low power consumption modes, and ultimately the overall power consumption of the comparator is greatly reduced compared with the traditional static comparator.

[0042] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. The present invention may be subject to various changes and improvements without departing from the spirit and scope of the present invention. These changes and improvements fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A fully dynamic comparator with programmable working mode, characterized in that: include: A full dynamic comparator Comparator, the Comparator is provided with clock signal interfaces CLK and CLKB, input voltage interfaces VIP and VIN, working mode control signals VN and VNB, output signal interfaces OUTP and OUTN, the Comparator is composed of a pre-amplifier Pre_AmpSA and a dynamic latch SA-Latch, one end of the Pre_AmpSA is connected to VIP, VIN, VN, VNB, CLK respectively, and the other end is connected to SA-Latch through signal interfaces op and on respectively, and the SA-Latch is connected to CLKB, OUTP, OUTN respectively; One end of the OR gate A1 of the Pre_AmpSA is connected to CLK and VNB respectively, and the other end is connected to the gate of the field effect transistor M5, the source of the M5 is connected to the source of the field effect transistor M6, and the gate of the M6 ​​is connected to CLK. After the M5 and M6 are connected, they are connected to the source of the field effect transistor M1 and the field effect transistor M2 respectively, the gate of the M1 is connected to VIP, the gate of the M2 is connected to VIN, the drain of the M1 is connected to the drain of the field effect transistor M3, and the other end is connected to on, the capacitor C1, and the drain of the field effect transistor M7 in sequence, and the gate of the M7 is connected to VN, the drain of the M2 is connected to the drain of the field effect transistor M4, and the other end is connected to op, the capacitor C2, and the drain of the field effect transistor M8 in sequence, and the gate of the M8 is connected to VN, the gate of the M3 and the gate of the M4 are connected through CLK, and the source of the M3, the source of the M4, the source of the M7, and the source of the M8 are connected; The source of the SA-Latch field effect transistor M15, the source of the field effect transistor M13, the source of the field effect transistor M14, and the source of the field effect transistor M16 are connected, the gate of the M15 is connected to CLKB, the drain of the M15 is connected to the drain of the field effect transistor M11, one way is connected to OUTN, one way is respectively connected to the gate of M14 and the gate of the field effect transistor M10, the gate of the M11 is connected to on, the source of the M11 is connected to the drain of the field effect transistor M9, the source of the M9 is connected to the source of the field effect transistor M10, the gate of the M9 is connected to the gate of M13, one way is connected to OUTP, one way is respectively connected to the drains of M14 and M16, one way is connected to the drain of the field effect transistor M12, the gate of the M16 is connected to CLKB, the gate of the M12 is connected to op, and the source of the M12 is connected to the drain of the field effect transistor M10; The source of M10 is connected to the source of M3 , and the source of M5 is connected to the source of M15 .

2. A fully dynamic comparator with programmable working mode according to claim 1, characterized in that: The source of M3 is connected to the ground potential, and the source of M5 is connected to the power supply potential.

3. A fully dynamic comparator with programmable working mode according to claim 1, characterized in that: The source of M10 is connected to the ground potential, and the source of M15 is connected to the power supply potential.

4. A fully dynamic comparator with programmable working mode according to claim 1, characterized in that: The VN and VNB are a pair of two-phase non-overlapping working mode control signal interfaces.

5. A fully dynamic comparator with programmable working mode according to claim 1, characterized in that: The CLK and CLKB are a pair of two-phase non-overlapping clock signal interfaces.

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