Substrates and electronic packages with embedded electronic components

Abstract

The present disclosure provides a substrate embedded with electronic components and an electronic package, wherein the substrate embedded with electronic components comprises: a core layer, having a first cavity and a second cavity on the first surface and the second surface of the core layer respectively, the second surface being opposite to the first surface in the thickness direction of the core layer; an electronic component arranged in the first cavity; a first insulating material covering at least a portion of the electronic component; a first wiring layer arranged on the first insulating material and connected to the electronic component; a built-in block arranged in the second cavity; and a second insulating material covering at least a portion of the built-in block.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0167954 filed on December 16, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a substrate with embedded electronic components and an electronic package. Background Art

[0003] Recently, electronic devices are required to be not only thinner and smaller, but also have relatively high performance and relatively high functionality. Therefore, the number of electronic components to be mounted on a printed circuit board is increasing, while the number of electronic components that can be mounted on the surface of the printed circuit board is limited. This is because the size of the printed circuit board is also required to be reduced according to the miniaturization and slimming of the electronic devices. Therefore, a technology for a substrate embedded with electronic components (embedding electronic components such as passive components and active components in a printed circuit board) has been developed. Summary of the invention

[0004] An aspect of the present disclosure is to provide an electronic component-embedded substrate having improved heat dissipation characteristics.

[0005] Another aspect of the present disclosure is to provide a substrate having electronic components embedded therein with improved warpage.

[0006] According to one aspect of the present disclosure, a substrate embedded with electronic components includes: a core layer, having a first cavity and a second cavity on a first surface and a second surface of the core layer, respectively, the second surface being opposite to the first surface; an electronic component disposed in the first cavity; a first insulating material covering at least a portion of the electronic component; a first wiring layer disposed on the first insulating material and connected to the electronic component; a built-in block disposed in the second cavity; and a second insulating material covering at least a portion of the built-in block.

[0007] According to another aspect of the present disclosure, an electronic package includes: the above-mentioned substrate embedded with electronic components; and a semiconductor package, which is mounted on the substrate embedded with electronic components through at least one electrically connecting metal piece, and the at least one electrically connecting metal piece electrically connects the semiconductor package to the substrate embedded with electronic components.

[0008] According to another aspect of the present disclosure, a substrate embedded with electronic components includes: a first build-up structure including a first wiring layer; one or more electronic components arranged in the first build-up structure and connected to the first wiring layer; a second build-up structure including a second wiring layer and arranged on the first build-up structure; one or more built-in blocks arranged in the second build-up structure; and an insulating layer arranged between the one or more electronic components in the first build-up structure and the one or more built-in blocks in the second build-up structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is an example of a block diagram schematically illustrating an electronic device system according to an exemplary embodiment.

[0011] Figure 2 is a perspective view schematically illustrating an electronic device according to an exemplary embodiment.

[0012] Figure 3 is a cross-sectional view schematically illustrating a substrate 100A in which an electronic component is embedded according to an exemplary embodiment.

[0013] FIG. 4A to FIG. 4D A manufacturing process of the electronic component-embedded substrate 100A according to an exemplary embodiment is schematically illustrated.

[0014] Figure 5 is a cross-sectional view schematically illustrating an electronic component-embedded substrate 100B according to another exemplary embodiment.

[0015] Figure 6 1 is a cross-sectional view schematically illustrating an electronic package in which a semiconductor package is mounted on an electronic component-embedded substrate 100A according to an exemplary embodiment. DETAILED DESCRIPTION

[0016] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clarity of description, the shapes and sizes of elements in the drawings may be exaggerated or reduced.

[0017] Electronic Devices

[0018] Figure 1 is an example of a block diagram schematically illustrating an electronic device system according to an exemplary embodiment.

[0019] Referring to the drawings, the electronic device 1000 may house a mainboard 1010 therein. The mainboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc., which are physically and / or electrically connected thereto. These components may be connected to other components to be described below through various signal lines 1090.

[0020] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters, application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0021] The network-related components 1030 may include components that operate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Only (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Wireless Local Area Network (LAN), Bluetooth, 3G protocol, 4G protocol and 5G protocol, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, but may also include components operating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020 together with each other.

[0022] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0023] The electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the mainboard 1010, depending on the type of the electronic device 1000. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, these other components are not limited thereto, but may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. These other components may also include other components for various purposes according to the type of the electronic device 1000, etc.

[0024] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device that processes data.

[0025] Figure 2 is a perspective view schematically illustrating an electronic device according to an exemplary embodiment.

[0026] Referring to the accompanying drawings, the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the electronic components 1120 may be the above-mentioned chip-related components (e.g., semiconductor package 1121), but is not limited thereto. The semiconductor package 1121 may be a surface-mounted component in which a semiconductor chip or a passive component is mounted on a packaging substrate in the form of a packaging substrate, but is not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0027] Substrate with embedded electronic components

[0028] Figure 3 is a cross-sectional view schematically illustrating a substrate 100A in which an electronic component is embedded according to an exemplary embodiment.

[0029] Reference Figure 3 According to an exemplary embodiment, a substrate 100A embedded with an electronic component may include: a core layer 110 having a first cavity 110HA and a second cavity 110HB at a first surface 110-1 and a second surface 110-2, respectively; an electronic component 120 disposed in the first cavity 110HA; a first insulating material 141A covering at least a portion of the electronic component 120; a first wiring layer 142A disposed on the first insulating material 141A; a first via 143A penetrating the first insulating material 141A and connecting the electronic component 120 and the first wiring layer 142A; a built-in block 130 disposed in the second cavity 110HB; a second insulating material 141B covering at least a portion of the built-in block 130 ; a second wiring layer 142B disposed on the second insulating material 141B; a second via 143B penetrating the second insulating material 141B and connecting the built-in block 130 and the second wiring layer 142B; a through via 113 penetrating the first insulating material 141A, the core layer 110, the built-in block 130, and the second insulating material 141B, and connecting the first wiring layer 142A and the second wiring layer 142B to each other; a first build-up structure 150 disposed on the first insulating material 141A; a second build-up structure 160 disposed on the second insulating material 141B; a first passivation layer 170 disposed on the first build-up structure 150; and a second passivation layer 180 disposed on the second build-up structure 160. As required, an electrically connected metal member (not shown) disposed in the opening of each of the first passivation layer 170 and the second passivation layer 180 may also be included.

[0030] The first cavity 110HA may penetrate a portion of the core layer 110 from the first surface 110-1 of the core layer 110 in the thickness direction of the core layer 110. Similarly, the second cavity 110HB may penetrate a portion of the core layer 110 from the second surface 110-2 of the core layer 110 in the thickness direction of the core layer 110. In this case, the thickness direction refers to the first direction 1 and / or the second direction 2. Therefore, the thickness direction may be a direction parallel to the direction connecting the first surface 110-1 and the second surface 110-2 of the core layer 110.

[0031] Each of the first cavity 110HA and the second cavity 110HB may penetrate less than one-half of the thickness of the core layer 110. For example, each of the first cavity 110HA and the second cavity 110HB may penetrate about one-third of the thickness of the core layer 110. Therefore, in a cross-sectional view, the first cavity 110HA and the second cavity 110HB may not have an overlapping area.

[0032] In this way, when the first cavity 110HA passes through the core layer 110 shallowly, it is advantageous to shorten the electrical connection path with the semiconductor package (not shown) mounted on the substrate embedded with electronic components. The thickness of the second cavity 110HB may be substantially the same as the thickness of the first cavity 110HA. However, the present disclosure is not limited thereto, and the thickness of the second cavity 110HB may be different from the thickness of the first cavity 110HA.

[0033] The term "substantially the same" in this specification does not mean completely the same with no errors, but includes a tolerance range with a degree understandable to those skilled in the art.

[0034] As shown in the drawings, the first cavity 110HA and the second cavity 110HB may be provided as a plurality of first cavities 110HA and a plurality of second cavities 110HB, respectively. Although the drawings show that two first cavities 110HA and three second cavities 110HB are formed, the present disclosure is not limited thereto. The number of the first cavity 110HA and the second cavity 110HB may vary according to design.

[0035] Each of the electronic component 120 and the built-in block 130 may also be provided in plural. In this case, one or more electronic components 120 may be provided in each of the plurality of first cavities 110HA. In addition, one or more built-in blocks 130 may be provided in each of the plurality of second cavities 110HB. The number of electronic components 120 provided in each of the plurality of first cavities 110HA may be greater than the number of built-in blocks 130 provided in each of the plurality of second cavities 110HB.

[0036] When the electronic component 120 is provided as a plurality of electronic components 120, one or more electronic components 120 may be provided in the first cavity 110HA. In addition, when the first cavity 110HA is provided as a plurality of first cavities 110HA, one or more electronic components 120 may be provided in each of the plurality of first cavities 110HA.

[0037] When the built-in block 130 is provided as a plurality of built-in blocks 130, one or more built-in blocks 130 may be provided in the second cavity 110HB. In addition, when the second cavity 110HB is provided as a plurality of second cavities 110HB, one or more built-in blocks 130 may be provided in each of the plurality of second cavities 110HB.

[0038] The electronic component 120 and the built-in block 130 may be arranged so that their projections on the plane deviate from each other. The plane may be perpendicular to the first direction 1 and the second direction 2 and parallel to the third direction 3 and the fourth direction 4. Therefore, a straight line connecting the center of the electronic component 120 and the center of the built-in block 130 may intersect a straight line connecting the first surface and the second surface of the core layer.

[0039] The first cavity 110HA and the second cavity 110HB may also be formed to be offset from each other on a plane. A portion of the first cavity 110HA and a portion of the second cavity 110HB may be formed to partially overlap each other on a plane.

[0040] As described above, the first cavity 110HA and the second cavity 110HB may be provided as a plurality of first cavities 110HA and a plurality of second cavities 110HB, respectively. In this case, each of the plurality of first cavities 110HA and each of the plurality of second cavities 110HB in the cross-sectional view may be formed to be alternately provided on the first surface 110-1 and the second surface 110-2 in the third direction or the fourth direction. Therefore, in the cross-sectional view, a line sequentially connecting the center of each of the plurality of first cavities 110HA and the center of each of the plurality of second cavities 110HB in the third direction or the fourth direction may have a V shape, a W shape, an inverted V shape, an inverted W shape, a sawtooth shape, etc.

[0041] Similarly, the electronic component 120 disposed in each of the plurality of first cavities 110HA and the built-in block 130 disposed in each of the plurality of second cavities 110HB in the cross-sectional view may also be formed to be alternately disposed on the first surface 110-1 and the second surface 110-2 in the third direction or the fourth direction. Therefore, in the cross-sectional view, a line sequentially connecting the center of the electronic component 120 disposed in each of the plurality of first cavities 110HA and the center of the built-in block 130 disposed in each of the plurality of second cavities 110HB in the third direction or the fourth direction may have a V shape, a W shape, an inverted V shape, an inverted W shape, a sawtooth shape, etc.

[0042] Recently, in the case of a substrate with embedded electronic components, in order to shorten the electrical connection path with a semiconductor package (not shown) mounted on the substrate with embedded electronic components, the electronic components may be embedded on one side of the substrate. In this case, since the electronic components are disposed adjacent to one side of the substrate with embedded electronic components, structural stability may be deteriorated due to the asymmetry of the entire substrate. Therefore, warping of the substrate with embedded electronic components may occur.

[0043] In the case of a substrate 100A embedded with electronic components according to an exemplary embodiment, the electronic component 120 may be disposed adjacent to the first surface 110-1 of the core layer 110. The built-in block 130 may be disposed on a second surface 110-2 of the core layer 110 opposite to the first surface 110-1 to improve asymmetry. Therefore, the warping of the substrate 100A embedded with electronic components may be improved. The built-in block 130 may be disposed in consideration of factors affecting the warping of the substrate 100A embedded with electronic components (such as the thermal expansion coefficient, volume, weight, etc. of each of the electronic component 120 and the built-in block 130).

[0044] The through via 113 may penetrate the core layer 110 and may further penetrate the built-in block 130. Therefore, the through via 113 may contact at least a portion of the built-in block 130.

[0045] As described below, the built-in block 130 may include a thermally conductive material. In this case, heat generated from a semiconductor package (not shown) mounted on the electronic component-embedded substrate 100A may be discharged not only through the through-via 113 but also through the built-in block 130 connected to the through-via 113. Therefore, the heat dissipation characteristics of the electronic component-embedded substrate 100A may be improved.

[0046] In this case, on the second surface 110-2 of the core layer 110, the second via holes 143B may be disposed around the through via holes 113. Therefore, heat transferred through the through via holes 113 and the built-in block 130 may be discharged through the second via holes 143B.

[0047] Hereinafter, each configuration of the electronic component embedded substrate 100A according to the exemplary embodiment will be described in more detail.

[0048] The core layer 110 can be used to increase the rigidity of the substrate to suppress the warping of the substrate, etc. The material used to form the core layer 110 is not particularly limited, and any material can be used as long as the material has insulating properties. For example, a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide) or a material including a reinforcing material (such as inorganic filler and / or glass cloth, glass fabric, etc.) and a thermosetting resin or a thermoplastic resin (such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0049] The electronic component 120 and the built-in block 130 may be disposed in the first cavity 110HA and the second cavity 110HB, respectively. Depths of the first cavity 110HA and the second cavity 110HB may be the same as or different from each other.

[0050] The through via 113 may penetrate the core layer 110 and the built-in block 130 and may connect the first wiring layer 142A and the second wiring layer 142B to each other. As shown in the drawing, the through via 113 may also penetrate the first insulating material 141A and the second insulating material 141B.

[0051] As a material for forming the through via 113, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, etc. may be used. The through via 113 may be completely filled with a conductive material, or may be formed by forming a conductive material along the wall of the via hole. When the through via 113 is a through via in which a conductive material is formed along the wall of the via hole, an insulating material may fill the inside of the via hole. In addition, the shape of the through via 113 may be all shapes known in the art, such as a conical shape, a cylindrical shape, etc.

[0052] The electronic component 120 may be a passive component such as a capacitor, an inductor, etc., and may be a chip-type passive component including a body 120B and an electrode 120P. For example, the electronic component 120 may be a multilayer ceramic capacitor (MLCC). However, the present disclosure is not limited thereto, and the electronic component 120 may be an active component such as an integrated circuit (IC), a semiconductor chip, etc. As described above, the electronic component 120 may be provided as a plurality of electronic components 120. In this case, the plurality of electronic components 120 may be the same or different from each other. For example, a portion of the plurality of electronic components 120 may be a capacitor, and a portion of the plurality of electronic components 120 may be an inductor.

[0053] The built-in block 130 may be disposed on a side of the substrate opposite to a side on which the electronic component 120 is disposed, and may be used to improve warpage of the substrate. In this case, a material for forming the built-in block 130 is not particularly limited.

[0054] The built-in block 130 may be in the form of a block, and the shape of the built-in block 130 is not particularly limited. For example, the shape of the built-in block 130 may be a rectangular parallelepiped, a regular hexahedron, a triangular prism, a pentagonal prism, a hexagonal prism, or the like.

[0055] The material of the built-in block 130 may include a thermally conductive material capable of transferring heat. For example, copper (Cu), graphene, aluminum (Al), silver (Ag), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used. For example, the built-in block 130 may be a copper block. Thus, when the built-in block 130 includes a thermally conductive material, the built-in block 130 may be used as a heat release path for heat transferred to the substrate 100A in which the electronic components are embedded and heat generated from the substrate 100A in which the electronic components are embedded.

[0056] However, the present disclosure is not limited thereto, and an insulating material may be used as the material of the built-in block 130. For example, a thermosetting resin such as an epoxy resin or a resin in which a reinforcing agent such as an inorganic filler and / or glass cloth, glass fabric, etc. is further included in the thermosetting resin may be used.

[0057] The first insulating material 141A may cover at least a portion of the electronic component 120 to perform physical and chemical protection. For example, the first insulating material 141A may cover at least a portion of each of the side surface of the electronic component 120 and the surface of the electronic component 120 facing the first accumulation structure 150, and may fill at least a portion of the first cavity 110HA. When a plurality of electronic components 120 are disposed in the first cavity 110HA, the space between the plurality of electronic components 120 may be filled. In addition, at least a portion of the first surface 110-1 of the core layer 110 may be covered.

[0058] The material used to form the first insulating material 141A is not particularly limited, and any material can be used as long as the material has insulating properties. For example, a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material including a reinforcing material (such as inorganic filler and / or glass cloth, glass fabric, etc.) and a thermosetting resin or a thermoplastic resin (such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0059] The first wiring layer 142A may be connected to the electronic component 120 and / or through the via 113. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), their alloys, etc. may be used as materials for forming the first wiring layer 142A. The first wiring layer 142A may perform various functions according to its design. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. may be included. In this case, the signal (S) pattern may include various signal patterns (e.g., data signal patterns, etc.) in addition to the ground (GND) pattern, the power (PWR) pattern, etc. In addition, a via pad, etc. may be included.

[0060] The first via 143A may connect the electronic component 120 and the first wiring layer 142A. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used as materials for forming the first via 143A. The first via 143A may be completely filled with a conductive material, or may be formed by forming a conductive material along the wall of the via hole. In addition, the shape of the first via 143A may be all shapes known in the art, such as a conical shape, a cylindrical shape, etc.

[0061] The second insulating material 141B may cover at least a portion of the built-in block 130 to perform physical and chemical protection. For example, the second insulating material 141B may cover at least a portion of each of the side surface of the built-in block 130 and the surface of the built-in block 130 facing the second accumulation structure 160, and may fill at least a portion of the second cavity 110HB. In addition, at least a portion of the second surface 110-2 of the core layer 110 may be covered.

[0062] The material used to form the second insulating material 141B is not particularly limited, and any material can be used as long as the material has insulating properties. For example, a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material including a reinforcing material (such as inorganic filler and / or glass cloth, glass fabric, etc.) and a thermosetting resin or a thermoplastic resin (such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0063] The second wiring layer 142B may be connected to the built-in block 130 and / or through the via 113. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), their alloys, etc. may be used as materials for forming the second wiring layer 142B. The second wiring layer 142B may perform various functions according to its design. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. may be included. In this case, the signal (S) pattern may include various signal patterns (e.g., data signal patterns, etc.) in addition to the ground (GND) pattern, the power (PWR) pattern, etc. In addition, a via pad, etc. may be included.

[0064] The second via 143B may connect the built-in block 130 and the second wiring layer 142B. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used as materials for forming the second via 143B. The second via 143B may be completely filled with a conductive material, or may be formed by forming a conductive material along the wall of the via hole. In addition, the shape of the second via 143B may be all shapes known in the art, such as a conical shape, a cylindrical shape, etc.

[0065] The first build-up structure 150 may include an insulating layer 151, a wiring layer 152, and a via 153. Specifically, the first build-up structure 150 may include: a first insulating layer 151A disposed on the first insulating material 141A and covering the first wiring layer 142A; a third wiring layer 152A disposed on the first insulating layer 151A; a third via 153A penetrating the first insulating layer 151A and connecting the first wiring layer 142A and the third wiring layer 152A; a second insulating layer 151B disposed on the first insulating layer 151A and covering the third wiring layer 152A; a fourth wiring layer 152B disposed on the second insulating layer 151B; and a fourth via 153B penetrating the second insulating layer 151B and connecting the third wiring layer 152A and the fourth wiring layer 152B.

[0066] The structure of the first accumulation structure 150 is not limited thereto and may be changed within the range that can be designed by those skilled in the art. For example, the number of insulating layers, wiring layers and / or vias included in the first accumulation structure 150 may be more or less than the number shown in the drawings.

[0067] The material used to form each of the first insulating layer 151A and the second insulating layer 151B is not particularly limited, and any material can be used as long as the material has insulating properties. For example, a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material including a reinforcing material (such as inorganic filler and / or glass cloth, glass fabric, etc.) and a thermosetting resin or a thermoplastic resin (such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0068] Depending on the materials and processes of the first insulating layer 151A and the second insulating layer 151B, the boundary between the first insulating layer 151A and the second insulating layer 151B may be made indistinguishable. For example, the first insulating layer 151A and the second insulating layer 151B may be integrated with each other, or the boundary therebetween may be made unclear during the stacking process. Therefore, it may be difficult to visually determine the boundary between the first insulating layer 151A and the second insulating layer 151B of the finally produced electronic component-embedded substrate.

[0069] In addition, depending on the materials and processes of the first insulating layer 151A and the first insulating material 141A, the boundary between the first insulating layer 151A and the first insulating material 141A contacting the first insulating layer 151A may also be made indistinguishable. For example, the first insulating layer 151A and the first insulating material 141A may be integrated with each other during the lamination process, or the boundary therebetween may be made unclear during the stacking process. Therefore, it may be difficult to visually determine the boundary between the first insulating layer 151A and the first insulating material 141A of the finally produced electronic component-embedded substrate.

[0070] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used as materials for forming each of the third wiring layer 152A and the fourth wiring layer 152B. Each of the third wiring layer 152A and the fourth wiring layer 152B may perform various functions according to its design. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. may be included. In this case, the signal (S) pattern may include various signal patterns (e.g., data signal patterns, etc.) in addition to the ground (GND) pattern, the power (PWR) pattern, etc. In addition, a via pad, etc. may be included.

[0071] As a material for forming each of the third via hole 153A and the fourth via hole 153B, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, etc. can be used. Each of the third via hole 153A and the fourth via hole 153B can be completely filled with a conductive material, or can be formed by forming a conductive material along the wall of the via hole. When the via hole is a via hole in which a conductive material is formed along the wall of the via hole, an insulating material can fill the inside of the via hole. In addition, the shape of each of the third via hole 153A and the fourth via hole 153B can be any shape known in the art, such as a conical shape, a cylindrical shape, etc.

[0072] The second build-up structure 160 may include an insulating layer 161, a wiring layer 162, and a via 163. Specifically, the second build-up structure 160 may include: a third insulating layer 161A disposed on the second insulating material 141B and covering the second wiring layer 142B; a fifth wiring layer 162A disposed on the third insulating layer 161A; a fifth via 163A penetrating the third insulating layer 161A and connecting the second wiring layer 142B and the fifth wiring layer 162A; a fourth insulating layer 161B disposed on the third insulating layer 161A and covering the fifth wiring layer 162A; a sixth wiring layer 162B disposed on the fourth insulating layer 161B; and a sixth via 163B penetrating the fourth insulating layer 161B and connecting the fifth wiring layer 162A and the sixth wiring layer 162B.

[0073] The structure of the second accumulation structure 160 is not limited thereto and may be changed within the range that can be designed by those skilled in the art. For example, the number of insulating layers, wiring layers and / or vias included in the second accumulation structure 160 may be more or less than the number shown in the drawings.

[0074] The material used to form each of the third insulating layer 161A and the fourth insulating layer 161B is not particularly limited, and any material can be used as long as the material has insulating properties. For example, a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material including a reinforcing material (such as inorganic filler and / or glass cloth, glass fabric, etc.) and a thermosetting resin or a thermoplastic resin (such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0075] Depending on the materials and processes of the third insulating layer 161A and the fourth insulating layer 161B, the boundary between the third insulating layer 161A and the fourth insulating layer 161B may be made indistinguishable. For example, the third insulating layer 161A and the fourth insulating layer 161B may be integrated with each other, or the boundary therebetween may be made unclear during the stacking process. Therefore, it may be difficult to visually determine the boundary between the third insulating layer 161A and the fourth insulating layer 161B of the finally produced electronic component-embedded substrate.

[0076] In addition, depending on the materials and processes of the third insulating layer 161A and the second insulating material 141B, the boundary between the third insulating layer 161A and the second insulating material 141B contacting the third insulating layer 161A may also be made indistinguishable. For example, the third insulating layer 161A and the second insulating material 141B may be integrated with each other during the lamination process, or the boundary therebetween may be made unclear during the stacking process. Therefore, it may be difficult to visually determine the boundary between the third insulating layer 161A and the second insulating material 141B of the finally produced electronic component-embedded substrate.

[0077] Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. may be used as materials for forming each of the fifth wiring layer 162A and the sixth wiring layer 162B. Each of the fifth wiring layer 162A and the sixth wiring layer 162B may perform various functions according to its design. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. may be included. In this case, the signal (S) pattern may include various signal patterns (e.g., data signal patterns, etc.) in addition to the ground (GND) pattern, the power (PWR) pattern, etc. In addition, a via pad, etc. may be included.

[0078] As a material for forming each of the fifth via hole 163A and the sixth via hole 163B, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, etc. can be used. Each of the fifth via hole 163A and the sixth via hole 163B can be completely filled with a conductive material, or can be formed by forming a conductive material along the wall of the via hole. When the via hole is a via hole in which a conductive material is formed along the wall of the via hole, an insulating material can fill the inside of the via hole. In addition, the shape of each of the fifth via hole 163A and the sixth via hole 163B can be any shape known in the art, such as a conical shape, a cylindrical shape, etc.

[0079] The first passivation layer 170 and the second passivation layer 180 may protect the internal structure of the substrate 100A in which the electronic components are embedded from external physical or chemical damage, etc. Each of the first passivation layer 170 and the second passivation layer 180 may include a thermosetting resin and an inorganic filler. For example, each of the first passivation layer 170 and the second passivation layer 180 may be ABF. The present disclosure is not limited thereto, and the first passivation layer 170 and the second passivation layer 180 may be a known photosensitive insulating layer, for example, a solder resist (SR) layer.

[0080] The first passivation layer 170 and the second passivation layer 180 may include the same kind of material and may have substantially the same thickness as each other. However, the present disclosure is not limited thereto, and the first passivation layer 170 and the second passivation layer 180 may include different kinds of materials and may have different thicknesses from each other.

[0081] The first passivation layer 170 may have one or more openings (not shown) that expose at least a portion of the fourth wiring layer 152B of the first accumulation structure 150. In addition, the second passivation layer 180 may have one or more openings (not shown) that expose at least a portion of the sixth wiring layer 162B of the second accumulation structure 160. In these cases, a surface treatment layer may be formed on the exposed portion of each of the wiring layers 152B and 162B. The surface treatment layer may be formed by, for example, a gold plating process, a tin plating process, a silver plating process, a nickel plating process, etc. As needed, the openings of each of the first passivation layer 170 and the second passivation layer 180 may be formed as a plurality of via holes.

[0082] FIG. 4A to FIG. 4D A manufacturing process of the electronic component-embedded substrate 100A according to an exemplary embodiment is schematically illustrated.

[0083] Reference Figure 4A First, a first cavity 110HA and a second cavity 110HB may be formed on the first surface 110-1 and the second surface 110-2 of the core layer 110, respectively. The electronic component 120 and the built-in block 130 may be disposed in the first cavity 110HA and the second cavity 110HB, respectively.

[0084] In this case, the electronic component 120 and the built-in block 130 may be respectively disposed to be attached to the core layer 110 by adhesive members (not shown) for fixing the electronic component 120 and the built-in block 130 , respectively.

[0085] When the electronic component 120 disposed in the first cavity 110HA is provided as a plurality of electronic components 120 , the plurality of electronic components 120 in the first cavity 110HA may be disposed to be spaced apart from each other by a predetermined distance.

[0086] Each of the first cavity 110HA and the second cavity 110HB may be formed by a sandblasting process using abrasive particles, a dry etching process using plasma, mechanical drilling, laser drilling, etc. When each of the first cavity 110HA and the second cavity 110HB is formed using mechanical drilling and / or laser drilling, a desmear treatment process such as a permanganate process may be performed to remove resin smears in each of the first cavity 110HA and the second cavity 110HB.

[0087] Next, refer to Figure 4B , a first insulating material 141A and a second insulating material 141B may be formed respectively.

[0088] The first insulating material 141A may be formed to cover at least a portion of each of the side surface of the electronic component 120, the outermost surface of the electronic component 120 in the first direction, and the first surface 110-1 of the core layer 110, and may be formed to fill at least a portion of the first cavity 110HA. When the electronic component 120 disposed in the first cavity 110HA is provided in plurality, the first insulating material 141A may be formed to fill the space between the plurality of electronic components 120.

[0089] The second insulating material 141B may be formed to cover at least a portion of each of the side surface of the built-in block 130 , the outermost surface of the built-in block 130 in the second direction, and the second surface 110 - 2 of the core layer 110 , and may be formed to fill at least a portion of the second cavity 110HB.

[0090] Each of the first insulating material 141A and the second insulating material 141B may be formed by a known method. For example, each of the first insulating material 141A and the second insulating material 141B may be formed by a process including laminating its precursors by a known lamination process and then curing the laminated precursors, may be formed by a process including coating its precursors and then curing the coated precursors, or may be formed by other processes.

[0091] Next, refer to Figure 4C , a first via hole 143A penetrating through the first insulating material 141A and a second via hole 143B penetrating through the second insulating material 141B may be formed. In addition, a through via 113 penetrating through the first insulating material 141A, the core layer 110, the built-in block 130, and the second insulating material 141B may be formed. In addition, a first wiring layer 142A and a second wiring layer 142B may be formed on the first insulating material 141A and the second insulating material 141B, respectively.

[0092] Each of these structures can be formed by a known process. For example, these structures can be formed by forming a through via hole or a via hole using a photolithography process, mechanical drilling, laser drilling, etc., patterning using a dry film, etc., and then filling the via hole and the patterned space using a plating process, etc.

[0093] Next, refer to Figure 4D , a first accumulation structure 150 and a second accumulation structure 160 may be formed on the first insulating material 141A and the second insulating material 141B, respectively. The steps used in this process may be the same as those used in the embodiment of the present invention. FIG. 4B to FIG. 4C The steps are the same as described in .

[0094] Furthermore, as needed, a first passivation layer 170 and a second passivation layer 180 may be respectively formed on the first accumulation structure 150 and the second accumulation structure 160. Each of the first passivation layer 170 and the second passivation layer 180 may also be formed by a known process, for example, by a process including stacking precursors of each of the first passivation layer 170 and the second passivation layer 180 and then curing the stacked precursors, by a process including coating a material for forming each of the first passivation layer 170 and the second passivation layer 180 and then curing the coated material, or by other processes.

[0095] The manufacturing process of the electronic component embedded substrate 100A according to the exemplary embodiment is not limited to the above process and can be performed by those skilled in the art. For example, the order of manufacturing some components can be changed, the process of manufacturing some components can be deleted, and / or other processes can be added.

[0096] Figure 5 is a cross-sectional view schematically showing an electronic component-embedded substrate 100B according to another example.

[0097] Compared to the electronic component-embedded substrate 100A according to the exemplary embodiment, in the electronic component-embedded substrate 100B according to another example, the core layer 110 may include an insulating layer 111 and a resin layer 112 stacked in a thickness direction of the core layer 110. Specifically, the core layer 110 may include a plurality of insulating layers 111A, 111B, and 111C and a plurality of resin layers 112A and 112B stacked in a thickness direction of the core layer 110. In this case, each of the plurality of insulating layers 111A, 111B, and 111C may be thicker than each of the plurality of resin layers 112A and 112B.

[0098] More specifically, the core layer 110 may be a core layer in which the first insulating layer 111A, the first resin layer 112A, the second insulating layer 111B, the second resin layer 112B, and the third insulating layer 111C are stacked in a direction from the first direction to the second direction. Therefore, the first resin layer 112A may be disposed between the first insulating layer 111A and the second insulating layer 111B, and the second resin layer 112B may be disposed between the second insulating layer 111B and the third insulating layer 111C.

[0099] The first insulating layer 111A disposed on the outermost side in the first direction among the plurality of insulating layers 111A, 111B, and 111C may have a first cavity 110HA. The third insulating layer 111C disposed on the outermost side in the second direction among the plurality of insulating layers 111A, 111B, and 111C may have a second cavity 110HB. When the first direction is an upward direction and the second direction is a downward direction, the first insulating layer 111A disposed on the uppermost side among the plurality of insulating layers 111A, 111B, and 111C may have a first cavity 110HA. In addition, the third insulating layer 111C disposed on the lowermost side among the plurality of insulating layers 111A, 111B, and 111C may have a second cavity 110HB.

[0100] The structure of the core layer 110 is not limited thereto, and the core layer 110 may be changed by a person skilled in the art. For example, the number of insulating layers and / or resin layers included in the core layer 110 may be more or less than the number shown in the drawings. In addition, as needed, a person skilled in the art may describe the core layer 110 in different ways. For example, the core layer 110 may include only the second insulating layer 111B, and the first insulating layer 111A, the first insulating material 141A, and the first wiring layer 142A may be collectively referred to as an upper accumulation structure, or the first insulating layer 111A, the first insulating material 141A, the first wiring layer 142A, and the first accumulation structure 150 may be collectively referred to as an upper accumulation structure, and similarly, the third insulating layer 111C, the second insulating material 141B, the second wiring layer 142B may be collectively referred to as a lower accumulation structure, or the third insulating layer 111C, the second insulating material 141B, the second wiring layer 142B, and the second accumulation structure 160 may be collectively referred to as a lower accumulation structure. In this case, the electronic component 120 may be disposed in the upper build-up structure and connected to the first wiring layer 142A, the built-in block 130 may be disposed in the lower build-up structure, and the second insulating layer 111B may be located between the electronic component 120 in the upper build-up structure and the built-in block 130 in the lower build-up structure.

[0101] The material used to form each of the first insulating layer 111A, the second insulating layer 111B, and the third insulating layer 111C is not particularly limited, and any material can be used as long as the material has insulating properties. For example, a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide), or a material including a reinforcing material (such as an inorganic filler and / or glass cloth, glass fabric, etc.) and a thermosetting resin or a thermoplastic resin (such as a prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0102] Through the pressurized and heated pressing process, the first resin layer 112A may combine the first insulating layer 111A and the second insulating layer 111B together, and the second resin layer 112B may combine the second insulating layer 111B and the third insulating layer 111C together. In the pressing process, the first resin layer 112A and the second resin layer 112B may be in a semi-cured state.

[0103] The material used to form each of the first resin layer 112A and the second resin layer 112B is not particularly limited, and any material can be used as long as the material has insulating properties. For example, a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material including a reinforcing material (such as inorganic filler and / or glass cloth, glass fabric, etc.) and a thermosetting resin or a thermoplastic resin (such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, bismaleimide triazine (BT), etc.) can be used. If necessary, a photosensitive dielectric (PID) resin can be used.

[0104] Since other contents may be substantially the same as those described in the electronic component-embedded substrate 100A according to the exemplary embodiment, a detailed description thereof will be omitted.

[0105] Figure 6 1 is a cross-sectional view schematically illustrating an example of an electronic package in which a semiconductor package is mounted on an electronic component-embedded substrate 100A according to an exemplary embodiment.

[0106] Referring to the drawings, when the above-described electronic component-embedded substrate 100A according to an exemplary embodiment of the present disclosure is used, a semiconductor package 200 may be mounted on the electronic component-embedded substrate 100A through an electrical connection metal member 210. In this case, the embedded electronic component 120 may be electrically connected to a semiconductor chip (not shown) included in the semiconductor package 200 through a relatively short electrical path.

[0107] The semiconductor package 200 may be a package in which a semiconductor chip (not shown) is mounted on a separate interposer, but is not limited thereto.

[0108] The semiconductor chip (not shown) included in the semiconductor package 200 may be an application specific integrated circuit (ASIC) and / or a high bandwidth memory (HBM), but is not limited thereto.

[0109] The electrical connection metal member 210 may include a low melting point metal, for example, tin (Sn) or an alloy containing tin (Sn). More specifically, the electrical connection metal member 210 may be formed using solder, etc., but this is only illustrative, and the material of the electrical connection metal member 210 is not particularly limited thereto.

[0110] In addition, the electrical connection metal member 210 may be fixed by using an underfill resin, but is not limited thereto.

[0111] In addition, the electronic component embedded substrate 100A may be mounted on a main board (not shown) through a separate electrical connection metal member (not shown).

[0112] The term "connection" or "combination" in this specification may be not only a direct connection, but also a concept including an indirect connection through an adhesive layer or the like. In addition, the term "electrically connected" or "electrically connected" in this specification is a concept including both physical connection and physical disconnection. In addition, the expressions "first", "second", etc. in this specification are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, without departing from the spirit of the present disclosure, the "first" component may be referred to as the "second" component, and similarly, the "second" component may be referred to as the "first" component.

[0113] The expression "example" used in this specification does not refer to examples that are identical to each other, but may be provided to emphasize and explain different specific features. However, the above examples do not exclude that the above examples are implemented in combination with features of other examples. For example, unless otherwise described or contradicted with another example, the description in a specific example, although not described in another example, may also be understood as an explanation related to another example.

[0114] The terms used in the present disclosure are only used to illustrate various examples and are not intended to limit the inventive concept. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0115] As one effect of the present disclosure, an electronic component-embedded substrate having improved heat dissipation characteristics can be provided.

[0116] As another one of the various effects of the present disclosure, an electronic component-embedded substrate having improved warpage may be provided.

[0117] While examples have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A substrate embedded with electronic components, comprising: A core layer, having a first cavity and a second cavity on a first surface and a second surface of the core layer respectively, and the second surface is opposite to the first surface in a thickness direction of the core layer; an electronic component disposed in the first cavity; a first insulating material covering at least a portion of the electronic component; a first wiring layer disposed on the first insulating material and connected to the electronic component; a built-in block, disposed in the second cavity; as well as a second insulating material covering at least a portion of the built-in block, Wherein, in a projection plane of the substrate along the thickness direction, the built-in block has a portion that does not overlap with the electronic component in the thickness direction.

2. The electronic component embedded substrate according to claim 1, wherein: The first cavity penetrates a portion of the core layer from the first surface in the thickness direction, and The second cavity penetrates a portion of the core layer from the second surface in the thickness direction.

3. The electronic component embedded substrate according to claim 1, wherein: The built-in block is a copper block, and the electronic component includes an active component.

4. The electronic component embedded substrate according to claim 1, wherein: The core layer has a plurality of first cavities and a plurality of second cavities, One or more electronic components are disposed in each of the plurality of first cavities, and One or more built-in blocks are disposed in each of the plurality of second cavities.

5. The electronic component embedded substrate according to claim 4, wherein: The number of the one or more electronic components disposed in each of the plurality of first cavities is greater than the number of the one or more built-in blocks disposed in each of the plurality of second cavities.

6. The substrate with embedded electronic components according to claim 1, further comprising: A second wiring layer, disposed on the second insulating material; as well as A through via penetrates the core layer and the built-in block and connects the first wiring layer and the second wiring layer to each other. 7 . The electronic component embedded substrate according to claim 6 , further comprising a via hole penetrating the second insulating material and connecting the built-in block and the second wiring layer to each other.

8. The substrate embedded with electronic components according to claim 7, further comprising: a first build-up structure disposed on the first insulating material and comprising a third wiring layer connected to the first wiring layer; as well as A second build-up structure is disposed on the second insulating material and includes a fourth wiring layer connected to the second wiring layer.

9. The electronic component embedded substrate according to claim 1, wherein: The built-in block includes a thermally conductive material.

10. The electronic component embedded substrate according to claim 9, wherein: The built-in block includes copper.

11. The electronic component embedded substrate according to claim 1, wherein: The core layer includes a plurality of insulating layers stacked in the thickness direction of the core layer, An uppermost insulating layer among the plurality of insulating layers has the first cavity, and A lowermost insulating layer among the plurality of insulating layers has the second cavity.

12. The electronic component embedded substrate according to claim 11, wherein: The core layer further includes one or more resin layers, and the one or more resin layers are respectively disposed between adjacent insulating layers among the plurality of insulating layers.

13. The electronic component embedded substrate according to claim 12, wherein: Each of the plurality of insulating layers is thicker than each of the one or more resin layers.

14. The electronic component embedded substrate according to claim 1, wherein: The electronic component includes a chip-type passive component having electrodes. 15 . The electronic component embedded substrate according to claim 1 , further comprising a via hole penetrating the first insulating material and connecting the electronic component and the first wiring layer to each other.

16. The electronic component embedded substrate according to claim 1, wherein: A portion of the second insulating material is filled in the second cavity and is disposed between the second cavity and the built-in block in a direction perpendicular to the thickness direction.

17. An electronic package, comprising: A substrate with embedded electronic components according to any one of claims 1 to 16; as well as A semiconductor package is mounted on the substrate embedded with electronic components through at least one electrical connection metal piece, and the at least one electrical connection metal piece electrically connects the semiconductor package to the substrate embedded with electronic components.

18. A substrate embedded with electronic components, comprising: a first build-up structure including a first wiring layer; one or more electronic components disposed in the first build-up structure and connected to the first wiring layer; a second build-up structure including a second wiring layer and disposed on the first build-up structure; one or more built-in blocks disposed in the second accumulation structure; as well as an insulating layer arranged between the one or more electronic components in the first build-up structure and the one or more built-in blocks in the second build-up structure, Wherein, the substrate embedded with electronic components further includes: a through via penetrating the built-in block and the insulating layer and connecting the first wiring layer and the second wiring layer to each other.

19. The substrate with embedded electronic components according to claim 18, further comprising: a first resin layer disposed between the insulating layer and the one or more electronic components; as well as A second resin layer is disposed between the insulating layer and the one or more built-in blocks.

Images