Semiconductor package assembly and method of forming the same

Abstract

The present invention discloses a semiconductor package component, comprising: a semiconductor grain and a first memory grain, which are arranged on a first surface of a substrate, wherein the first memory grain comprises a first edge facing the semiconductor grain, and the semiconductor grain comprises: a peripheral region, having a second edge facing the first edge of the first memory grain and a third edge opposite to the second edge; and a circuit region, which is surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge, wherein the distance between the second edge and the fourth edge is a first distance, and the distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance. In this way, the distance between the semiconductor grain and the memory grain remains consistent with the previous distance, ensuring the structural stability of the package.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor packaging component and a forming method thereof. Background Art

[0002] Semiconductor packaging components can not only provide protection for semiconductor die from environmental pollutants, but also provide electrical connections between semiconductor die packaged in the semiconductor packaging component and a substrate (e.g., a printed circuit board (PCB)). For example, the semiconductor die can be packaged in a packaging material and electrically connected to the semiconductor die and the substrate with traces.

[0003] In advanced packaging technology, memory dies in a semiconductor package assembly can be packaged horizontally with semiconductor dies, and the semiconductor package assembly can provide electrical connections between the semiconductor dies and the memory dies. However, the problem with such semiconductor package assemblies is that there are many memory dies of different sizes on the market. Therefore, it is necessary to design different layouts for semiconductor package assemblies using memory dies of different sizes, which requires redesigning and manufacturing the previous substrate or intermediate layer, which may lead to an increase in the cost of manufacturing these semiconductor package assemblies.

[0004] Therefore, a novel semiconductor package assembly and a method of forming the same are desired to solve the above problems. Summary of the invention

[0005] In view of this, the present invention provides a semiconductor package structure to reduce the manufacturing cost of semiconductor package components using memory dies of different sizes.

[0006] According to a first aspect of the present invention, a semiconductor package assembly is disclosed, comprising:

[0007] A semiconductor die and a first memory die are disposed on a first surface of a substrate, wherein the first memory die comprises a first edge facing the semiconductor die, and the semiconductor die comprises:

[0008] a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite the second edge; and

[0009] a circuit area surrounded by the peripheral area, wherein the circuit area has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge,

[0010] The distance between the second edge and the fourth edge is a first distance, the distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

[0011] According to a second aspect of the present invention, a semiconductor package assembly is disclosed, comprising:

[0012] Semiconductor grains and memory grains are arranged on the first surface of the intermediate layer, wherein the semiconductor grains include:

[0013] a peripheral region having a first edge facing the memory die and a second edge opposite the first edge; and

[0014] a circuit region surrounded by the peripheral region, wherein the circuit region has a third edge adjacent to the memory die and a fourth edge opposite to the third edge,

[0015] wherein a first distance between the first edge and the third edge is different from a second distance between the second edge and the fourth edge,

[0016] The third distance between the first edge and the second edge is greater than the fourth distance between the third edge and the fourth edge.

[0017] According to a third aspect of the present invention, a semiconductor package assembly is disclosed. A semiconductor package assembly comprises:

[0018] A semiconductor die, a first memory die and a second memory die are disposed on a first surface of a substrate, wherein the first memory die and the second memory die are disposed at least on opposite sides of the semiconductor die, the first memory die includes a first edge facing the semiconductor die, the second memory die includes a second edge facing the semiconductor die, and the semiconductor die includes:

[0019] a peripheral region having a third edge facing the first edge of the first memory die and a fourth edge facing the second edge of the first memory die; and

[0020] a circuit area surrounded by the peripheral area, wherein the circuit area has a fifth edge adjacent to the third edge and a sixth edge adjacent to the fourth edge,

[0021] The distance between the third edge and the fifth edge is a first distance, the distance between the fourth edge and the sixth edge is a second distance, and the first distance is the same as or different from the second distance.

[0022] According to a fourth aspect of the present invention, a method for forming a semiconductor package assembly is disclosed, comprising:

[0023] performing a sawing process along a first scribe line of the wafer to separate a first circuit region from a second circuit region, wherein the first circuit region has a first edge, the second circuit region has a second edge, the first edge is adjacent to the second edge, and a first distance between the first edge and the first scribe line is different from a second distance between the second edge and the first scribe line;

[0024] After performing a sawing process, a semiconductor die having a first circuit region is formed; and

[0025] The semiconductor die and the first memory die are bonded to a first surface of a substrate.

[0026] According to a fifth aspect of the present invention, a method for forming a semiconductor package assembly is disclosed, comprising:

[0027] Performing a cutting process along a first scribe line of the wafer and performing a cutting process along a second scribe line of the wafer to separate a first circuit region from a second circuit region, wherein the first scribe line and the second scribe line are located between the first circuit region and the second circuit region; the first circuit region has a first edge, the second circuit region has a second edge, the first edge is adjacent to the second edge, and there is a first distance between the first edge and the first scribe line, and there is a second distance between the second edge and the first scribe line, and the first distance is the same as or different from the second distance;

[0028] After performing a sawing process, a semiconductor die having a first circuit region is formed; and

[0029] The semiconductor die, the first memory die and the second memory die are bonded to a first surface of a substrate.

[0030] There are many memory grains of different sizes on the market. In the prior art, if the size of the memory grain changes, the layout of the semiconductor package assembly needs to be changed accordingly, and the substrate needs to be redesigned and manufactured, which leads to an increase in the cost of manufacturing the semiconductor package assembly. However, in the semiconductor package structure provided by the present invention, since the first distance between the second edge and the fourth edge is different from the second distance between the third edge and the fifth edge, the cutting edges of the opposite sides of each semiconductor grain (i.e., the opposite sides of each circuit area) are different for memory grains of different sizes, so that the relative position of the circuit area of ​​the semiconductor grain on the substrate does not change. By adjusting the cutting margin, the distance between the semiconductor grain and the memory grain is kept consistent with the previous one, thereby ensuring the structural stability of the package. The present invention does not need to change the previous substrate design, and can use the previous substrate design. The relative positions of the circuit area of ​​the semiconductor grain and the circuit area of ​​the memory grain on the substrate do not change, and the distance between the semiconductor grain and the memory grain still meets the regulations, so there is no extra time and extra cost spent on redesigning the substrate. Compared with redesigning the substrate, a large amount of time and cost is saved, the manufacturing cost of semiconductor packaging components using memory grains of different sizes is reduced, and production efficiency is improved.

[0031] These and other objects of the present invention will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments which is illustrated in the various drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a cross-sectional view of a semiconductor package assembly according to some embodiments of the present invention;

[0033] Figure 2 is a top view of a wafer according to some embodiments of the present invention, illustrating a method for forming semiconductor grains;

[0034] Figure 3A is a top view of a semiconductor package assembly for comparison;

[0035] Figure 3B is a top view of a semiconductor package assembly according to some embodiments of the present invention, Figure 1 It is along Figure 3B A cross-sectional view of the semiconductor package assembly taken along the dashed line 1-1';

[0036] Figure 3C is a top view of a semiconductor package assembly according to some other embodiments of the present invention;

[0037] Figure 4A is a top view of a semiconductor package assembly for comparison;

[0038] Figure 4B is a top view of a semiconductor package assembly according to some embodiments of the present invention;

[0039] Figure 4C is a top view of a semiconductor package assembly according to some other embodiments of the present invention;

[0040] Figure 5 is a top view of a wafer according to some other embodiments of the present invention, illustrating a method for forming semiconductor grains;

[0041] Fig. 6A is a top view of a semiconductor package assembly according to some embodiments of the present invention;

[0042] Figure 6B is a top view of a semiconductor package assembly according to some other embodiments of the present invention;

[0043] Figure 6C 1 is a top view of a semiconductor package assembly according to some other embodiments of the present invention. DETAILED DESCRIPTION

[0044] Specific terms are used throughout the specification and the claims that follow to refer to specific components. As those skilled in the art will appreciate, manufacturers may refer to components by different names. This document is not intended to distinguish between components that have different names but the same function. In the following specification and claims, the terms "include" and "comprising" are used in an open-ended manner and should be interpreted to mean "including, but not limited to...". In addition, the term "coupled" is intended to mean an indirect or direct electrical connection. Therefore, if one device is coupled to another device, the connection may be a direct electrical connection, or an indirect electrical connection via other devices and connections.

[0045] The following description is the best contemplated mode of implementing the present invention. This description is intended to illustrate the general principles of the present invention and is not intended to limit the present invention. The scope of the present invention is determined by the appended claims.

[0046] The present invention will be described below with reference to specific embodiments and with reference to certain drawings, but the invention is not limited thereto and is limited only by the claims. The drawings described are only schematic and non-restrictive. In the drawings, for the purpose of illustration, the size of some elements may be exaggerated and not drawn to scale. In the practice of the present invention, the size and relative size do not correspond to the actual size.

[0047] Figure 11 is a cross-sectional view of a semiconductor package assembly 100b according to some embodiments of the present invention. The semiconductor package structure 100b may have other additional features / devices. For different embodiments, some of the features described below may be replaced or removed. Figure 1 Only a portion of the semiconductor package assembly 100b is depicted in FIG. In some embodiments, the semiconductor package assembly 100b may include a wafer-level semiconductor package. In addition, the semiconductor package assembly 100b may be a flip-chip semiconductor package.

[0048] Reference Figure 1 , the semiconductor package component 100b includes a substrate 107. The substrate 107 may be a printed circuit board (PCB) and may be formed of polypropylene (PP). It should also be noted that the substrate 107 may be a single-layer or multi-layer structure, and the substrate 107 may include a redistribution layer (RDL) structure 105 in the substrate 107. The substrate 107 has a first surface 107a and a second surface 107b opposite to the first surface 107a. A plurality of conductive pads 109 are disposed on the first surface 107a, and a plurality of conductive pads 103 are disposed on the second surface 107b. In some embodiments, the conductive pads 103 and the conductive pads 109 may be conductive traces, and the conductive traces may include a power segment, a signal trace segment, or / and a ground trace segment. The conductive pads 103 and the conductive pads 109 are used for input / output (I / O) connections of the semiconductor package component 100b.

[0049] In addition, the semiconductor package assembly 100b includes a plurality of conductive structures 111 bonded to a first surface 107a of a substrate 107 and a plurality of conductive structures 101 bonded to a second surface 107b of the substrate 107. The conductive pads 103 are disposed between the conductive structures 101 and the substrate 107, and the conductive pads 109 are disposed between the conductive structures 111 and the substrate 107. In some embodiments, the conductive structure 101 may be a conductive ball structure, such as a ball grid array (BGA), a conductive pillar structure, or a conductive paste structure, and the conductive structure 111 may be a controlled collapse chip connection (C4) structure, a ball grid array, a conductive pillar structure, or a conductive paste structure.

[0050] like Figure 1 As shown, the semiconductor package assembly 100b includes a substrate 121. From a top view, the size of the substrate 121 can be smaller than the size of the base 107, so as to adopt a fan-out packaging structure, facilitate the arrangement of more conductive structures 101 on the substrate, and facilitate the installation and connection of the semiconductor package assembly. The substrate 121 has a first surface 121a and a second surface 121b opposite thereto, and the semiconductor package assembly 100b also includes a plurality of conductive vias 119 penetrating from the first surface 121a of the substrate 121 to the second surface 121b of the substrate 121. In some embodiments, the substrate 121 can be an interposer, and the conductive vias 119 can be through interposer vias (TIVs). The interposer can be made of inorganic materials, and the interposer can have a higher circuit and wiring density, so as to facilitate wiring and improve the package integration. The interposer can also facilitate the manufacture of semiconductor packages and improve production efficiency. The substrate can be made of organic materials, and the substrate can be, for example, a PCB (Printed Circuit Board).

[0051] However, the embodiments of the present invention are not limited thereto. In some other embodiments, the substrate 121 may have a wiring structure in the substrate 121. For example, the wiring structure in the substrate 121 may be a fan-out structure and may include one or more conductive pads, conductive vias, conductive layers, and conductive pillars. In this case, the wiring structure in the substrate 121 may be disposed in one or more inter-metal dielectric (IMD) layers. In some embodiments, the IMD layer may be formed of an organic material including a polymer base material, or may be formed of an inorganic material including silicon nitride (SiNx), silicon oxide (SiOx), graphene, and the like. For example, the IMD layer is made of a polymer base material. It should be noted that the number and configuration of the IMD layer, conductive pads, conductive vias, conductive layers, and conductive pillars described in this embodiment are only some examples and are not limitations of the present invention.

[0052] In addition, the passivation layer 115 is disposed on the second surface 121b of the substrate 121, and the passivation layer 115 is penetrated by the conductive via 119. In some embodiments, a plurality of under-bump metallurgy (UBM) layers 113 are inserted between the conductive structure 111 and the passivation layer 115. The substrate 121 is electrically connected to the base 107 through the UBM layer 113, the conductive structure 111 and the conductive pad 109. Each UBM layer 113 may include one or more layers, such as a barrier layer and a seed layer. As an example, the UBM layer 113 described in the present invention includes a single layer (e.g., a single layer of barrier layer or seed layer). In addition, the conductive structure 111 is surrounded by a bottom fill layer 117, and the bottom fill layer 117 is located between the first surface 107a of the substrate 107 and the passivation layer 115. In addition, the size of the base 107 is larger than that of the substrate 121, so the size of the bottom filling layer 117 close to the substrate 121 is smaller, and the size of the bottom filling layer 117 close to the substrate 107 is larger. In this way, a fan-out packaging structure can be adopted, which facilitates the arrangement of more conductive structures 101 on the substrate, facilitates the installation and connection of semiconductor packaging components, and also maintains the structural stability of the bottom filling layer 117 and the packaging components.

[0053] Still reference Figure 1 The semiconductor package assembly 100b includes a plurality of conductive pads 123 and a dielectric layer 125 disposed on the first surface 121a of the substrate 121. In some embodiments, the dielectric layer 125 extends on the conductive pads 123, and a portion of the conductive pads 123 is exposed by the dielectric layer 125.

[0054] In addition, the semiconductor package assembly 100b further includes a semiconductor die 144b and a memory die 150b. The semiconductor die 144b and the memory die 150b are bonded to the first surface 121a of the substrate 121 (e.g., connected to the conductive pad 123) through a plurality of conductive structures 127. In some embodiments, the semiconductor die 144b may be a system-on-chip (SOC), such as a logic die, including a central processing unit (CPU), a graphics processing unit (GPU), or any combination thereof. In some embodiments, the memory die 150b may be a hybrid dynamic random access memory (DRAM) die, such as a high bandwidth memory (HBM) die.

[0055] In some embodiments, the semiconductor die 144b and the memory die 150b each have a plurality of conductive pads 133 and a dielectric layer 131 thereon, the conductive pads 133 and the dielectric layer 131 may face the first surface 121a of the substrate 121, the dielectric layer 131 extends on the conductive pads 133, and a portion of the conductive pads 133 is exposed by the dielectric layer 131. The semiconductor die 144b and the memory die 150b are electrically connected to the substrate 121 through the conductive pads 133, the conductive structure 127, and the conductive pads 123. In some embodiments, the conductive structure 127 is surrounded by an underfill layer 129, and the underfill layer 129 is interposed between the semiconductor die 144b, the memory die 150b, and the dielectric layer 125 on the first surface 121a of the substrate 121.

[0056] It should be noted that the semiconductor grain 144b and the memory grain 150b are separated by a portion of the bottom filling layer 129, and there is a distance D1 between the semiconductor grain 144b and the memory grain 150b. The distance between the semiconductor grain 144b and the memory grain 150b is generally constant. In addition, the distance D1 can be specified as a specific value, such as 50 mm, 60 mm or 70 mm. Of course, the distance D1 can also be specified to be within a certain range, for example, the distance D1 can be between 50 mm and 70 mm, so the distance D1 can use the minimum distance, such as 50 mm, and of course other values ​​that meet the requirements can also be used. In the manufacture of semiconductor packaging components, the value of the distance D1 generally needs to comply with regulations (for example, a specific value mentioned above or within a specified range). This is because if D1 is too small, it may cause interference or collision between the semiconductor grains and / or memory grains during assembly, and may also cause changes in the degree of package warping and affect the stability of the process and structure. If D1 is too large, it may cause the semiconductor package to be easily warped, affecting the structural stability of the package. Therefore, it is necessary to reasonably set the distance D1 in the design, and layout the semiconductor grains and memory grains according to the distance D1 of the design. In addition, for example, there is also a bottom filling layer 129 in the gap D1 between the semiconductor grain 144b and the memory grain 150b. In addition, from a top-down perspective, the size of the substrate 121 is relatively large, and the size of the semiconductor grain 144b, the memory grain 150b and the bottom filling layer 129 therebetween is relatively small after the combination, so part of the substrate 121 can be seen from a top-down perspective (when the dielectric layer 125 is not provided). In this embodiment, the dielectric layer 125 can cover the entire first surface 121a, so a molding compound 135 can be provided on the dielectric layer 125. The bottom filling layer 129, the semiconductor grain 144b and the memory grain 150b are surrounded by the molding compound 135. That is, as Figure 1As shown, the edges of the semiconductor die 144b and the memory die 150b that are away from each other are covered by the molding compound 135. Of course, the other edges of the semiconductor die 144b and the memory die 150b may also be covered by the molding compound 135. Specifically, the semiconductor die 144b may have edges on four sides, wherein the edge of the semiconductor die 144b facing the memory die 150b may be covered by the bottom filling layer 129, and the edges of the remaining three sides may be covered by the molding compound 135. Similarly, the memory die 150b may have edges on four sides, wherein the edge of the memory die 150b facing the semiconductor die 144b may be covered by the bottom filling layer 129, and the edges of the remaining three sides may be covered by the molding compound 135. In addition, the molding compound 135 and / or the bottom filling layer 129 may be flush with the semiconductor die 144b and the memory die 150b, or the molding compound 135 and / or the bottom filling layer 129 may be shorter or taller than the semiconductor die 144b and the memory die 150b. In this embodiment, the upper surface of the semiconductor die 144b and the memory die 150b is coplanar with the upper surface of the molding compound 135 and the bottom filling layer 129, that is, the molding compound 135 and the bottom filling layer 129 may not cover the upper surface of the semiconductor die 144b and the memory die 150b, and a cover structure may be provided on the upper surface of the semiconductor die 144b and the memory die 150b to increase the mechanical strength of the semiconductor package assembly and prevent the semiconductor package assembly from warping, and a heat sink may also be provided on the upper surface of the semiconductor die 144b and the memory die 150b to help dissipate heat from the semiconductor die 144b and the memory die 150b and other components. The heat sink may be in direct contact with the upper surface of the semiconductor grain 144b and the memory grain 150b, or in contact with the upper surface of the semiconductor grain 144b and the memory grain 150b through a thermal interface material layer. Of course, the heat sink may be separated from the semiconductor grain 144b and the memory grain 150b by a cover structure. Of course, in other embodiments, the molding compound 135 and / or the bottom filling layer 129 may also cover the upper surface of the semiconductor grain 144b and / or the memory grain 150b. In addition, the size of the substrate 121 is larger than the size of the semiconductor grain 144b, the memory grain 150b and the bottom filling layer 129 therebetween. Therefore, the size of the bottom filling layer 129 close to the semiconductor grain 144b and the memory grain 150b is smaller, while the size of the side close to the substrate 121 is larger, so as to adopt a fan-out packaging structure, facilitate the arrangement of more conductive structures 101 on the substrate, facilitate the installation and connection of the semiconductor packaging component, and also maintain the structural stability of the bottom filling layer 129 and the packaging component. In addition, from a top view, the outer dimensions of the molding material 135 may be the same as the dimensions of the substrate 121 , or the molding material may be thicker to protect the semiconductor die 144 b and the memory die 150 b and maintain the structural stability of the package assembly.

[0057] In some embodiments, the molding compound 135 may be formed of a non-conductive material, such as an epoxy, a resin, a moldable polymer, etc. The molding compound 135 may be applied while being substantially liquid and may then be cured by a chemical reaction, such as in an epoxy or a resin.

[0058] Figure 2 is a top view of a wafer 200 illustrating a method for forming semiconductor dies according to some embodiments of the present invention.

[0059] Since there are many memory dies of different sizes on the market, it is necessary to design different layouts for semiconductor package components using memory dies of different sizes, which may lead to an increase in the cost of manufacturing these semiconductor package components. To solve this problem, the cutting process performed on the wafer to form the semiconductor dies can be modified. Specifically, the position of the scribe line on the wafer can be adjusted so that the cutting margins of the opposite sides of each semiconductor die (i.e., the opposite sides of each circuit area) are different.

[0060] like Figure 2 As shown, in order to simplify the diagram, only two adjacent circuit regions 1421 and 1422 on the wafer 200 and three groups of scribe lines S1, S2 and S3 are depicted. Figure 2 After the wafer 200 is cut, semiconductor grains can be obtained, such as Figure 1 The semiconductor crystal grain 144b shown in FIG. 144b; and then the obtained semiconductor crystal grain is mounted on a substrate or an intermediate layer, for example, mounted on Figure 1 On the substrate 121 shown; thereby obtaining Figure 1 The structure shown. The two dotted lines included in each group of scribe lines correspond to the two sides of the tool (e.g., a cutting knife) for performing cutting. Generally, the same or same model of cutting tool can be used. For example, the width of the cutting knife for performing three cuts is equal, so the width of each group of scribe lines can be equal. Of course, different widths can also be used, that is, the width of each group of scribe lines can be different. In addition, the three groups of scribe lines S1, S2, and S3 are parallel to each other. Scribe lines S1 and S2 are located on opposite sides of circuit area 1421, scribe lines S1 and S3 are located on opposite sides of circuit area 1422, and scribe line S1 is located between circuit areas 1421 and 1422. In addition, for the three groups of scribe lines S1, S2, and S3, generally, after cutting along one scribe line, cutting along another scribe line is performed, for example, first cutting along scribe line S1, then cutting along scribe line S2, and then cutting along scribe line S3. Of course, the order of cutting can be freely changed, for example, first cutting along scribe line S2, and then cutting along scribe lines S3 and S1.

[0061] In some embodiments, scribe lines S1, S2, and S3 have the same width K. Circuit region 1421 has a first edge E1 adjacent to scribe line S1, and circuit region 1422 has a second edge E2 adjacent to scribe line S1. A third edge E3 of circuit region 1421 opposite to first edge E1 is adjacent to scribe line S2, and a fourth edge E4 of circuit region 1422 opposite to second edge E2 is adjacent to scribe line S3.

[0062] It should be noted that there is a distance D2 between the first edge E1 and the scribe line S1, a distance D3 between the second edge E2 and the scribe line S1, and the distance D2 is not equal to the distance D3, for example, the distance D2 is greater than or less than the distance D3. Of course, the distances D2 and D3 can also be equal, which can be adaptively adjusted according to the size of the memory die used. In addition, there is a distance D3 between the third edge E3 and the scribe line S2, and there is a distance D2 between the fourth edge E4 and the scribe line S3.

[0063] The area between the first edge E1 and the scribe line S1 and the area between the third edge E3 and the scribe line S2 are semiconductor grains (eg, Figure 1 The area between the second edge E2 and the scribe line S1 and the fourth edge E4 and the scribe line S3 is a semiconductor crystal grain (eg, Figure 1 The cutting allowance of the semiconductor grain 144b in the embodiment of the present invention is as follows.

[0064] After the cutting process is performed, the circuit area 1421 is separated from the circuit area 1422 (that is, they belong to two different semiconductor dies respectively). The circuit area 1421 and the peripheral area of ​​the wafer 200 surrounding the circuit area 1421 (that is, the cutting margin) constitute a semiconductor die, and the circuit area 1422 and the peripheral area of ​​the wafer 200 surrounding the circuit area 1422 (that is, the cutting margin) constitute another semiconductor die. In some embodiments, there is no circuit in the peripheral area, and they are used to form the cutting margin of the semiconductor die. For example, the peripheral area is a molding compound, which is filled between the semiconductor die and is cut during the cutting process, so that the circuit area can be protected not only during the cutting process but also after cutting. In addition, as Figure 2 As shown, the present embodiment shows the scribing lines cut in the length direction of the circuit regions 1421 and 1422. For the cutting in the width direction, the distance between the scribing lines and the width edge can be set according to actual needs. For example, the distance between the width edge of all circuit regions and the scribing lines can be equal, or the scribing lines can be made in the width direction in the manner of the prior art. In addition, Figure 2The marking lines in the length direction are taken as an example. The marking lines in the width direction can also be applied in this embodiment. For example, the distances between the edges in the two width directions and their respective marking lines are D2 and D3 respectively, and D2 and D3 are not equal. For example, D2 is greater than or less than D3, etc., so that the cutting allowances on the opposite sides of the width of the obtained semiconductor grain are not equal.

[0065] like Figure 1 As shown, a semiconductor die having a circuit region 1421 (ie, as Figure 2 The semiconductor die having the circuit region 1421 and the peripheral region of the wafer 200 surrounding the circuit region 1421 (i.e., the cutting margin) constitutes a semiconductor die) and the semiconductor die having the circuit region 1422 can be packaged horizontally with the memory die 150b. That is, the semiconductor die having the circuit region 1421 and the semiconductor die having the circuit region 1422 can be packaged horizontally with the memory die 150b. Figure 1 It should be noted that the circuit regions 1421 and 1422 are completely surrounded by the peripheral region, and the outer edge of the peripheral region is the physical edge of the semiconductor die and is covered by the molding compound 135. The physical edge refers to the edge of a real object, and the edge of the circuit region, for example, can be an artificially divided edge, not a physical separation.

[0066] Figure 3A is a top view of a semiconductor package assembly 100 a for comparison. Figure 3B is a top view of a semiconductor package assembly 100b according to some embodiments of the present invention, Figure 1 It is along Figure 3B 1 - 1 ′ is a cross-sectional view of the semiconductor package assembly 100 b . Figure 3C FIG. 1 is a top view of a semiconductor package assembly 100c according to some other embodiments of the present invention. Figure 3A , each of the illustrations in FIGS. 3B and 3C only shows one semiconductor die and two memory die on the substrate 121 .

[0067] like Figure 3A As shown, the semiconductor package assembly 100a for comparison includes two memory dies 150a and one semiconductor die 144a disposed on a substrate 121. The memory dies 150a, the semiconductor die 144a and the substrate 121 are similar to those previously described with reference to FIG. Figure 1 The memory grains 150b, semiconductor grains 144b and substrate 121 described are similar or identical and are not repeated for brevity. In addition, the two memory grains 150a have the same width W3. The lengths of the two memory grains 150a may be the same or different.

[0068] The semiconductor die 144a may be composed of a circuit region 142 and a peripheral region 140a surrounding the circuit region 142. The two memory die 150a have edges 151a and 152a, respectively. The semiconductor die 144a has an edge 145a facing the edges 151a and 152a of the memory die 150a, and an edge 146a opposite to the edge 145a. The edges 145a and 146a of the semiconductor die 144a are physical edges, and they are also part of the outer edge of the peripheral region 140a.

[0069] In addition, the circuit region 142 has an edge 147a adjacent to the edge 145a and an edge 148a opposite to the edge 147a. The edge 148a of the circuit region 142 is adjacent to the edge 146a of the peripheral region 140a. In other words, the edges 147a and 148a are part of the interface between the circuit region 142 and the peripheral region 140a. There is a distance between the edge 145a and the edge 146a, which is defined as the width W1 of the semiconductor grain 144a. There is a distance between the edge 147a and the edge 148a, which is defined as the width W2 of the circuit region 142. The width W1 is greater than the width W2, and the position of the width W2 is completely covered by the position of the width W1.

[0070] In this embodiment, the distance D1 is between the edge 151a of the memory die 150a and the edge 145a of the semiconductor die 144a, which is consistent with Figure 1 It should be noted that there is a distance D2a between edge 145a and edge 147a, and a distance D3a between edge 146a and edge 148a, and that distance D2a is equal to distance D3a because the cutting process for forming semiconductor grain 144a is not the same as Figure 2 That is, the circuit region 142 is located at the center of the semiconductor die 144a. Of course, the other two edges of the circuit region 142 and the two edges of the corresponding peripheral region 140a may also have distances therebetween, and these two distances may be equal.

[0071] However, there are many memory chips of different sizes on the market. In the prior art, if the size of the memory chip 150a changes (for example, the width W3 of the memory chip 150a changes), the layout of the semiconductor package component 100a needs to be changed accordingly, and the substrate needs to be redesigned and manufactured, which leads to an increase in the cost of manufacturing the semiconductor package component 100a.

[0072] In order to solve the above problems, a method is provided by Figure 2 The semiconductor grains 144b (eg, Figure 1 or Figure 3B See Figure 3B, two memory dies 150b and one semiconductor die 144b are disposed on a substrate 121 of a semiconductor package assembly 100b, wherein the size of the memory die 150b is smaller than Figure 3A The size of the memory die 150a.

[0073] Specifically, the two memory dies 150b have the same width W4, and the width W4 may be smaller than Figure 3A In addition, the length of the memory chip 150b can be Figure 3A The lengths of the memory grains 150a in the peripheral region 140b are equal. The two memory grains 150b have edges 151b and 152b, respectively. The semiconductor grain 144b has an edge 145b facing the edges 151b and 152b of the memory grain 150b and an edge 146b opposite to the edge 145b. The distance D1 between the edge 151b and the edge 145b of the peripheral region 140b is the same as the distance D1 between the edge 152b and the edge 145b of the peripheral region 140b.

[0074] In this embodiment, the distance D1 between the memory die 150b and the semiconductor die 144b may be Figure 3A The distance D1 between the memory die 150 a and the semiconductor die 144 a is the same. As described above, maintaining the distance D1 can reduce warpage and prevent reliability issues of the semiconductor package assembly.

[0075] In addition, the circuit region 142 has an edge 147b adjacent to the edge 145b and an edge 148b opposite to the edge 147b. The edge 148b of the circuit region 142 is adjacent to the edge 146b of the peripheral region 140b. In other words, the edges 147b and 148b are part of the interface between the circuit region 142 and the peripheral region 140b.

[0076] There is a distance between edge 145b and edge 146b, which is defined as width W1 of semiconductor grain 144b. There is a distance between edge 147b and edge 148b, which is defined as width W2 of circuit region 142. Width W1 is greater than width W2, and the position of width W2 is completely covered by the position of width W2. Figure 3B The width W1 and Figure 3A The width W1 is the same as Figure 3B The width W2 is Figure 3A The width W2 is the same. However, Figure 3B The location of the circuit region 142 is different from Figure 3A The location of the circuit area 142.

[0077] Still reference Figure 3B, the distance D2b between edge 145b and edge 147b, and the distance D3b between edge 146b and edge 148b. Figure 3A In the same layout of the semiconductor package assembly 100a in FIG. 1 (i.e., the semiconductor die and the memory die are mounted on the same substrate or intermediate layer), the distance D2b between the edge 145b and the edge 147b can be greater than the distance D3b between the edge 146b and the edge 148b. It should be noted that the semiconductor die 144b can be Figure 2 The circuit region 142 is formed by the cutting process in the circuit region 142. Therefore, the cutting edges on the opposite sides of the circuit region 142 are different. In other words, the circuit region 142 is not located at the center of the semiconductor crystal grain 144b. In addition, the remaining two edges of the circuit region 142 and the two edges of the corresponding peripheral region 140b may also have distances, respectively, and these two distances may be equal or unequal. In other words, the circuit region 142 may not be located at the center of the semiconductor crystal grain 144b in the up-down direction, and may be located or not located at the center of the semiconductor crystal grain 144b in the left-right direction.

[0078] Typically, the positions reserved for mounting semiconductor die and memory die on a substrate (e.g., substrate 121) or an intermediate layer are fixed, such as the reserved solder joint positions, wiring positions, etc., so the relative positions of the circuit area of ​​the semiconductor die (e.g., circuit area 142) and the circuit area of ​​the memory die on the substrate or intermediate layer are fixed and cannot be moved. There are many different sizes of memory die on the market, such as Figure 3A The memory grain 150a in has a width W3, Figure 3B The memory grain 150b in the embodiment has a width W4 (W4 is smaller than W3). Figure 3B The memory die 150b is mounted to Figure 3AIn the prior art, when the size (such as width) of the memory grain changes, the layout design of the previous substrate or the intermediate layer may not be used. In order to adapt to the size of different memory grains, it is necessary to change the layout design of the previous substrate or the intermediate layer to meet the layout of the size of the corresponding memory grain, which not only greatly increases the design and manufacturing costs, but also reduces production efficiency and delays the construction period. The solution of the present invention can solve the above problems. Specifically, the width W4 of the memory grain 150b is smaller than the width W3 of the memory grain 150a, and the larger distance D2b between the physical edge 145b of the semiconductor grain 144b and the edge 147b of the circuit area 142 is set to be closer to the memory grain 150b than the smaller distance D3b between the edge 146b of the semiconductor grain 144b and the edge 148b of the circuit area 142. In this way, the relative position of the circuit area 142 of the semiconductor die 144b on the substrate 121 does not change, and by leaving a larger cutting margin (the cutting margin corresponding to D2b), the distance between the entire semiconductor die 144b and the memory die 150b can still be maintained at the distance D1. Therefore, the layout of the semiconductor package component 100b can be similar to that of the semiconductor package component 100a (such as Figure 3A ) are the same. Specifically, the present invention is for memory grains of different sizes. The cutting edges of the opposite sides of each semiconductor grain (i.e., the opposite sides of each circuit area) are different. The present invention does not need to change the previous substrate design and can use the previous substrate design. The relative positions of the circuit area of ​​the semiconductor grain and the circuit area of ​​the memory grain on the substrate do not change, and the distance between the semiconductor grain and the memory grain still meets the regulations, so there is no extra time and extra cost spent on redesigning the substrate. Compared with redesigning the substrate, a lot of time and cost are saved, and production efficiency is improved. It should also be noted that the relative position of the circuit area of ​​the memory grain on the substrate 121 does not change. In addition, in the present invention, the value obtained by subtracting D2a from D2b can be equal to the value obtained by subtracting W4 from W3, so that the cutting margin in the cutting process can be adjusted according to the change in the size of the memory grain. In addition, as Figure 3A, 3B, 3C, the widths of semiconductor grains 144a, 144b, 144c can be the same, that is, they are all equal to W1, and the cutting position can be adjusted based on the width W1 during cutting. In addition, if the width of the memory grain is too small or too large, exceeding the adjustable range for semiconductor grain cutting (that is, it is impossible to cut out a semiconductor grain that meets the circuit area installation position requirements and the distance D1 requirements), it is necessary to replace the memory grain that meets the size requirements, so as to facilitate the cutting of the semiconductor grain. Of course, when the size of the memory grain changes, the present invention provides a possible method without changing the substrate or intermediate layer design to provide more solutions.

[0079] In some other embodiments, such as Figure 3C As shown, two memory grains 150c are provided, and the size of the memory grain 150c is larger than Figure 3A The electrical connections between the memory grain 150c, the semiconductor grain 144c and the substrate 121 are similar to those previously described with reference to Figure 1 The electrical connections of the memory die 150 b , the semiconductor die 144 b and the substrate 121 are similar or identical and will not be repeated for the sake of brevity.

[0080] Specifically, the two memory dies 150c have the same width W5, and the width W5 may be greater than Figure 3A The two memory grains 150c have edges 151c and 152c, respectively. The semiconductor grain 144c has an edge 145c facing the edges 151c and 152c of the memory grain 150c and an edge 146c opposite to the edge 145c. The distance D1 between the edge 151c and the edge 145c of the peripheral region 140c is the same as the distance D1 between the edge 152c and the edge 145c of the peripheral region 140c.

[0081] In this embodiment, the distance D1 between the memory die 150c and the semiconductor die 144c may be Figure 3A The distance D1 between the memory die 150a and the semiconductor die 144a is the same, as described above, which can reduce warpage and prevent reliability issues of the semiconductor package assembly.

[0082] As mentioned above, in order to use Figure 3A In the same layout of the semiconductor package assembly 100a in FIG. 1 (i.e., the semiconductor die and the memory die are mounted on the same substrate or intermediate layer), the distance D2c between the edge 145c and the edge 147c can be smaller than the distance D3c between the edge 146c and the edge 148c. It should be noted that the semiconductor die 144c can be Figure 2The circuit region 142 is formed by the cutting process shown. Therefore, the cutting edges on the opposite sides of the circuit region 142 are different. In other words, the circuit region 142 is not located at the center of the semiconductor crystal grain 144c. In addition, the remaining two edges of the circuit region 142 and the two edges of the corresponding peripheral region 140b may also have distances respectively, and these two distances may be equal or unequal. In other words, the circuit region 142 may not be located at the center of the semiconductor crystal grain 144b in the up-down direction, and may be located or not located at the center of the semiconductor crystal grain 144b in the left-right direction.

[0083] Typically, the positions reserved for mounting semiconductor die and memory die on a substrate (e.g., substrate 121) or an intermediate layer are fixed, such as the reserved solder joint positions, wiring positions, etc., so the relative positions of the circuit area of ​​the semiconductor die (e.g., circuit area 142) and the circuit area of ​​the memory die on the substrate or intermediate layer are fixed and cannot be moved. There are many different sizes of memory die on the market, such as Figure 3A The memory grain 150a in has a width W3, Figure 3C The memory grain 150c in the embodiment has a width W5 (W5 is greater than W3). Figure 3C The memory die 150b is mounted to Figure 3AIn the prior art, when the size (such as width) of the memory grain changes, the layout design of the previous substrate or the intermediate layer may not be used. In order to adapt to the size of different memory grains, it is necessary to change the layout design of the previous substrate or the intermediate layer to meet the layout of the size of the corresponding memory grain, which not only greatly increases the design and manufacturing costs, but also reduces the production efficiency and delays the construction period. The solution of the present invention can solve the above problems. Specifically, the width W5 of the memory grain 150c is greater than the width W3 of the memory grain 150a, and the smaller distance D2c between the physical edge 145c of the semiconductor grain 144c and the edge 147c of the circuit area 142 is set to be closer to the memory grain 150c than the larger distance D3c between the edge 146c of the semiconductor grain 144c and the edge 148c of the circuit area 142. Thus, the relative position of the circuit region 142 of the semiconductor die 144c on the substrate 121 does not change, and by leaving a smaller cutting margin (the cutting margin corresponding to D2c), the distance between the entire semiconductor die 144b and the memory die 150b can still be maintained at the distance D1. Therefore, the layout of the semiconductor package component 100c can be similar to that of the semiconductor package component 100a (such as Figure 3A ) are the same. Specifically, the present invention is for memory grains of different sizes. The cutting edges of the opposite sides of each semiconductor grain (i.e., the opposite sides of each circuit area) are different. The present invention does not need to change the previous substrate design and can use the previous substrate design. The relative positions of the circuit area of ​​the semiconductor grain and the circuit area of ​​the memory grain on the substrate do not change, and the distance between the semiconductor grain and the memory grain still meets the regulations, so there is no extra time and extra cost spent on redesigning the substrate. Compared with redesigning the substrate, a lot of time and cost are saved, and production efficiency is improved. It should also be noted that the relative position of the circuit area of ​​the memory grain on the substrate 121 does not change. In addition, in the present invention, the value obtained by subtracting D2c from D2a can be equal to the value obtained by subtracting W3 from W5, so that the cutting margin in the cutting process can be adjusted according to the change in the size of the memory grain. In addition, as Figure 3A, 3B, 3C, the widths of semiconductor grains 144a, 144b, 144c can be the same, that is, they are all equal to W1, and the cutting position can be adjusted based on the width W1 during cutting. In addition, if the width of the memory grain is too small or too large, exceeding the adjustable range for semiconductor grain cutting (that is, it is impossible to cut out a semiconductor grain that meets the circuit area installation position requirements and the distance D1 requirements), it is necessary to replace the memory grain that meets the size requirements, so as to facilitate the cutting of the semiconductor grain. Of course, when the size of the memory grain changes, the present invention provides a possible method without changing the substrate or intermediate layer design to provide more solutions.

[0084] Figure 4A is a top view of a semiconductor package assembly 100 a for comparison. Figure 4B is a top view of a semiconductor package assembly 100 b according to some embodiments of the present invention. Figure 4C is a top view of a semiconductor package assembly 100 c according to some other embodiments of the present invention. Figure 4A , 4B and 4C are similar to Figure 3A , 3B and 3C. Figures 4A-4C and Figures 3A-3C The difference is Figures 4A-4C A plurality of conductors 160a, 160b and 160c are shown.

[0085] like Figure 4A As shown, the conductive line 160a is disposed on the semiconductor die 144a and the memory die 150a, and the memory die 150a is electrically connected to the semiconductor die 144a through the conductive line 160a.

[0086] The six conductive lines 160a have the same length L. The length L1a is the length of the portion of the conductive line 160a overlapping the memory die 150a, and the length L2 is the length of the portion of the conductive line 160a overlapping the circuit region 142 of the semiconductor die 144a. The conductive line 160a extends over the edge 151a of the memory die 150a, the edge 145a of the peripheral region 140a, and the edge 147a of the circuit region 142.

[0087] like Figure 4B As shown, similar to the semiconductor package component 100a (such as Figure 4A As shown in FIG. 1 , the semiconductor package assembly 100 b includes a wire 160 b disposed on the semiconductor die 144 b and the memory die 150 b, and the memory die 150 b is electrically connected to the semiconductor die 144 b through the wire 160 b. Figure 4B Only six conductive lines 160b are shown, but it should be noted that there is no limit to the number of conductive lines 160b on the memory die 150b and the semiconductor die 144b.

[0088] The six conductive lines 160b have the same length L. The length L1b is the length of the portion of the conductive line 160b overlapping the memory die 150b, and the length L2 is the length of the portion of the conductive line 160b overlapping the circuit region 142 of the semiconductor die 144b. The conductive line 160b extends over the edge 151b of the memory die 150b, the edge 145b of the peripheral region 140b, and the edge 147b of the circuit region 142.

[0089] With the semiconductor package component 100a (such as Figure 4A ), the length L of the wire 160b is relatively the same as that of the wire 160a (as shown in FIG. Figure 4A The length L of the conductive line 160b and the semiconductor die 144b overlap the circuit region 142, and the length L2 ... Figure 4A The conductive line 160 a shown has the same length L2 as the portion overlapping the circuit region 142 of the semiconductor die 144 a .

[0090] It should be noted that the size of the memory die 150b is smaller than that of the memory die 150a (eg, Figure 4A ), and the center of each memory die 150b is located at the same position as each memory die 150a (as shown in FIG. Figure 4A Therefore, the length L1b of the portion where the conductive line 160b overlaps with the memory die 150b is shorter than the length L1a of the portion where the conductive line 160a overlaps with the memory die 150a.

[0091] like Figure 4C As shown, similar to the semiconductor package component 100a (such as Figure 4A As shown in FIG. 1 , the semiconductor package assembly 100c includes a conductive line 160c disposed on a semiconductor die 144c and a memory die 150c, and the memory die 150c is electrically connected to the semiconductor die 144c through the conductive line 160c.

[0092] The six conductive lines 160c have the same length L. The length L1c is the length of the portion of the conductive line 160c overlapping the memory die 150c, and the length L2 is the length of the portion of the conductive line 160c overlapping the circuit region 142 of the semiconductor die 144c. The conductive line 160c extends over the edge 151c of the memory die 150c, the edge 145c of the peripheral region 140c, and the edge 147c of the circuit region 142.

[0093] With the semiconductor package component 100a (such as Figure 4A ) compared to the length L of the wire 160c and the wire 160a (as shown Figure 4A The length L of the conductor 160c and the overlapping portion of the circuit region 142 are the same as those of the conductor 160c and the overlapping portion of the circuit region 142. Figure 4A The conductive line 160 a shown has the same length L2 as the portion overlapping the circuit region 142 of the semiconductor die 144 a .

[0094] It should be noted that the size of the memory die 150c is larger than that of the memory die 150a (eg, Figure 4A ), and the center of each memory die 150c is located at the same position as each memory die 150a (as shown in FIG. Figure 4A Therefore, the length L1c of the portion of the conductive line 160c that overlaps the memory die 150c is greater than that of the conductive line 160a (as shown in FIG. Figure 4A ) has a length L1a of a portion overlapping with the memory die 150a.

[0095] In addition, although the sizes of the memory grains 150a, 150b, and 150c are different from each other, the solder joints of the memory grains 150a, 150b, and 150c for outputting signals are located at the same position. Therefore, the wires 160b and 160c can have the same length L as the wire 160a, and when the memory grains 150b and 150c having different sizes from the memory grain 150a are used, the signal performance is not degraded.

[0096] Figure 5 FIG. 3 is a top view of a wafer 300, illustrating a method for forming a semiconductor grain according to some other embodiments of the present invention. Figure 5 As shown, the wafer 300 has two circuit regions 1421 and 1422 , and the circuit region 1421 has an edge E1 facing an edge E2 of the circuit region 1422 .

[0097] Figure 5 The wafer 300 and Figure 2 The difference between the wafer 200 is that Figure 5 In the wafer 300, there are two scribe lines S1 and S2 between two adjacent circuit regions 1421 and 1422. Scribe line S1 is adjacent to edge E1, and scribe line S2 is adjacent to edge E2. Scribe line S1 is separated from edge E2 by scribe line S2, and scribe line S2 is separated from edge E1 by scribe line S1. Figure 2 Compared with the wafer 200, due to the Figure 5There are more scribe lines between the circuit areas 1421 and 1422 in the wafer 300. The distance between two adjacent circuit areas 1421 and 1422, the distance D4 between the edge E1 and the scribe line S1, and the distance D5 between the edge E2 and the scribe line S2 can be adjusted more flexibly. In some embodiments, the distance D4 may be the same as the distance D5. In some other embodiments, the distance D4 may be different from the distance D5, for example, the distance D4 is greater than or less than the distance D5. The distances D4 and D5 can be adjusted according to the size of the memory grain, and the memory grain will be packaged together with the semiconductor grains having the circuit areas 1421 and 1422 in the following process. In addition, for the scribe lines S1 and S2, generally, after cutting along one scribe line, cutting is performed along another scribe line, for example, first cutting along the scribe line S1, and then cutting along the scribe line S2. Of course, the order of cutting can be freely changed, for example, first cutting along the scribe line S2, and then cutting along the scribe line S1. In addition, for the sake of simplicity, in Figure 5 Only the scribing line between the circuit regions 1421 and 1422 is shown in the figure. In fact, there are other scribing lines at other edges of the circuit region, which can be used together with the scribing lines during cutting. Figure 5 The settings of the scribe lines S1, S2, distances D4 and D5 are similar and will not be described in detail here. In addition, in this embodiment, the width of the semiconductor grains (such as 144d, 144e, 144f described below) does not need to be fixed to W1 (such as Figure 3A , 3B, 3C), because there are at least two scribe lines between the circuit regions 1421 and 1422 in this embodiment, the width of the peripheral region of the semiconductor crystal grain obtained by cutting (i.e., the distance between the edge of the circuit region and the edge of the peripheral region) can be freely adjusted. Of course, the circuit region 142 (such as Figure 3A , 3B, 3C) is generally kept constant, for example Figure 3A , the width W2 shown in 3B and 3C is the same.

[0098] Fig. 6A is a top view of a semiconductor package assembly 100d according to some embodiments of the present invention. Figure 6B is a top view of a semiconductor package assembly 100 e according to some other embodiments of the present invention. Figure 6C is a top view of a semiconductor package assembly 100 f according to some other embodiments of the present invention.

[0099] like Fig. 6A As shown, four memory grains 150b and one semiconductor grain 144d are provided on the substrate 121. The four memory grains 150b have the same width W4 and are Figure 3B The width of the memory chip 150b is the same as that of the memory chip 150b and is smaller than Figure 3A The width W3 of the memory grain 150a is Figure 3BCompared with the semiconductor package assembly 100b in FIG. 1 , the semiconductor package assembly 100d further includes two memory dies 150b disposed adjacent to the edge 146d of the peripheral region 140d. That is, the memory dies 150b are disposed on opposite sides of the semiconductor die 144d.

[0100] In this embodiment, the distance D1 between the edge 151d of the memory grain 150b and the edge 145d of the peripheral region 140d is the same as the distance D1 between the edge 153d of the memory grain 150b and the edge 146d of the peripheral region 140d. Figure 5 The cutting process shown in FIG. 1 is formed, so the distance D2b between the edge 145d of the peripheral region 140d and the edge 147d of the circuit region 142 can be the same as the distance D2b between the edge 146d of the peripheral region 140d and the edge 148d of the circuit region 142 (that is, when performing Figure 5 In the case of cutting, the distance D4 and the distance D5 may be the same). In addition, in this embodiment, the width of the semiconductor grain 144d does not need to be fixed to W1 (e.g. Figure 3A , 3B, 3C), of course, the width of the circuit area 142 generally remains unchanged, for example Figure 3A , the width W2 shown in 3B and 3C is the same.

[0101] In other embodiments, if the memory grains 150b disposed on opposite sides of the semiconductor grain 144d have different sizes, the distance D2b between the edge 145d and the edge 147d may be different from the distance D2b between the edge 146d and the edge 148d. Fig. 6A In the embodiment of the present invention, a memory chip may be provided on one or both of the left and right sides of the semiconductor chip 144d, and the distance between the memory chip and the semiconductor chip 144d should also meet the requirements so that the semiconductor package meets the stability requirements. Therefore, similar to adjusting the distance D2b, a similar adjustment of the cutting margin may be adopted for the other side or both sides of the semiconductor chip 144d, so that the distance between the edge of the circuit area 142 and the edge of the semiconductor chip 144d is adjusted according to the size of the memory chip, so as to layout the semiconductor chip and the memory chip on the previous substrate and meet the distance regulations or requirements between the semiconductor chip and the memory chip.

[0102] like Figure 6B As shown, four memory grains 150c and one semiconductor grain 144e are provided on the substrate 121. The four memory grains 150c have the same width W5 and are Figure 3C The width of the memory chip 150c is the same as that of the memory chip 150c and is larger than Figure 3AThe width W3 of the memory grain 150a is Figure 3C Compared with the semiconductor package assembly 100c in FIG. 1 , the semiconductor package assembly 100e further includes two memory dies 150c disposed adjacent to the edge 146e of the peripheral region 140e. That is, the memory dies 150c are disposed on opposite sides of the semiconductor die 144e.

[0103] In this embodiment, the distance D1 between the edge 151e of the memory grain 150c and the edge 145e of the peripheral region 140e is the same as the distance D1 between the edge 153e of the memory grain 150c and the edge 146e of the peripheral region 140e. Figure 5 The cutting process shown in FIG. 1 is formed, so the distance D2c between the edge 145e of the peripheral region 140e and the edge 147e of the circuit region 142 can be the same as the distance D2c between the edge 146e of the peripheral region 140e and the edge 148e of the circuit region 142 (that is, when performing Figure 5 In the cutting process, the distance D4 and the distance D5 may be the same). In addition, in this embodiment, the width of the semiconductor grain 144e does not need to be fixed to W1 (e.g. Figure 3A , 3B, 3C), of course, the width of the circuit area 142 generally remains unchanged, for example Figure 3A , the width W2 shown in 3B and 3C is the same.

[0104] In other embodiments, if the memory grains 150c disposed on opposite sides of the semiconductor grain 144e have different sizes, the distance D2c between the edge 145e and the edge 147e may be different from the distance D2c between the edge 146e and the edge 148e. Figure 6B In the embodiment of the present invention, a memory chip may be provided on one or both of the left and right sides of the semiconductor chip 144e, and the distance between the memory chip and the semiconductor chip 144e should also meet the requirements so that the semiconductor package meets the stability requirements. Therefore, similar to adjusting the distance D2c, a similar adjustment of the cutting margin may be adopted for the other side or both sides of the semiconductor chip 144e, so that the distance between the edge of the circuit area 142 and the edge of the semiconductor chip 144e is adjusted according to the size of the memory chip, so as to layout the semiconductor chip and the memory chip on the previous substrate and meet the distance regulations or requirements between the semiconductor chip and the memory chip.

[0105] like Figure 6CAs shown, two memory grains 150c, two memory grains 150b and one semiconductor grain 144f are provided on the substrate 121. The two memory grains 150c and the two memory grains 150b are respectively provided on opposite sides of the semiconductor grain 144f. The two memory grains 150c have a width W5 (similar to Figure 6B ), the two memory grains 150b have a width W4 (similar to Fig. 6A ), and where W5 is greater than Figure 3A The widths W3 and W4 of the memory grain 150a are smaller than Figure 3A The width W3 of the memory grain 150a is Fig. 6A and 6B Compared with the semiconductor package assembly in the figure, the memory die 150 c and the memory die 150 b on opposite sides of the semiconductor package assembly 100 f have different widths W5 and W4 , respectively.

[0106] In this embodiment, the distance D1 between the edge 151f of the memory chip 150c and the edge 145f of the peripheral region 140f is Figure 3A , 3B, 3C, 6A, 6B, 6C are the same, and the distance D1 between the edge 153f of the memory die 150b and the edge 146f of the peripheral region 140f is the same as Figure 3A , 3B, 3C, 6A, 6B, 6C have the same distance D1. In addition, since the semiconductor grain 144f can be Figure 5 The cutting process shown in FIG. 1 may form a distance D2c between an edge 145f of the peripheral region 140f and an edge 147f of the circuit region 142 and a distance D2b between an edge 146f of the peripheral region 140f and an edge 148f of the circuit region 142 different from each other (i.e., when performing Figure 5 When cutting in the embodiment, the distance D4 and the distance D5 may be different, for example, the distance D4 is greater than or less than the distance D5). Specifically, the distance D2b may be greater than the distance D2c. Of course, in other embodiments, the distance D2b may be less than the distance D2c, for example, when the width W5 is less than the width W4. In addition, in this embodiment, the width of the semiconductor grain 144f does not need to be fixed to W1 (for example, Figure 3A , 3B, 3C), of course, the width of the circuit area 142 generally remains unchanged, for example Figure 3A , the width W2 shown in 3B and 3C is the same.

[0107] In other embodiments, if the memory grains 150c and 150b disposed on opposite sides of the semiconductor grain 144f have different sizes, the distance D2c between the edge 145f and the edge 147f may be the same as the distance D2b between the edge 146f and the edge 148f. Figure 6C One or both of the left and right sides in the circuit region 142 may also be provided with a memory grain, and the distance between the memory grain and the semiconductor grain 144f should also meet the requirements so that the semiconductor package meets the stability requirements. Therefore, similar to adjusting the distance D2b and / or D2c, for the other side or both sides of the semiconductor grain 144f, a similar adjustment of the cutting margin may also be adopted, so that the distance between the edge of the circuit region 142 and the edge of the semiconductor grain 144f is adjusted according to the size of the memory grain, so as to layout the semiconductor grains and the memory grains on the previous substrate, and meet the distance regulations or requirements between the semiconductor grains and the memory grains. The present invention is aimed at memory grains of different sizes, and the cutting edges of the opposite sides of each semiconductor grain (that is, the opposite sides of each circuit area) are different, so that the relative position of the circuit area of ​​the semiconductor grain on the substrate does not change. By adjusting the cutting margin, the distance between the semiconductor grain and the memory grain is kept consistent with the previous one, thereby ensuring the structural stability of the package. The present invention does not need to change the previous substrate design, and can use the previous substrate design. The relative positions of the circuit area of ​​the semiconductor grain and the circuit area of ​​the memory grain on the substrate do not change, and the distance between the semiconductor grain and the memory grain still meets the regulations. Therefore, there is no extra time and extra cost spent on redesigning the substrate. Compared with redesigning the substrate, a lot of time and cost are saved, and production efficiency is improved.

[0108] Since there are so many memory grains of different sizes on the market, it is necessary to design different layouts for semiconductor package components using memory grains of different sizes, which requires redesigning and manufacturing the previous substrate or intermediate layer, which may lead to an increase in the cost of manufacturing these semiconductor package components. According to the above-mentioned embodiment, the position of the scribing line on the wafer can be adjusted in the present invention so that the cutting edges of the opposite sides of each semiconductor grain (i.e., the opposite sides of each circuit area) are different, so that the relative positions of the circuit area of ​​the semiconductor grain and the circuit area of ​​the memory grain on the substrate or intermediate layer remain unchanged, and the distance between the semiconductor grain and the memory grain remains unchanged by the different cutting edges, so that the previous substrate or intermediate layer can be used without redesigning the substrate or intermediate layer. In the present invention, the distance between the physical edge of the semiconductor grain and the edge of the circuit area inside the semiconductor grain is different or the same on the opposite sides of the circuit area. In other words, the peripheral area surrounding the circuit area has different widths or the same width on the opposite sides of the circuit area. For memory grains of different sizes, the widths of each edge of the peripheral area of ​​the semiconductor grain can be adjusted in the cutting process.

[0109] Many changes and / or modifications may be made to the embodiments of the present invention. The semiconductor package structure according to some embodiments of the present invention may be used to form a three-dimensional (3D) package, a 2.5D package, a fan-out package or other suitable package. The 3D package may be a package in which the internal conductive structure is all conductive through holes, and the 2.5D package may be a package in which the internal conductive structure has conductive solder balls or conductive pillars.

[0110] Those skilled in the art will readily observe that many modifications and variations of the apparatus and method can be made while maintaining the teachings of the present invention.Accordingly, the above disclosure should be interpreted as being limited only by the metes and bounds of the appended claims.

Claims

1. A semiconductor package assembly, characterized in that: include: A semiconductor grain and a first memory grain are disposed on a first surface of a substrate or an intermediate layer, wherein the first memory grain comprises a first edge facing the semiconductor grain, and the semiconductor grain comprises: a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite the second edge; and a circuit area surrounded by the peripheral area, wherein the circuit area has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge, The distance between the second edge and the fourth edge is a first distance, the distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

2. The semiconductor package assembly according to claim 1, wherein: Also includes: A second memory grain is arranged on the first surface of the substrate or the intermediate layer, wherein the width of the first memory grain is the same as the width of the second memory grain; the second memory grain includes a sixth edge facing the second edge, and the second edge is located between the fourth edge and the sixth edge of the second memory grain.

3. The semiconductor package assembly according to claim 2, wherein: A distance between the first edge and the second edge is the same as a distance between the sixth edge and the second edge.

4. The semiconductor package assembly according to claim 1, wherein: Also includes: a plurality of first conductive structures disposed on the substrate or the intermediary layer, wherein the semiconductor die and the first memory die are electrically connected to the substrate or the intermediary layer through the first conductive structures; as well as A first bottom filling layer is inserted between the first surface of the substrate or the intermediate layer and the semiconductor grain and the first memory grain, wherein the first bottom filling layer surrounds the first conductive structure.

5. The semiconductor package assembly according to claim 4, wherein: A portion of the first underfill layer separates the semiconductor die from the first memory die.

6. The semiconductor package assembly according to claim 5, wherein: Also includes: A molding compound surrounds the first underfill layer, the semiconductor die, and the first memory die, wherein the molding compound covers a second edge of the peripheral region of the semiconductor die.

7. The semiconductor package assembly according to claim 1, wherein: The distance between the semiconductor die and the first memory die is a distance that complies with regulations.

8. The semiconductor package assembly according to claim 1, wherein: Also includes: A conductive line, disposed on the semiconductor grain and the first memory grain; The semiconductor die is electrically connected to the first memory die through the conductive line.

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