Interface circuit and interface device

Abstract

An interface device includes a plurality of interface circuits, wherein each of the plurality of interface circuits includes a first switching element connected in series to a second switching element, and a first capacitor and a second capacitor connected to an output terminal, the first switching element and the second switching element being connected to the output terminal; and a controller configured to determine a plurality of output signals corresponding to the plurality of interface circuits by controlling the first switching element and the second switching element, and configured to adjust conversion rates of the plurality of output signals by charging and discharging the first capacitor and the second capacitor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2020-0000863 filed on January 3, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to an interface circuit and an interface device. Background Art

[0004] Multiple integrated circuit chips included in electronic devices can exchange data with each other via interface circuits. As the volume of data processed by electronic devices increases, interface circuits capable of providing high-speed data communication between integrated circuit chips have been proposed. Furthermore, as the number of integrated circuit chips included in electronic devices increases and their types change, various methods for improving the operation of interface circuits have been proposed. Summary of the Invention

[0005] Provided are an interface circuit and an interface device, wherein by adjusting the slew rate of an output signal, an eye margin of a signal can be improved, data can be transmitted at a high speed, and further, electromagnetic interference (EMI) can be significantly reduced.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0007] According to one aspect of the present disclosure, an interface circuit includes: a first switching element, which is controlled by a first input signal and is connected to a first power supply node configured to supply a first power supply voltage and an output node configured to output an output signal; a second switching element, which is controlled by a second input signal different from the first input signal and is connected to the output node and a second power supply node configured to supply a second power supply voltage lower than the first power supply voltage; a first resistor, which is connected between the first power supply node and the first switching element; a second resistor, which is connected between the second power supply node and the second switching element; a first capacitor, which is connected to the output node and controlled by a first control signal; a second capacitor, which is connected to the output node and controlled by a second control signal different from the first control signal; a third capacitor, which is connected to a node between the first resistor and the first switching element; and a fourth capacitor, which is connected to a node between the second resistor and the second switching element.

[0008] According to one aspect of the present disclosure, an interface device includes: a plurality of interface circuits, wherein each interface circuit of the plurality of interface circuits includes a first switching element connected in series to a second switching element, and a first capacitor and a second capacitor connected to an output terminal, wherein the first switching element and the second switching element are connected to the output terminal; and a controller configured to determine a plurality of output signals corresponding to the plurality of interface circuits by controlling the first switching element and the second switching element, and configured to adjust a conversion rate of the plurality of output signals by charging and discharging the first capacitor and the second capacitor.

[0009] According to one aspect of the present disclosure, an interface circuit includes: a first switching element configured to receive a first power supply voltage and to be turned on and off by a first input signal; a second switching element configured to receive a second power supply voltage lower than the first power supply voltage and to be turned on and off by a second input signal different from the first input signal; a first capacitor, wherein a first terminal of the first capacitor is connected to an output node, the first switching element and the second switching element are connected to the output node, and a second terminal of the first capacitor is configured to receive a first control signal; and a second capacitor, wherein a first terminal of the second capacitor is connected to the output node, and a second terminal of the second capacitor is configured to receive a second control signal different from the first control signal, wherein, based on an increase in an output signal output from the output node, at least one of the first control signal and the second control signal increases from a low level to a high level, and wherein, based on a decrease in the output signal, the at least one of the first control signal and the second control signal decreases from the high level to the low level. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 and Figure 2 is a diagram schematically illustrating an electronic device including an interface circuit according to an example embodiment;

[0012] Figure 3 and Figure 4 is a diagram illustrating the operation of an interface device according to an example embodiment;

[0013] Figure 5 is a circuit diagram of an interface circuit according to an example embodiment;

[0014] Figure 6 and Figure 7is a diagram illustrating the operation of an interface circuit according to an example embodiment;

[0015] Figure 8 and Figure 9 is a diagram illustrating the operation of an interface circuit according to an example embodiment;

[0016] Figure 10 and Figure 11 is a diagram illustrating the operation of an interface circuit according to an example embodiment;

[0017] Figure 12 and Figure 13 is a diagram illustrating the operation of an interface circuit according to an example embodiment;

[0018] Figure 14 and Figure 15 is a diagram illustrating the operation of an interface circuit according to an example embodiment;

[0019] Figure 16 and Figure 17 is a diagram illustrating the operation of an interface circuit according to an example embodiment;

[0020] Figure 18 is a circuit diagram of an interface circuit according to an example embodiment;

[0021] Figure 19 and Figure 20 is a diagram illustrating the operation of an interface circuit according to an example embodiment;

[0022] Figure 21 and Figure 22 is a diagram illustrating the operation of an interface circuit according to an example embodiment;

[0023] Figure 23 is a schematic diagram illustrating an interface device according to an example embodiment;

[0024] Figure 24 and Figure 25 is a diagram illustrating the operation of an interface device according to an example embodiment;

[0025] Figure 26 is a diagram schematically illustrating an interface device according to an example embodiment;

[0026] Figures 27 to 30 is a diagram illustrating the operation of an interface device according to an example embodiment; and

[0027] Figure 31 is a schematic block diagram of an electronic device including an interface circuit according to an example embodiment. DETAILED DESCRIPTION

[0028] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. The embodiments described below are exemplary, and thus, the inventive concept is not limited to the embodiments disclosed below and can be implemented in various other forms.

[0029] Figure 1 is a simplified block diagram of an electronic device including an interface circuit according to an example embodiment.

[0030] Reference Figure 1 , the electronic device 10 may include an application processor 20 and a display driver 30. The interface device 21 of the application processor 20 may exchange data with the interface device 31 of the display driver 30. Each of the interface device 21 and the interface device 31 may include a plurality of interface circuits.

[0031] The interface device 21 and the interface device 31 can exchange data with each other according to a predetermined protocol. For example, the interface device 21 of the application processor 20 and the interface device 31 of the display driver 30 can exchange data according to a protocol defined in the Mobile Industry Processor Interface (MIPI) standard. Each of the interface device 21 and the interface device 31 may include a transmitting circuit and a receiving circuit.

[0032] Next, refer to Figure 2 In the electronic device 40, the application processor 50 can exchange data with the image sensor 60. The interface device 51 of the application processor 50 and the interface device 61 of the image sensor 60 can exchange data with each other. Figure 1 Similar to the described embodiments, the interface device 51 and the interface device 61 may include a plurality of interface circuits for exchanging data.

[0033] The interface circuit included in at least one of the interface devices 21, 31, 51, and 61 according to an example embodiment may have a function of adjusting the slew rate of the output signal. The slew rate of the output signal may be determined by a control signal input to the interface devices 21, 31, 51, and 61 by a controller included in the application processors 20 and 50, the display driver 30, and the image sensor 60. In an example embodiment, when it is determined that high-speed data transmission is required, the controller may increase the slew rate of the output signal. In addition, when high-speed data transmission is not required and EMI characteristics need to be improved, the controller may reduce the slew rate of the output signal.

[0034] Figure 3 and Figure 4 is a diagram provided to illustrate the operation of an interface device according to an example embodiment.

[0035] Figure 3 1 is a diagram showing the operation of the interface device 70 that transmits data and clock signals using a differential signaling method. Figure 3The described example embodiments may be applied to a D-phy interface according to the MIPI standard. Figure 3 , the plurality of transmitters TX0 to TX9 may output data DN0 to DN3 and DP0 to DP3 and clock signals CLKN and CLKP through the plurality of transmission pads TP0 to TP9.

[0036] The transmission pads TP0 to TP9 can be connected to the plurality of reception pads RP0 to RP9 through the plurality of data channels L0 to L9, and the reception pads RP0 to RP9 can be connected to the plurality of receivers RX0 to RX4. For example, each of the receivers RX0 to RX4 can be connected to a pair of reception pads among the reception pads RP0 to RP9, and the receivers RX0 to RX4 can generate data D0 to D3 and a clock signal CLK using a differential signaling method. Therefore, in Figure 3 In the example embodiment shown in FIG, in order to transmit data using a differential signaling method, 10 transmission pads TP0 to TP9 and 10 data channels L0 to L9 and 10 reception pads RP0 to RP9 may be used. According to an example embodiment, dummy pads for obtaining an electrical shielding effect may be added to the transmission pads TP0 to TP9 and the reception pads RP0 to RP9. For example, Figure 3 The interface device 70 shown in FIG. 7 may be applied to an application processor, a display driver, an image sensor, and the like.

[0037] Figure 4 is a diagram provided for describing the operation of the interface device 80 that transmits data using a single-ended signaling method. Figure 4 The described example embodiments may be applied to a C-phy interface according to the MIPI standard. Figure 4 , multiple transmitters TX0 to TX8 can output data A0 to C0, A1 to C1, and A2 to C2 through multiple transmission pads TP0 to TP8. Since image data can be output through a single-ended signal method, Figure 4 The interface of the illustrated example embodiment may not have a separate data channel for outputting a clock signal.

[0038] Transmit pads TP0 to TP8 can be connected to multiple receive pads RP0 to RP8 via multiple data channels L0 to L8, and receive pads RP0 to RP8 can be connected to multiple receivers RX0 to RX8. Transmit pads TP0 to TP8 can be divided into multiple groups TP0 to TP2, TP3 to TP5, and TP6 to TP8 based on data A0 to C0, A1 to C1, and A2 to C2, and receive pads RP0 to RP8 can also be divided into multiple groups RP0 to RP2, RP3 to RP5, and RP6 to RP8. Each of receivers RX0 to RX8 can be connected to a pair of receive pads included in each of groups RP0 to RP2, RP3 to RP5, and RP6 to RP8. For example, the first receiver RX0 can output the difference between signal A0 and signal B0, and the second receiver RX1 can output the difference between signal B0 and signal C0. In addition, the third receiver RX2 can output the difference between signal C0 and signal A0.

[0039] exist Figure 4 In the example embodiment shown in , in order to transmit data using a single-ended signaling method, nine transmission pads TP0 to TP8, nine data channels L0 to L8, and nine reception pads RP0 to RP8 may be required. However, even if a single-ended signaling method is used, according to an example embodiment, a dummy pad for obtaining an electrical shielding effect may be added. Figure 4 The interface device 80 shown in FIG. 8 can also be applied to application processors, display drivers, and image sensors.

[0040] As the volume of data transmitted by interface devices 70 and 80 gradually increases and the data transmission speed required by the system increases, the noise characteristics of the signals output by interface devices 70 and 80 may deteriorate. In an exemplary embodiment, by connecting capacitors to the output terminals of interface devices 70 and 80 and controlling the charging and discharging of the capacitors, the noise characteristics of interface devices 70 and 80 can be improved. In addition, by controlling the charging and discharging of the capacitors according to the operation of interface devices 70 and 80, the conversion rate of interface devices 70 and 80 can be adjusted so that interface devices 70 and 80 operate with optimal characteristics.

[0041] Figure 5 is a circuit diagram of an interface circuit according to an example embodiment.

[0042] Reference Figure 5 The interface circuit 100 according to the example embodiment may include a first switching element SW1, a second switching element SW2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, and a second resistor R2. The first switching element SW1 and the second switching element SW2 may be connected in series with each other between a first power supply node 101 and a second power supply node 102.

[0043] The first switching element SW1 may be connected to the first power supply node 101 through the first resistor R1, and the second switching element SW2 may be connected to the second power supply node 102 through the second resistor R2. A first power supply voltage VDD may be supplied through the first power supply node 101, and a second power supply voltage VSS may be supplied through the second power supply node 102. In example embodiments, the first power supply voltage VDD may be greater than the second power supply voltage VSS.

[0044] exist Figure 5 In the example embodiment shown, a node between the first resistor R1 and the first switch element SW1 may be defined as a first node N1, and a node between the second resistor R2 and the second switch element SW2 may be defined as a second node N2. An output node N3 may be defined between the first switch element SW1 and the second switch element SW2. An output signal OUT output to the output node N3 may be determined by controlling a first input signal IN1 of the first switch element SW1 and a second input signal IN2 of the second switch element SW2.

[0045] A first capacitor C1 and a second capacitor C2 may be connected to an output node N3. The first capacitor C1 may be charged and discharged by a first control signal CTR1, and the second capacitor C2 may be charged and discharged by a second control signal CTR2. A third capacitor C3 may be connected to the first node N1, and a fourth capacitor C4 may be connected to the second node N2. The third capacitor C3 may be charged and discharged by a third control signal CTR3, and the fourth capacitor C4 may be charged and discharged by a fourth control signal CTR4.

[0046] In example embodiments, the first to fourth capacitors C1 to C4 may be implemented as metal oxide semiconductor (MOS) capacitors, etc. When the first to fourth capacitors C1 to C4 are MOS capacitors, the first to fourth control signals CTR1 to CTR4 may be input to gate terminals of the first to fourth capacitors C1 to C4, respectively.

[0047] The capacitance values ​​of the first capacitor C1 to the fourth capacitor C4 can be selected differently. For example, the capacitance value of the first capacitor C1 and the second capacitor C2 can be greater than the capacitance value of the third capacitor C3 and the fourth capacitor C4. For example, the capacitance value of the first capacitor C1 and the second capacitor C2 can be greater than or equal to 2 times the capacitance value of the third capacitor C3 and the fourth capacitor C4 and less than or equal to 10 times the capacitance value of the third capacitor C3 and the fourth capacitor C4. In an example embodiment, the capacitance value of the first capacitor C1 and the second capacitor C2 can be approximately 5 times the capacitance value of the third capacitor C3 and the fourth capacitor C4. In addition, in an example embodiment, the first capacitor C1 and the second capacitor C2 may have the same capacitance value, and the third capacitor C3 and the fourth capacitor C4 may have the same capacitance value.

[0048] When the interface circuit 100 transmits data using a differential signaling method, the first input signal IN1 and the second input signal IN2 may have opposite phases. For example, the first input signal IN1 may be the complementary signal of the second input signal IN2. When the first switching element SW1 is turned on by the first input signal IN1 and the second switching element SW2 is turned off by the second input signal IN2, the output signal OUT may have a high level. In addition, when the first switching element SW1 is turned off by the first input signal IN1 and the second switching element SW2 is turned on by the second input signal IN2, the output signal OUT may have a low level.

[0049] When the output signal OUT decreases from a high level to a low level, or increases from a low level to a high level, the slew rate of the output signal OUT may be affected by the magnitudes of the first input signal IN1 and the second input signal IN2, and by parasitic components present in various elements and nodes 101, 102, and N1 to N3. In example embodiments, the slew rate of the output signal OUT may be increased or decreased by controlling the charging and discharging of the first to fourth capacitors C1 to C4.

[0050] When the interface circuit 100 transmits data using a single-ended signaling method, the first input signal IN1 and the second input signal IN2 may not have completely opposite phases. For at least a certain amount of time, the first input signal IN1 and the second input signal IN2 may have the same value, and the output signal OUT may have one of a high level, a low level, and an intermediate level between the high level and the low level.

[0051] Even when the interface circuit 100 transmits data using a single-ended signaling method, the slew rate of the output signal OUT can be increased or decreased by controlling the charging and discharging of the first to fourth capacitors C1 to C4. In an exemplary embodiment, when the interface circuit 100 operates using a differential signaling method and a single-ended signaling method, different methods can be used to control at least one of the first to fourth capacitors C1 to C4. For example, when the interface circuit 100 operates using a differential signaling method, the second capacitor C2 can receive the first input signal IN1 as the second control signal CTR2, and when the interface circuit 100 operates using a single-ended signaling method, the second capacitor C2 can receive a signal different from the first input signal IN1 as the second control signal CTR2.

[0052] In an exemplary embodiment of the interface device, according to Figure 5 The interface circuit 100 of the illustrated example embodiment can be defined as a unit circuit, and a plurality of unit circuits can be connected to one output pad that outputs the output signal OUT. For example, one or more first unit circuits and one or more second unit circuits can be connected to one output pad. For example, the values ​​of the resistors R1 and R2 and the capacitors C1 to C4 included in the first unit circuit can be the same as or different from the values ​​of the resistors R1 and R2 and the capacitors C1 to C4 included in the second unit circuit.

[0053] In an example embodiment, five first unit circuits and two second unit circuits can be connected to one output pad. For example, the sum of the on-resistances of the first resistor R1 and the first switch element SW1 included in each first unit circuit can be half the sum of the on-resistances of the first resistor R1 and the first switch element SW1 included in each second unit circuit. Similarly, the sum of the on-resistances of the second resistor R2 and the second switch element SW2 included in each first unit circuit can be half the sum of the on-resistances of the second resistor R2 and the second switch element SW2 included in each second unit circuit. In an example embodiment of the interface device, a desired resistance value can be set by appropriately controlling the first switch element SW1 and the second switch element SW2 included in the first unit circuit and the second unit circuit, respectively.

[0054] In an example embodiment, the size of each of the first switching element SW1 and the second switching element SW2 can be determined based on the resistance condition described above. For example, assuming that the gate lengths of the first switching element and the second switching element included in each of the first unit circuit and the second unit circuit are the same, the gate width of the first switching element included in the first unit circuit can be twice the gate width of the first switching element included in the second unit circuit. In the above example, the gate width can be defined in a direction intersecting with the gate length. Similarly, the gate width of the second switching element included in the first unit circuit can be twice the gate width of the second switching element included in the second unit circuit.

[0055] In an embodiment including the number of first unit circuits and second unit circuits as described above, the capacity of the first capacitor C1 included in the first unit circuit may be approximately twice the capacity of the first capacitor C1 included in the second unit circuit. In addition, the capacity of the second capacitor C2 included in the first unit circuit may be approximately twice the capacity of the second capacitor C2 included in the second unit circuit.

[0056] In the case of a C-Phy interface operating using a single-ended signaling method, as mentioned above Figure 4 As described above, at least three output pads may be required to transmit data. The output signals output from the three output pads may not have the same value, and as described above, may have one of a high level, a low level, and an intermediate level. For example, the number of unit circuits operating in a plurality of unit circuits connected to the output pad may be changed according to the output signal OUT outputted through the output pad.

[0057] Figure 6 and Figure 7 2 is a diagram provided to illustrate the operation of an interface circuit according to example embodiments.

[0058] In reference Figure 6 and Figure 7 In the described example embodiment, the interface circuit 110 may operate using a differential signaling approach. Figure 7 As shown, when the first switching element SW1 is turned on and the second switching element SW2 is turned off, the output signal OUT may have a high level, and when the first switching element SW1 is turned off and the second switching element SW2 is turned on, the output signal OUT may have a low level.

[0059] exist Figure 6 In the example embodiment shown, the first capacitor C1 and the second capacitor C2 can be charged and discharged by the first input signal IN1. In detail, the first control signal input to the first capacitor C1 and the second control signal input to the second capacitor C2 can be the same as the first input signal IN1. Therefore, it can be as follows Figure 6 The equivalent circuit is defined as shown.

[0060] In example embodiments, the third control signal CTR3 input to the third capacitor C3 and the fourth control signal CTR4 input to the fourth capacitor C4 may each be a predetermined constant voltage signal. Figure 7 , the third control signal CTR3 may have a first constant voltage V1, and the fourth control signal CTR4 may have a second constant voltage V2. The magnitudes of the first constant voltage V1 and the second constant voltage V2 may be determined differently. For example, the magnitudes of the first constant voltage V1 and the second constant voltage V2 may be the same. The first constant voltage V1 and the second constant voltage V2 may have different magnitudes, and the first constant voltage V1 may be greater than the second constant voltage V2, or the first constant voltage V1 may be less than the second constant voltage V2.

[0061] Refer to it together Figure 6 and Figure 7 When the first switching element SW1 is turned on by the first input signal IN1, the second switching element SW2 can be turned off by the second input signal IN2. Furthermore, when the first switching element SW1 is turned on, the first capacitor C1 and the second capacitor C2 can be charged. As the first capacitor C1 and the second capacitor C2 are charged, the output signal OUT can quickly rise from a low level to a high level.

[0062] When the first switch element SW1 is turned off by the first input signal IN1 and the second switch element SW2 is turned on by the second input signal IN2, the output signal OUT may decrease from a high level to a low level. The first capacitor C1 and the second capacitor C2 may be discharged by the first input signal IN1, and the output signal OUT may decrease from a high level to a low level quickly. Therefore, in reference Figure 6 and Figure 7 In the described example embodiment, the slew rate of the output signal OUT can be increased.

[0063] Figure 8 and Figure 9 2 is a diagram provided to illustrate the operation of an interface circuit according to example embodiments.

[0064] In reference Figure 8 and Figure 9 In the described example embodiment, the interface circuit 120 may operate using a single-ended signaling method. Figure 9When the first switching element SW1 is turned on and the second switching element SW2 is turned off, the output signal OUT increases from a low level to a high level. When the first switching element SW1 is turned off and the second switching element SW2 is turned on, the output signal OUT may decrease from a high level to a low level. Furthermore, depending on whether one of the first switching element SW1 and the second switching element SW2 is turned on or off, the output signal OUT may have an intermediate level between a high level and a low level. As an example, the output signal OUT may be determined as shown in Table 1 below.

[0065] [Table 1]

[0066] First input signal (IN1) Second input signal (IN2) Output signal (OUT) Low → High High → Low Low → High High → Low Low → High High → Low Low High → Low Low → Middle Low Low → High Middle → Low Low → High Low Middle → High High → Low Low High → Middle

[0067] The first capacitor C1 in the interface circuit 120 can be charged and discharged by the first input signal IN1. In detail, the first control signal input to the first capacitor C1 can be the same as the first input signal IN1. Therefore, it can be as follows Figure 8 1 is an equivalent circuit diagram of the interface circuit 120 .

[0068] Reference Figure 9 , the second control signal CTR2 input to the second capacitor C2 may have a complementary relationship with the second input signal IN2. The first input signal IN1 input to the first capacitor C1 may be input as the first control signal, and a signal having a complementary relationship with the second input signal IN2 is input to the second capacitor C2 as the second control signal CTR2, thereby improving the conversion rate of the output signal OUT.

[0069] Reference Figure 9 When the amount of change in the output signal OUT is a first value, only one of the first control signal CTR1 (i.e., the first input signal IN1) and the second control signal CTR2 may be raised or lowered, and when the amount of change in the output signal OUT is a second value, the first control signal CTR1 and the second control signal CTR2 may be raised or lowered simultaneously. The first value may be a difference between a high level and an intermediate level and a difference between an intermediate level and a low level, and the second value may be a difference between a high level and a low level.

[0070] For example, when the output signal OUT rises from a low level to an intermediate level, only the second control signal CTR2 may rise, and when the output signal OUT rises from an intermediate level to a high level, only the first control signal CTR1 may rise. When the output signal OUT falls from a high level to an intermediate level, only the first control signal CTR1 may fall. When the output signal OUT falls from an intermediate level to a low level, only the second control signal CTR2 may fall. When the output signal OUT rises from a low level to a high level, the first control signal CTR1 and the second control signal CTR2 may rise simultaneously, and when the output signal OUT falls from a high level to a low level, the first control signal CTR1 and the second control signal CTR2 may fall simultaneously.

[0071] Each of the third control signal CTR3 input to the third capacitor C3 and the fourth control signal CTR4 input to the fourth capacitor C4 may be a predetermined constant voltage signal. Figure 9 , the magnitude of the third control signal CTR3 may have a first constant voltage V1, and the magnitude of the fourth control signal CTR4 may have a second constant voltage V2. Figure 6 and Figure 7 As mentioned above, the magnitudes of the first constant voltage V1 and the second constant voltage V2 may be determined differently.

[0072] Refer to it together Figure 8 and Figure 9 When the first switching element SW1 is turned on by the first input signal IN1, the first capacitor C1 is charged to quickly increase the output signal OUT. Furthermore, when the second switching element SW2 is turned on by the second input signal IN2, the second capacitor C2 is discharged to quickly decrease the output signal OUT. Therefore, the slew rate of the output signal OUT can be increased.

[0073] Figure 10 and Figure 11 2 is a diagram provided to illustrate the operation of an interface circuit according to example embodiments.

[0074] In reference Figure 10 and Figure 11 In the example embodiment described, the interface circuit 130 can operate using a differential signal method. The first capacitor C1 to the fourth capacitor C4 in the interface circuit 130 can be charged and discharged by the first input signal IN1. In detail, the first control signal to the fourth control signal input to the first capacitor C1 to the fourth capacitor C4 can be the same as the first input signal IN1. Therefore, it can be as follows Figure 10 The equivalent circuit of the interface circuit 130 is shown in FIG. Figure 10 In the illustrated example embodiment, the third capacitor C3 may include a parasitic capacitor included in the first switching element SW1 .

[0075] When the first switching element SW1 is turned on by the first input signal IN1, the second switching element SW2 can be turned off by the second input signal IN2. In addition, when the first switching element SW1 is turned on, the first to fourth capacitors C1 to C4 can be charged. Since the first to fourth capacitors C1 to C4 are charged, the output signal OUT can quickly rise from a low level to a high level.

[0076] When the first switch element SW1 is turned off by the first input signal IN1 and the second switch element SW2 is turned on by the second input signal IN2, the output signal OUT may decrease from a high level to a low level. The first to fourth capacitors C1 to C4 may be discharged by the first input signal IN1, and the output signal OUT may decrease from a high level to a low level quickly. Therefore, in reference to Figure 10 and Figure 11 In the described example embodiment, the slew rate of the output signal OUT can be increased.

[0077] Figure 12 and Figure 13 2 is a diagram provided to illustrate the operation of an interface circuit according to example embodiments.

[0078] In reference Figure 12 and Figure 13 In the described example embodiment, the interface circuit 140 may operate using a single-ended signaling method. The output signal OUT may be determined by the first input signal IN1 and the second input signal IN2 as shown in Table 1 described above.

[0079] Reference Figure 12 , the first capacitor C1 and the third capacitor C3 in the interface circuit 140 can be charged and discharged by the first input signal IN1. In addition, the second capacitor C2 and the fourth capacitor C4 can be charged or discharged at the same time by receiving the second control signal CTR2 together. Figure 12 The equivalent circuit of the interface circuit 140 is shown in FIG. Figure 13 , the second control signal CTR2 may have a complementary relationship with the second input signal IN2.

[0080] When the first switching element SW1 is turned on by the first input signal IN1, the first capacitor C1 and the third capacitor C3 are charged, rapidly increasing the output signal OUT. Furthermore, when the second switching element SW2 is turned on by the second input signal IN2, the second capacitor C2 and the fourth capacitor C4 are discharged, rapidly decreasing the output signal OUT. Consequently, the slew rate of the output signal OUT can be increased.

[0081] Figure 14 and Figure 152 is a diagram provided to illustrate the operation of an interface circuit according to example embodiments.

[0082] In reference Figure 14 and Figure 15 In the example embodiment described, the output signal OUT may be a differential signal, and the first to fourth capacitors C1 to C4 may be charged and discharged by the second input signal IN2. Specifically, the first to fourth control signals input to the first to fourth capacitors C1 to C4 may be the same as the second input signal IN2. Therefore, Figure 14 1 is an equivalent circuit diagram of the interface circuit 150 .

[0083] When the first switching element SW1 is turned on by the first input signal IN1, the second switching element SW2 can be turned off by the second input signal IN2. In addition, when the second switching element SW2 is turned off, the first to fourth capacitors C1 to C4 can be discharged. Because the first to fourth capacitors C1 to C4 are discharged, the speed at which the output signal OUT rises from a low level to a high level can be reduced.

[0084] When the first switch element SW1 is turned off by the first input signal IN1 and the second switch element SW2 is turned on by the second input signal IN2, the output signal OUT may decrease from a high level to a low level. At this time, the first capacitor C1 to the fourth capacitor C4 may be charged by the second input signal IN2, and the output signal OUT may slowly decrease from a high level to a low level. Therefore, in reference to Figure 14 and Figure 15 In the described example embodiment, the slew rate of the output signal OUT can be reduced. As the slew rate of the output signal OUT is reduced, noise components generated in the interface circuit 150, such as electromagnetic interference (EMI), can be reduced.

[0085] Figure 16 and Figure 17 2 is a diagram provided to illustrate the operation of an interface circuit according to example embodiments.

[0086] In reference Figure 16 and Figure 17 In the described example embodiment, the output signal OUT may be a single-ended signal having a high level, a low level, and an intermediate level. Figure 16 , the first capacitor C1 and the third capacitor C3 receive the first control signal CTR1 in common, and the second capacitor C2 and the fourth capacitor C4 can receive the second input signal IN2 in common. Figure 16 1 is an equivalent circuit diagram of the interface circuit 160 .

[0087] Since the output signal OUT is a single-ended signal, the relationship between the first input signal IN1, the second input signal IN2 and the output signal OUT can be as described with reference to Table 1 above. Figure 17 , the first input signal IN1 and the first control signal CTR1 may have a complementary relationship with each other. Therefore, when the first switching element SW1 is turned on, the first capacitor C1 and the third capacitor C3 are discharged, and when the first switching element SW1 is turned off, the first capacitor C1 and the third capacitor C3 may be charged.

[0088] Since the second input signal IN2 is input to the second capacitor C2 and the fourth capacitor C4, when the second switch element SW2 is turned on, the second capacitor C2 and the fourth capacitor C4 are charged, and when the second switch element SW2 is turned off, the second capacitor C2 and the fourth capacitor C4 may be discharged. Figure 17 As shown, the slew rate of the output signal OUT can be reduced. As described above, as the slew rate of the output signal OUT is reduced, noise components generated in the interface circuit 160, such as electromagnetic interference (EMI), can be reduced.

[0089] Reference Figures 6 to 17 The described example embodiments may be Figure 5 The operation of the interface circuit 100 is described as follows. For example, when Figure 5 When the interface circuit 100 of the exemplary embodiment shown uses a differential signaling method to output the output signal OUT, the interface circuit 100 may be operated to increase the conversion rate of the output signal OUT, such as Figure 6 or Figure 10 For example, the first input signal IN1 can be input to the interface circuit 100 as the first control signal CTR1 and the second control signal CTR2, and a constant voltage can be input as the third control signal CTR3 and the fourth control signal CTR4, so that Figure 6 In addition, by inputting the first input signal IN1 as the first control signal CTR1 to the fourth control signal CTR4 to the interface circuit 100, the interface circuit 100 can be operated as shown. Figure 10 The operation interface circuit 100 is shown.

[0090] In addition, in the exemplary embodiment, when the interface circuit 100 outputs the output signal OUT in a single-ended signal method, it may be as follows. Figure 8 or Figure 12The interface circuit 100 is operated as shown to improve the conversion rate of the output signal OUT. In this example, the first input signal IN1 can be input to the interface circuit 100 as the first control signal CTR1, the complementary signal of the second input signal IN2 can be input to the interface circuit 100 as the second control signal CTR2, and a constant voltage can be input as the third control signal CTR3 and the fourth control signal CTR4, so that Figure 8 The interface circuit 100 is operated as shown. In addition, the first input signal IN1 can be input to the interface circuit 100 as the first control signal CTR1 and the third control signal CTR3, and the complementary signal of the second input signal IN2 can be input to the interface circuit 100 as the second control signal CTR2 and the fourth control signal CTR4, so that Figure 12 An interface circuit 100 is shown implemented.

[0091] In detail, according to the reference Figures 6 to 17 The interface circuits 110 to 160 of the described example embodiment may be configured by adjusting the Figure 5 The equivalent circuit can be obtained by appropriately selecting the first control signal CTR1 to the fourth control signal CTR4 in the interface circuit 100 of the exemplary embodiment shown in FIG. Figure 5 The first input signal IN1, the second input signal IN2, and the first control signal CTR1 to the fourth control signal CTR4 in the interface circuit 100 implemented as shown can be based on the reference Figures 6 to 17 Various methods of operating the interface circuit 100 are described for example embodiments.

[0092] As another example, refer to Figures 6 to 17 The described example embodiment may be an interface circuit 110 to 160 implemented as circuits separated from each other. For example, one end of each of the first capacitor C1 and the second capacitor C2 may be physically connected to the gate of the first switching element SW1 to implement Figure 6 In addition, one end of each of the first capacitor C1 and the third capacitor C3 may be physically connected to the gate of the first switching element SW1, and the second control signal CTR2 as a complementary signal of the second input signal IN2 may be input to the second capacitor C2 and the fourth capacitor C4, thereby implementing the following. Figure 12 The interface circuit 140 is shown.

[0093] Figure 18 is a circuit diagram of an interface circuit according to an example embodiment.

[0094] Reference Figure 18The interface circuit 200 according to the example embodiment includes a first switching element SW1, a second switching element SW2, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, etc. The first switching element SW1 and the second switching element SW2 may be connected in series with each other between a first power supply node 201 and a second power supply node 202.

[0095] exist Figure 18 In the example embodiment shown, the output signal OUT output to the output node ON can be determined by controlling the first input signal IN1 of the first switching element SW1 and the second input signal IN2 of the second switching element SW2. For example, when the first switching element SW1 is turned on, the output signal OUT increases, and when the second switching element SW2 is turned on, the output signal may decrease.

[0096] The first capacitor C1 and the second capacitor C2 may be connected to the output node ON. The first capacitor C1 may be charged and discharged by the first control signal CTR1, and the second capacitor C2 may be charged and discharged by the second control signal CTR2.

[0097] In an example embodiment, the first capacitor C1 and the second capacitor C2 may be implemented as MOS capacitors, etc. When the first capacitor C1 and the second capacitor C2 are MOS capacitors, the first control signal CTR1 and the second control signal CTR2 may be input to the gate terminals of the first capacitor C1 and the second capacitor C2, respectively. In an example embodiment, the first capacitor C1 and the second capacitor C2 may have the same capacitance value. In an example embodiment, the capacitance value of the first capacitor C1 may be different from the capacitance value of the second capacitor C2.

[0098] When the interface circuit 200 transmits data using a differential signaling method, the first input signal IN1 and the second input signal IN2 may have opposite phases, and the output signal may swing between a high level and a low level. The first input signal IN1 may be a complementary signal of the second input signal IN2. In an example embodiment, when the output signal OUT decreases from a high level to a low level or increases from a low level to a high level, the charging and discharging of the first capacitor C1 and the second capacitor C2 may be controlled, thereby increasing or decreasing the slew rate of the output signal OUT.

[0099] When the interface circuit 200 transmits data using a single-ended signaling method, the first input signal IN1 and the second input signal IN2 may not have completely opposite phases, and the output signal OUT may have at least one intermediate level, in addition to a high level and a low level, that is less than the high level and greater than the low level. For at least a certain amount of time, the first input signal IN1 and the second input signal IN2 may have the same value.

[0100] Even when the interface circuit 200 transmits data using a single-ended signaling method, the slew rate of the output signal OUT can be increased or decreased by controlling the charging and discharging of the first capacitor C1 and the second capacitor C2. In an exemplary embodiment, at least one of the first capacitor C1 and the second capacitor C2 can be controlled differently when the interface circuit 200 operates using a differential signaling method and when it operates using a single-ended signaling method. For example, when the interface circuit 200 operates using a differential signaling method, the second capacitor C2 can receive the first input signal IN1 as the second control signal CTR2, and when the interface circuit 200 operates using a single-ended signaling method, the second capacitor C2 can receive the complementary signal of the second input signal IN2 as the second control signal CTR2.

[0101] As mentioned above Figure 5 As described above, in an example embodiment of the interface device, the interface circuit 200 can be defined as a unit circuit, and a plurality of unit circuits can be connected to one output pad that outputs the output signal OUT. For example, one or more first unit circuits and one or more second unit circuits can be connected to one output pad. For example, the values ​​of the resistors R1 and R2 and the capacitors C1 and C2 included in the first unit circuit can be the same as or different from the values ​​of the resistors R1 and R2 and the capacitors C1 and C2 included in the second unit circuit. In addition, the number of unit circuits in operation in the unit circuit connected to each output pad can be changed according to the method by which the interface device sends a signal.

[0102] Figure 19 and Figure 20 2 is a diagram provided to illustrate the operation of an interface circuit according to example embodiments.

[0103] In reference Figure 19 and Figure 20 In the exemplary embodiment described, the interface circuit 210 may output the output signal OUT using a differential signaling method. Therefore, when the first switch element SW1 is turned on and the second switch element SW2 is turned off, the output signal OUT may be raised to a high level, and when the first switch element SW1 is turned off and the second switch element SW2 is turned on, the output signal OUT may be lowered to a low level.

[0104] The first capacitor C1 and the second capacitor C2 can be charged and discharged by the first input signal IN1. As an example, the first input signal IN1 can be input to the first capacitor C1 and the second capacitor C2 as the first control signal and the second control signal. Figure 19 2 is an equivalent circuit diagram of the interface circuit 210.

[0105] Reference Figure 20When the first switching element SW1 is turned on by the first input signal IN1, the second switching element SW2 can be turned off by the second input signal IN2. Furthermore, when the first switching element SW1 is turned on, the first capacitor C1 and the second capacitor C2 can be charged. As the first capacitor C1 and the second capacitor C2 are charged, the output signal OUT can quickly rise from a low level to a high level.

[0106] Furthermore, when the first switching element SW1 is turned off by the first input signal IN1 and the second switching element SW2 is turned on by the second input signal IN2, the output signal OUT can decrease from a high level to a low level. At this time, the first capacitor C1 and the second capacitor C2 can be discharged by the first input signal IN1, and the output signal OUT can quickly decrease from a high level to a low level. Therefore, the slew rate of the output signal OUT can be increased.

[0107] Figure 21 and Figure 22 2 is a diagram provided to illustrate the operation of an interface circuit according to example embodiments.

[0108] In reference Figure 21 and Figure 22 In the described example embodiment, the interface circuit 220 may operate using a single-ended signaling method. Figure 22 When the first switching element SW1 is turned on and the second switching element SW2 is turned off, the output signal OUT may increase from a low level to a high level, and when the first switching element SW1 is turned off and the second switching element SW2 is turned on, the output signal OUT may decrease from a high level to a low level. Furthermore, as one of the first switching element SW1 and the second switching element SW2 is turned on or off, the output signal OUT may have an intermediate level between a high level and a low level. The output signal OUT may be determined by the first input signal IN1 and the second input signal IN2, as shown in Table 1 described above.

[0109] The first capacitor C1 in the interface circuit 220 can be charged and discharged by the first input signal IN1. In detail, the first control signal input to the first capacitor C1 can be the same as the first input signal IN1. A separate second control signal CTR2 can be input to the second capacitor C2. Therefore, Figure 21 , which shows an equivalent circuit of the interface circuit 220. For example, the second control signal CTR2 may have a complementary relationship with the second input signal IN2. The first capacitor C1 may be charged and discharged with the first input signal IN1, and the second capacitor C2 may be charged and discharged with the complementary signal of the second input signal IN2, thereby improving the conversion rate of the output signal OUT. Figure 22 shown.

[0110] Reference Figures 19 to 22The described example embodiments may be Figure 18 The operation of the interface circuit 200 is described in detail. Figure 19 The interface circuit 210 and Figure 21 Each of the illustrated interface circuits 220 may be based on Figure 18 An equivalent circuit of the operation of the interface circuit 200 is shown.

[0111] In addition, different from the reference Figures 19 to 22 In the manner described above, the slew rate of the output signal OUT can be reduced by appropriately selecting the first control signal CTR1 and the second control signal CTR2. For example, when the output signal OUT is a differential signal, the second input signal IN2 can be selected as the first control signal CTR1 and the second control signal CTR2, thereby reducing the slew rate of the output signal OUT. When the output signal OUT is a single-ended signal, the complementary signal of the first input signal IN1 can be selected as the first control signal CTR1, and the second input signal IN2 can be selected as the second control signal CTR2, thereby reducing the slew rate of the output signal OUT. By reducing the slew rate of the output signal OUT, the noise generated in the interface circuit 200 can be reduced, and power consumption can be reduced.

[0112] Figure 23 is a diagram illustrating an interface device according to an example embodiment. Figure 24 and Figure 25 is a diagram provided to illustrate the operation of an interface device according to an example embodiment.

[0113] Reference Figure 23 , the interface device 300 according to the example embodiment may operate using a differential signaling method. The interface device 300 may include a first circuit 310 that outputs a first output signal DN0 and a second circuit 320 that outputs a second output signal DP0. The first output signal DN0 and the second output signal DP0 may have opposite phases and may be transmitted from the output pads TP0 and TP1 to the receiving pads RP0 and RP1 through the first data channel L0 and the second data channel L1. A termination circuit including a termination resistor RT and a termination capacitor CT may be connected to each of the first receiving pad RP0 and the second receiving pad RP1. The receiver RX0 may use the first output signal DN0 and the second output signal DP0 to generate received data D0.

[0114] The first circuit 310 and the second circuit 320 may have the same structure. The first circuit 310 may include a first switching element SW1, a second switching element SW2, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, etc. The operations of the first switching element SW1 and the second switching element SW2 may be controlled by a first input signal IN1 and a second input signal IN2, respectively, and a first output signal DN0 may be output through an output node ON1 and an output pad TP0.

[0115] The second circuit 320 may include a third switching element SW3, a fourth switching element SW4, a third resistor R3, a fourth resistor R4, a third capacitor C3, a fourth capacitor C4, etc. Operations of the third switching element SW3 and the fourth switching element SW4 may be controlled by a third input signal IN3 and a fourth input signal IN4, respectively, and a second output signal DP0 may be output through the output node ON2 and the output pad TP1.

[0116] In a different Figure 23 In the example embodiment shown in the example embodiment, the first circuit 310 may further include a fifth capacitor and a sixth capacitor. For example, the fifth capacitor may be connected between the first resistor R1 and the first switching element SW1 to receive a constant voltage or a separate control signal, and the sixth capacitor may be connected between the second resistor R2 and the second switching element SW2 to receive a constant voltage or a separate control signal.

[0117] In the following, we will refer to Figure 24 and Figure 25 The operation of the interface device 300 will be described.

[0118] Figure 24 1 is a waveform diagram provided to illustrate an example embodiment in which the conversion rates of the first output signal DN0 and the second output signal DP0 are improved. Figure 24 , the first input signal IN1 and the second input signal IN2 may have opposite phases, and the third input signal IN3 and the fourth input signal IN4 may have opposite phases. The first input signal IN1 and the fourth input signal IN4 may have the same phase. Therefore, the first output signal DN0 and the second output signal DP0 may have opposite phases.

[0119] For example, the first input signal IN1 can be selected as the first control signal CTR1 and the second control signal CTR2. Therefore, when the first switch element SW1 is turned on, the first capacitor C1 is charged, and the first output signal DN0 can quickly increase. In addition, when the second switch element SW2 is turned on, the second capacitor C2 is discharged, and the first output signal DN0 can quickly decrease.

[0120] In addition, the third input signal IN3 can be selected as the third control signal CTR3 and the fourth control signal CTR4 input to the second circuit 320. Therefore, when the third switch element SW3 is turned on in the second circuit 320, the second output signal DP0 quickly increases, and when the fourth switch element SW4 is turned on, the second output signal DP0 can quickly decrease. As described above, by controlling the capacitors C1 to C4, Figure 24 Furthermore, the time during which the reception data D0 outputted by the receiver RX0 has a high level or a low level can be sufficiently guaranteed, and the reception side can accurately detect the reception data D0.

[0121] Figure 25 1 and 2 may be waveform diagrams provided to illustrate an example embodiment of reducing the slew rates of the first output signal DN0 and the second output signal DP0. Figure 25 , input signals IN1 to IN4 can be compared with the reference Figure 24 Same as described.

[0122] For example, the second input signal IN2 may be selected as the first control signal CTR1 and the second control signal CTR2 input to the first circuit 310. When the first switching element SW1 is turned on, the first capacitor C1 is discharged, and the first output signal DN0 may slowly increase. In addition, when the second switching element SW2 is turned on, the second capacitor C2 is charged, and the first output signal DN0 may slowly decrease.

[0123] In addition, the fourth input signal IN4 may be selected as the third control signal CTR3 and the fourth control signal CTR4 input to the second circuit 320. Therefore, when the third switch element SW3 is turned on, the second output signal DP0 slowly increases, and when the fourth switch element SW4 is turned on, the second output signal DP0 slowly decreases. Figure 25 As shown, the eye diagram margin and conversion rate of the output signals DN0 and DP0 can be reduced.

[0124] As a result, the interface device 300 according to the exemplary embodiment can intentionally increase or decrease the conversion rate of the output signals DN0 and DP0. When high-speed data communication is not required by intentionally decreasing the conversion rate as described above, the interference of the operation of the interface device 300 on the performance of other adjacent components such as the RF module, the GPS module, etc. can be significantly reduced.

[0125] Figure 26 is a diagram illustrating an interface device according to an example embodiment. Figures 27 to 30 is a diagram provided to illustrate the operation of an interface device according to an example embodiment.

[0126] First refer to Figure 26, the interface device 400 according to an example embodiment may include a first circuit 410 that outputs a first output signal A0, a second circuit 420 that outputs a second output signal B0, and a third circuit 430 that outputs a third output signal C0. Figure 26 The interface device 400 of the illustrated example embodiment can support communication according to the C-Phy interface in accordance with the MIPI standard. The first to third output signals A0 to C0 can have any one of a high level, a low level, and an intermediate level, and the first to third output signals A0 to C0 may not have the same level.

[0127] The first output signal A0 may be input to the first receiving pad RP0 along the first data channel L0, the second output signal B0 may be input to the second receiving pad RP1 along the second data channel L1, and the third output signal C0 may be input to the third receiving pad RP2 through the third data channel L2. A termination circuit may be connected to each of the receiving pads RP0 to RP2, and the termination circuit may include a termination resistor RT and a termination capacitor CT.

[0128] The first to third receivers RX0 to RX2 may respectively use the first to third output signals A0 to C0 to generate first to third received data AB0, BC0, and CA0. The first receiver RX0 may use the difference between the first output signal A0 and the second output signal B0 to generate the first received data AB0, and the second receiver RX1 may use the difference between the second output signal B0 and the third output signal C0 to generate the second received data BC0. The third receiver RX2 may generate the third received data CA0 by using the difference between the third output signal C0 and the first output signal A0. In an example embodiment, the receiving side may convert the first to third received data AB0, BC0, and CA0 into state information having three bits, and may use the change in the state information to generate symbol information.

[0129] The first circuit 410, the second circuit 420, and the third circuit 430 may have the same structure. In an example embodiment, the first circuit 410 may include a first switching element SW1, a second switching element SW2, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, etc. The first capacitor C1 and the second capacitor C2 may be connected to the output node ON1. The first capacitor C1 may be charged and discharged by a first control signal CTR1, and the second capacitor C2 may be charged and discharged by a second control signal CTR2.

[0130] In an example embodiment, the second circuit 420 may include a third switching element SW3, a fourth switching element SW4, a third resistor R3, a fourth resistor R4, a third capacitor C3, a fourth capacitor C4, etc. The third capacitor C3 and the fourth capacitor C4 may be connected to the output node ON2. The third capacitor C3 may be charged and discharged by a third control signal CTR3, and the fourth capacitor C4 may be charged and discharged by a fourth control signal CTR4.

[0131] In an example embodiment, the third circuit 430 may include a fifth switching element SW5, a sixth switching element SW6, a fifth resistor R5, a sixth resistor R6, a fifth capacitor C5, a sixth capacitor C6, etc. The fifth capacitor C5 and the sixth capacitor C6 may be connected to the output node ON3. The fifth capacitor C5 may be charged and discharged by a fifth control signal CTR5, and the sixth capacitor C6 may be charged and discharged by a sixth control signal CTR6.

[0132] In the following, we will refer to Figures 27 to 30 The operation of the interface device 400 is described.

[0133] Figure 27 and Figure 28 This corresponds to an operation embodiment in which the conversion rate of the first output signal A0 to the third output signal C0 can be increased. Figure 27 , the size of each of the first to third output signals A0 to C0 may be determined as one of a high level, a low level, and an intermediate level, and the first to third output signals A0 to C0 may not have the same level at the same time.

[0134] Figure 28 is shown with Figure 27 FIGURE 4 illustrates input signals IN1 to IN6 and control signals CTR1 to CTR6 corresponding to first output signals A0 to third output signal C0. Referring to first circuit 410 as an example, first control signal CTR1 and first input signal IN1 may be the same signal, and second control signal CTR2 may be the complement of second input signal IN2. By selecting first control signal CTR1 and second control signal CTR2 as described above, the conversion rate of first output signal A0 may be improved. Similarly, in second circuit 420, third control signal CTR3 may be the same signal as third input signal IN3, and fourth control signal CTR4 may be the complement of fourth input signal IN4. Furthermore, in third circuit 430, fifth control signal CTR5 may be the same signal as fifth input signal IN5, and sixth control signal CTR6 may be the complement of sixth input signal IN6.

[0135] Figure 29 and Figure 30This may correspond to an operation embodiment in which the conversion rate of the first output signal A0 to the third output signal C0 may be reduced. Figure 29 , the size of each of the first to third output signals A0 to C0 is determined to be one of a high level, a low level, and an intermediate level, and the first to third output signals A0 to C0 may not have the same level at the same time.

[0136] Figure 30 is shown with Figure 29 FIGURE 4 illustrates input signals IN1 to IN6 and control signals CTR1 to CTR6 corresponding to first to third output signals A0 to C0. Referring to first circuit 410 as an example, first control signal CTR1 may be the complementary signal of first input signal IN1, and second control signal CTR2 may be equal to second input signal IN2. Thus, by selecting first control signal CTR1 and second control signal CTR2, the slew rate of first output signal A0 may be reduced. Similarly, in second circuit 420, third control signal CTR3 may be the complementary signal of third input signal IN3, and fourth control signal CTR4 may be equal to fourth input signal IN4. Furthermore, in third circuit 430, fifth control signal CTR5 may be the complementary signal of fifth input signal IN5, and sixth control signal CTR6 may be equal to sixth input signal IN6.

[0137] As reference Figure 27 and Figure 28 As described above, the conversion rate from the first output signal A0 to the third output signal C0 can be increased to improve the operating performance of the interface device 400. Figure 29 and Figure 30 As described above, the conversion rate of the first output signal A0 to the third output signal C0 can be reduced to improve the noise characteristic of the interface device 400 and reduce power consumption.

[0138] Figure 31 is a block diagram of a mobile system including an interface circuit according to an example embodiment.

[0139] Reference Figure 31 , the mobile system 1000 may include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, DRAMs 1500a and 1500b, flash memory devices 1600a and 1600b, input / output (I / O) devices 1700a and 1700b, and an application processor (hereinafter referred to as “AP”) 1800.

[0140] The mobile system 1000 may be implemented by a laptop computer, a portable terminal, a smart phone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device. In addition, the mobile system 1000 may be implemented by a server or a personal computer.

[0141] Camera 1100 can capture still images or videos according to user control. Mobile system 1000 can obtain specific information by using still images / videos captured by camera 1100, or can convert still images / videos into other types of data, such as text, and store the converted data. In an example embodiment, mobile system 1000 can recognize a string of characters included in a still image / video captured by camera 1100 and provide a text or audio translation corresponding to the string of characters. In this way, the use areas of camera 1100 in mobile system 1000 are becoming increasingly diverse. In an example embodiment, camera 1100 can transmit data, such as still images / videos, to AP 1800 using a D-Phy or C-Phy interface based on the MIPI standard.

[0142] The display 1200 may be implemented in various forms, such as a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, an active-matrix organic light-emitting diode (AM-OLED), a plasma display panel (PDP), a field emission display (FED), or electronic paper. In an exemplary embodiment, the display 1200 may also serve as an input device for the mobile system 1000 by providing a touch screen function. In addition, the display 1200 may be integrally provided with a fingerprint sensor or the like to provide security functions for the mobile system 1000. In an exemplary embodiment, the AP 1800 may transmit image data to be displayed on the display 1200 to the display 1200 using a D-Phy or C-Phy interface based on the MIPI standard.

[0143] The interface device described with reference to the exemplary embodiments may be applied to communication between the AP 1800 and the display 1200, and communication between the AP 1800 and the camera 1100. At least one of the AP 1800, the display 1200, and the camera 1100 appropriately selects a control signal for charging and discharging a capacitor included in the interface device as needed, and thus, the conversion rate of the output signal output by the interface device may be increased or decreased.

[0144] For example, by increasing the conversion rate of the output signal output by the interface device, the data transmission speed between the AP 1800 and the display 1200 and / or between the AP 1800 and the camera 1100 can be increased, and the noise characteristics can be improved. In addition, by reducing the conversion rate of the output signal output by the interface device, the impact of the communication between the AP 1800 and the display 1200 and / or between the AP 1800 and the camera 1100 on other components can be significantly reduced, and power consumption can be reduced.

[0145] The audio processor 1300 may process audio data stored in the flash memory devices 1600a and 1600b, or may process audio data included in content received externally through the modem 1400 or the I / O devices 1700a and 1700b. For example, the audio processor 1300 may perform various processes such as encoding / decoding, amplification, and noise filtering on the audio data.

[0146] Modem 1400 modulates and transmits signals to transmit / receive wired / wireless data, while demodulating signals received from the outside to restore the original signals. I / O devices 1700a and 1700b are devices that provide digital input and output, and may include: a port that can be connected to an external recording medium, an input device such as a touch screen or mechanical button keys, an output device that can output vibration in a tactile manner, etc. In some examples, I / O devices 1700a and 1700b can be connected to an external recording medium via a port such as a USB, a lightning cable, an SD card, a micro SD card, a DVD, a network adapter, etc.

[0147] The AP 1800 may control the overall operation of the mobile system 1000. Specifically, the AP 1800 may control the display 1200 so that a portion of the content stored in the flash memory devices 1600a and 1600b is displayed on the screen. Furthermore, when a user input is received through the I / O devices 1700a and 1700b, the AP 1800 may perform a control operation corresponding to the user input.

[0148] The AP 1800 may be provided as a system-on-chip (SoC) that drives applications, an operating system (OS), and the like. Furthermore, the AP 1800 may be included in other devices included in the mobile system 1000, for example, included in the DRAM 1500a, the flash memory 1620, and / or the memory controller 1610, and included in a single semiconductor package. For example, at least one device other than the AP 1800 may be provided in a package such as a package-on-package (PoP), a ball grid array (BGA), a chip scale package (CSP), a system-in-package (SIP), a multi-chip package (MCP), a wafer-level fabrication package (WFP), or a wafer-level processing stack package (WSP). The kernel of the operating system running on the AP 1800 may include an input / output scheduler and a device driver for controlling the flash memory devices 1600a and 1600b. The device driver may control access performance of the flash memory devices 1600a and 1600b by referring to the number of synchronization queues managed by the I / O scheduler, or may control a CPU mode, a dynamic voltage frequency scaling (DVFS) level, etc. inside the SoC.

[0149] In an exemplary embodiment, the AP 1800 may include a processor block that executes operations or drives an application program and / or an operating system, and various other peripheral components connected via the processor block and a system bus. The peripheral components may include a memory controller, an internal memory, a power management block, an error detection block, and a monitoring block. The processor block may include one or more cores, and when the processor block includes multiple cores, each core includes a cache memory, and a common cache shared by the cores may be included in the processor block.

[0150] In an exemplary embodiment, AP 1800 may include an accelerator block 1820, which is a dedicated circuit for AI data calculations. In an exemplary embodiment, according to an exemplary embodiment, a separate accelerator chip may be provided separately from AP 1800, and DRAM 1500b may be additionally connected to accelerator block 1820 or the accelerator chip. Accelerator block 1820 is a functional block that specializes in performing specific functions of AP 1800 and includes: a graphics processing unit (GPU), which is a functional block that specializes in performing graphics data processing; a neural processing unit (NPU), which is a block for specializing in performing AI calculations and reasoning; and a data processing unit (DPU), which is a block specializing in data transmission.

[0151] According to an example embodiment, the mobile system 1000 may include a plurality of DRAMs 1500a and 1500b. In an example embodiment, the AP 1800 may include a controller 1810 for controlling the DRAMs 1500a and 1500b, and the DRAM 1500a may be directly connected to the AP 1800.

[0152] The AP 1800 controls the DRAM by setting commands and mode register settings (MRS) that comply with JEDEC standard specifications, or can communicate by establishing specifications and functions such as a DRAM interface protocol for low voltage, high speed, reliability, and CRC / ECC required by the mobile system 1000. For example, the AP 1800 can communicate with the DRAM 1500a via an interface that complies with JEDEC standards such as LPDDR4 and LPDDR5. In an example embodiment, the AP 1800 can set a new DRAM interface protocol to control the DRAM 1500b used for an accelerator, where an accelerator chip provided separately from the accelerator block 1820 or the AP 1800 has a higher bandwidth than the DRAM 1500a.

[0153] Despite Figure 31 Only DRAMs 1500a and 1500b are shown, but the configuration of mobile system 1000 is not necessarily limited to this type. For example, other memories in addition to DRAMs 1500a and 1500b may be included in mobile system 1000 depending on the bandwidth, response speed, and voltage conditions of AP 1800 or accelerator block 1820. In an example, controller 1810 and / or accelerator block 1820 may control various memories such as PRAM, SRAM, MRAM, RRAM, FRAM, hybrid RAM, etc. DRAMs 1500a and 1500b have relatively low latency and relatively high bandwidth compared to I / O devices 1700a and 1700b or flash memory devices 1600a and 1600b. DRAMs 1500a and 1500b may be initialized at a power-on point of the mobile system 1000 and may be used as a temporary storage location for an operating system and application data or as an execution space for various software codes when the operating system and application data are loaded.

[0154] In DRAM 1500a and 1500b, addition / subtraction / multiplication / division arithmetic operations and vector operations, address operations, or FFT operation data can be stored. In another embodiment, DRAM 1500a and 1500b can be provided as a memory processing (PIM) equipped with a computing function. For example, a function for executing a function for reasoning in DRAM 1500a and 1500b can be executed. In this case, reasoning can be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training operation of a model through various data training operations and an inference operation using the trained model to identify data. For example, the function for reasoning may include a hyperbolic tangent function, a sigmoid function, and a rectified linear unit (ReLU) function.

[0155] As an example embodiment, an image captured by a user through the camera 1100 may be signal processed and stored in the DRAM 1500 b , and the accelerator block 1820 or accelerator chip may perform AI data operations for recognizing data using the data stored in the DRAM 1500 b and a function for inference.

[0156] According to an example embodiment, the mobile system 1000 may include a plurality of storages or a plurality of flash memory devices 1600a and 1600b having a larger capacity than the DRAMs 1500a and 1500b. The flash memory devices 1600a and 1600b may include a memory controller 1610 and a flash memory 1620. The memory controller 1610 receives a control command and data from the AP 1800, writes data to the flash memory 1620 in response to a control command, or reads data stored in the flash memory 1620 to access the AP 1800, and may transmit data to the AP 1800.

[0157] According to an example embodiment, the accelerator block 1820 or the accelerator chip can use the flash memory devices 1600a and 1600b to perform training operations and AI data calculations. In an example embodiment, operation logic capable of performing predetermined operations within the flash memory devices 1600a and 1600b can be implemented in the memory controller 1610, and the operation logic can appropriately perform at least a portion of the training operations and inference AI data operations performed by the AP 1800 and / or the accelerator block 1820 using data stored in the flash memory 1620.

[0158] In an exemplary embodiment, the AP 1800 may include an interface 1830, and thus, the flash memory devices 1600a and 1600b may be directly connected to the AP 1800. For example, the AP 1800 may be implemented as an SoC, the flash memory device 1600a may be implemented as a chip separate from the AP 1800, and the AP 1800 and the flash memory device 1600a may be mounted in one package. However, exemplary embodiments are not limited thereto, and a plurality of flash memory devices 1600a and 1600b may be electrically connected to the mobile system 1000 through a connector.

[0159] The flash memory devices 1600a and 1600b can store data such as still images / movies captured by the camera 1100, or can store data received through a communication network and / or ports included in the I / O devices 1700a and 1700b, and for example, can store augmented reality / virtual reality content, high-definition (HD) content, or ultra-high-definition (UHD) content.

[0160] As described above, according to example embodiments, by connecting a capacitor to an output terminal of an interface circuit and by charging or discharging the capacitor according to on / off operations of a first switching element and a second switching element included in the interface circuit, a conversion rate of an output signal output from the interface circuit can be adjusted.

[0161] While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope as defined in the appended claims.

Claims

1. An interface circuit comprising: a first switching element controlled by a first input signal and connected to a first power supply node configured to supply a first power supply voltage and an output node configured to output an output signal; a second switching element controlled by a second input signal different from the first input signal and connected to the output node and a second power supply node configured to supply a second power supply voltage lower than the first power supply voltage; a first resistor connected between the first power supply node and the first switching element; a second resistor connected between the second power supply node and the second switching element; a first capacitor connected to the output node and controlled by a first control signal; a second capacitor connected to the output node and controlled by a second control signal different from the first control signal; a third capacitor connected to a node between the first resistor and the first switching element; as well as A fourth capacitor is connected to a node between the second resistor and the second switching element.

2. The interface circuit according to claim 1, wherein: The first control signal is equal to the first input signal.

3. The interface circuit according to claim 1, wherein: The second control signal is complementary to the second input signal.

4. The interface circuit according to claim 1, wherein: The third capacitor is controlled by a third control signal, and the fourth capacitor is controlled by a fourth control signal.

5. The interface circuit according to claim 4, wherein: The third control signal and the fourth control signal are constant voltage signals, and The magnitude of the third control signal is equal to the magnitude of the fourth control signal.

6. The interface circuit according to claim 4, wherein: The third control signal is a first constant voltage signal, Wherein, the fourth control signal is a second constant voltage signal, and The magnitude of the second constant voltage signal is different from the magnitude of the first constant voltage signal.

7. The interface circuit according to claim 4, wherein: The third control signal is equal to the first control signal, and The fourth control signal is equal to the second control signal.

8. The interface circuit according to claim 1, wherein: The third capacitor includes a parasitic capacitor included in the first switching element.

9. The interface circuit according to claim 1, wherein: The magnitude of the output signal includes one of a first level, a second level greater than the first level, and a third level greater than the second level.

10. The interface circuit according to claim 9, wherein: The second capacitor is charged based on the magnitude of the output signal increasing from the first level to the second level. wherein, based on the magnitude of the output signal increasing from the second level to the third level, the first capacitor is charged, and Wherein, based on the magnitude of the output signal increasing from the first level to the third level, the first capacitor and the second capacitor are charged simultaneously.

11. The interface circuit according to claim 9, wherein: The first capacitor is discharged based on the magnitude of the output signal decreasing from the third level to the second level. wherein, based on the magnitude of the output signal decreasing from the second level to the first level, the second capacitor is discharged, and Wherein, based on the magnitude of the output signal decreasing from the third level to the first level, the first capacitor and the second capacitor are discharged simultaneously.

12. The interface circuit according to claim 1, wherein: The magnitude of the output signal includes one of a first level and a second level greater than the first level.

13. The interface circuit according to claim 12, wherein: Based on the magnitude of the output signal increasing from the first level to the second level, the first capacitor is charged, and Wherein, based on the magnitude of the output signal decreasing from the second level to the first level, the second capacitor is discharged.

14. An interface device comprising: a plurality of interface circuits, wherein each of the plurality of interface circuits includes a first switching element connected in series to a second switching element, and a first capacitor and a second capacitor connected to an output terminal, wherein the first switching element and the second switching element are connected to the output terminal; as well as a controller configured to determine a plurality of output signals corresponding to the plurality of interface circuits by controlling the first switching element and the second switching element, and configured to adjust conversion rates of the plurality of output signals by charging and discharging the first capacitor and the second capacitor, and The controller inputs a first input signal to a control terminal of the first switching element and the first capacitor.

15. The interface device according to claim 14, wherein: Based on the fact that the plurality of output signals are differential signals, the controller is further configured to input the first input signal to the second capacitor.

16. The interface device according to claim 14, wherein: Based on the plurality of output signals being multi-level signals, the controller is further configured to input a second input signal to the control terminal of the second switching element, and input a complementary signal of the second input signal to the second capacitor.

17. The interface device according to claim 14, wherein: The capacitance of the first capacitor is equal to the capacitance of the second capacitor.

18. An interface circuit comprising: a first switching element configured to receive a first power supply voltage and be turned on and off by a first input signal; a second switching element configured to receive a second power supply voltage lower than the first power supply voltage and to be turned on and off by a second input signal different from the first input signal; a first capacitor, wherein a first terminal of the first capacitor is connected to an output node, the first switching element and the second switching element are connected to the output node, and a second terminal of the first capacitor is configured to receive a first control signal; as well as a second capacitor, wherein a first terminal of the second capacitor is connected to the output node and a second terminal of the second capacitor is configured to receive a second control signal different from the first control signal, wherein, based on the output signal output from the output node rising, at least one of the first control signal and the second control signal rises from a low level to a high level, and Wherein, based on the output signal decreasing, the at least one of the first control signal and the second control signal decreases from the high level to the low level.

19. The interface circuit according to claim 18, wherein: Based on the amount of change in the magnitude of the output signal being a first value, only one of the first control signal and the second control signal is changed, and Wherein, based on the change amount of the magnitude of the output signal being a second value greater than the first value, the first control signal and the second control signal are changed simultaneously.

20. The interface circuit according to claim 18, wherein: The first control signal is equal to the first input signal, and the second control signal is complementary to the second input signal.

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