Integrated chip and method for forming the same

Abstract

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed above a substrate and a top electrode disposed above the bottom electrode. A ferroelectric switching layer is disposed between the bottom electrode and the top electrode. The ferroelectric switching layer is configured to change polarization based on one or more voltages applied to the bottom electrode or the top electrode. A seed layer is disposed between the bottom electrode and the top electrode. The seed layer and the ferroelectric switching layer have a non-monoclinic phase. Embodiments of the present application also relate to a method for forming an integrated chip.

Description

Technical Field

[0001] Embodiments of the present application relate to an integrated chip and a method for forming the same. Background Art

[0002] Many modern electronic devices contain electronic memory configured to store data. Ferroelectric memory can be either volatile memory or non-volatile memory. Volatile memory stores data when power is applied, while non-volatile memory can still store data when power is removed. Ferroelectric random access memory (FeRAM) devices are promising candidates for the next generation of non-volatile memory technology. This is because FeRAM devices offer many advantages, including short write times, high endurance, low power consumption, and low sensitivity to radiation damage. Summary of the invention

[0003] Some embodiments of the present application provide an integrated chip, comprising: a bottom electrode, arranged above a substrate; a top electrode, arranged above the bottom electrode; a ferroelectric switching layer, arranged between the bottom electrode and the top electrode, wherein the ferroelectric switching layer is configured to change polarization based on one or more voltages applied to the bottom electrode or the top electrode; and a seed layer, arranged between the bottom electrode and the top electrode, wherein the seed layer and the ferroelectric switching layer include a non-monoclinic phase.

[0004] Other embodiments of the present application provide an integrated chip, comprising: a bottom electrode, arranged above a substrate; a top electrode, arranged above the bottom electrode; a seed layer, arranged between the bottom electrode and the top electrode, wherein the seed layer comprises a non-monoclinic phase; a ferroelectric switching layer, arranged between the bottom electrode and the top electrode, wherein the ferroelectric switching layer comprises a first region having a monoclinic phase and a second region having a non-monoclinic phase.

[0005] Still other embodiments of the present application provide a method for forming an integrated chip, comprising: forming a bottom electrode layer above a substrate; forming a seed layer above the bottom electrode layer; forming a ferroelectric switching layer above the bottom electrode layer and contacting the seed layer, wherein the ferroelectric switching layer is formed to have a first region and a second region, the first region has a first crystal phase, and the second region has a different crystal phase; forming a top electrode layer above the ferroelectric switching layer; and performing one or more patterning processes on the bottom electrode layer, the seed layer, the ferroelectric switching layer, and the top electrode layer to form a ferroelectric random access memory (FeRAM) device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 Cross-sectional views of some embodiments of an integrated chip having a ferroelectric random access memory (FeRAM) device including a data storage structure including a seed layer configured to enhance the performance of the FeRAM device are shown.

[0008] FIG. 2A to FIG. 2B Some additional embodiments of integrated chips having FeRAM devices including data storage structures including a seed layer are shown.

[0009] Figure 3 Some additional embodiments of integrated chips having FeRAM devices including data storage structures including a seed layer are shown in cross-sectional views.

[0010] Figure 4 A cross-sectional view of a more detailed embodiment of an integrated chip having a FeRAM device including a data storage structure including a seed layer is shown.

[0011] FIG. 5A to FIG. 6 A cross-sectional view of an additional embodiment of an integrated chip having a FeRAM device including a data storage structure including one or more seed layers is shown.

[0012] FIG. 7A to FIG. 7B A graph showing the read window of FeRAM devices with different data storage structures is shown.

[0013] Figures 8 to 21 Cross-sectional views of embodiments of some methods of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer are shown.

[0014] Fig. 22 A flow chart illustrating a method of some embodiments of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer.

[0015] Figures 23 to 30 Cross-sectional views of some additional embodiments of methods of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer are shown.

[0016] Fig.31Flowcharts illustrating some additional embodiments of methods of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer.

[0017] Figure 32 to Figure 39 Cross-sectional views of some additional embodiments of methods of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer are shown.

[0018] Fig.40 Flowcharts illustrating some additional embodiments of methods of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer.

[0019] Figures 41 to 48 Cross-sectional views of some additional embodiments of methods of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer are shown.

[0020] Fig.49 Flowcharts illustrating some additional embodiments of methods of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various embodiments. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0023] A ferroelectric random access memory (FeRAM) device has a bottom electrode separated from a top electrode by a data storage structure comprising a ferroelectric material. Ferroelectric materials have an intrinsic electric dipole that can be switched between opposite polarities by applying an external electric field. The different polarities provide the FeRAM device with different capacitances, which can be sensed by the voltage on the bit line during a read operation. The different capacitances represent different data states (e.g., logical "0" or "1"), allowing the FeRAM device to store data digitally.

[0024] The read window is the voltage difference on the bit line between a low data state (e.g., a logic "0") and a high data state (e.g., a logic "1"). As FeRAM device size decreases, the operating voltage of the FeRAM device also decreases. The reduction in operating voltage reduces the size of the read window. For example, a FeRAM device having a width of about 0.27 micrometers (μm) may have an average overlap of about 3% between the low voltage state and the high voltage state, while a smaller FeRAM device having a width of about 0.135 μm may have an average overlap of about 37% between the low voltage state and the high voltage state. The considerable overlap of the smaller FeRAM device reduces the ability of the sensing circuit to distinguish between the low voltage state and the high voltage state during a read operation.

[0025] It should be understood that some ferroelectric materials used in data storage structures (e.g., hafnium zirconium oxide, HfZrO) can be formed to have a monoclinic phase, however, the monoclinic phase may have a negative impact on the ferroelectricity of the data storage structure, which may result in a relatively small read window (i.e., a relatively small difference in the bit line voltage between a low data state and a high data state). During the operation of the FeRAM device, a sufficiently large read window is required because a large read window makes it easy to distinguish different data states from each other during a read operation.

[0026] In some embodiments, the present disclosure relates to an integrated chip including a data storage structure, the data storage structure having a seed layer, the seed layer having a crystalline phase (i.e., a crystal structure) configured to improve the ferroelectricity of the data storage structure. In some embodiments, the integrated chip may include a bottom electrode disposed above a substrate and a top electrode disposed above the bottom electrode. The data storage structure includes a ferroelectric switching layer and a seed layer arranged between the bottom electrode and the top electrode. The seed layer has a crystalline phase (e.g., an orthorhombic phase) configured to change the crystalline phase of the ferroelectric switching layer adjacent to the seed layer region to a non-monoclinic phase (e.g., to an orthorhombic phase). Changing the crystalline phase of the ferroelectric switching layer adjacent to the seed layer region to a non-monoclinic phase improves the ferroelectricity of the data storage structure, and correspondingly improves the performance (e.g., read window) of the FeRAM device.

[0027] Figure 1A cross-sectional view of some embodiments of an integrated chip 100 having a ferroelectric random access memory (FeRAM) device including a data storage structure including a seed layer configured to enhance the performance of the FeRAM device is shown.

[0028] The integrated chip 100 includes a FeRAM device 103 disposed within a dielectric structure 104 above a substrate 102. The dielectric structure 104 includes a plurality of stacked interlayer dielectric (ILD) layers. In some embodiments, the plurality of stacked ILD layers may include one or more lower ILD layers 104L disposed between the FeRAM device 103 and the substrate 102, and an upper ILD layer 104U surrounding the FeRAM device 103. In some embodiments, the one or more lower ILD layers 104L surround a bottom interconnect 106 disposed below the FeRAM device 103.

[0029] The ferroelectric device 103 includes a bottom electrode 108 coupled to a bottom interconnect 106. A data storage structure 109 is disposed between the bottom electrode 108 and a top electrode 114. A top electrode via 116 extends through the upper ILD layer 104U to connect the top electrode 114. The data storage structure 109 includes a seed layer 110 and a ferroelectric switching layer 112. In some embodiments, the seed layer 110 may be located between the ferroelectric switching layer 112 and the bottom electrode 108. In some embodiments, the seed layer 110 directly contacts the ferroelectric switching layer 112.

[0030] The seed layer 110 is configured to influence the crystal phase (i.e., crystal structure) of the ferroelectric switching layer 112 during the manufacture of the FeRAM device 103. For example, during the manufacture of the FeRAM device 103, the seed layer 110 may be configured as a nucleation site for changing the crystal phase of the ferroelectric switching layer 112 (e.g., during epitaxial growth of the ferroelectric switching layer 112, during an annealing process performed after the ferroelectric switching layer 112 is deposited, etc.). By changing the crystal phase of the ferroelectric switching layer 112, the seed layer 110 can cause at least a portion of the ferroelectric switching layer 112 to have a non-monoclinic crystal phase. It has been noted that the ferroelectric switching layer 112 having a non-monoclinic crystal phase will have a higher ferroelectricity than the ferroelectric switching layer 112 having a monoclinic crystal phase, thereby causing the seed layer 110 to improve the overall ferroelectricity of the data storage structure 109. Improving the ferroelectricity of the data storage structure 109 improves the performance (e.g., read window) of the FeRAM device 103.

[0031] FIG. 2A to FIG. 2B Some additional embodiments of integrated chips having FeRAM devices including data storage structures including a seed layer are shown.

[0032] Figure 2AA cross-sectional view 200 of an integrated chip is shown. As shown in the cross-sectional view 200, the integrated chip includes a FeRAM device 103, which includes a data storage structure 109 located between a bottom electrode 108 and a top electrode 114. The data storage structure 109 includes a seed layer 110 and a ferroelectric switching layer 112. The seed layer 110 is disposed on the bottom electrode 108, and the ferroelectric switching layer 112 is disposed on the seed layer 110, so that the seed layer 110 separates the ferroelectric switching layer 112 from the bottom electrode 108.

[0033] In some embodiments, the seed layer 110 may include zirconium oxide (eg, ZrO x ), hafnium oxide (eg, HfO x ), silicon oxide (e.g., SiO x ), tantalum oxide (e.g., TaO x ), aluminum oxide (e.g., AlO x ), titanium oxide (e.g., TiO x ), yttrium oxide (such as YO x ), gadolinium oxide (eg, GdO x ), lanthanum oxide (eg, LaO x ), strontium oxide (eg, SrO x ) etc. In some embodiments, the ferroelectric switching layer 112 may include a high-k dielectric material. For example, in some embodiments, the ferroelectric switching layer 112 may include hafnium oxide, hafnium zirconium oxide (HZO), lead zirconate titanate (PZT), etc.

[0034] The seed layer 110 includes a first crystalline phase. The ferroelectric switching layer 112 includes a first region 202 adjacent to the seed layer 110 and a second region 204 separated from the seed layer 110 by the first region 202. In some embodiments, the first region 202 contacts the seed layer 110. The first region 202 of the ferroelectric switching layer 112 has a first crystalline phase, and the second region 204 of the ferroelectric switching layer 112 has a second crystalline phase, which is different from the first crystalline phase. In some embodiments, the first crystalline phase is a non-monoclinic crystalline phase. For example, in some embodiments, the first crystalline phase may include an orthorhombic crystalline phase, a cubic crystalline phase, a tetragonal crystalline phase, etc. In some embodiments, the second crystalline phase is a monoclinic crystalline phase.

[0035] In some embodiments, the seed layer 110 may have a thickness of about 10 angstroms. To date In another embodiment, the seed layer 110 may have a thickness 206 between about To date Between To date If the thickness 206 of the seed layer 110 is greater than about The first region 202 of the ferroelectric switching layer 112 is less likely to have a non-monoclinic phase. In some embodiments, the ferroelectric switching layer 112 may have a thickness 208 in the range of about To date Between To date In some embodiments, first region 202 of ferroelectric switching layer 112 can have a thickness between about 10% and about 100%, between about 20% and about 90%, or other similar values ​​of thickness 208.

[0036] In some embodiments, the seed layer 110 may include a material having a crystallization temperature of less than or equal to about 800° C. (i.e., a temperature at which the material achieves a non-monoclinic phase). In some embodiments, the seed layer 110 may include a material having a crystallization temperature of less than or equal to about 500° C., a crystallization temperature of less than or equal to about 400° C., or a crystallization temperature of less than or equal to about 300° C. For the seed layer, having a relatively low crystallization temperature (e.g., less than or equal to about 800° C., less than or equal to about 500° C., etc.) allows it to be formed to have a non-monoclinic phase without damaging other components of the integrated chip that may be sensitive to high temperatures (e.g., a gate dielectric layer of a transistor device within the substrate 102).

[0037] In some embodiments, the seed layer 110 can affect the grain size and / or orientation of grains (i.e., crystallites) within the ferroelectric switching layer 112. For example, the seed layer 110 can be configured to reduce the grain size of grains within the ferroelectric switching layer 112. For example, the ferroelectric switching layer 112 includes a hafnium zirconium oxide (HZO) film having a hafnium to zirconium ratio of 1:1, and the seed layer 110 can cause the grain size to be between about 0.5 angstroms and about 0.5 angstroms. to about 20 nanometers (nms), or about to about 10 nms, or other similar values. It has been noted that as the grain size of the grains in the ferroelectric switching layer 112 decreases, the percentage of the ferroelectric switching layer 112 having a non-monoclinic phase may increase. Therefore, in terms of reducing the grain size of the grains in the ferroelectric switching layer 112, the seed layer 110 can reduce the percentage of the ferroelectric switching layer 112 having a monoclinic phase and further improve the performance (e.g., read window) of the FeRAM device 103.

[0038] In some additional and / or optional embodiments, the seed layer 110 may be configured to change the crystal orientation of the ferroelectric switching layer 112. For example, the seed layer 110 may cause the ferroelectric switching layer 112 to have a crystal phase (i.e., a crystal structure) with a Miller index of (110) or (111). The ferroelectric switching layer 112 having a Miller index of (110) or (111) further improves the orthorhombic phase growth within the ferroelectric switching layer 112 and further improves the performance (e.g., read window) of the FeRAM device 103.

[0039] During operation, a bias applied to the bottom electrode 108 and / or the top electrode 114 is used to polarize the data storage structure 109 (e.g., move ions upward or downward within the crystal structure of the ferroelectric switching layer). The polarization is maintained even after the bias is removed. The polarization of the data storage structure 109 represents the data state (e.g., logical "0" or "1") stored by the data storage structure 109.

[0040] The magnetic response of the data storage structure 109 will follow a hysteresis loop. Figure 2B A graph 210 is shown showing exemplary hysteresis loops corresponding to FeRAM devices having different crystalline phases. Graph 210 shows a first hysteresis loop 212 corresponding to a FeRAM device having a data storage structure that does not include a disclosed seed layer and a second hysteresis loop 216 corresponding to a FeRAM device having a disclosed seed layer (e.g., Figure 2A A FeRAM device having a data storage structure of a seed layer 110).

[0041] As shown by the first hysteresis loop 212, for the data storage structure that does not include the disclosed seed layer, the difference 214 between the polarization of the high data state and the polarization of the low data state is relatively small. However, as shown by the second hysteresis loop 216, for the data storage structure that includes the seed layer, the difference 218 between the polarization of the high data state and the polarization of the low data state is relatively large. The relatively large difference in polarization allows the high data state to be distinguished from the low data state, thereby improving the operation (i.e., read window) of the FeRAM device.

[0042] Figure 3 Some additional embodiments of an integrated chip 300 having a FeRAM device including a data storage structure including a seed layer are shown in cross-sectional views.

[0043] The integrated chip 300 includes a FeRAM device 302 disposed within a dielectric structure 104 above a substrate 102. The FeRAM device 302 has a data storage structure 304 disposed between a bottom electrode 108 and a top electrode 114. The data storage structure 304 includes a ferroelectric switching layer 112 disposed on the bottom electrode 108. A seed layer 110 is disposed on the ferroelectric switching layer 112 such that the ferroelectric switching layer 112 separates the seed layer 110 from the bottom electrode 108. In some embodiments, the ferroelectric switching layer 112 may contact a lower surface of the seed layer 110. In some embodiments, having the seed layer 110 disposed above the ferroelectric switching layer 112 may simplify the fabrication of the FeRAM device 302 by eliminating one or more process steps (e.g., annealing) used during fabrication.

[0044] The ferroelectric switching layer 112 has a first region 202 and a second region 204. The first region 202 is adjacent to the seed layer 110, and the second region 204 is separated by the first region 202 and the seed layer 110. In some embodiments, the first region 202 contacts the seed layer 110. The first region 202 has a first crystalline phase, and the second region 204 has a second crystalline phase different from the first crystalline phase. In some embodiments, the first region 202 may have a non-monoclinic phase, and the second region 204 may have a monoclinic phase.

[0045] Figure 4 4 shows a cross-sectional view of a more detailed embodiment of an integrated chip 400 having a FeRAM device including a data storage structure including a seed layer.

[0046] The integrated chip 400 includes a FeRAM device 103 disposed within a dielectric structure 104 disposed above a substrate 102. In some embodiments, the dielectric structure 104 includes a plurality of stacked interlayer dielectric (ILD) layers 104a-104e. The plurality of stacked ILD layers 104a-104e include one or more lower ILD layers 104a-104d laterally surrounding one or more lower interconnect layers 404-408, the lower interconnect layers 404-408 configured to couple the FeRAM device 103 to an access device 402 disposed within the substrate 102. In some embodiments, the one or more lower interconnect layers 404-408 may include a conductive contact 404, an interconnect line 406, and an interconnect via 408. In some embodiments, the access device 402 may include a transistor device (e.g., a MOSFET device, a BJT, etc.)

[0047] In some embodiments, the lower insulating structure 410 is disposed above one or more lower ILD layers 104a-104d. The lower insulating structure 410 includes sidewalls forming an opening extending through the lower insulating structure 410. In different embodiments, the lower insulating structure 410 may include one or more of silicon nitride, silicon dioxide, silicon carbide, etc. In some embodiments, an upper insulating structure 416 is disposed above the FeRAM device 103 and disposed on the lower insulating structure 410. The upper insulating structure 416 extends continuously from a first position directly above the FeRAM device 103 to a second position adjacent to the upper surface of the lower insulating structure 410. The upper insulating structure 416 separates the FeRAM device 103 from the upper ILD layer 104e. In some embodiments, the upper insulating structure 416 may include one or more of silicon nitride, silicon dioxide, silicon carbide, tetraethyl orthosilicate (TEOS), etc.

[0048] The bottom electrode via 107 extends through the lower insulating structure 410. In some embodiments, the bottom electrode via 107 may include a diffusion barrier layer 107a and a bottom electrode via layer 107b above the diffusion barrier layer 107a. The FeRAM device 103 is disposed above the bottom electrode via 107 and the lower insulating structure 410. In some embodiments, the FeRAM device 103 includes a bottom electrode 108 separated from a top electrode 114 via a data storage structure 109. In some embodiments, the data storage structure 109 may include a seed layer 110 and a ferroelectric switching layer 112.

[0049] In some embodiments, a hard mask 412 may be disposed on the top electrode 114. One or more sidewall spacers 414 may be disposed on opposite sides of the top electrode 114 and the hard mask 412. In some embodiments, the hard mask 412 may include a metal (e.g., titanium, tantalum, etc.) and / or a dielectric (e.g., nitride, carbide, etc.). In some embodiments, one or more sidewall spacers 414 may include an oxide (e.g., silicon-rich oxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), etc. A top electrode via 116 extends through the upper ILD layer 104e and the hard mask 412 to electrically connect the top electrode 114.

[0050] FIG. 5A to FIG. 5B A cross-sectional view of an additional embodiment of an integrated chip 500 having a FeRAM device including a data storage structure including a dual seed layer is shown.

[0051] The integrated chip 500 includes a FeRAM device 502 disposed within a dielectric structure 104 above a substrate 102. The FeRAM device 502 has a data storage structure 504 disposed between a bottom electrode 108 and a top electrode 114. The data storage structure 504 includes a first seed layer 110a disposed on the bottom electrode 108, a ferroelectric switching layer 112 disposed on the first seed layer 110a, and a second seed layer 110b disposed on the ferroelectric switching layer 112. The ferroelectric switching layer 112 is disposed between the first seed layer 110a and the second seed layer 110b.

[0052] The first seed layer 110a and the second seed layer 110b have a non-monoclinic phase. In some embodiments, the first seed layer 110a and the second seed layer 110b include the same material. For example, in some embodiments, the first seed layer 110a and the second seed layer 110b may both include zirconium oxide (e.g., ZrO2). In other embodiments, the first seed layer 110a and the second seed layer 110b may include different materials. For example, in some embodiments, the first seed layer 110a may include zirconium oxide, and the second seed layer 110b may include hafnium oxide. In some such embodiments, the first seed layer 110a may have a first non-monoclinic phase (e.g., orthorhombic phase), and the second seed layer 110b may have a second non-monoclinic phase (e.g., cubic phase).

[0053] Figure 5B Shows Figure 5A FIG. 5 is a cross-sectional view 506 of an integrated chip 500 showing regions having different crystalline phases.

[0054] As shown in the cross-sectional view 506, the ferroelectric switching layer 112 includes a first region 508 and a second region 510. The first region 508 is adjacent to the first seed layer 110a, and the second region 510 is adjacent to the second seed layer 110b. During the manufacture of the FeRAM device 502, the first seed layer 110a changes the crystal phase of the first region 508 to give the first region 508 a non-monoclinic phase. Similarly, the second seed layer 110b changes the crystal phase of the second region 510 to give the second region 510 a non-monoclinic phase. In some embodiments, the first region 508 and the second region 510 may have the same non-monoclinic phase. In other embodiments, the first region 508 may have a first non-monoclinic phase (e.g., an orthorhombic phase), and the second region 510 may have a second non-monoclinic phase (e.g., a cubic phase).

[0055] In some embodiments, the ferroelectric switching layer 112 may further include a third region 512 separating the first region 508 from the second region 510. The third region 512 may have a monoclinic phase. In other embodiments, the first region 508 may be connected to the second region 510 along an interface 514, and the interface 514 includes a grain boundary. In these embodiments, all or substantially all of the ferroelectric switching layer 112 has a non-monoclinic phase. By having the first seed layer 110a and the second seed layer 110b located on opposite sides of the ferroelectric switching layer 112, the first seed layer 110a and the second seed layer 110b are able to change the crystalline phase of most of the ferroelectric switching layer 112, and thus minimize or eliminate the third region 512 to improve the performance (e.g., read window) of the FeRAM device 502.

[0056] Figure 6 Some additional embodiments of an integrated chip 600 having a FeRAM device including a data storage structure including a seed layer are shown in cross-sectional views.

[0057] The integrated chip 600 includes a FeRAM device 602 disposed within a dielectric structure 104 above a substrate 102. The FeRAM device 602 has a data storage structure 604 disposed between a bottom electrode 108 and a top electrode 114. The data storage structure 604 includes a seed layer 110 disposed between a first ferroelectric switching layer 112a and a second ferroelectric switching layer 112b. In some embodiments, the first ferroelectric switching layer 112a contacts a lower surface of the seed layer 110, and the second ferroelectric switching layer 112b contacts an upper surface of the seed layer 110. Having the seed layer 110 between the first ferroelectric switching layer 112a and the second ferroelectric switching layer 112b allows the seed layer 110 to change the crystalline phase of both the first ferroelectric switching layer 112a and the second ferroelectric switching layer 112b.

[0058] For example, the seed layer 110 can form a first region 606a having a non-monoclinic phase in the first ferroelectric switching layer 112a, and form a second region 606b having a non-monoclinic phase in the second ferroelectric switching layer 112b. By changing the crystal phases of both the first ferroelectric switching layer 112a and the second ferroelectric switching layer 112b, the seed layer 110 can further improve the performance of the FeRAM device 602.

[0059] FIG. 7A to FIG. 7B A graph showing the read window of FeRAM devices with different data storage structures is shown.

[0060] Fig. 7AGraph 700 is shown showing voltage values ​​corresponding to a first data state (e.g., a low data state having a logic "0") and a second data state (e.g., a high data state having a logic "1") as a function of an operating cycle. A first voltage range 702 corresponds to the first data state, and a second voltage range 704 corresponds to the second data state. For FeRAM having a single seed layer (e.g., in Figure 1 ), the voltage value corresponding to the first data state 706 is distinguished from the voltage value corresponding to the second data state 708 by a first memory window 710. For FeRAM with a dual seed layer (e.g., in Figure 5A ), the voltage value corresponding to the first data state 712 is distinguished from the voltage value corresponding to the second data state 714 by the second storage window 716, and the second storage window 716 is larger than the first storage window 710.

[0061] Figure 7B A graph 718 is shown showing the average memory window for a FeRAM device 720 without a seed layer, for a FeRAM device 722 with a single seed layer, and for a FeRAM device 724 with a dual (double) seed layer over 10,100 operating cycles. As shown in graph 718, the average memory window of the FeRAM device 720 without a seed layer is equal to about 0V, such that the average difference between the first data state and the second data state is equal to about 0V. The average memory window of the FeRAM device 722 with a single seed layer is equal to about 0.1V, such that the average difference between the first data state and the second data state is equal to about 0.1V. The average memory window of the FeRAM device 724 with a dual seed layer is equal to about 0.3V, such that the average difference between the first data state and the second data state is equal to about 0.3V. Therefore, graphs 700 and 718 show that the disclosed seed layer improves the memory window of the FeRAM device, thereby improving the performance of the FeRAM device.

[0062] Figures 8 to 21 A cross-sectional view illustrating some embodiments of a method of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer. Figures 8 to 21 The method is described with reference to, but it should be understood that Figures 8 to 21 The disclosed structure is not limited to these methods, and the structure may exist independently of the method.

[0063] like Figure 8As shown in the cross-sectional view 800 of , a substrate 102 is provided. In multiple embodiments, the substrate 102 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and may also be any other type of semiconductor and / or epitaxial layer associated therewith. In some embodiments, the access device 402 is formed on and / or in the substrate 102. In some embodiments, the access device 402 may include a transistor. In some embodiments, the access device 402 may be formed by depositing a gate dielectric film and a gate electrode film over the substrate 102. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric and a gate electrode. Subsequently, the substrate 102 may be implanted to form a source region and a drain region in the substrate 102 on opposite sides of the gate electrode.

[0064] In some embodiments, the lower interconnect 106 may be formed in one or more lower ILD layers 104L formed over the substrate 102. In some embodiments, the one or more lower ILD layers 104L may include a first lower ILD layer 104a and a second lower ILD layer 104b. In some embodiments, the lower interconnect 106 may include a conductive contact, an interconnect line, or an interconnect via. The lower interconnect 106 may be formed by forming a lower ILD layer (e.g., oxide, low-k dielectric, or ultra-low-k dielectric) of the one or more lower ILD layers 104a-104b over the substrate 102, selectively etching the lower ILD layer to form a via and / or trench in the lower ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) in the conductive via and / or trench, and performing a planarization process (e.g., a chemical mechanical polishing process) to remove excess conductive material over the lower ILD layer.

[0065] like Fig. 9 As shown in the cross-sectional view 900 of , the lower insulating structure 410 is formed above the lower interconnect 106. In some embodiments, the lower insulating structure 410 includes one or more of silicon-rich oxide, silicon carbide, silicon nitride, etc. In some embodiments, the lower insulating structure 410 can be formed by a deposition process (e.g., a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PE-CVD) process, etc.). In some embodiments, the lower insulating structure 410 is selectively etched to form an opening 902, and the opening 902 extends through the lower insulating structure 410 to expose the upper surface of the lower interconnect 106.

[0066] like Fig.10As shown in the cross-sectional view 1000 of FIG. 1 , a diffusion barrier layer 1002 is formed in the opening 902. In some embodiments, a bottom electrode via layer 1004 is formed above the diffusion barrier layer 1002. In some embodiments, the diffusion barrier layer 1002 may include a metal nitride, such as titanium nitride, tantalum nitride, etc. In some embodiments, the bottom electrode via layer 1004 may include a metal, a metal nitride, etc. For example, the bottom electrode via layer 1004 may include tungsten, tantalum nitride, titanium nitride, ruthenium, platinum, iridium, etc. In some embodiments, the diffusion barrier layer 1002 and the bottom electrode via layer 1004 may be formed by a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, etc.).

[0067] like Fig.11 As shown in the cross-sectional view 1100 of , after forming the bottom electrode via layer 1004, a planarization process (e.g., a chemical mechanical polishing (CMP) process) may be performed (along line 1102). In some embodiments, the planarization process may remove excess material of the diffusion barrier layer 107a and / or the bottom electrode via 107b from above the top of the lower insulating structure 410 to form the bottom electrode via 107 above the lower interconnect 106.

[0068] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a bottom electrode layer 1202 is formed above the bottom electrode through hole 107. In some embodiments, the bottom electrode layer 1202 may include tungsten, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, platinum, iridium, etc. In some embodiments, the bottom electrode layer 1202 may be formed by a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, etc.).

[0069] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a seed layer 1302 is formed above the bottom electrode layer 1202. In various embodiments, the seed layer 1302 may include zirconium oxide (e.g., ZrO x ), hafnium oxide (eg, HfO x ), silicon oxide (e.g., SiO x ), tantalum oxide (e.g., TaO x ), aluminum oxide (e.g., AlO x ), titanium oxide (e.g., TiO x ), yttrium oxide (such as YO x ), gadolinium oxide (eg, GdO x ), lanthanum oxide (eg, LaO x ), strontium oxide (eg, SrO x ) etc. In some embodiments, the seed layer 1302 may be formed by a deposition process (eg, a PVD process, a CVD process, a PE-CVD process, etc.).

[0070] In some embodiments, the seed layer 1302 is formed at a relatively high temperature, which allows the seed layer 1302 to have a non-monoclinic phase (e.g., an orthorhombic phase, a cubic phase, etc.). For example, in some embodiments, the seed layer 1302 is formed at a temperature of about 300° C., less than or equal to about 400° C., less than or equal to about 500° C., or other similar values. In other embodiments, a first annealing process may be performed after the seed layer 1302 is deposited. The first annealing process changes the crystalline phase of the seed layer 1302 to a non-monoclinic phase (e.g., to an orthorhombic phase). In some embodiments, the first annealing process may be performed at a temperature of about 300° C., less than or equal to about 400° C., less than or equal to about 500° C., between about 300° C. and about 500° C., or other similar values.

[0071] like Fig.14 As shown in the cross-sectional view 1400 of , a ferroelectric switching layer 1402 is formed on the seed layer 1302. In some embodiments, the ferroelectric switching layer 1402 may include hafnium oxide, hafnium zirconium oxide (HZO), lead zirconate titanate (PZT), etc. In some embodiments, the ferroelectric switching layer 1402 may be formed by a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, etc.). In some embodiments, the ferroelectric switching layer 1402 may be configured to have a monoclinic phase. In some embodiments, a second annealing process may be performed after the ferroelectric switching layer 1402 is deposited to change the crystal phase of part or all of the ferroelectric switching layer 1402 to a non-monoclinic phase. In some embodiments, the second annealing process may be performed at a temperature of about 300° C., less than or equal to about 400° C., less than or equal to about 500° C., between about 300° C. and 500° C., or other similar values.

[0072] like Fig.15 As shown in the cross-sectional view 1500 of , a top electrode layer 1502 is formed above the ferroelectric switching layer 1402. The top electrode layer 1502 may include a metal, a metal nitride, or the like. In some embodiments, the top electrode layer 1502 may include tungsten, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, platinum, iridium, or the like. In some embodiments, the top electrode layer 1502 may be formed by a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, or the like). In some embodiments, a second annealing process may be performed after the top electrode layer 1502 is deposited. Performing the second annealing process after the top electrode layer 1502 is deposited may cause the top electrode layer 1502 to induce tensile stress on the ferroelectric switching layer 1402. The tensile stress increases the transition of the crystalline phase of the ferroelectric switching layer 1402 to a non-monoclinic phase so as to obtain a ferroelectric switching layer 1402 having a higher percentage of a non-monoclinic phase.

[0073] like Fig.16 As shown in the cross-sectional view 1600, the top electrode layer ( Fig.151502) performs a first patterning process to form the top electrode 114. In some embodiments, the first patterning process forms the top electrode layer ( Fig.15 1502) is selectively exposed to a first etchant 1602 to form the top electrode 114. In various embodiments, the hard mask 412 may include a metal (e.g., titanium, titanium nitride, tantalum, etc.) and / or a dielectric material (e.g., silicon nitride, silicon carbide, etc.). In some embodiments (not shown), the first patterning process forms the top electrode layer ( Fig.15 1502) is selectively exposed to a first etchant 1602 to form a top electrode 114.

[0074] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 17 , one or more sidewall spacers 414 are formed along the sidewalls of the top electrode 114 and the hard mask 412. In various embodiments, the one or more sidewall spacers 414 may include silicon nitride, silicon dioxide, silicon oxynitride, etc. In some embodiments, the one or more sidewall spacers 414 may be formed by forming a spacer layer above the substrate 102. The spacer layer is then exposed to an etchant (e.g., a dry etchant) that removes the spacer layer from the horizontal surface. Removing the spacer layer from the horizontal surface retains the spacer layer along the opposite sidewalls of the top electrode 114 and the hard mask 412 as one or more sidewall spacers 414.

[0075] like Fig.18 As shown in the cross-sectional view 1800, the ferroelectric switching layer ( Fig.17 1402), seed layer ( Fig.17 1302) and the bottom electrode layer ( Fig.17 The second patterning process forms the FeRAM device 103 having the data storage structure 109, the data storage structure 109 including the seed layer 110 and the ferroelectric switching layer 112 disposed between the bottom electrode 108 and the top electrode 114. In some embodiments, the second patterning process forms the ferroelectric switching layer ( Fig.17 1402), seed layer ( Fig.17 1302) and the bottom electrode layer ( Fig.17 1202) is selectively exposed to an etchant.

[0076] like Fig.19As shown in the cross-sectional view 1900 of FIG. 19 , an upper insulating structure 416 is formed above the FeRAM device 103. In some embodiments, the upper insulating structure 416 includes a plurality of stacked different dielectric materials. For example, in some embodiments, the upper insulating structure 416 includes a first dielectric layer 1902 and a second dielectric layer 1904 above the first dielectric layer 1902. In some embodiments, the first dielectric layer 1902 may include silicon-rich oxide, silicon carbide, silicon nitride, tetraethyl orthosilicate (TEOS), etc. In some embodiments, the second dielectric layer 1904 may include silicon carbide, silicon nitride, etc. In some embodiments, the upper insulating structure 416 may be formed using one or more deposition processes (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.).

[0077] like Fig. 20 As shown in the cross-sectional view 2000 of , an upper ILD layer 104U is formed over the upper insulating structure 416 to form the dielectric structure 104 over the substrate 102. In some embodiments, the upper ILD layer 104U may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In many embodiments, the upper ILD layer 104U may include one or more of silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphate silicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric material, etc.

[0078] like Fig.21 As shown in the cross-sectional view 2100 of FIG. 21 , a top electrode via 116 is formed on the top electrode 114. The top electrode via 116 extends through the upper ILD layer 104U and the upper insulating structure 416 to the top electrode 114. In some embodiments, the top electrode via 116 can be formed by selectively etching the upper ILD layer 104U and the upper insulating structure 416 to form a via 2102, which extends from the top surface of the upper ILD layer 104U to expose the upper surface of the top electrode 114. In some embodiments, the via 2102 can be formed by a third patterning process, which selectively etches the upper ILD layer 104U according to the mask layer using a third etchant. A conductive material (e.g., copper, aluminum, etc.) is formed in the via 2102. In some embodiments, after the conductive material is formed in the via 2102, a planarization process (e.g., a CMP process) is performed to remove excess conductive material from above the top surface of the upper ILD layer 104U.

[0079] Fig. 22 A flow chart illustrating some embodiments of a method 2200 of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer.

[0080] Although method (for example, method 2200,3100,4000 and 4900) is shown and described as a series of steps or events here, it should be understood that the order shown of these steps or events is not interpreted as limiting.For example, some steps can occur in different orders and / or with other steps or events except some shown and / or described here.In addition, it may not be necessary for all steps shown to implement one or more aspects or embodiments described here.In addition, one or more steps described here can be implemented in one or more separate steps and / or stages.

[0081] In step 2202, a lower interconnect is formed within a lower inter-layer dielectric (ILD) layer over a substrate. Figure 8 A cross-sectional view 800 corresponding to some embodiments of step 2202 is shown.

[0082] In step 2204, a lower insulating structure is formed over the lower ILD layer and the lower interconnect. Fig. 9 A cross-sectional view 900 corresponding to some embodiments of step 2204 is shown.

[0083] In step 2206, a bottom electrode layer is formed over the lower insulating structure and the lower interconnect. Figures 10 to 12 Cross-sectional views 1000 - 1200 corresponding to some embodiments of step 2206 are shown.

[0084] In step 2208, a seed layer is formed on the bottom electrode layer. Fig.13 A cross-sectional view 1300 corresponding to some embodiments of step 2208 is shown.

[0085] In step 2210, a ferroelectric switching layer is formed on the seed layer. Fig.14 A cross-sectional view 1400 is shown corresponding to some embodiments of step 2210. The crystalline phase of the ferroelectric switching layer is configured to grow and / or change based on the crystalline phase of the seed layer.

[0086] In step 2212, an annealing process is performed. The annealing process may change the crystal phase of the ferroelectric switching layer. In various embodiments, the annealing process may be performed after step 2210 and before or after step 2214. Fig.14 A cross-sectional view 1400 corresponding to some embodiments of step 2212 is shown.

[0087] In step 2214, a top electrode layer is formed over the ferroelectric switching layer. Fig.15 A cross-sectional view 1500 corresponding to some embodiments of step 2214 is shown.

[0088] In step 2216, a first patterning process is performed on the first top electrode layer to form a top electrode. Fig.16 A cross-sectional view 1600 corresponding to some embodiments of step 2216 is shown.

[0089] In step 2218, one or more sidewall spacers are formed along opposing sides of the top electrode. Fig.17 A cross-sectional view 1700 corresponding to some embodiments of step 2218 is shown.

[0090] In step 2220, a second patterning process is performed on the ferroelectric switching layer, the seed layer, and the bottom electrode layer. The second patterning process forms a data storage structure and a bottom electrode. Fig.18 A cross-sectional view 1800 corresponding to some embodiments of step 2220 is shown.

[0091] In step 2222, an upper insulating structure is formed over the top electrode. Fig.19 A cross-sectional view 1900 corresponding to some embodiments of step 2222 is shown.

[0092] In step 2224 , an upper ILD layer is formed over the upper insulating structure. Fig. 20 A cross-sectional view 2000 corresponding to some embodiments of step 2224 is shown.

[0093] In step 2226, a top electrode via is formed extending through the upper ILD layer to the top electrode. Fig.21 A cross-sectional view 2100 corresponding to some embodiments of step 2226 is shown.

[0094] Figures 23 to 30 Cross-sectional views of some alternative embodiments of a method of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer are shown. Figures 23 to 30 The method is described with reference to, but it should be understood that Figures 23 to 30 The disclosed structure is not limited to these methods, and the structure may exist independently of the method.

[0095] like Fig.23 As shown in cross-sectional view 2300 of FIG. 23 , a substrate 102 is provided. In some embodiments, an access device 402 is formed on and / or in the substrate 102. In some embodiments, the lower interconnect 106 may be formed in one or more lower ILD layers 104L formed above the substrate 102.

[0096] A lower insulating structure 410 having an opening 902 is formed over the one or more lower ILD layers 104L. A diffusion barrier layer 107a is formed within the opening 902, and a bottom electrode via layer 107b is formed over the diffusion barrier layer 107a and within the opening 902. A planarization process (e.g., a chemical mechanical polishing (CMP) process) may be performed (along line 2302) to remove excess material of the diffusion barrier layer 107a and the bottom electrode via layer 107b from over the top of the lower insulating structure 410 and form a bottom electrode via 107.

[0097] like Fig.24 As shown in the cross-sectional view 2400 of FIG. 1 , a bottom electrode layer 1202 is formed on the bottom electrode through hole 107. In some embodiments, the bottom electrode layer 1202 is formed by Fig.12 The bottom electrode layer 1202 is formed in the same or similar manner as described in the cross-sectional view 1200 .

[0098] like Fig.25 As shown in the cross-sectional view 2500 of , a ferroelectric switching layer 2502 is formed on the bottom electrode layer 1202. In some embodiments, the ferroelectric switching layer 2502 can be formed by a deposition process (eg, PVD, CVD, PE-CVD, ALD, sputtering, etc.).

[0099] like Fig.26 As shown in the cross-sectional view 2600 of , a seed layer 2602 is formed on the ferroelectric switching layer 2502. In some embodiments, the seed layer 2602 is formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In some embodiments, the seed layer 2602 is formed at a temperature of less than or equal to about 300° C., less than or equal to about 400° C., or other similar values. In some additional embodiments, an annealing process is performed after the seed layer 2602 is deposited. The annealing process changes the crystalline phase of the seed layer 2602 and / or the ferroelectric switching layer 2502 to a non-monoclinic phase. In some embodiments, the annealing process may be performed at a temperature greater than or equal to about 300° C., greater than or equal to about 400° C., greater than or equal to about 500° C., between about 300° C. and about 500° C., or other similar values.

[0100] like Fig. 27 As shown in the cross-sectional view 2700 of , a top electrode layer 1502 is formed on the seed layer 2602. A first patterning process is performed on the top electrode layer 1502 to form the top electrode 114. In some embodiments, the first patterning process selectively exposes the top electrode layer 1502 to the first etchant 1602 according to the hard mask 412. In some embodiments, an annealing process may be performed after the top electrode 1502 is deposited.

[0101] like Fig.28As shown in the cross-sectional view 2800 of FIG. 28 , one or more sidewall spacers 414 are formed along the sidewalls of the top electrode 114 and the hard mask 412. In some embodiments, the one or more sidewall spacers 414 are formed in the same manner as the reference Fig.17 One or more sidewall spacers 414 may be formed in the same or similar manner as described in cross-sectional view 1700 .

[0102] like Fig.29 As shown in the cross-sectional view 2900, the seed layer ( Fig.28 2602), ferroelectric switching layer ( Fig.28 2502) and the bottom electrode layer ( Fig.28 The second patterning process forms a FeRAM device 302 having a data storage structure 109, the data storage structure 109 including a seed layer 110 and a ferroelectric switching layer 112 disposed between the bottom electrode 108 and the top electrode 114. In some embodiments, the second patterning process forms a seed layer ( Fig.28 2602), ferroelectric switching layer ( Fig.28 2502) and the bottom electrode layer ( Fig.28 1202) is selectively exposed to a second etchant 1802.

[0103] like Fig.30 As shown in the cross-sectional view 3000 of FIG. 3001 , an upper insulating structure 416 is formed over the FeRAM device 302. An upper ILD layer 104U is formed over the upper insulating structure 416 to form a dielectric structure 104 over the substrate 102. A top electrode via 116 is formed over the top electrode 114. The top electrode via 116 extends through the upper ILD layer 104U and the upper insulating structure 416 to the top electrode 114.

[0104] Fig.31 A flow chart of a method 3100 of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer is shown.

[0105] In step 3102, a lower interconnect is formed within a lower inter-layer dielectric (ILD) layer over a substrate. Fig.23 A cross-sectional view 2300 corresponding to some embodiments of step 3102 is shown.

[0106] In step 3104, a lower insulating structure is formed over the lower ILD layer and the lower interconnect. Fig.23 A cross-sectional view 2300 corresponding to some embodiments of step 3104 is shown.

[0107] In step 3106, a bottom electrode layer is formed over the lower insulating structure and the lower interconnect. Figure 23-24 Cross-sectional views 2300 - 2400 corresponding to some embodiments of step 3106 are shown.

[0108] In step 3108, a ferroelectric switching layer is formed on the bottom electrode layer. Fig.25 A cross-sectional view 2500 corresponding to some embodiments of step 3108 is shown.

[0109] In step 3110, a seed layer is formed on the ferroelectric switching layer. Fig.26 A cross-sectional view 2600 corresponding to some embodiments of step 3110 is shown.

[0110] In step 3112, an annealing process may be performed. The annealing process changes the crystalline phase of the ferroelectric switching layer. In various embodiments, the annealing process may be performed after step 3110 and before or after step 3114. Fig.26 A cross-sectional view 2600 corresponding to some embodiments of step 3112 is shown.

[0111] In step 3114, a top electrode layer is formed over the seed layer. Fig. 27 A cross-sectional view 2700 corresponding to some embodiments of step 3114 is shown.

[0112] In step 3116, a first patterning process is performed on the top electrode layer to form a top electrode. Fig. 27 A cross-sectional view 2700 corresponding to some embodiments of step 3116 is shown.

[0113] In step 3118, one or more sidewall spacers are formed along opposing sides of the top electrode. Fig.28 A cross-sectional view 2800 corresponding to some embodiments of step 3118 is shown.

[0114] In step 3120, a second patterning process is performed on the ferroelectric switching layer, the seed layer, and the bottom electrode layer. The second patterning process forms a data storage structure and a bottom electrode. Fig.29 A cross-sectional view 2900 corresponding to some embodiments of step 3120 is shown.

[0115] In step 3122, an upper insulating structure is formed over the top electrode. Fig.30 A cross-sectional view 3000 corresponding to some embodiments of step 3122 is shown.

[0116] In step 3124, an upper ILD layer is formed over the upper insulating structure. Fig.30 A cross-sectional view 3000 corresponding to some embodiments of step 3124 is shown.

[0117] In step 3126, a top electrode via is formed extending through the upper ILD layer to the top electrode. Fig.30 A cross-sectional view 3000 corresponding to some embodiments of step 3126 is shown.

[0118] Figures 32 to 40 Cross-sectional views of some alternative embodiments of a method of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer are shown. Figures 32 to 40 The method is described with reference to, but it should be understood that Figures 32 to 40 The disclosed structure is not limited to these methods, and the structure may exist independently of the method.

[0119] like Fig.32 As shown in the cross-sectional view 3200 of FIG. 3 , a substrate 102 is provided. In some embodiments, an access device 402 is formed on and / or in the substrate 102. In some embodiments, the lower interconnect 106 may be formed in one or more lower ILD layers 104L formed above the substrate 102.

[0120] A lower insulating structure 410 having an opening 902 is formed over the lower interconnect 106. A diffusion barrier layer 107a is formed within the opening 902, and a bottom electrode via layer 107b is formed over the diffusion barrier layer 107a and within the opening 902. A planarization process (e.g., a chemical mechanical polishing (CMP) process) may be performed (along line 3202) to remove excess material of the diffusion barrier layer 107a and the bottom electrode via layer 107b from over the top of the lower insulating structure 410 to form the bottom electrode via 107.

[0121] like Fig.33 As shown in the cross-sectional view 3300 of FIG. 1 , a bottom electrode layer 1202 is formed above the bottom electrode through hole 107. In some embodiments, the bottom electrode layer 1202 is formed similar to the reference Fig.12 The bottom electrode layer 1202 is formed in the same or similar manner as described in the cross-sectional view 1200 .

[0122] like Fig.34 As shown in the cross-sectional view 3400 of , a first ferroelectric switching layer 3402 is formed on the bottom electrode layer 1202. In some embodiments, the first ferroelectric switching layer 3402 can be formed by a deposition process (eg, PVD, CVD, PE-CVD, ALD, sputtering, etc.).

[0123] like Fig.35As shown in the cross-sectional view 3500 of , a seed layer 3502 is formed over the first ferroelectric switching layer 3402. In some embodiments, the seed layer 3502 is formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In some embodiments, the seed layer 3502 is formed at a temperature of about 300° C. or less, about 400° C. or less, about 300° C. to 500° C., or other similar values.

[0124] like Fig.36 As shown in the cross-sectional view 3600 of , a second ferroelectric switching layer 3602 is formed on the seed layer 3502. In some embodiments, the second ferroelectric switching layer 3602 is formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In some additional embodiments, an annealing process is performed after the second ferroelectric switching layer 3602 is deposited. The annealing process further changes the crystal phase of the second ferroelectric switching layer 3602 to a non-monoclinic phase. In some embodiments, the annealing process further changes the crystal phase of the first ferroelectric switching layer 3402 and / or the seed layer 3502 to a non-monoclinic phase. In some embodiments, the annealing process can be performed at a temperature greater than or equal to about 300° C., greater than or equal to about 400° C., greater than or equal to about 500° C., between about 300° C. and 500° C., or other similar values.

[0125] like Fig.37 As shown in the cross-sectional view 3700 of FIG. 3700 , a top electrode layer 1502 is formed on the second ferroelectric switching layer 3602. In some embodiments, an annealing process may be performed after depositing the top electrode 1502. In some embodiments, the top electrode layer 1502 is formed using the same Fig.15 The top electrode layer 1502 is formed in the same or similar manner as described in the cross-sectional view 1500 .

[0126] After forming the top electrode layer 1502 , a first patterning process is performed on the top electrode layer 1502 to form the top electrode 114 . In some embodiments, the first patterning process selectively exposes the top electrode layer 1502 to the first etchant 1602 according to the hard mask 412 .

[0127] like Fig.38 As shown in the cross-sectional view 3800 of FIG. 38A , one or more sidewall spacers 414 are formed along the sidewalls of the top electrode 114 and the hard mask 412. In some embodiments, the one or more sidewall spacers 414 are formed in the same manner as the reference Fig.17 One or more sidewall spacers 414 may be formed in the same or similar manner as described in cross-sectional view 1700 .

[0128] Subsequently, the second ferroelectric switching layer ( Fig.37 3602), seed layer ( Fig.373502), the first ferroelectric switching layer ( Fig.37 3402) and the bottom electrode layer ( Fig.37 1202) performs a second patterning process to form the FeRAM device 602. In some embodiments, the second patterning process forms a second ferroelectric switching layer ( Fig.37 3602), seed layer ( Fig.37 3502), the first ferroelectric switching layer ( Fig.37 3402) and the bottom electrode layer ( Fig.37 1202) is selectively exposed to a second etchant 1802.

[0129] like Fig.39 As shown in the cross-sectional view 3900 of FIG. 39 , an upper insulating structure 416 is formed over the FeRAM device 602. An upper ILD layer 104U is formed over the upper insulating structure 416 to form a dielectric structure 104 over the substrate 102. A top electrode via 116 is formed over the top electrode 114. The top electrode via 116 extends through the upper ILD layer 104U and the upper insulating structure 416.

[0130] Fig.40 A flow chart of a method 4000 of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer is shown.

[0131] In step 4002, a lower interconnect is formed within a lower inter-layer dielectric (ILD) layer over a substrate. Fig.32 A cross-sectional view 3200 corresponding to some embodiments of step 4002 is shown.

[0132] In step 4004, a lower insulating structure is formed over the lower ILD layer and the lower interconnect. Fig.32 A cross-sectional view 3200 corresponding to some embodiments of step 4004 is shown.

[0133] In step 4006, a bottom electrode layer is formed over the lower insulating structure and the lower interconnect. Figure 32 to Figure 33 Cross-sectional views 3200 - 3300 are shown corresponding to some embodiments of step 4006 .

[0134] In step 4008, a first ferroelectric switching layer is formed on the bottom electrode layer. Fig.34 A cross-sectional view 3400 corresponding to some embodiments of step 4008 is shown.

[0135] In step 4010, a seed layer is formed on the first ferroelectric switching layer. Fig.35A cross-sectional view 3500 corresponding to some embodiments of step 4010 is shown.

[0136] In step 4012, a second ferroelectric switching layer is formed on the seed layer. Fig.36 A cross-sectional view 3600 corresponding to some embodiments of step 4012 is shown.

[0137] In step 4014, an annealing process is performed. The annealing process changes the crystal phase of the first ferroelectric switching layer, the seed layer and / or the second ferroelectric switching layer. In various embodiments, the annealing process may be performed after step 4012 and before or after step 4016. Fig.36 A cross-sectional view 3600 corresponding to some embodiments of step 4014 is shown.

[0138] In step 4016, a top electrode layer is formed over the second ferroelectric switching layer. Fig.37 A cross-sectional view 3700 corresponding to some embodiments of step 4016 is shown.

[0139] In step 4018, a first patterning process is performed on the top electrode layer to form a top electrode. Fig.37 A cross-sectional view 3700 corresponding to some embodiments of step 4018 is shown.

[0140] In step 4020, one or more sidewall spacers are formed along opposing sides of the top electrode. Fig.38 A cross-sectional view 3800 corresponding to some embodiments of step 4020 is shown.

[0141] In step 4022, a second patterning process is performed on the first ferroelectric switching layer, the seed layer, the second ferroelectric switching layer, and the bottom electrode. The second patterning process forms a data storage structure and a bottom electrode. Fig.38 A cross-sectional view 3800 corresponding to some embodiments of step 4022 is shown.

[0142] In step 4024, an upper insulating structure is formed over the top electrode. Fig.39 A cross-sectional view 3900 corresponding to some embodiments of step 4024 is shown.

[0143] In step 4026 , an upper ILD layer is formed over the upper insulating structure. Fig.39 A cross-sectional view 3900 corresponding to some embodiments of step 4026 is shown.

[0144] In step 4028, a top electrode via is formed extending through the upper ILD layer to the top electrode. Fig.39 A cross-sectional view 3900 corresponding to some embodiments of step 4028 is shown.

[0145] Figures 41 to 48 Cross-sectional views of some alternative embodiments of a method of forming an integrated chip having a FeRAM device including a data storage structure including a dual seed layer are shown. Figures 41 to 48 The method is described with reference to, but it should be understood that Figures 41 to 48 The disclosed structure is not limited to these methods, and the structure may exist independently of the method.

[0146] like Fig.41 As shown in cross-sectional view 4100 of FIG. 4 , a substrate 102 is provided. In some embodiments, an access device 402 is formed on and / or in the substrate 102. In some embodiments, a lower interconnect 106 may be formed in one or more lower ILD layers 104L formed above the substrate 102.

[0147] A lower insulating structure 410 having an opening 902 is formed over the lower interconnect 106. A diffusion barrier layer 107a is formed within the opening 902, and a bottom electrode via layer 107b is formed over the diffusion barrier layer 107a and within the opening 902. A planarization process (e.g., a chemical mechanical polishing (CMP) process) may be performed (along line 4102) to remove excess material of the diffusion barrier layer 107a and the bottom electrode via layer 107b from over the top of the lower insulating structure 410 to form the bottom electrode via 107.

[0148] like Fig.42 As shown in the cross-sectional view 4200 of FIG. 4 , a bottom electrode layer 1202 is formed above the bottom electrode through hole 107. In some embodiments, the bottom electrode layer 1202 is formed by Fig.12 The bottom electrode layer 1202 is formed in the same or similar manner as described in the cross-sectional view 1200 .

[0149] like Fig.43 As shown in the cross-sectional view 4300 of FIG. 4 , a first seed layer 4302 is formed on the bottom electrode layer 1202. In some embodiments, the first seed layer 4302 can be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In some embodiments, the first seed layer 4302 is formed at a temperature of about 300° C. or less, about 400° C. or less, or other similar values.

[0150] like Fig.44 As shown in the cross-sectional view 4400 of , a ferroelectric switching layer 4402 is formed on the first seed layer 4302. In some embodiments, the ferroelectric switching layer 4402 can be formed by a deposition process (eg, PVD, CVD, PE-CVD, ALD, sputtering, etc.).

[0151] like Fig.45As shown in the cross-sectional view 4500 of , a second seed layer 4502 is formed on the ferroelectric switching layer 4402. In some embodiments, the second seed layer 4502 can be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In some embodiments, the second seed layer 4502 is formed at a temperature of about 300° C. or less, about 400° C. or less, or other similar values. In some embodiments, an annealing process is performed after the second seed layer 4502 is formed to change the crystal phase of the ferroelectric switching layer 4402, the first seed layer 4302, and / or the second seed layer 4502. In various embodiments, the annealing process is performed at a temperature of about 300° C., about 400° C. or less, between about 300° C. and 500° C., or other similar values.

[0152] like Fig.46 As shown in the cross-sectional view 4600 of FIG. 46 , a top electrode layer 1502 is formed on the second seed layer 4502. In some embodiments, an annealing process may be performed after the top electrode layer 1502 is deposited. In some embodiments, the top electrode layer 1502 is formed by Fig.15 The top electrode layer 1502 is formed in the same or similar manner as described in the cross-sectional view 1500 .

[0153] After forming the top electrode layer 1502 , a first patterning process is performed on the top electrode layer 1502 to form the top electrode 114 . In some embodiments, the first patterning process selectively exposes the top electrode layer 1502 to the first etchant 1602 according to the hard mask 412 .

[0154] like Fig.47 As shown in the cross-sectional view 4700 of FIG. 47A , one or more sidewall spacers 414 are formed along the sidewalls of the top electrode 114 and the hard mask 412. In some embodiments, the one or more sidewall spacers 414 are formed in the same manner as the reference Fig.17 One or more sidewall spacers 414 may be formed in the same or similar manner as described in cross-sectional view 1700 .

[0155] For the second seed layer ( Fig.46 4502), ferroelectric switching layer ( Fig.46 4402), the first seed layer ( Fig.46 4302) and the bottom electrode layer ( Fig.46 1202) performs a second patterning process to form the FeRAM device 502. In some embodiments, the second patterning process forms a second seed layer ( Fig.46 4502), ferroelectric switching layer ( Fig.46 4402), the first seed layer ( Fig.46 4302) and the bottom electrode layer ( Fig.46 1202) is selectively exposed to a second etchant 1802.

[0156] like Fig.48 As shown in the cross-sectional view 4800 of FIG. 48 , an upper insulating structure 416 is formed over the FeRAM device 502. An upper ILD layer 104U is formed over the upper insulating structure 416 to form a dielectric structure 104 over the substrate 102. A top electrode via 116 is formed over the top electrode 114. The top electrode via 116 extends through the upper ILD layer 104U and the upper insulating structure 416 to the top electrode 114.

[0157] Fig.49 A flow chart illustrating method 4900 of some embodiments of a method of forming an integrated chip having a FeRAM device including a data storage structure including a seed layer.

[0158] In step 4902, a lower interconnect is formed within a lower inter-layer dielectric (ILD) layer over a substrate. Fig.41 A cross-sectional view 4100 corresponding to some embodiments of step 4902 is shown.

[0159] In step 4904, a lower insulating structure is formed over the lower ILD layer and the lower interconnect. Fig.41 A cross-sectional view 4100 corresponding to some embodiments of step 4904 is shown.

[0160] In step 4906, a bottom electrode layer is formed over the lower insulating structure and the lower interconnect. Figure 41 to Figure 42 Cross-sectional views 4100 - 4200 of some embodiments corresponding to step 4906 are shown.

[0161] In step 4908, a first seed layer is formed on the bottom electrode layer. Fig.43 A cross-sectional view 4300 corresponding to some embodiments of step 4908 is shown.

[0162] In step 4910, a ferroelectric switching layer is formed on the first seed layer. Fig.44 A cross-sectional view 4400 corresponding to some embodiments of step 4910 is shown.

[0163] In step 4912, a second seed layer is formed on the ferroelectric switching layer. Fig.45 A cross-sectional view 4500 corresponding to some embodiments of step 4912 is shown.

[0164] In step 4914, an annealing process is performed. The annealing process changes the crystal phase of the ferroelectric switching layer, the first seed layer, and / or the second seed layer. In various embodiments, the annealing process may be performed after step 4912 and before or after step 4916. Fig.45 A cross-sectional view 4500 corresponding to some embodiments of step 4914 is shown.

[0165] In step 4916, a top electrode layer is formed over the second seed layer. Fig.46 A cross-sectional view 4600 corresponding to some embodiments of step 4916 is shown.

[0166] In step 4918, a first patterning process is performed on the top electrode layer to form a top electrode. Fig.46 A cross-sectional view 4600 corresponding to some embodiments of step 4918 is shown.

[0167] In step 4920, one or more sidewall spacers are formed along opposing sides of the top electrode. Fig.47 A cross-sectional view 4700 corresponding to some embodiments of step 4920 is shown.

[0168] In step 4922, a second patterning process is performed on the first seed layer, the ferroelectric switching layer, the second seed layer, and the bottom electrode. The second patterning process forms a data storage structure and a bottom electrode. Fig.47 A cross-sectional view 4700 corresponding to some embodiments of step 4922 is shown.

[0169] In step 4924, an upper insulating structure is formed over the top electrode. Fig.48 A cross-sectional view 4800 corresponding to some embodiments of step 4924 is shown.

[0170] In step 4926, an upper ILD layer is formed over the upper insulating structure. Fig.48 A cross-sectional view 4800 corresponding to some embodiments of step 4926 is shown.

[0171] In step 4928, a top electrode via is formed extending through the upper ILD layer to the top electrode. Fig.48 A cross-sectional view 4800 corresponding to some embodiments of step 4928 is shown.

[0172] Accordingly, in some embodiments, the present disclosure relates to an integrated chip having a FeRAM device including a data storage structure having a seed layer whose crystalline phase (eg, orthorhombic phase) is configured to improve the ferroelectricity of a ferroelectric switching layer.

[0173] In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed above a substrate; a top electrode disposed above the bottom electrode; a ferroelectric switching layer disposed between the bottom electrode and the top electrode, the ferroelectric switching layer being configured to change polarization based on one or more voltages applied to the bottom electrode or the top electrode; and a seed layer disposed between the bottom electrode and the top electrode, the seed layer and the ferroelectric switching layer having a non-monoclinic phase. In some embodiments, the ferroelectric switching layer includes a first region having a monoclinic phase and a second region having a non-monoclinic phase. In some embodiments, the non-monoclinic phase includes a cubic phase, a tetragonal phase, or an orthorhombic phase. In some embodiments, the seed layer includes zirconium oxide, hafnium oxide, silicon oxide, tantalum oxide, aluminum oxide, titanium oxide, yttrium oxide, gadolinium oxide, lanthanum oxide, or strontium oxide. In some embodiments, the seed layer is disposed between the ferroelectric switching layer and the bottom electrode. In some embodiments, the seed layer is disposed between the ferroelectric switching layer and the top electrode. In some embodiments, the integrated chip further comprises a second ferroelectric switching layer between the bottom electrode and the top electrode, the ferroelectric switching layer separating the seed layer from the bottom electrode, and the second ferroelectric switching layer separating the seed layer from the top electrode. In some embodiments, the integrated chip further comprises a second seed layer disposed between the ferroelectric switching layer and the top electrode, the seed layer separating the ferroelectric switching layer from the bottom electrode, and the second seed layer separating the ferroelectric switching layer from the top electrode. In some embodiments, the seed layer and the second seed layer are of different materials. In some embodiments, the ferroelectric switching layer directly contacts the seed layer.

[0174] In other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed above a substrate; a top electrode disposed above the bottom electrode; a seed layer disposed between the bottom electrode and the top electrode, the seed layer having a non-monoclinic phase; and a ferroelectric switching layer disposed between the bottom electrode and the top electrode, the ferroelectric switching layer including a first region having a monoclinic phase and a second region having a non-monoclinic phase. In some embodiments, the non-monoclinic phase includes a cubic phase, a tetragonal phase, or an orthorhombic phase. In some embodiments, the second region contacts the seed layer and separates the seed layer from the first region. In some embodiments, the seed layer is disposed between the ferroelectric switching layer and the bottom electrode. In some embodiments, the integrated chip further includes a second seed layer disposed between the ferroelectric switching layer and the top electrode, the ferroelectric switching layer also having a third region, the third region being separated from the second region by the first region and having a second non-monoclinic phase. In some embodiments, the seed layer has a crystallization temperature of less than about 500°C.

[0175] In yet another embodiment, the present disclosure relates to a method for forming an integrated chip. The method includes forming a bottom electrode layer above a substrate; forming a seed layer above the bottom electrode layer; forming a ferroelectric switching layer contacting the seed layer above the bottom electrode layer, the ferroelectric switching layer being formed to have a first region and a second region, the first region having a first crystal phase, and the second region having a different crystal phase; forming a top electrode layer above the ferroelectric switching layer; and performing one or more patterning processes on the bottom electrode layer, the seed layer, the ferroelectric switching layer, and the top electrode layer to form a FeRAM device. In some embodiments, the method also includes performing an annealing process after forming both the seed layer and the ferroelectric switching layer, wherein the annealing process changes the crystal phase of at least a portion of the ferroelectric switching layer. In some embodiments, the annealing process is performed at a temperature between about 300°C and about 500°C. In some embodiments, the method also includes forming a ferroelectric switching layer to contact an upper surface of the seed layer; and forming a second seed layer to contact an upper surface of the ferroelectric switching layer.

[0176] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated chip, comprising: a bottom electrode disposed above the substrate; a top electrode disposed above the bottom electrode; a ferroelectric switching layer disposed between the bottom electrode and the top electrode, wherein the ferroelectric switching layer is configured to change polarization based on one or more voltages applied to the bottom electrode or the top electrode; and a seed layer disposed between the bottom electrode and the top electrode, wherein the seed layer and the ferroelectric switching layer comprise a non-monoclinic phase, The ferroelectric switching layer includes a first region having a monoclinic phase and a second region having a non-monoclinic phase, the first region and the second region are stacked on each other, and the first region is separated from the seed layer by the second region.

2. The integrated chip according to claim 1, wherein: The integrated chip has a read window of 0.3V.

3. The integrated chip according to claim 1, wherein: The non-monoclinic phase includes a cubic phase, a tetragonal phase or an orthorhombic phase.

4. The integrated chip according to claim 1, wherein: The seed layer includes zirconium oxide, hafnium oxide, silicon oxide, tantalum oxide, aluminum oxide, titanium oxide, yttrium oxide, gadolinium oxide, lanthanum oxide or strontium oxide.

5. The integrated chip according to claim 1, wherein: The seed layer is disposed between the ferroelectric switching layer and the bottom electrode.

6. The integrated chip according to claim 1, wherein: The seed layer is disposed between the ferroelectric switching layer and the top electrode.

7. The integrated chip according to claim 1, further comprising: A second ferroelectric switching layer is disposed between the bottom electrode and the top electrode, wherein the ferroelectric switching layer separates the seed layer from the bottom electrode and the second ferroelectric switching layer separates the seed layer from the top electrode.

8. The integrated chip according to claim 1, further comprising: A second seed layer is disposed between the ferroelectric switching layer and the top electrode, wherein the seed layer separates the ferroelectric switching layer from the bottom electrode and the second seed layer separates the ferroelectric switching layer from the top electrode.

9. The integrated chip according to claim 8, wherein: The seed layer and the second seed layer are made of different materials.

10. The integrated chip according to claim 1, wherein: The ferroelectric switching layer directly contacts the seed layer.

11. An integrated chip, comprising: a bottom electrode disposed above the substrate; a top electrode disposed above the bottom electrode; a seed layer disposed between the bottom electrode and the top electrode, wherein the seed layer comprises a non-monoclinic phase; A ferroelectric switching layer is arranged between the bottom electrode and the top electrode, wherein the ferroelectric switching layer includes a first region having a monoclinic phase and a second region having a non-monoclinic phase, the first region and the second region are stacked on each other and the first region is separated from the seed layer by the second region.

12. The integrated chip according to claim 11, wherein: The non-monoclinic phase includes a cubic phase, a tetragonal phase or an orthorhombic phase.

13. The integrated chip according to claim 11, wherein: The second region contacts the seed layer.

14. The integrated chip according to claim 11, wherein: The seed layer is disposed between the ferroelectric switching layer and the bottom electrode.

15. The integrated chip according to claim 14, further comprising: A second seed layer is disposed between the ferroelectric switching layer and the top electrode, wherein the ferroelectric switching layer further comprises a third region separated from the second region by the first region and having a second non-monoclinic phase.

16. The integrated chip according to claim 11, wherein: The seed layer has a crystallization temperature less than 500°C.

17. A method for forming an integrated chip, comprising: forming a bottom electrode layer over the substrate; forming a seed layer above the bottom electrode layer; forming a ferroelectric switching layer contacting the seed layer over the bottom electrode, wherein the ferroelectric switching layer is formed to have a first region and a second region stacked on each other, the first region has a first crystal phase, the second region has a different crystal phase, and the first region is separated from the seed layer by the second region; forming a top electrode layer over the ferroelectric switching layer; and One or more patterning processes are performed on the bottom electrode layer, the seed layer, the ferroelectric switching layer, and the top electrode layer to form a ferroelectric random access memory (FeRAM) device.

18. The method according to claim 17, further comprising: An annealing process is performed after forming both the seed layer and the ferroelectric switching layer, wherein the annealing process changes a crystalline phase of at least a portion of the ferroelectric switching layer.

19. The method according to claim 18, wherein: The annealing process is performed at a temperature between 300°C and 500°C.

20. The method of claim 18, further comprising: forming the ferroelectric switching layer to contact an upper surface of the seed layer; as well as A second seed layer is formed to contact an upper surface of the ferroelectric switching layer.

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