Electronic component and method of manufacturing the same

Abstract

The present invention improves heat dissipation from the side in an electronic component having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately stacked on a substrate. The electronic component (1) comprises a substrate (2), a plurality of conductor layers (M1 to M4) alternately stacked on the substrate (2), and a plurality of insulating layers (11 to 14). The side surfaces (11s to 14s) of the plurality of insulating layers (11 to 14) have recessed portions (11a to 14a) that are set back from the side surfaces (2s) of the substrate (2) and convex portions (11b to 14b) that protrude from the recessed portions (11a to 14a). Thus, since the side surfaces (11s to 14s) of the insulating layers (11 to 14) have a concave-convex shape, the exposed area of ​​the side surfaces (11s to 14s) is increased. Thus, heat dissipation from the side surfaces (11s to 14s) can be improved.

Description

Technical Field

[0001] The present invention relates to an electronic component and a method for manufacturing the same, and in particular to an electronic component having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately stacked on a substrate and a method for manufacturing the same. Background Art

[0002] Patent Document 1 discloses an electronic component having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately stacked on a substrate. The electronic component described in Patent Document 1 has capacitors and inductors formed on the substrate, thereby functioning as an LC filter. Usually, a plurality of such electronic components are simultaneously manufactured using a collective substrate, and a plurality of them are obtained by dicing and singulation.

[0003] Prior art literature:

[0004] Patent Literature:

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-34626 Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] However, if the electronic components are singulated by cutting the collective substrate, the side surfaces of the electronic components become flat, so the heat dissipation from the side surfaces is not necessarily high. In addition, if the number of layers or the thickness of the insulating layer is large, there is also a problem that it is difficult to cut the collective substrate.

[0008] Therefore, an object of the present invention is to improve heat dissipation from the side surfaces of an electronic component having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately stacked on a substrate.

[0009] Another object of the present invention is to facilitate cutting in a method for manufacturing an electronic component having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately stacked on a substrate, even when the number of insulating layers or the thickness thereof is large.

[0010] Technical means to solve technical problems

[0011] The electronic component of the present invention is characterized by comprising a substrate and a plurality of conductor layers and a plurality of insulating layers alternately stacked on the substrate, wherein at least one side surface of the plurality of insulating layers has a recessed portion retreated from a side surface of the substrate and a protrusion protruding from the recessed portion.

[0012] According to the present invention, since the side surface of the insulating layer has a concavo-convex shape, the exposed area of ​​the side surface increases, thereby improving the heat dissipation from the side surface.

[0013] In the present invention, the side surfaces of the plurality of insulating layers may each have a concave portion and a convex portion, thereby further increasing the exposed area of ​​the side surfaces and further improving the heat dissipation from the side surfaces.

[0014] In the present invention, at least one side surface of the plurality of insulating layers may have concave portions and convex portions over the entire circumference. This further increases the exposed area of ​​the side surface, and thus further improves heat dissipation from the side surface.

[0015] In the present invention, the side surface of the substrate and the end surface of the protrusion may form the same plane, thereby preventing the outer diameter of the electronic component from being increased more than necessary.

[0016] In the present invention, the protrusion amount of the convex portion from the concave portion may be 3 μm or more and 10 μm or less. This can suppress an increase in the outer diameter and can sufficiently improve heat dissipation from the side surface.

[0017] The manufacturing method of the electronic component of the present invention is characterized in that it comprises: a process of simultaneously producing multiple electronic components by alternately stacking multiple conductor layers and multiple insulating layers including a sacrificial pattern on a substrate; a process of forming a space between the multiple electronic components by removing the sacrificial pattern; and a process of singulating the multiple electronic components by cutting the substrate along the space.

[0018] According to the present invention, since the substrate is cut along the space, even when the number of layers or the thickness of the insulating layer is large, cutting can be easily performed.

[0019] Effects of the Invention

[0020] Thus, according to the present invention, in an electronic component having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately stacked on a substrate, heat dissipation from the side can be improved. In addition, according to the present invention, in a method for manufacturing an electronic component having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately stacked on a substrate, cutting can be easily performed even when the number of layers or thickness of the insulating layer is large. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a cross-sectional view for explaining the structure of an electronic component 1 according to one embodiment of the present invention.

[0022] Figure 2 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0023] Figure 3 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0024] Figure 4 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0025] Figure 5 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0026] Figure 6 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0027] Figure 7 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0028] Figure 8 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0029] Fig. 9 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0030] Fig.10 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0031] Fig.11 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0032] Fig.12 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0033] Fig.13 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0034] Fig.14 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0035] Fig.15 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0036] Fig.16 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0037] Fig.17 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0038] Fig.18 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0039] Fig.19 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0040] Fig. 20 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0041] Fig.21 The following are process diagrams for explaining a method for manufacturing the electronic component 1 .

[0042] Fig. 22 1 is a partial cross-sectional view showing the relationship between the cutting widths D1 and D2 and the space A.

[0043] Fig.23 This is a schematic plan view for explaining a method of forming a concavo-convex shape over the entire circumference of a side surface.

[0044] Fig.24 This is a schematic plan view for explaining a method of forming a concavo-convex shape only on a part of the outer circumference.

[0045] Fig.25 This is a schematic plan view for explaining a method of forming a concavo-convex shape only on a part of the outer circumference.

[0046] Fig.26 It is a cross-sectional view for explaining the structure of an electronic component 1A according to a first modification.

[0047] Fig. 27 It is a cross-sectional view for explaining the structure of an electronic component 1B according to a second modification.

[0048] Fig.28 It is a cross-sectional view for explaining the structure of an electronic component 1C according to a third modification.

[0049] Explanation of symbols:

[0050] 1. 1A~1C Electronic components

[0051] 2 substrate

[0052] 2s Side of the substrate

[0053] 3 Planarization layer

[0054] 4 Dielectric film

[0055] 11~14 Insulation layer

[0056] 11a~14a concave part

[0057] 11b~14b convex part

[0058] 11s~14s Side of the insulation layer

[0059] 21~29 Conductor pattern

[0060] 30~38 Sacrifice Pattern

[0061] 41-44, 52-54, 61-64, 73, 74 Opening

[0062] A Space

[0063] D, D1, D2 Cutting width

[0064] E1, E2 terminal electrodes

[0065] L Protrusion

[0066] M1~M4、MM conductor layer

[0067] P coating

[0068] R1~R3 Resist layer

[0069] S Seed layer DETAILED DESCRIPTION

[0070] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0071] Figure 1 This is a cross-sectional view for explaining the structure of an electronic component 1 according to one embodiment of the present invention.

[0072] The electronic component 1 of this embodiment is an LC filter. Figure 1 As shown, it has a substrate 2 and conductor layers M1 to M4 and insulating layers 11 to 14 alternately stacked on the upper surface of the substrate 2. The material of the substrate 2 is not particularly limited as long as it is chemically / thermally stable, generates little stress, and can maintain surface smoothness. Single crystal silicon, aluminum oxide, sapphire, aluminum nitride, MgO single crystal, SrTiO3 single crystal, surface silicon oxide, glass, quartz, ferrite, etc. can be used. The surface of the substrate 2 is covered with a planarization layer 3. As the planarization layer 3, aluminum oxide or silicon oxide, etc. can be used.

[0073] The conductor layer M1 is the conductor layer located at the bottom layer, and includes conductor patterns 21 and 22. The conductor patterns 21 and 22 are both composed of a thin seed layer S connected to the planarization layer 3 and a plating layer P disposed on the seed layer S and having a film thickness greater than that of the seed layer S. The same is true for the conductor patterns located in other conductor layers, which are composed of a stack of the seed layer S and the plating layer P. Here, the conductor pattern 21 constitutes the lower electrode of the capacitor, and its upper surface and side are covered by a dielectric film (capacitor insulating film) 4. At the periphery of the electronic component 1, the dielectric film 4 is removed, thereby relieving stress.

[0074] A conductor pattern 23 is formed on the upper surface of the conductor pattern 21 via a dielectric film 4. The conductor pattern 23 belongs to the conductor layer MM located between the conductor layer M1 and the conductor layer M2, and constitutes the upper electrode of the capacitor. Thus, a capacitor is formed with the conductor pattern 21 as the lower electrode and the conductor pattern 23 as the upper electrode. The conductor layer M1 and the conductor layer MM are covered by the insulating layer 11.

[0075] Conductive layer M2 is a second conductive layer provided on the surface of insulating layer 11 and includes conductive patterns 24 and 25. Conductive pattern 24 is connected to conductive patterns 22 and 23 via an opening provided in insulating layer 11. Conductive layer M2 is covered by insulating layer 12.

[0076] Conductive layer M3 is a third conductive layer provided on the surface of insulating layer 12, and includes conductive patterns 26 and 27. Conductive pattern 26 is connected to conductive pattern 24 via an opening provided in insulating layer 12. Conductive layer M3 is covered with insulating layer 13.

[0077] The conductor layer M4 is a fourth conductor layer provided on the surface of the insulating layer 13 and includes conductor patterns 28 and 29. The conductor pattern 28 is connected to the conductor pattern 26 via an opening provided in the insulating layer 13. The conductor layer M4 is covered with the insulating layer 14.

[0078] Terminal electrodes E1 and E2 are provided on the upper surface of insulating layer 14. Terminal electrodes E1 and E2 are connected to conductor patterns 28 and 29 respectively via openings provided in insulating layer 14. Conductor patterns 25, 27 and 29 are, for example, parts of coil patterns, and thus capacitors and inductors are integrated on substrate 2.

[0079] like Figure 1 As shown, in the present embodiment, the side surfaces 11s to 14s of the insulating layers 11 to 14 are not flat and have a step difference. Here, the "side surface" refers to the end surface in the plane direction perpendicular to the stacking direction. In addition, the side surface 11s of the insulating layer 11 has: a recessed portion 11a, which is set back inwardly compared to the side surface 2s of the substrate 2; and a convex portion 11b, which protrudes from the recessed portion 11a. The side surfaces 12s to 14s of the other insulating layers 12 to 14 are also the same, and have: recessed portions 12a to 14a, which are set back inwardly compared to the side surface 2s of the substrate 2; and convex portions 12b to 14b, which protrude from the recessed portions 12a to 14a.

[0080] In the electronic component 1 of the present embodiment, the side surfaces 11s to 14s of the insulating layers 11 to 14 have a concavo-convex shape, so that the exposed area of ​​the side surfaces 11s to 14s is increased, thereby improving the heat dissipation from the side surfaces 11s to 14s. Figure 1Even when the orientation shown is turned upside down and mounted on a circuit board, it is difficult for the solder covering the terminal electrodes E1 and E2 to be wrapped around the side surfaces 11s to 14s, so the reliability is improved. Here, the protrusion amount L of the convex portions 11b to 14b from the concave portions 11a to 14a is preferably not less than 3 μm and not more than 10 μm. This is because by setting the protrusion amount L to not less than 3 μm, the effect of improving the heat dissipation can be fully obtained, and by setting the protrusion amount L to not more than 10 μm, the increase in the plane size can be fully suppressed. In addition, the height H of the concave portions 11a to 14a is consistent with the thickness of the conductor pattern located on the same conductor layer in the manufacturing process described later.

[0081] Next, a method for manufacturing the electronic component 1 according to the present embodiment will be described.

[0082] Figure 2 to Figure 21 The process diagram is for explaining the manufacturing method of the electronic component 1 of the present embodiment. In the manufacturing process of the electronic component 1, a plurality of electronic components 1 are obtained using a collective substrate, but the manufacturing process described below is explained focusing on the manufacturing process of one electronic component 1.

[0083] First, if Figure 2 As shown, a planarization layer 3 is formed on a substrate (collective substrate) 2 by sputtering or the like, and its surface is smoothed by grinding or CMP or the like. Then, a seed layer S is formed on the surface of the planarization layer 3 by sputtering or the like. Next, as shown in FIG. Figure 3 As shown, after the resist layer R1 is spin-coated on the seed layer S, the resist layer R1 is patterned in such a way that the seed layer S in the region where the conductor layer M1 is to be formed is exposed. In this state, electrolytic plating is performed using the seed layer S as a power source, as shown in FIG. Figure 4 As shown in FIG. 1 , a plating layer P is formed on the seed layer S. The stack of the seed layer S and the plating layer P constitutes the conductor layer M1. Figure 4 In the cross section shown in FIG. 1 , the conductor layer M1 includes conductor patterns 21, 22 and sacrificial patterns 31, 32. Figure 5 As shown, the resist layer R1 is removed, as shown in Figure 6 As shown, when the seed layer S exposed on the surface is removed, the conductor layer M1 is completed. The seed layer S can be removed by etching or ion milling.

[0084] Next, if Figure 7 As shown, a dielectric film 4 is formed on the entire surface including the upper surface and the side surface of the conductor layer M1. As the dielectric film 4, for example, in addition to normal dielectric materials such as silicon nitride (SiNx) or silicon oxide (SiOx), a well-known ferroelectric material can also be used. As a film forming method of the dielectric film 4, a sputtering method, a plasma CVD method, a MOCVD method, a sol-gel method, an electron beam evaporation method, etc. can be used.

[0085] Then, if Figure 8 As shown, by using the same method as the method for forming the conductor layer M1, a conductor pattern 23 is formed on the upper surface of the conductor pattern 21 via the dielectric film 4. The conductor pattern 23 is also composed of a stack of a seed layer S and a plating layer P. Thus, the conductor layer MM is completed, and a capacitor is formed with the conductor pattern 21 as a lower electrode and the conductor pattern 23 as an upper electrode. Although not particularly limited, it is preferred to improve the processing accuracy of the conductor layer MM by making the film thickness of the conductor layer MM thinner than the film thickness of the conductor layer M1, thereby reducing the deviation of the capacitance caused by the processing accuracy. Thereafter, as Fig. 9 As shown, the dielectric film 4 of the portion that will become the outer periphery of the electronic component 1 is finally removed.

[0086] Then, if Fig.10 As shown, after forming the insulating layer 11 covering the conductor layers M1 and MM, the insulating layer 11 is patterned, as shown in FIG. Fig.11 As shown, openings 41 to 44 are formed in insulating layer 11. Thus, upper surfaces of conductor patterns 23 and 22 are exposed through openings 41 and 42, respectively, and dielectric film 4 covering the upper surfaces of conductor patterns 23 and 22 is exposed through openings 43 and 44, respectively.

[0087] Then, if Fig.12 As shown, after forming a resist layer R2 on the insulating layer 11, an opening 52 is formed in the resist layer R2. As a result, the dielectric film 4 covering the upper surface of the conductor pattern 22 is exposed through the opening 52. In this state, by performing ion milling or the like, the dielectric film 4 exposed in the opening 52 is removed, and the upper surface of the conductor pattern 22 is exposed.

[0088] Then, after removing the resist layer R2, as Fig.13 As shown in FIG. 1 , the conductor layer M2 is formed on the insulating layer 11 by the same method as the method of forming the conductor layer M1. Fig.13 In the cross section shown, the conductor patterns 24, 25 and the sacrificial patterns 33, 34 are included in the conductor layer M2. Each conductor pattern and the sacrificial pattern constituting the conductor layer M2 are also composed of a stack of the seed layer S and the plating layer P. Here, the conductor pattern 24 is commonly connected to the conductor patterns 22, 23 via the opening provided in the insulating layer 11, and the sacrificial patterns 33, 34 are respectively connected to the sacrificial patterns 31, 32 via the opening provided in the insulating layer 11. Next, as Fig.14 As shown, an insulating layer 12 is formed to cover the conductor layer M2.

[0089] Afterwards, by repeating the same process, Fig.15 As shown, the conductor layer M3, the insulating layer 13, the conductor layer M4 and the insulating layer 14 are formed in sequence. Fig.15In the cross section shown, the conductor patterns 26, 27 and the sacrificial patterns 35, 36 are included in the conductor layer M3, and the conductor patterns 28, 29 and the sacrificial patterns 37, 38 are included in the conductor layer M4. Here, the conductor pattern 26 is connected to the conductor pattern 24 via an opening provided in the insulating layer 12, and the sacrificial patterns 35, 36 are connected to the sacrificial patterns 33, 34 respectively via an opening provided in the insulating layer 12. In addition, the conductor pattern 28 is connected to the conductor pattern 26 via an opening provided in the insulating layer 13, and the sacrificial patterns 37, 38 are connected to the sacrificial patterns 35, 36 respectively via an opening provided in the insulating layer 13.

[0090] Then, if Fig.16 As shown in FIG. 1 , the insulating layer 14 is patterned to form openings 61 and 62. Thus, the upper surfaces of the conductor patterns 28 and 29 are exposed through the openings 61 and 62, respectively. Fig.17 As shown, terminal electrodes E1 and E2 are formed on the insulating layer 14 . The terminal electrode E1 is connected to the conductive pattern 28 via an opening provided in the insulating layer 14 , and the terminal electrode E2 is connected to the conductive pattern 29 via an opening provided in the insulating layer 14 .

[0091] Then, if Fig.18 As shown in FIG. 1 , the insulating layer 14 is patterned to form openings 63 and 64. Thus, the upper surfaces of the sacrificial patterns 37 and 38 are exposed through the openings 63 and 64, respectively. Fig.19 As shown in FIG. 1 , after a resist layer R3 is formed on the entire surface of the insulating layer 14 including the terminal electrodes E1 and E2, openings 73 and 74 are formed in the resist layer R3 to expose the sacrificial patterns 37 and 38. In this state, etching is performed using acid or the like. Fig. 20 As shown in FIG. 1 , the sacrificial patterns 31 to 38 are removed. Thus, a space A is formed in a region where the sacrificial patterns 31 to 38 are removed.

[0092] Then, after removing the resist layer R3, as shown in FIG. Fig.21 As shown, the electronic component 1 is divided into individual pieces by cutting the substrate 2 along the space A. Thus, the electronic component 1 of the present embodiment is completed.

[0093] Here, Fig.21 The symbol D shown is the cutting width (cutting amount). The cutting width D is narrower than the maximum width of the space A, and thus the side surface of the singulated electronic component 1 becomes Figure 1 There is no particular limitation on the relationship between the cutting width D and the minimum width of the space A. Fig. 22As shown in FIG. 1 , if the cutting width D1 is wider than the minimum width of the space A, the front ends of the protrusions 11b to 14b of the insulating layers 11 to 14 are removed, so that the side surface 2s of the substrate 2 and the end surfaces of the protrusions 11b to 14b form the same plane. On the other hand, if the cutting width D2 is narrower than the minimum width of the space A, the side surface 2s of the substrate 2 protrudes from the protrusions 11b to 14b. In order to minimize the outer diameter of the electronic component 1, it is preferable to set the cutting width to D1 as in the former.

[0094] Here, the side surface of the electronic component 1 may have a concavo-convex shape over the entire circumference, or may have a concavo-convex shape partially. Fig.23 As shown in FIG. 1 , it is sufficient to form the sacrificial pattern 30 on the entire circumference of the electronic component 1. On the other hand, in order to form a concave-convex shape only on a portion of the side surface, as shown in FIG. 10 in the top view, Fig.24 and Fig.25 As shown in FIG. 1 , it is sufficient to form the sacrificial pattern 30 on a portion of the outer periphery of the electronic component 1. Fig.24 In the example shown, the sacrificial pattern 30 is formed on the straight line portion of the side surface of the electronic component 1 except for the corner portion. In this case, since the insulating layers 11 to 14 remain at the corner portion where the sacrificial pattern 30 does not exist, the insulating layers 11 to 14 located at the corner portion need to be cut when singulating. Fig.25 In the example shown, the sacrificial pattern 30 is formed at the corner of the side surface of the electronic component 1. In this case, since the insulating layers 11 to 14 remain in the straight line portion where the sacrificial pattern 30 does not exist, the insulating layers 11 to 14 located in the straight line portion need to be cut during individualization.

[0095] As described above, the electronic component 1 of this embodiment has a concave-convex shape on the side surfaces 11s to 14s of the insulating layers 11 to 14, so that the heat dissipation from the side surfaces 11s to 14s is improved, and the solder covering the terminal electrodes E1 and E2 is unlikely to be wrapped around the side surfaces 11s to 14s. In addition, in the manufacturing process of the electronic component 1, since the substrate 2 is cut along the space A formed by removing the sacrificial patterns 31 to 38, the load applied to the cutting blade can be greatly reduced. As a result, even if the number of layers or thickness of the insulating layer is large, cutting can be easily performed.

[0096] In the electronic component 1 of the above embodiment, the side surfaces 11s to 14s of the insulating layers 11 to 14 all have a concavo-convex shape, but in the present invention, this is not essential, as long as the side surface of at least one insulating layer has a concavo-convex shape. Fig.26As in the electronic component 1A of the first modification shown, the side surfaces 13s and 14s of the insulating layers 13 and 14 may have a concave-convex shape, and the side surfaces 11s and 12s of the insulating layers 11 and 12 may be flat. Such a shape can be obtained by omitting the sacrificial patterns 31 to 34 located in the conductive layers M1 and M2.

[0097] Fig. 27 It is a cross-sectional view for explaining the structure of an electronic component 1B according to a second modification.

[0098] Fig. 27 The electronic component 1B shown is Figure 1 The electronic component 1 shown in the figure is different in that the protrusion amount of the protrusions 11b to 14b from the recesses 11a to 14a is not constant but varies for each insulating layer 11 to 14. Figure 1 The electronic component 1 shown is the same, and therefore the same elements are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0099] Fig. 27 The electronic component 1B shown in the figure satisfies L2>L4>L3>L1 when the protrusion amounts of the convex parts 11b~14b from the concave parts 11a~14a are set to L1, L2, L3, and L4 respectively. As shown in the electronic component 1B of the second modified example, in the present invention, the protrusion amounts L1~L4 are not necessarily constant, and may be partially or completely different. If the protrusion amounts L1~L4 are made different from each other, the stress dispersion effect can be obtained.

[0100] Fig.28 It is a cross-sectional view for explaining the structure of an electronic component 1C according to a third modification.

[0101] Fig.28 The electronic component 1C shown is Fig. 27 The difference of the electronic component 1B shown is that the protrusion amounts L1 to L4 satisfy L1>L2>L3>L4. The other basic structures are the same as Fig. 27 The electronic component 1B shown is the same, so the same reference numerals are given to the same elements and redundant descriptions are omitted. According to such a structure, the rigidity of the upper insulating layer, which is likely to be insufficient in rigidity, can be further improved.

[0102] As mentioned above, although the preferred embodiment of the present invention has been described, the present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the gist of the present invention, and these modifications are naturally included in the scope of the present invention.

[0103] For example, in the above-mentioned embodiment, the case where the present invention is applied to an LC filter is described as an example, but the electronic component to which the present invention is applied is not limited to the LC filter, and may be applied to other types of electronic components.

Claims

1. An electronic component, characterized in that: have: substrate; and A plurality of conductor layers and a plurality of insulating layers are alternately stacked on the substrate, A side surface of at least one of the plurality of insulating layers has: a concave portion that is set back from a side surface of the substrate; and a convex portion protruding from the concave portion, The height of the recessed portion is equal to the thickness of the conductor pattern of the conductor layer located at the same position in the stacking direction among the plurality of conductor layers.

2. The electronic component according to claim 1, characterized in that The plurality of insulating layers each have the concave portion and the convex portion on the side surface.

3. The electronic component according to claim 1, characterized in that The side surface of at least one of the plurality of insulating layers has the concave portion and the convex portion over the entire circumference.

4. The electronic component according to claim 1, characterized in that The side surface of the substrate and the end surface of the protrusion form a flush plane.

5. The electronic component according to claim 1, characterized in that The protrusion amount of the convex portion from the concave portion is 3 μm or more and 10 μm or less.

6. The electronic component according to any one of claims 1 to 5, characterized in that: The electronic component functions as an LC filter.

7. A method for manufacturing an electronic component, characterized in that: have: A process for simultaneously manufacturing a plurality of electronic components by alternately stacking a plurality of conductor layers including sacrificial patterns and a plurality of insulating layers on a substrate; A step of forming a space between the plurality of electronic components by removing the sacrificial pattern and forming a concave portion having a height that matches the thickness of the sacrificial pattern of the conductor layer located at the same position in the stacking direction among the plurality of conductor layers and a convex portion protruding from the concave portion on at least one side surface of the plurality of conductor layers; as well as A step of cutting the substrate along the space to separate the plurality of electronic components.

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