Organic light emitting diode display device and manufacturing method thereof

Abstract

An organic light emitting diode display device and a manufacturing method thereof are provided. The organic light emitting diode display device includes: a substrate in which a pixel region and a non-pixel region are defined; a power line formed on the substrate; a buffer film covering the power line; an active interconnection line formed on the buffer film; an auxiliary interconnection line extending through the buffer film and connecting one end of the active interconnection line to an auxiliary electrode; a first passivation film covering the auxiliary interconnection line and having a contact hole formed through the first passivation film, an undercut structure formed in the contact hole so that the active interconnection line is exposed through the undercut structure; and a light emitting element including a first electrode, a light emitting layer, and a second electrode sequentially stacked on the first passivation film in the pixel region, wherein the second electrode extends into the non-pixel region so that the second electrode is connected to a portion of the active interconnection line exposed through the undercut structure in the contact hole.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0180134, filed on Dec. 31, 2019, which is hereby incorporated by reference in its entirety for all purposes. Technical Field

[0003] The present invention relates to an organic light emitting diode (OLED) display device and a manufacturing method thereof. Background Art

[0004] As the information society progresses, various types of display devices have been developed. Recently, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) display device have been used.

[0005] Since the organic light emitting elements constituting the organic light emitting diode display device are self-luminous elements, such an organic light emitting diode display device does not require an additional light source, thereby realizing a thin and light display device. In addition, such an organic light emitting diode (OLED) display device exhibits high quality characteristics such as low power consumption, high brightness, and fast response speed.

[0006] OLED display devices include an array of multiple pixels, each of which includes a transistor, a capacitor, and a light-emitting element. As the resolution and size of the display device increase, the number and density of pixels arranged in the display device also increase accordingly. In order to ensure the operation and performance reliability of such a large, high-density display device, it is necessary to reduce the complexity of the manufacturing process and improve the yield.

[0007] Specifically, an organic light emitting diode (OLED) display device has an undercut structure in a contact hole through which one electrode is connected to another electrode. In this case, it is necessary to prevent defects caused by short circuits of interconnection lines after forming the undercut structure and optimize the manufacturing process for production efficiency of the OLED display device. Summary of the invention

[0008] The present invention has been made in view of the problems occurring in the related art, and an object of the present invention is to provide an OLED display device having a simplified undercut structure.

[0009] Another object of the present invention is to provide a method for manufacturing an OLED display device having a simplified undercut structure.

[0010] The objects of the present invention are not limited to the above objects, and other objects and advantages not mentioned above will be clearly understood by those skilled in the art from the following description.

[0011] In order to achieve one of the objects of the present invention, an organic light emitting diode (OLED) display device according to some exemplary embodiments of the present invention includes: a substrate, in which a pixel area and a non-pixel area are defined; an auxiliary electrode formed on the substrate; a buffer film covering the auxiliary electrode; an active interconnection line formed on the buffer film; an auxiliary interconnection line, the auxiliary interconnection line extending through the buffer film and connecting one end of the active interconnection line to the auxiliary electrode; a first passivation film, the first passivation film covering the auxiliary interconnection line and having a contact hole formed through the first passivation film, wherein an undercut structure is formed in the contact hole so that the active interconnection line is exposed through the undercut structure; and a light emitting element, the light emitting element including a first electrode, a light emitting layer, and a second electrode stacked sequentially on the first passivation film in the pixel area, wherein the second electrode extends into the non-pixel area so that the second electrode is connected to a portion of the active interconnection line exposed by the undercut structure located in the contact hole.

[0012] In some embodiments of the present invention, the second electrode may extend along an upper surface of the active interconnection line and extend into the undercut structure to be connected with the auxiliary interconnection line.

[0013] In some embodiments of the present invention, a portion of the first passivation film protrudes outwardly above the active interconnection line, and the light emitting layer may not be formed on an upper surface of the active interconnection line overlapping the first passivation film.

[0014] In some embodiments of the present invention, the organic light emitting diode display device may further include a driving transistor, which is formed on the substrate and drives the light emitting element, wherein the driving transistor includes a gate electrode and a drain electrode electrically connected to the first electrode, and the gate electrode, the drain electrode and the auxiliary interconnection line may be formed in the same process step.

[0015] In some embodiments of the present invention, the organic light emitting diode display device may further include an auxiliary substrate provided with a color filter and bonded to the substrate via a filling material provided between the auxiliary substrate and the substrate.

[0016] In some embodiments of the present invention, an upper end of the undercut structure may be defined by a lower surface of the first passivation film.

[0017] In some embodiments of the present invention, a portion of the first passivation film may protrude into the contact hole to protrude outward above the active interconnect line and overlap with the active interconnect line when viewed from above, and the second electrode may extend to an upper surface of the active interconnect line overlapping with the first passivation film.

[0018] In some embodiments of the present invention, the organic light emitting diode display device may further include a second passivation film for filling the undercut structure.

[0019] To achieve another object of the present invention, a method for manufacturing an organic light emitting diode (OLED) display device according to some exemplary embodiments of the present invention includes: forming an auxiliary electrode on a substrate, wherein a pixel area and a non-pixel area are defined in the substrate; forming a buffer film in a manner covering the auxiliary electrode; forming an active interconnection line on the buffer film; forming an auxiliary interconnection line, wherein the auxiliary interconnection line passes through the buffer film and connects at least one of the auxiliary electrodes to the active interconnection line; forming a passivation film covering the auxiliary interconnection line; etching the passivation film in the non-pixel area to expose a portion of the auxiliary interconnection line; forming a contact hole including an undercut structure by partially etching the exposed auxiliary interconnection line; and forming a light emitting element, wherein the light emitting element includes a first electrode, a light emitting layer, and a second electrode sequentially formed on the passivation film, wherein the second electrode extends into the non-pixel area to be connected to the active interconnection line exposed by the undercut structure.

[0020] In some embodiments of the present invention, forming the active interconnect line may include: forming an active pattern including a silicon-based semiconductor or an oxide-based semiconductor on the buffer film; and performing at least one of plasma treatment and heat treatment on the active pattern to make the active pattern conductive.

[0021] In some embodiments of the present invention, in the method, the second electrode is formed to extend along an upper surface of the active interconnection line and to extend into the undercut structure, so that the second electrode is connected to the auxiliary interconnection line within the undercut structure.

[0022] In some embodiments of the present invention, the method may further include forming a driving transistor for driving the light-emitting element on the substrate, wherein the driving transistor includes a gate electrode and a drain electrode electrically connected to the first electrode. In addition, the gate electrode, the drain electrode and the auxiliary interconnection line may be formed in the same process step.

[0023] In some embodiments of the present invention, the method may further include bonding an auxiliary substrate provided with a color filter to the substrate, the color filter being disposed to face the substrate.

[0024] The organic light emitting diode (OLED) display device according to various embodiments of the present invention has the advantage of low contact resistance because the second electrode of the light emitting element and the active interconnection line are directly connected to each other, which reduces power consumption and heat generation.

[0025] Furthermore, since the second electrode directly contacts the auxiliary interconnection line within the undercut structure, the area of ​​the contact surface on which the conductive path between the second electrode and the auxiliary electrode can be formed is increased. Therefore, the power consumption of the OLED display device can be reduced.

[0026] The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will become apparent to those skilled in the art from the description of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a block diagram illustrating a configuration of a display device according to an exemplary embodiment of the present invention;

[0028] Figure 2 It is a graphic Figure 1 A circuit diagram of a pixel of a display device;

[0029] Figure 3 yes Figure 1 A perspective view of a display device;

[0030] Figure 4 is a cross-sectional view of a display panel of a display device according to an embodiment of the present invention;

[0031] Figure 5A and Figure 5B It is a graphic Figure 4 A magnified view of the undercut structure;

[0032] Figures 6 to 13 is a diagram illustrating an intermediate manufacturing step of a display device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0033] Hereinafter, various exemplary embodiments will be described with reference to the accompanying drawings. Throughout the specification, when a component is described as being "disposed on" another component, "connected to" another component, "joined to" another component, or "combined with" another component, it should be understood that the component may be disposed on, connected to, joined to, or combined with another component directly or with another component interposed therebetween.

[0034] In all the drawings, the same reference numerals represent the same constituent elements. In addition, for effective description and explanation, the thickness, ratio and size of each constituent element shown in the drawings are exaggerated. The term "and / or" includes all combinations of one or more associated elements.

[0035] Although used to describe various constituent elements, the terms first, second, etc. do not impose any limitation on the terms. These terms are used to distinguish one constituent component from one or more other constituent components. Therefore, the first constituent element to be described below may be the second constituent element within the scope of the technical concept of the present invention.

[0036] When the terms "over", "above", "under", "below", "under", "adjacent to", etc. are used to describe the positional relationship between two constituent elements, one or more other constituent elements may be located between the two constituent elements. These terms are relatively determined between the constituent elements based on the directions indicated in the drawings.

[0037] It will be further understood that when the terms "include" and / or "comprises", or "has", are used in this application, they specify the presence of the stated features, regions, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, parts and / or combinations thereof.

[0038] Figure 1 is a block diagram illustrating a configuration of a display device according to an exemplary embodiment of the present invention.

[0039] Reference Figure 1 , the display device 1 includes a timing controller 10 , a gate driver 20 , a data driver 30 , a power supply unit 40 and a display panel 50 .

[0040] The timing controller 10 may receive an image signal RGB and a control signal CS from an external device. The image signal RGB may be grayscale data consisting of a plurality of grayscales. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

[0041] The timing controller 10 processes the image signal RGB and the control signal CS into operating conditions suitable for the display panel 50 , thereby generating and outputting image data, a gate driving control signal CONT1 , a data driving control signal CONT2 , and a power control signal CONT3 .

[0042] The gate driver 20 may be connected to the pixels PX of the display panel 50 through the plurality of gate lines GL1 to GLn. The gate driver 20 may generate gate signals according to the gate driving control signals CONT1 output from the timing controller 10. The gate driver 20 may provide the generated gate signals to the pixels PX through the plurality of gate lines GL1 to GLn.

[0043] The data driver 30 may be connected to the pixels PX of the display panel 50 through the plurality of data lines DL1 to DLm. The data driver 30 may generate data signals according to the image data DATA and the data driving control signal CONT2 output from the timing controller 10. The data driver 30 may provide the generated data signals to the pixels PX through the plurality of data lines DL1 to DLm.

[0044] The power supply unit 40 may be connected to the pixels PX of the display panel 50 through a plurality of power supply lines PL1 and PL2. The power supply unit 40 may generate a driving voltage to be provided to the display panel 50 based on a power supply control signal CONT3. For example, the driving voltage may include a high potential driving voltage ELVDD and a low potential driving voltage ELVSS. The power supply unit 40 may supply the generated driving voltages ELVDD and ELVSS to the pixels PX through the corresponding power supply lines PL1 and PL2.

[0045] A plurality of pixels (or referred to as sub-pixels) PX are arranged on the display panel 50. The pixels PX may be arranged on the display panel 50 in a matrix form.

[0046] Each pixel PX is electrically connected to a corresponding one of the gate lines and a corresponding one of the data lines. The pixel PX emits light having a brightness level corresponding to gate signals and data signals supplied through the gate lines GL1 to GLn and the data lines DL1 to DLm.

[0047] Each pixel PX can display one of three colors, respectively referred to as a first color, a second color, and a third color. According to one embodiment, each pixel PX displays any one of red, green, and blue. According to another embodiment, each pixel PX displays any one of cyan, magenta, and yellow. In various embodiments, each pixel PX is configured to display any one of four or more colors. For example, each pixel PX can display any one of red, green, blue, and white.

[0048] The timing controller 10, the gate driver 20, the data driver 30, and the power supply unit 40 may be implemented as separate integrated circuits (ICs), respectively. Alternatively, two or more of the timing controller 10, the gate driver 20, the data driver 30, and the power supply unit 40 may be integrated into a single integrated circuit (IC). For example, the timing controller 10 and at least one of the data driver 30 and the power supply unit 40 may be combined into a single integrated circuit.

[0049] exist Figure 1 , the gate driver 20 and the data driver 30 are illustrated as components separated from the display panel 50. However, the display panel and at least one of the gate driver 20 and the data driver 30 may be integrated into a single unit referred to as an in-panel type. For example, in the case of a gate-in-panel (GIP) scheme, the gate driver 20 is integrated into the display panel 50.

[0050] Figure 2 It is a graphic Figure 1 For example, Figure 2 Schematic diagram of connection to the i-th gate line GL i and the jth data line DL j The pixel P ij .

[0051] Reference Figure 2 , pixel P ij It includes a switching transistor ST, a driving transistor DT, a storage capacitor Cst and a light emitting element LD.

[0052] A first electrode (eg, a source electrode) of the switching transistor ST is electrically connected to the j-th data line DL j , and the second electrode (eg, drain electrode) is electrically connected to the first node N1. The gate electrode of the switching transistor ST is electrically connected to the i-th gate line GL i When a gate signal having a gate-on level is applied to the i-th gate line GL i When the switch transistor ST is turned on, the jth data line DL j The provided data signal is transmitted to the first node N1.

[0053] A first electrode of the storage capacitor Cst is electrically connected to the first node N1, and a second electrode of the storage capacitor Cst is electrically connected to the anode electrode of the light emitting element LD. The driving transistor DT operates according to the data voltage stored in the storage capacitor Cst to flow a driving current between a voltage terminal for providing a high potential driving voltage ELVDD and a voltage terminal for providing a low potential driving voltage ELVSS.

[0054] The first electrode (e.g., source electrode) of the driving transistor DT is configured to receive the high potential driving voltage ELVDD, and the second electrode (e.g., drain electrode) is electrically connected to the first electrode (e.g., anode electrode) of the light emitting element LD. The gate electrode of the driving transistor DT is electrically connected to the first node N1. The driving transistor DT is turned on when a voltage corresponding to the gate-on level is applied to its gate electrode through the first node N1, and controls the amount of driving current flowing through the light emitting element LD according to the voltage applied to its gate electrode.

[0055] The light emitting element LD emits an amount of light corresponding to the driving current. The light emitting element LD may emit light of any color selected from red, green, and blue. The light emitting element LD may be an organic light emitting diode (OLED) or an ultra-small inorganic light emitting diode having a size ranging from micrometers to nanometers, but the present invention is not limited thereto. Hereinafter, an embodiment of realizing the light emitting element LD using an organic light emitting diode will be described.

[0056] In various embodiments of the present invention, the structure of the pixel PX is not limited to Figure 2 According to one embodiment, each pixel PX may include at least one element selected from an element for compensating for a change in a threshold voltage of the driving transistor DT and an element for initializing a voltage of a gate electrode of the driving transistor DT and / or a voltage of an anode electrode of the light emitting element LD.

[0057] Figure 2 The example in which the switch transistor ST and the drive transistor DT are NMOS transistors is illustrated, but the present invention is not limited thereto. For example, at least some or all of the transistors constituting each pixel PX may be implemented with PMOS transistors. In various embodiments, each of the switch transistor ST and the drive transistor DT may be implemented with a low temperature polycrystalline silicon (LTPS) thin film transistor (TFT), an oxide thin film transistor, or a low temperature polycrystalline oxide (LTPO) thin film transistor (TFT).

[0058] Figure 3 yes Figure 1 A perspective view of a display device. Figure 1 , Figure 2 and Figure 3 The components of the display device 1 are described in more detail.

[0059] The display device 1 is a device that displays an image and may be a self-luminous display such as an organic light emitting diode display, or a non-luminous display such as a liquid crystal display (LCD), an electrophoretic display (EPD), and an electrowetting display (EWD).

[0060] The display device 1 can be implemented in various forms. For example, the display device 1 can be in the shape of a rectangular plate. However, the present invention is not limited thereto. For example, the display device 1 can have a square shape, a circular shape, an elliptical shape, or a polygonal shape. The display device 1 can have a shape with rounded corners or a shape with chamfered corners. The display device 1 can be shaped so that the thickness of at least a portion thereof gradually changes. Optionally, at least a portion of the display device 1 can be flexible.

[0061] The display panel 50 includes a display area DA and a non-display area NDA. The display area DA is an area in which pixels PX are disposed. The display area DA is also referred to as an active area. The non-display area NDA may be disposed at the periphery of the display area DA. For example, the non-display area NDA may be disposed along the periphery of the display area DA. The term "non-display area NDA" refers collectively to an area other than the display area DA within the display panel 50, and may be referred to as a non-active area.

[0062] The non-display area NDA is provided with a gate driver 20 to drive the pixels PX. The gate driver 20 may be provided in the non-display area NDA and adjacent to one side or two opposite sides of the display area DA. The gate driver 20 may be provided in the non-display area NDA of the display panel 50 in the form of a gate-in-panel, such as Figure 3 However, in another embodiment, the gate driver 20 may be implemented as a driving chip mounted on a flexible film or the like and bonded to the non-display area NDA using a tape automated bonding (TAB) method.

[0063] The non-display area NDA may be provided with a plurality of pads (not shown). The pads are not covered by the insulating layer. That is, the pads are exposed from the surface of the display panel 50 and are electrically connected to the data driver 30 and the circuit board 70 to be described later.

[0064] The display panel 50 may include interconnection lines through which electrical signals are transmitted to the pixels PX. The interconnection lines may include, for example, gate lines GL1 to GLn, data lines DL1 to DLm, and power lines PL1 and PL2.

[0065] The power lines PL1 and PL2 are electrically connected to the power supply unit 40 (or the timing controller 10 ) through pads, thereby transmitting the high potential driving voltage ELVDD and the low potential driving voltage ELVSS provided from the power supply unit 40 (or the timing controller 10 ) to the pixels PX.

[0066] The flexible film 60 has a first end attached to the pad area PA of the display panel 50 and a second end attached to the circuit board 70. The flexible film 60 electrically connects the display panel 50 and the circuit board 70. The flexible film 60 includes a plurality of interconnection lines for electrically connecting the pads formed in the pad area PA with the interconnection lines of the circuit board 70. According to one embodiment, the flexible film 60 is attached to the upper surface of the corresponding pad via an anisotropic conductive film (ACF).

[0067] When the data driver 30 is manufactured as a driver chip, the data driver 30 may be mounted on the flexible film 60 in a chip on film (COF) or chip on plastic (COP) manner. The data driver 30 generates data signals based on the image data DATA and the data driving control signal CONT2 received from the timing controller 10, and outputs the data signals to the data lines DL1 to DLm through the connected pads.

[0068] A plurality of circuits each implemented in the form of a driving chip may be mounted on the circuit board 70. The circuit board 70 may be a printed circuit board or a flexible printed circuit board, but the type of the circuit board 70 is not limited thereto.

[0069] The circuit board 70 may include a timing controller 10 and a power supply unit 40, each of which is mounted in the form of an integrated circuit. Figure 3 , the timing controller 10 and the power supply unit 40 are illustrated as separate components, but the embodiments of the present invention are not limited thereto. That is, in various embodiments, the power supply unit 40 and the timing controller 10 may be integrated. Alternatively, the timing controller 10 may be configured to perform the function of the power supply unit 40.

[0070] Figure 4 is a cross-sectional view of a display panel according to an exemplary embodiment of the present invention.

[0071] Reference Figure 4 The display panel 50 includes a pixel area PXA and a non-pixel area NPXA disposed around the pixel area PXA, in which a pixel PX composed of a circuit element and a light emitting element 250 is formed. The non-pixel area NPXA may include a non-display area NDA and / or a boundary between adjacent pixels PX.

[0072] like Figure 4 As shown in , a display panel 50 according to an exemplary embodiment of the present invention may include a top-emitting light emitting element 250. When the light emitting element 250 is a top-emitting element, light emitted from an organic light emitting layer leaves the light emitting element 250 through a cathode electrode formed on a top surface. The emitted light selectively passes through a color filter 320. That is, only a specific wavelength passes through the color filter 320. The color filter 320 is an optional component and thus may be omitted.

[0073] The display panel 50 includes a first substrate 100 , a buffer film 110 , auxiliary electrodes ( 105 , 106 , 107 , and 120 ), auxiliary interconnection lines 145 , a first passivation film 150 , a coating film 160 , and a light emitting element 250 , and a contact hole 215 .

[0074] The first substrate 100 is a base substrate of the display panel 50, which may be a light-transmitting substrate (i.e., a transparent substrate). The first substrate 100 may be a rigid substrate made of glass or tempered glass, or may be a flexible substrate made of plastic. For example, the first substrate 100 is made of a plastic material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), etc. However, the material of the first substrate 100 is not limited thereto.

[0075] Auxiliary electrodes 105, 106, 107, and 120 may be disposed on the first substrate 100. The auxiliary electrode 105 disposed under the active pattern 130 serves as a light shielding layer to protect the oxide semiconductor device from external light. That is, the auxiliary electrode and the active pattern 130 are disposed at different heights to overlap each other.

[0076] At least one of the auxiliary electrodes 105, 106, 107 and 120 is connected to a first power line PL1 to which a high potential driving voltage ELVDD is applied or a second power line PL2 to which a low potential driving voltage ELVSS is applied. However, the present invention is not limited thereto. Specifically, the auxiliary electrode 120 connected to the auxiliary interconnection line 145 may be connected to a second power line PL2 to which a low potential driving voltage ELVSS is applied. In addition, another auxiliary electrode (not shown) adjacent to the auxiliary electrode 120 is also connected to a second power line PL2 to which a low potential driving voltage ELVSS is applied. That is, there may be two paths for applying a low potential driving voltage ELVSS. According to this configuration, the effect of reducing the resistance of the interconnection line can be obtained.

[0077] The auxiliary electrodes 105, 106, 107 and 120 are made of a metal or a metal alloy selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and alloys of these metals.

[0078] The buffer film 110 is formed on the first substrate 100 in a manner covering the auxiliary electrodes 105, 106, 107 and 120. The buffer film 110 prevents ions or impurities from diffusing from the first substrate 100 and blocks moisture. In addition, the buffer film 110 improves surface uniformity of the first substrate 100.

[0079] The buffer film 110 is made of an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite. The buffer film 110 may have a single-layer structure or a multi-layer structure. For example, the buffer film 110 may be a multi-layer structure consisting of three or more layers. For example, the buffer film 110 is a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0080] The active pattern 130 is formed on the buffer film 110. The active pattern 130 is made of a silicon-based semiconductor material or an oxide-based semiconductor material. Amorphous silicon or polycrystalline silicon may be used as the silicon-based semiconductor material. As oxide-based semiconductor materials, quaternary metal oxides such as indium tin gallium zinc oxide (InSnGaZnO); ternary metal oxides such as indium gallium zinc oxide (InGaZnO), indium tin zinc oxide (InSnZnO), indium aluminum zinc oxide (InAlZnO), tin gallium zinc oxide (SnGaZnO), aluminum gallium zinc oxide (AlGaZnO), tin aluminum zinc oxide (SnAlZnO); or binary metal oxides such as indium zinc oxide (InZnO), tin zinc oxide (SnZnO), aluminum zinc oxide (AlZnO), zinc magnesium oxide (ZnMgO), tin magnesium oxide (SnMgO), indium magnesium oxide (InMgO), indium gallium oxide (InGaO); indium oxide (InO), tin oxide (SnO) and zinc oxide (ZnO) can be used.

[0081] The active pattern 130 may include a drain region 136 and a source region 137 including p-type or n-type impurities. A channel may be formed between the drain region 136 and the source region 137.

[0082] An active interconnection line 131 is formed on the buffer film 110. As described later, the active interconnection line 131 may electrically connect the second electrode 210 and the auxiliary interconnection line 145.

[0083] The active interconnect 131 may be a conductive line made of a silicon-based semiconductor or an oxide-based semiconductor. For example, the oxide-based semiconductor formed on the buffer film 110 may be changed into a conductor by a plasma etching process or an enhanced capacitively coupled plasma treatment process. However, the method of changing the oxide semiconductor into a conductor is not limited thereto. The oxide semiconductor can be changed into a conductor by thermal treatment. In some embodiments, the active interconnect 131 may be formed on the buffer film 110 by the same process as the method of forming the active pattern 130 before performing the plasma treatment.

[0084] The gate insulating film 140 is interposed between a gate electrode 143 described later and the active pattern 130. The gate insulating film 140 may be formed to cover the buffer film 110.

[0085] The gate insulating film 140 is a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a double film of SiOx and SiNx.

[0086] A first conductive film is disposed on the gate insulating film 140. The first conductive film may include a gate electrode 143. The gate electrode 143 is disposed at a position corresponding to a channel between the drain region 136 and the source region 137 of the active pattern 130.

[0087] The gate electrode 143 is made of a material selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these metals. Alternatively, the gate electrode 143 may have a multilayer structure made of one or more materials selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these metals. For example, the gate electrode 143 may be a double layer of molybdenum and aluminum neodymium, or a double layer of molybdenum and aluminum.

[0088] The first conductive film may further include an auxiliary interconnection line 145. The auxiliary interconnection line 145 is formed to extend through the gate insulating film 140 and the first buffer film 110 and is connected to the auxiliary electrode 120. The auxiliary interconnection line 145 extends to the non-pixel area NPXA, thereby being directly connected to the active interconnection line 131. Therefore, the first auxiliary interconnection line 145 forms an intermediate conductive path between the active interconnection line 131 and the auxiliary electrode 120.

[0089] The first auxiliary interconnection line 145 is formed in the same process step as the gate electrode 143. Here, the expression "one element is formed in the same process step as another element" means that one element is formed at the same time as the other element, that is, formed by the same process. That is, the gate electrode 143 and the first auxiliary interconnection line 145 are formed at the same time by the same process. This process may be a process of depositing a conductive material on the gate insulating film 140.

[0090] The first auxiliary interconnection line 145 and the active interconnection line 131 define one side surface and a bottom surface of the contact hole 215, respectively, and the first auxiliary interconnection line 145 and the active interconnection line 131 are electrically connected to the second electrode 210 through the contact hole 215. Figure 5A and Figure 5B A more detailed description is given.

[0091] Figure 5A and 5B It is a graphic Figure 4 An enlarged view of the contact hole 215 is shown.

[0092] First refer to Figure 5A, the contact hole 215 has an undercut structure 170 formed by etching the first auxiliary interconnection line 145 more than the first passivation film 150. The undercut structure 170 here refers to a recessed structure defined by the lower surface of the first passivation film 150, the side surface of the first auxiliary interconnection line 145, and the upper surface of the active interconnection line 131. The undercut structure 170 is introduced in order to make contact between the second electrode 210 and the active interconnection line 131 or the first auxiliary interconnection line 145.

[0093] That is, since a portion of the first passivation film 150 protrudes from the wall surface of the contact hole 215 and protrudes outwardly above the active interconnection line 131 in the contact hole 215, or the first passivation film 150 is formed to protrude outwardly above the bottom of the contact hole 215, the light emitting layer 200 cannot be uniformly formed on the surface of the contact hole 215, and is thus partially cut off. When the second electrode 210 is formed on the light emitting layer 200, the second electrode 210 and the active interconnection line 131 can be directly connected to each other. Since the second electrode 210 and the active interconnection line 131 are in direct contact with each other, the contact resistance in the contact hole 215 is reduced. This improves the characteristics of the OLED display device in terms of power consumption and heat generation.

[0094] A contact surface 211 between the second electrode 210 and the active interconnection line 131 exists within the undercut structure 170. Thus, the contact surface 211 may at least partially overlap the first passivation film 150 when viewed from above.

[0095] The remaining space in the contact hole 215 after the second electrode 210 is formed is filled with the second passivation film 220. A void may be formed in the contact hole 215 according to the step coverage of the second passivation film 220.

[0096] Figure 5B The diagram illustrates a structure in which the second electrode 210 is larger than Figure 5A The second electrode 210 of the example extends further into the undercut structure 170 to be directly connected to the first auxiliary interconnection line 145 .

[0097] Since the second electrode 210 is in direct contact with the first auxiliary interconnection line 145, the area of ​​the contact surfaces 211, 212 capable of forming a conductive path between the second electrode 210 and the auxiliary electrode 120 increases. Figure 5A Compared with the previous example, this example further reduces the contact resistance in the contact hole 215. That is, through this structure, the power consumption characteristics of the OLED display device can be improved.

[0098] Reference Figure 5B , the undercut structure 170 is defined as a space defined by the lower surface of the first passivation film 150. By using the structure of the undercut structure 170, when the second electrode 210 is Figure 5B In the example of the second electrode 210, a larger amount of the second electrode 210 is deposited, so that the second electrode 210 can contact the lower surface of the first passivation film 150, and the short circuit problem can be prevented. In this way, the working reliability of the OLED display can be improved.

[0099] The first conductive film includes a source electrode 141 and a drain electrode 142. The source electrode 141 and the drain electrode 142 are disposed on the active pattern 130 with the gate electrode 143 therebetween, and the source electrode 141 and the drain electrode 142 are spaced apart by a predetermined distance. The source electrode 141 and the drain electrode 142 are connected to the source region 137 and the drain region 136 of the active pattern 130, respectively.

[0100] The source electrode 141, the drain electrode 142, the gate electrode 143 and the first auxiliary interconnection line 145 are all included in the first conductive film. Therefore, the source electrode 141, the drain electrode 142, the gate electrode 143 and the first auxiliary interconnection line 145 are formed in the same process step. Therefore, the source electrode 141, the drain electrode 142, the gate electrode 143 and the first auxiliary interconnection line 145 can be formed using a single mask. This reduces process complexity.

[0101] The source electrode 141, the drain electrode 142, the gate electrode 143, and the active pattern 130 constitute a transistor. The transistor may be, for example, a driving transistor DT or a switching transistor ST. Figure 4 An example in which the drain electrode 142 of the driving transistor DT is connected to the first electrode 180 of the light emitting element 250 is illustrated.

[0102] For example, the first conductive film further includes a lower electrode of the storage capacitor Cst, electrodes of circuit elements such as the gate lines GL1 to GLn, and driving lines.

[0103] A first passivation film 150 is formed on the first conductive film. The first passivation film 150 covers the source electrode 141, the drain electrode 142, the gate electrode 143, and the first auxiliary interconnection line 145 formed by the first conductive film. When a contact hole is formed through the first passivation film 150, an undercut structure 170 is formed under the first passivation film 150, and at least a portion of the upper surface of the active interconnection line 131 is exposed through the undercut structure 170.

[0104] The first passivation film 150 is an insulating film for protecting the lower layer elements. The first passivation film 150 may be a single layer structure of silicon oxide (SiOx) or silicon nitride (SiNx), or a multilayer structure consisting of a SiOx layer and a SiNx layer.

[0105] The coating film 160 is formed on the first passivation film 150. The coating film 160 is a planarization film (also called a step cover film) for mitigating steps formed in the underlying structure. The coating film 160 is made of an organic material such as polyimide, benzocyclobutene series resin, or acrylate.

[0106] The light emitting elements 250 are formed on the coating film 160. Each light emitting element 250 includes a first electrode 180, a light emitting layer 200, and a second electrode 210. The first electrode 180 may be an anode electrode, and the second electrode 210 may be a cathode electrode. Figure 4 In the top emission type element shown in , the first electrode 180 is a reflective electrode and the second electrode 210 is a transmissive electrode.

[0107] The first electrode 180 is formed on the coating film 160. The first electrode 180 is connected to the drain electrode 142 of the transistor by passing through the through hole of the coating film 160 and the first passivation film 150. The first electrode 180 is made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO) or zinc oxide (ZnO). When the first electrode 180 is a reflective electrode, the first electrode 180 may include a reflective layer. The reflective layer is made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni) or any alloy thereof. In one embodiment, the reflective layer can be an APC structure as an alloy stack of silver / palladium / copper.

[0108] A bank insulating film 190 is formed on the coating film 160. The bank insulating film 190 is a pixel defining film that defines the light emitting area of ​​the pixel PX. The bank insulating film 190 is formed to expose a portion (e.g., a central portion) of the first electrode 180 and cover the remaining portion (e.g., an edge portion). In view of ensuring a sufficient aperture ratio, it is preferred that the area of ​​the exposed portion of the first electrode 180 is as large as possible. The exposed portion of the first electrode 180 that is not covered by the bank insulating film 190 is the light emitting area of ​​the pixel PX.

[0109] In the light emitting region, the first electrode 180, the light emitting layer 200, and the second electrode 210 are stacked in direct contact with each other. The bank insulating film 190 is made of an organic material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0110] The light emitting layer 200 is formed on the first electrode 180 and the bank insulating film 190. The light emitting layer 200 extends into the non-pixel area NPXA, thereby filling the bottom portion of the contact hole 215 while partially exposing the top surface of the active interconnection line 131.

[0111] The light emitting layer 200 has a multi-layer structure including a light generating layer and includes a hole injection layer (HIL), a hole transport layer (HTL), an organic light emitting layer, an electron injection layer (EIL), and an electron transport layer (ETL).

[0112] The light-emitting layer 200 may have a series structure consisting of two or more stacks. In this case, each stack includes a hole transport layer, an organic light-emitting layer and an electron transport layer. When the light-emitting layer 200 has a series structure consisting of two or more stacks, a charge generation layer is provided between each stack. The charge generation layer includes an n-type charge generation layer positioned adjacent to the stack of the lower layer, and a p-type charge generation layer formed on the n-type charge generation layer and positioned adjacent to the stack of the upper layer. The n-type charge generation layer injects electrons into the stack of the lower layer, and the p-type charge generation layer injects holes into the stack of the upper layer. The n-type charge generation layer may be a metal-doped organic layer prepared by doping an organic host material layer that can be electron-transported with an alkali metal such as lithium (Li), sodium (Na), potassium (K) or cesium (Cs) or an alkaline earth metal such as magnesium (Mg), strontium (Sr), barium (Ba) or radium (Ra). The p-type charge generation layer may be an organic layer that can be hole-transported doped with a dopant.

[0113] The color of the light generated by the light emitting element 250 is red, green or blue, but the present invention is not limited thereto. For example, the color of the light generated by the light generating layer of the light emitting layer 200 may be magenta, cyan, yellow or white.

[0114] The second electrode 210 is formed on the light emitting layer 200. The second electrode 210 is formed to cover the light emitting layer 200. The second electrode 210 is formed to directly contact the active interconnection line 131 or the auxiliary interconnection line 145 within the contact hole 215.

[0115] The second electrode 210 is made of a transparent conductive material (TCO). Alternatively, the second electrode 210 may be made of a semi-transmissive conductive material such as molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) and any alloy thereof. When the second electrode 210 is made of a semi-transmissive conductive material, the light emitting efficiency is improved by the microcavity.

[0116] The second passivation film 220 is formed to cover the light emitting element 250. The second passivation film 220 prevents oxygen or moisture from penetrating into the light emitting element 250.

[0117] The second passivation film 220 is made of at least one of inorganic materials such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, and titanium oxide.

[0118] The second passivation film 220 extends into the non-pixel area NPXA to fill the contact hole 215 .

[0119] The second substrate 300 is disposed to face the first substrate 100. The second substrate 300 is bonded to the first substrate 100 using a filling material. The second substrate 300 includes a transparent substrate made of a transparent material such as glass, plastic, or quartz to improve light transmittance.

[0120] A black matrix 310 is disposed on the second substrate 300. A color filter 320 is disposed between the black matrixes 310. The color filter 320 is disposed at a position corresponding to the light emitting element 250. That is, the color filter 320 is disposed above the light emitting element 250. When the light emitting layer 200 can emit red light, green light, or blue light, the color filter 320 may be omitted.

[0121] Figures 6 to 13 is a diagram illustrating an intermediate step of a method for manufacturing an organic light emitting diode display device according to an embodiment of the present invention.

[0122] Reference Figure 6 , auxiliary electrodes 105 , 106 , 107 and 120 are formed on the first substrate 100 .

[0123] The auxiliary electrodes 105 , 106 , 107 and 120 are formed by depositing a conductive material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) on the first substrate 100 .

[0124] The buffer film 110 is formed to cover the first substrate 100 and the auxiliary electrodes 105, 106, 107 and 120. The buffer film 110 includes an inorganic material (eg, oxide or nitride), an organic material or an organic / inorganic composite. The buffer film 110 has a single layer structure or a multi-layer structure.

[0125] Reference Figure 7 , an active pattern 130 , an active interconnection line 131 , and a gate insulating film 140 are formed on the buffer film 110 .

[0126] The active pattern 130 is made of a silicon-based semiconductor material or an oxide-based semiconductor material. The active interconnection line 131 is formed by changing the oxide semiconductor into a conductor through a plasma treatment process or a heat treatment process on the active pattern.

[0127] The gate insulating film 140 is formed to cover at least a portion of the active pattern 130 and the active interconnection line 131 .

[0128] Reference Figure 8 , a first conductive film is formed on the gate insulating film 140, the active pattern 130, and the active interconnection line 131. The first conductive film includes a gate electrode 143, a source electrode 141, a drain electrode 142, and an auxiliary interconnection line 145. The first conductive film extends through the buffer film 110 and is connected to the auxiliary electrodes 105, 106, 107, and 120. Figure 8 As shown in FIG. 1 , in the early stage of forming the first conductive film, the auxiliary interconnection line 145 completely covers the active interconnection line 131 .

[0129] Reference Fig. 9 , a first passivation film 150 and a coating film 160 are formed on the first conductive film. The first passivation film 150 has a single layer structure or a multilayer structure made of silicon oxide (SiOx), silicon nitride, or both. The coating film 160 includes an organic material such as polyimide, benzocyclobutene series resin, and acrylate.

[0130] Reference Fig.10 , the first passivation film 150 is partially removed to expose a portion of the first conductive film. When the first passivation film 150 is partially etched away, the pre-contact hole 255 is formed to expose a portion of the auxiliary interconnection line 145.

[0131] Reference Fig.11 , the auxiliary interconnection line 145 exposed through the pre-contact hole 255 is selectively etched to form an undercut structure 170. The upper surface of the active interconnection line 131 is exposed through the undercut structure 170. Due to the formation of the undercut structure 170, a portion of the first passivation film 150 protrudes outward on the upper surface of the active interconnection line 131.

[0132] Reference Fig.12 , a first electrode 180 and a bank insulating film 190 are formed on the coating film 160. The first electrode 180 is connected to the drain electrode 142 through a through hole formed through the coating film 160. The bank insulating film 190 is formed in such a manner as to expose a central portion of the first electrode 180. The central portion of the first electrode 180 that is not covered by the bank insulating film 190 and is thus exposed is defined as a light emitting region.

[0133] Reference Fig.13, a light emitting layer 200 and a second electrode 210 are sequentially formed on the first electrode 180 and the bank insulating film 190. Due to the existence of the undercut structure 170, the light emitting layer 200 is cut off in the contact hole 215. The second electrode 210 covers one end of the light emitting layer 200 and directly contacts the active interconnection line 131. In some embodiments, the second electrode 210 extends into the undercut structure 170, thereby contacting the auxiliary interconnection line 145.

[0134] Reference Figure 4 , the second substrate 300 is bonded to the first substrate 100. A filler (not specifically shown) is injected into the gap between the second substrate 300 and the first substrate 100 to maintain adhesion between the first substrate 100 and the second substrate 300. Optionally, an encapsulation layer is interposed between the second substrate 300 and the first substrate 100 to prevent moisture or foreign matter from penetrating. For example, the encapsulation layer may have a multilayer structure in which an inorganic film and an organic film are alternately stacked.

[0135] Those skilled in the art will appreciate that the present invention can be implemented in various specific forms without departing from the spirit of the technology or changing the essential features. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects, rather than restrictive. The scope of the present invention is represented by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as falling within the scope of the present invention.

Claims

1. An organic light emitting diode (OLED) display device, comprising: A substrate, in which a pixel region and a non-pixel region are defined; an auxiliary electrode formed on the substrate; a buffer film covering the auxiliary electrode; forming an active interconnection line on the buffer film; an auxiliary interconnection line extending through the buffer film and connecting one end of the active interconnection line to the auxiliary electrode; a first passivation film, the first passivation film covering the auxiliary interconnection line and having a contact hole, the contact hole being formed through the first passivation film, and an undercut structure being formed in the contact hole so that the active interconnection line is exposed through the undercut structure, and an upper surface of the undercut structure is defined by a lower surface of the first passivation film; and a light emitting element, the light emitting element comprising a first electrode, a light emitting layer, and a second electrode sequentially stacked on the first passivation film in the pixel region, wherein the second electrode extends into the non-pixel region so that the second electrode is connected to a portion of the active interconnect line exposed by the undercut structure in the contact hole, and The active interconnection line is made of a silicon-based semiconductor or an oxide-based semiconductor and is formed of a layer different from that of the auxiliary electrode. 2 . The organic light emitting diode display device according to claim 1 , wherein the second electrode extends along an upper surface of the active interconnection line and reaches a position within the undercut structure to be connected to the auxiliary interconnection line within the undercut structure.

3. The organic light emitting diode display device according to claim 2, wherein a portion of the first passivation film protrudes from a wall surface of the contact hole and protrudes outward above the active interconnection line within the contact hole, so that the first passivation film partially overlaps the active interconnection line when viewed from above, and The light emitting layer is not formed on an upper surface of a portion of the active interconnection line overlapping the first passivation film.

4. The organic light emitting diode display device according to claim 1, further comprising a driving transistor formed on the substrate and driving the light emitting element, wherein the driving transistor includes a gate electrode and a drain electrode electrically connected to the first electrode of the light emitting element, and The gate electrode, the drain electrode, and the auxiliary interconnection line are formed in the same process step. 5 . The organic light emitting diode display device according to claim 1 , further comprising an auxiliary substrate provided with a color filter, the auxiliary substrate being bonded to the substrate through a filler. 6 . The organic light emitting diode display device according to claim 1 , wherein the second electrode extends into the undercut structure to further contact the auxiliary interconnection line and a lower surface of the first passivation film.

7. The organic light emitting diode display device according to claim 1 , wherein a portion of the first passivation film protrudes from a wall surface of the contact hole and protrudes outward above the active interconnection line within the contact hole, so that the first passivation film partially overlaps the active interconnection line when viewed from above, and The second electrode extends to cover an upper surface of a portion of the active interconnection line overlapping the first passivation film when viewed from above. 8 . The organic light emitting diode display device according to claim 1 , further comprising a second passivation film for filling the undercut structure.

9. A method for manufacturing an organic light emitting diode (OLED) display device, the method comprising: forming an auxiliary electrode on a substrate, wherein a pixel region and a non-pixel region are defined in the substrate; forming a buffer film to cover the auxiliary electrode; forming an active interconnection line on the buffer film; forming an auxiliary interconnection line formed to pass through the buffer film and configured to connect at least one of the auxiliary electrodes to the active interconnection line; forming a passivation film covering the auxiliary interconnection line; Etching the passivation film in the non-pixel area so that a portion of the auxiliary interconnection line is exposed; forming a contact hole by partially etching the exposed auxiliary interconnection line so that an undercut structure is generated within the contact hole, an upper surface of the undercut structure being defined by a lower surface of the passivation film; and forming a light emitting element, the light emitting element comprising a first electrode, a light emitting layer and a second electrode sequentially formed on the passivation film, wherein the second electrode extends into the non-pixel region to be connected to the active interconnection line exposed by the undercut structure, and The active interconnection line is made of a silicon-based semiconductor or an oxide-based semiconductor and is formed of a layer different from that of the auxiliary electrode.

10. The method of claim 9, wherein forming the active interconnect line comprises: forming an active pattern made of a silicon-based semiconductor or an oxide-based semiconductor on the buffer film; and A plasma treatment process or a heat treatment process is performed on the active pattern so that the semiconductor becomes conductive. 11 . The method according to claim 9 , wherein the second electrode extends along an upper surface of the active interconnection line to enter into the undercut structure such that the second electrode is connected to the auxiliary interconnection line.

12. The method according to claim 9, further comprising forming a driving transistor for driving the light emitting element on the substrate, wherein the driving transistor includes a gate electrode and a drain electrode electrically connected to the first electrode, and The gate electrode, the drain electrode and the auxiliary interconnection line are formed in the same process step.

13. The method according to claim 12, wherein a portion of the passivation film protrudes outwardly above the active interconnection line within the contact hole so that the passivation film overlaps the active interconnection line when viewed from above, and The second electrode extends along an upper surface of the active interconnection line overlapping the passivation film when viewed from above. 14 . The method of claim 9 , further comprising bonding an auxiliary substrate provided with a color filter to the substrate, the color filter being disposed to face the substrate. 15 . The method according to claim 9 , wherein the second electrode extends into the undercut structure to further contact the auxiliary interconnection line and a lower surface of the passivation film.

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