Mold sealing method and semiconductor package structure

Abstract

The present disclosure provides a molding method and a semiconductor package structure, wherein the semiconductor package structure comprises a substrate, at least two bare chips disposed on the substrate, and a package layer, each bare chip is disposed on the upper surface of the substrate, the upper surface of each bare chip is provided with a glass, and the package layer covers each bare chip and the glass provided on the upper surface of each bare chip, the upper surface of the glass provided on the upper surface of each bare chip is exposed outside the package layer, and the height of the glass provided on at least two bare chips from the upper surface of the substrate is different. In order to average the uneven pressure caused by the height difference of the upper surfaces of the glasses by using adhesive tape or a protective layer in the two molding methods for obtaining the above semiconductor package structure, the demolding or glass breakage problems that may exist in the existing CIS products can be reduced or avoided, and the yield of the CIS products is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, specifically to molding methods and semiconductor packaging structures. Background Technology

[0002] In CMOS (Complementary Metal-Oxide-Semiconductor) image sensor (CIS) products, there are generally at least two bare wafers arranged in parallel. The upper surface of each bare wafer may also be provided with a barrier (Dam, also known as a wall, barrier, or dam), and a glass is provided on the barrier to protect the bare wafer.

[0003] To meet the operational requirements of bare wafers, the top surface of the glass needs to expose the surface of the molding compound. However, due to process variations, the height of different glasses on different bare wafers may differ. When a rigid release film is applied to the glass for molding, if the Young's modulus of the barrier is low, meaning the barrier is more prone to deformation, the pressure exerted by the molding flow on the barrier during the molding process (molding pressure) may cause the barrier to deform and become shorter. Consequently, the height of the glass on that barrier will also decrease, potentially resulting in the molding compound remaining on the glass surface above the shortened barrier. This can lead to mold bleeding, where the remaining molding compound covers the glass, preventing the glass from exposing the molding compound surface, ultimately causing the product to fail. Conversely, if the barrier has a high Young's modulus, meaning it is not easily deformed, the pressure exerted by the molding flow on the barrier during the molding process will not cause the barrier to deform, and the glass on the barrier may crack under the action of molding. Summary of the Invention

[0004] This disclosure presents a molding method and a semiconductor packaging structure.

[0005] In a first aspect, this disclosure provides a molding method, including:

[0006] A semiconductor structure is provided, the semiconductor structure including a substrate and at least two bare wafers disposed on the substrate, each bare wafer having a glass disposed on its upper surface, and the glass disposed on the at least two bare wafers having a different height from the upper surface of the substrate;

[0007] The upper surface of the semiconductor structure is covered with tape, wherein the tape consists of an adhesive layer and a PI film, and the adhesive layer contacts the glass disposed on each of the bare wafers;

[0008] The semiconductor structure is encapsulated using a mold and packaging material, wherein the mold contacts the PI film;

[0009] Remove the mold;

[0010] Remove the encapsulation material formed on the PI film;

[0011] Remove the tape.

[0012] In some alternative embodiments, the removal of the encapsulation material formed on the PI film includes:

[0013] The encapsulation material formed on the PI film is ground off.

[0014] In some alternative implementations, removing the tape includes:

[0015] Use the nozzle to suck up and tear off the tape.

[0016] In some alternative embodiments, prior to molding the semiconductor structure using a mold and packaging material, the method further includes:

[0017] A pressing tool is used to press the tape onto the semiconductor structure, thereby pressing the tape deeper into the glass direction of the semiconductor structure.

[0018] In some alternative embodiments, the upper surface of the bare wafer is provided with glass, including:

[0019] The bare wafer has a barrier and glass disposed sequentially on its upper surface.

[0020] In some alternative embodiments, the horizontal longitudinal section of the barrier is a hollow, closed shape.

[0021] In some alternative embodiments, the semiconductor structure further includes wire bonding that passes through the barrier and is connected at one end to the bare wafer and at the other end to the substrate.

[0022] Secondly, this disclosure provides a molding method, including:

[0023] A semiconductor structure is provided, the semiconductor structure including a substrate and at least two bare wafers disposed on the substrate, each bare wafer having a glass disposed on its upper surface, and the glass disposed on the at least two bare wafers having a different height from the upper surface of the substrate;

[0024] A protective layer is placed on the mold, wherein the protective layer is composed of a release layer, a first base film, an elastic film, and a second base film stacked sequentially;

[0025] The semiconductor structure is encapsulated using the mold with the protective layer and the encapsulation material, wherein the release layer contacts the glass disposed on the upper surface of each bare wafer;

[0026] Remove the mold on which the protective layer is provided.

[0027] In some alternative embodiments, the protective layer has a Young's coefficient of 5 to 20 megapascals at 175 degrees Celsius.

[0028] In some alternative embodiments, the upper surface of the bare wafer is provided with glass, including:

[0029] The bare wafer has a barrier and glass disposed sequentially on its upper surface.

[0030] In some alternative embodiments, the horizontal longitudinal section of the barrier is a hollow, closed shape.

[0031] In some alternative embodiments, the semiconductor structure further includes wire bonding that passes through the barrier and is connected at one end to the bare wafer and at the other end to the substrate.

[0032] Thirdly, this disclosure provides a semiconductor packaging structure, including:

[0033] Substrate;

[0034] At least two bare wafers are disposed on the upper surface of the substrate, and the upper surface of the bare wafers is provided with glass.

[0035] An encapsulation layer covers each of the bare wafers and the glass disposed on their upper surfaces, wherein the upper surfaces of the glass disposed on the upper surfaces of each of the bare wafers are exposed outside the encapsulation layer, and the heights at which the glass disposed on at least two of the bare wafers are exposed above the upper surface of the encapsulation layer are different.

[0036] In some alternative embodiments, the upper surface of the bare wafer is provided with glass, including:

[0037] The bare wafer has a barrier and glass disposed sequentially on its upper surface.

[0038] In some alternative embodiments, the horizontal longitudinal section of the barrier is a hollow, closed shape.

[0039] In some alternative embodiments, the semiconductor package structure further includes wire bonding that passes through the barrier and is connected at one end to the bare wafer and at the other end to the substrate.

[0040] Figure 1 This is a schematic diagram of a longitudinal cross-sectional structure of an embodiment of a semiconductor packaging structure in the prior art. For example... Figure 1As shown, the semiconductor packaging structure 10 includes a substrate 11, a bare wafer 12 disposed on the substrate 11, a barrier 14 disposed on the bare wafer 12, and a glass 13 disposed on the barrier 14. In a conventional molding process, a release film 80 is disposed within the mold 30. Figure 1 As can be seen from this, using the traditional molding method, Figure 1 There is encapsulation material between the leftmost glass 13 and the release film 80, meaning demolding has occurred, which prevents the surface of the encapsulation material from being exposed on the glass 13, leading to product failure. Figure 1 The glass 13 in the middle may crack because it hits the release film 80.

[0041] To address potential issues such as demolding or glass breakage in existing CIS products, this disclosure provides a molding method and a semiconductor packaging structure. The semiconductor packaging structure includes a substrate, at least two bare wafers disposed on the substrate, and a packaging layer. Each bare wafer is disposed on the upper surface of the substrate, and a glass is disposed on the upper surface of the bare wafer. The packaging layer covers each bare wafer and the glass disposed on its upper surface. The upper surface of the glass disposed on the upper surface of each bare wafer is exposed outside the packaging layer, and the height of the glass disposed on at least two of the bare wafers from the upper surface of the substrate is different.

[0042] One molding method for obtaining the aforementioned semiconductor package structure involves first covering the upper surface of the semiconductor structure with a thick tape comprising an adhesive layer and a PI film (polyimide film). Then, a mold and encapsulation material are used to mold the semiconductor structure. The mold contacts the PI film, followed by removal of the mold, then removal of the encapsulation material formed on the PI film, and finally removal of the tape. This method utilizes the thickness of the tape to distribute and even out differences in glass height, and by removing any encapsulation material that may be formed on the PI film, it reduces or avoids potential demolding or glass breakage problems in CIS products.

[0043] Another molding method for achieving the aforementioned semiconductor package structure employs traditional molding techniques, but replaces the traditional release film with a protective layer sequentially stacked with a release layer, a first base film, a plastic film, and a second base film on the mold. The semiconductor structure is then molded using the mold with the protective layer and packaging materials. The release layer contacts the glass on the surface of each bare wafer. Finally, the mold with the protective layer is removed. In other words, during the molding process, the release layer contacts the glass. The plastic film, being softer, acts as a buffer to accommodate height differences between the glass layers. The multi-layered protective layer evenly distributes pressure and weight. The first and second base films are rigid structures used to protect the plastic film, thus avoiding potential demolding or glass breakage problems found in existing CIS products.

[0044] In summary, the molding method and semiconductor packaging structure provided in this disclosure can reduce or avoid demolding or glass breakage problems that may exist in existing CIS products, thereby improving the yield of CIS products. Attached Figure Description

[0045] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0046] Figure 1 This is a schematic diagram of a longitudinal cross-sectional structure of an embodiment of a semiconductor packaging structure in the prior art;

[0047] Figure 2A This is a perspective view of an embodiment of the adhesive tape used in one embodiment of the molding method according to the present disclosure;

[0048] Figure 2B-2F A longitudinal cross-sectional structural schematic diagram of a semiconductor package structure manufactured at various stages according to an embodiment of the molding method of this disclosure;

[0049] Figure 3A This is a perspective view of an embodiment of the protective layer used in one embodiment of the molding method according to the present disclosure;

[0050] Figure 3B-3D A longitudinal cross-sectional structural diagram of a semiconductor package structure manufactured at various stages according to another embodiment of the molding method of this disclosure;

[0051] Figure 4 This is a longitudinal cross-sectional structural diagram of one embodiment of the semiconductor packaging structure according to the present disclosure.

[0052] Symbol explanation:

[0053] 10 - Semiconductor structure; 23 - Release layer;

[0054] 11-Substrate; 30-Mold;

[0055] 12 - Bare wafer; 40 - Packaging material;

[0056] 13 - Glass; 50 - Nozzle;

[0057] 14 - Barrier; 60 - Pressed component;

[0058] 15 - Wire bonding; 70 - Protective layer;

[0059] 16 - Encapsulation layer; 71 - Release layer;

[0060] h - Height of glass exposed above the encapsulation layer; 72 - First base film;

[0061] 20 - Adhesive tape; 73 - Elastic film;

[0062] 21-PI film; 74-Second base film;

[0063] 22 - Adhesive layer; 80 - Release film. Detailed Implementation

[0064] The specific embodiments of the present invention will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present invention and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0065] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the invention. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and objectives of the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0066] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0067] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0068] refer to Figure 2A , Figure 2A A perspective view of an embodiment of the adhesive tape used in one embodiment of the molding method according to the present disclosure is shown.

[0069] like Figure 2A As shown, the tape 20 may include a PI film 21, an adhesive layer 22, and a release layer 23, which are sequentially bonded together from the outside to the inside. The PI film 21 and the release layer 23 are non-adhesive, while the adhesive layer 22 is adhesive, and the release layer 23 is easily peeled off from the adhesive layer 22. The release layer 23 can be peeled off before using the tape 20 in the molding process.

[0070] The following is for reference. Figure 2B-2E , Figure 2B-2E A longitudinal cross-sectional view of a semiconductor package structure fabricated at various stages according to an embodiment of the molding method of this disclosure. The figures have been simplified for better understanding of the aspects of this disclosure.

[0071] refer to Figure 2B , providing semiconductor structure 10.

[0072] Here, the semiconductor structure 10 includes a substrate 11 and at least two bare wafers 12 disposed on the substrate 11. Each bare wafer 12 has a glass 13 disposed on its upper surface, and the glass 13 disposed on the at least two bare wafers 12 is at a different height from the upper surface of the substrate 11.

[0073] Here, substrate 11 can be of various types, and this disclosure does not specifically limit it. Substrate 11 may include organic and / or inorganic materials, wherein organic materials may be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylenebenzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials may be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0074] The substrate 11 can also be, for example, a printed circuit board (PCB), such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate.

[0075] The substrate 11 may also include interconnect structures, such as conductive traces, conductive vias, etc. Here, the conductive vias may be through-holes, buried vias, or blind vias, and the through-holes, buried vias, or blind vias may be filled with conductive materials such as metals or metal alloys. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0076] Same reference Figure 2B The upper surface of the semiconductor structure 10 is covered with tape.

[0077] Here, the tape consists of an adhesive layer 22 and a PI film 21, and the adhesive layer 22 contacts the glass 13 disposed on each bare wafer 12. That is, the PI film 21 is bonded to the glass 13 on each bare wafer 12 by the adhesive layer 22.

[0078] refer to Figure 2D The semiconductor structure 10 is encapsulated using mold 30 and packaging material 40.

[0079] Here, during the process of using mold 30 and packaging material 40 to encapsulate semiconductor structure 10, mold 30 contacts PI film 21.

[0080] Here, the encapsulating material 40 can be formed from various molding compounds. For example, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0081] The specific molding process can be at least one of the following: transfer molding, injection molding, compression molding, liquid molding, and spray molding. For example, it can be transfer molding.

[0082] refer to Figure 2E Remove the mold 30 and the encapsulation material 40 formed on the PI film 21.

[0083] Although the PI film 21 is in contact with the mold 30, since the PI film 21 itself is not adhesive, the PI film 21 will detach from the mold 30 when the mold 30 is removed. However, since the adhesive layer 22 is adhesive, the PI film 21 will still be bonded to the adhesive layer 22.

[0084] from Figure 2D As can be seen, since the PI film 21 and adhesive layer 22 are pre-attached to the semiconductor structure 10, rather than being pre-set in the mold, during the molding process, for the lower-height glass 13, some of the encapsulation material 40 may be squeezed onto the PI film of that lower-height glass 13. Therefore, after removing the mold 30, the encapsulation material 40 formed on the PI film can be removed. For example, grinding or similar techniques can be used. It is understood that some PI film may be removed during the grinding process, but this has no impact on the subsequent formation of the semiconductor encapsulation structure.

[0085] refer to Figure 2F Remove the tape.

[0086] Here, a nozzle can be used to pick up and tear off the tape, that is, to remove the PI film 21 and the adhesive layer 22. Of course, other similar techniques can also be used to remove the tape, thereby realizing the molding operation of the semiconductor structure 10. Although the heights of the individual glass pieces in the molded semiconductor structure 10 may be different, the use of a thicker PI film and adhesive layer to share the molding pressure and to distribute and balance the pressure of the PI film and adhesive layer themselves during the molding process accommodates the height differences between the glass pieces. Furthermore, the encapsulation material remaining on the PI film is removed, thus preventing demolding and glass breakage caused by differences in glass height, thereby improving the product yield of the semiconductor packaging structure.

[0087] In some alternative implementations, before molding the semiconductor structure 10 using molds and packaging materials, i.e. Figure 2D Previously, it was possible to... Figure 2CAs shown, a pressing member 60 is used to press the tape onto the semiconductor structure 10, thereby pressing the tape to a deeper depth in the direction of the glass 13 within the semiconductor structure 10. Optionally, the pressing member 60 can be rubber. Because rubber has a certain pressure, the adhesive layer can adhere more closely to the glass under the pressure of the rubber pressing member 60, while the relatively soft rubber will not cause the glass to crack.

[0088] In some alternative embodiments, a barrier 14 and a glass 13 may be sequentially disposed on the upper surface of the bare wafer 12. Here, the barrier 14 can protect the upper surface of the bare wafer 12.

[0089] In some alternative implementations, the horizontal longitudinal section of the barrier 14 can be a hollow closed shape, for example, it can be a hollow circle or rectangle, or it can be attached to the outer periphery of the upper surface of the bare wafer 12.

[0090] In some alternative embodiments, the semiconductor structure 10 may also include wire bonding 15, which passes through the barrier 14 and is connected at one end to the bare wafer 12 and at the other end to the substrate 11, that is, the bare wafer 12 and the substrate 11 are electrically connected by wire bonding.

[0091] The molding method provided in the above embodiments of this disclosure first covers the upper surface of a semiconductor structure with a thick adhesive tape including an adhesive layer and a PI film, then molds the semiconductor structure using a mold and encapsulation material. The mold contacts the PI film, then the mold is removed, followed by the removal of the encapsulation material formed on the PI film, and finally the adhesive tape is removed. In other words, by utilizing the thickness of the adhesive tape to adhere to the glass, differences in glass height are mitigated, and by removing any encapsulation material that may be formed on the PI film, potential demolding or glass breakage problems in CIS products are reduced or avoided.

[0092] The following is for reference. Figure 3A , Figure 3A A perspective schematic diagram of an embodiment of a protective layer used in one embodiment of the molding method according to the present disclosure is shown.

[0093] like Figure 3A As shown, the protective layer 70 includes a release layer 71, a first base film 72, an elastic film 73, and a second base film 74, which are sequentially bonded together from the inside out. Here, the first base film 72 and the second base film 74 can be rigid structures used to provide protection for the elastic film 73. For example, the first base film 72 and the second base film 74 can be plastic films.

[0094] The following is for reference. Figure 3B and Figure 3C , Figure 3B and Figure 3CA cross-sectional schematic diagram of the semiconductor package structure fabricated at various stages according to yet another embodiment of the molding method of this disclosure is shown. The figures have been simplified for a better understanding of the aspects of this disclosure.

[0095] refer to Figure 3B , providing semiconductor structure 10.

[0096] Here, the semiconductor structure 10 includes a substrate 11 and at least two bare wafers 12 disposed on the substrate 11. Each bare wafer 12 has a glass 13 disposed on its upper surface, and the glass 13 disposed on the at least two bare wafers 12 is at a different height from the upper surface of the substrate 11. For details regarding the semiconductor structure 10, please refer to [reference needed]. Figure 2B The relevant descriptions in the document will not be repeated here.

[0097] refer to Figure 3C The protective layer 70 is disposed on the mold 30, and the semiconductor structure 10 is encapsulated using the mold 30 with the protective layer 70 and the encapsulation material 40.

[0098] Here, the protective layer 70 is formed by sequentially stacking a release layer 71, a first base film 72, an elastic film 73, and a second base film 74. In practice, the protective layer 70 can be placed on the mold 30 in various ways.

[0099] During the process of setting the protective layer 70 on the mold 30, the release layer 71 contacts the glass 13 disposed on the upper surface of each bare wafer 12. Meanwhile, the second base film 74 contacts the mold 30.

[0100] It should be noted that here Figure 3C Mold 30 is not shown in the figure.

[0101] Here, during the molding process, the protective layer 70 can be used to distribute and balance the pressure on each glass 13 in the semiconductor structure 10, thereby avoiding uneven pressure caused by inconsistent heights of the glass during molding. This ensures a consistent height when the mold covers the glass during the molding process, avoiding demolding and glass breakage problems that may occur in the prior art, and thus improving product yield. Here, the elastic mold 73 can act as a cushioning film, that is, it can overcome the difference in height between the glass with a relatively soft hardness. Because it is not adhesive, it can only be placed on the mold and cannot be bonded to the glass 13. That is, when using a protective layer to achieve the molding of the semiconductor structure 10, it is not suitable to use a... Figures 2B to 2E The molding method shown.

[0102] refer to Figure 3D Remove the mold 30 with the protective layer 70.

[0103] Since the release layer 71 contacts each glass, when the mold 30 is removed, the protective layer 70 will be removed together with the mold 30, thus obtaining the packaged semiconductor package structure 10. Moreover, the height of each glass 13 exposed above the upper surface of the package layer 40 in the semiconductor package structure 10 can be different. It should be noted that the difference in the height of each glass 13 exposed above the upper surface of the package layer 40 is mostly caused by process differences.

[0104] exist Figures 3B-3D In the molding method shown, since the protective layer 70 is disposed on the mold 30, each layer of the protective layer 70 is treated as a whole. During the molding process, the encapsulating material cannot enter between the layers of the protective layer 70. The height of the encapsulating material can be controlled by controlling the injection amount during the molding process, thus preventing encapsulating material residue on the glass with a lower height. In other words, there is no demolding phenomenon, and there is no need for the step of removing excess encapsulating material. Moreover, since the part of the protective layer 70 that contacts the glass is the release layer 71, due to the easy detachment characteristic of the release layer 71, when the mold 30 is removed, the release layer 71 will detach from the glass 13 together with the mold 30.

[0105] In some optional embodiments, the Young's coefficient of the protective layer 70 at 175 degrees Celsius is 5 to 20 MPa. That is, the overall Young's coefficient of the protective layer 70 is low, and the protective layer 70 is more prone to deformation. By covering the glass with the protective layer 70, the pressure can be evenly distributed, preventing uneven pressure caused by different height differences of the glass below. This effectively ensures a consistent height when the mold is covered during the molding process, avoiding product damage problems such as demolding and glass breakage.

[0106] In some alternative embodiments, a barrier 14 and a glass 13 may be sequentially disposed on the upper surface of the bare wafer 12.

[0107] In some alternative implementations, the horizontal longitudinal section of the barrier 14 can be a hollow, closed shape.

[0108] In some alternative embodiments, the semiconductor structure 10 may also include wire bonding 15, which passes through the barrier 14 and is connected at one end to the bare wafer 12 and at the other end to the substrate 11.

[0109] The molding method provided in the above embodiments of this disclosure adopts a conventional molding method, but replaces the traditional release film with a protective layer formed by sequentially stacking a release layer, a first base film, an elastic film, and a second base film on the mold. The mold with the protective layer and encapsulation material are then used to mold the semiconductor structure, with the release layer contacting the glass on the upper surface of each bare wafer. Finally, the mold with the protective layer is removed. That is, during the molding process, the release layer contacts the glass. The elastic film, due to its softer hardness, acts as a buffer layer to accommodate height differences between different glass layers. The entire multi-layered protective layer can evenly distribute pressure and weight. The first and second base films are rigid structures (base film plastic films) used to protect the elastic film. This avoids product damage problems such as demolding and glass breakage that may occur in conventional molding processes, improving product yield.

[0110] The following is for reference. Figure 4 , Figure 4 This is a longitudinal cross-sectional structural diagram of one embodiment of the semiconductor packaging structure according to the present disclosure.

[0111] like Figure 4 As shown, the semiconductor package structure 10 includes a substrate 11, at least two bare wafers 12, and a package layer 16. Each bare wafer 12 is disposed on the upper surface of the substrate 11, and a glass 13 is disposed on the upper surface of the bare wafer 12. The package layer 16 covers each bare wafer 12 and the glass 13 disposed on its upper surface. The upper surface of the glass 13 disposed on the upper surface of each bare wafer 12 is exposed outside the package layer 16, and at least two of the glass 13 disposed on each bare wafer 12 have different heights of glass 13 that are exposed above the upper surface of the package layer 16.

[0112] For details regarding substrate 11, please refer to [link / reference]. Figure 2B The relevant descriptions in the document will not be repeated here.

[0113] The encapsulation layer 16 can be formed from various molding compounds. For example, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0114] In some alternative embodiments, a barrier 14 and a glass 13 are sequentially disposed on the upper surface of the bare wafer 12. Here, the barrier 14 can protect the upper surface of the bare wafer 12.

[0115] In some alternative implementations, the horizontal longitudinal section of the barrier 14 can be a hollow closed shape, for example, it can be a hollow circle or rectangle, or it can be attached to the outer periphery of the upper surface of the bare wafer 12.

[0116] In some alternative embodiments, the semiconductor package structure 10 may further include wire bonding 15, which passes through the barrier 14 and is connected at one end to the bare wafer 12 and at the other end to the substrate 11, that is, the bare wafer 12 and the substrate 11 are electrically connected by wire bonding.

[0117] The semiconductor packaging structure 10 provided in the above embodiments of this disclosure can realize glass with different heights to adapt to different product functional requirements. In addition, each glass can expose the packaging layer, thereby realizing the product function of the bare wafer corresponding to each glass.

[0118] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A mold sealing method, comprising: providing a semiconductor structure, the semiconductor structure comprising a substrate and at least two dies disposed on the substrate, an upper surface of each of the dies being provided with glass, and a height of the glass provided on the at least two dies from an upper surface of the substrate being different; covering an upper surface of the semiconductor structure with a tape, wherein the tape comprises an adhesive layer and a PI film, the adhesive layer being in contact with the glass provided on each of the dies; sealing the semiconductor structure with a mold and a packaging material, wherein the mold is in contact with the PI film; wherein the PI film and the adhesive layer are pre-bonded to the semiconductor structure, instead of being pre-disposed on the mold; removing the mold; removing the packaging material formed on the PI film; removing the tape; the removing the packaging material formed on the PI film comprises grinding away the packaging material formed on the PI film, and sucking and tearing the tape with a nozzle.

2. The mold sealing method of claim 1, wherein, Before the sealing the semiconductor structure with the mold and the packaging material, the method further comprises: pressing a pressing piece on the semiconductor structure to press the tape deeper into the glass of the semiconductor structure with the pressing piece.

3. The mold sealing method of claim 1, wherein, the upper surface of the die is provided with glass, comprising: the upper surface of the die is sequentially provided with a barrier and glass.

4. The mold sealing method of claim 3, wherein, a horizontal longitudinal section of the barrier is a hollow closed shape.

5. The mold sealing method according to claim 3 or 4, wherein, the semiconductor structure further comprises a wire, the wire passing through the barrier and being connected to the die at one end and to the substrate at the other end. 6.A mold sealing method, comprising: providing a semiconductor structure, the semiconductor structure comprising a substrate and at least two dies disposed on the substrate, an upper surface of each of the dies being provided with glass, and a height of the glass provided on the at least two dies from an upper surface of the substrate being different; disposing a protective layer on a mold, wherein the protective layer is sequentially laminated by a release layer, a first base film, an elastic film and a second base film; sealing the semiconductor structure with the mold provided with the protective layer and a packaging material, wherein the release layer is in contact with the glass provided on the upper surface of each of the dies; removing the mold provided with the protective layer; a Young's modulus of the protective layer at 175 degrees Celsius is 5-20 MPa.

7. The mold sealing method of claim 6, wherein, the upper surface of the die is provided with glass, comprising: the upper surface of the die is sequentially provided with a barrier and glass.

8. The mold sealing method of claim 7, wherein, a horizontal longitudinal section of the barrier is a hollow closed shape.

9. The mold sealing method according to claim 7 or 8, wherein, the semiconductor structure further comprises a wire, the wire passing through the barrier and being connected to the die at one end and to the substrate at the other end.

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