Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device and a method for manufacturing the semiconductor device are provided, which can prevent the degradation of the semiconductor chip and thus improve the reliability. The semiconductor device comprises: a first semiconductor chip (1) having a metal layer (1C) on the surface; a first wiring member (7) arranged opposite to the metal layer (1C); a sintered metal layer (4a, 4b) arranged between the metal layer (1C) and the first wiring member (7), comprising a first region and a plurality of second regions arranged inside the first region, wherein the tensile strength of each second region is lower than the tensile strength of the first region; and a metal material (3) arranged inside the sintered metal layer (4a, 4b), wherein the tensile strength of the second region of the sintered metal layer (4a, 4b) is lower than the tensile strength of the metal layer (1C) of the first semiconductor chip (1).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] A general power semiconductor device includes a semiconductor element such as an insulated gate bipolar transistor (IGBT) or a MOS field effect transistor (MOSFET), an insulating circuit substrate, and a heat sink. In the bonding between the semiconductor element, the insulating circuit substrate, and the heat sink, a lead frame is used that is bonded using bonding materials such as bonding wires and solder. In recent years, under the requirements of miniaturization, lightness, and high functionality of power semiconductor devices, the high integration of circuits of power semiconductor devices has developed. In addition, the development of semiconductor device applications using semiconductor elements such as silicon carbide (SiC) that can operate at high temperatures has been promoted, thereby seeking high reliability of semiconductor devices in high-temperature operating environments.

[0003] As bonding materials for semiconductor devices, solder materials such as tin-antimony (SnSb) solder materials and tin-silver (SnAg) solder materials have been used. However, the operating temperature of the semiconductor device is close to the melting point of the solder material, so the reliability may be reduced. Therefore, as a bonding material that can cope with high-temperature operation, the application of sintered metal paste and sintered metal sheets that utilize the sintering effect of metal particles is studied. In patent documents 1 to 3, a structure using sintered metal materials as a bonding layer between semiconductor elements and insulating circuit substrates and wiring components is proposed.

[0004] When a power semiconductor device is turned on or is affected by temperature changes in the surrounding environment, stress is generated in its bonding layer due to the difference in thermal expansion coefficients of each component. Repeated stress can cause cracks in the bonding layer due to thermal fatigue degradation. When the cracks extend and the extension distance becomes longer, the heat generation temperature during power on will increase due to the increase in thermal resistance, causing the semiconductor device to fail.

[0005] Regarding the failure mode caused by cracks in the bonding layer, sintered metal, which is 3 to 4 times stronger than solder materials, can prevent cracks from occurring, and is expected to help improve high-temperature operation and reliability. However, it has been found that in actual power-on cycles, although the metal sintered layer does not crack, the aluminum (Al) alloy layer of the semiconductor chip electrode is prone to cracks. Sometimes, during the process of cracks in the electrode layer of the semiconductor element extending, the circuit is disconnected by the semiconductor chip, causing failure in advance.

[0006] A solution to the crack generation in the electrode layer of a semiconductor element has been studied. For example, Patent Document 3 describes the following: a recess is provided in the wiring layer of an insulating circuit substrate, so that stress is concentrated in the area where the bonding layer of the bonding layer contacts the recess to cause cracks to be generated preferentially in the area, thereby suppressing the generation of cracks in the area where the bonding layer does not contact the recess. In addition, Patent Documents 2 and 4 propose the following: an Al metal layer with a yield stress lower than the yield stress of the bonding layer is used as the wiring layer of the insulating circuit substrate to cause cracks to be generated in the wiring layer and to extend the cracks in the wiring layer to improve the reliability of the bonding layer. However, the strength of the Al alloy used for the electrode of the semiconductor chip is the same as the strength of the Al in the wiring layer, and it is impossible to control which side the cracks are generated. In addition, the generation and extension of cracks will lead to an increase in the thermal resistance of the bonding layer, thereby reducing the heat dissipation characteristics of the semiconductor chip. In Patent Document 5, it is recorded that a plurality of protrusions are provided in the contact area of ​​the connecting plate connected to the lead frame, and the contact area is bonded to the semiconductor element by means of a welding member, but there is no record of the degradation of the semiconductor chip caused by cracks. Patent Document 6 describes a composition having two layers with different porosities. Patent Document 7 describes an adhesive composition containing silver particles (90% by mass or more) and zinc particles (0.01% by mass or more and 0.6% by mass or less).

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 2012-138470

[0010] Patent Document 2: Japanese Patent Application Publication No. 2010-251457

[0011] Patent Document 3: Japanese Patent Application Publication No. 2010-245227

[0012] Patent Document 4: International Publication No. 2017 / 002793

[0013] Patent Document 5: U.S. Patent No. 8987879

[0014] Patent Document 6: U.S. Patent No. 9929111

[0015] Patent Document 7: Japanese Patent Application Publication No. 2013-258122 Summary of the invention

[0016] Problem that the invention aims to solve

[0017] In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device which can prevent degradation of a semiconductor chip and thus improve reliability.

[0018] Solutions for solving problems

[0019] The purpose of one embodiment of the present invention is a semiconductor device comprising: (a) a first semiconductor chip having a metal layer on its surface; (b) a first wiring member arranged opposite to the metal layer; (c) a sintered metal layer arranged between the metal layer and the first wiring member, comprising a first region and a plurality of second regions arranged inside the first region, wherein the tensile strength of each second region is lower than the tensile strength of the first region; and (d) a metal material arranged inside the sintered metal layer, wherein (e) the tensile strength of the second region of the sintered metal layer is lower than the tensile strength of the metal layer of the first semiconductor chip.

[0020] Another embodiment of the present invention is a method for manufacturing a semiconductor device, which includes the following steps: (a) joining a first semiconductor chip to a wiring layer arranged on the upper surface of an insulating circuit substrate; (b) applying a sintered metal paste to the upper surface of the first semiconductor chip and drying it to stack a first sintered metal layer; (c) arranging a first metal plate having a plurality of first grooves on the lower surface and a plurality of second grooves on the upper surface on the first sintered metal layer in such a manner that the lower surface of the first metal plate is in contact with the first sintered metal layer; (d) applying a sintered metal paste to the upper surface of the first metal plate and drying it to stack a second sintered metal layer; (e) arranging a first wiring component on the second sintered metal layer; and (f) heating and pressurizing the first and second sintered metal layers, joining the first sintered metal layer between the lower surface of the first metal plate and the first semiconductor chip in such a manner that the plurality of first grooves are filled, and joining the second sintered metal layer between the upper surface of the first metal plate and the first wiring component in such a manner that the plurality of second grooves are filled.

[0021] Effects of the Invention

[0022] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device which can prevent degradation of a semiconductor chip and thus improve reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention.

[0024] Figure 2 yes Figure 1 Magnified view of part A in FIG.

[0025] Figure 3 This is a schematic plan view showing an example of the metal plate according to the first embodiment.

[0026] Figure 4 It is from along Figure 3 Cross-sectional view observed in the direction of line BB.

[0027] Figure 5 yes Figure 1 Magnified view of part C.

[0028] Figure 6 This is a cross-sectional view illustrating a state in which a crack occurs in a conventional semiconductor device.

[0029] Figure 7 This is a SEM image of the cross-sectional structure when the sintered metal layer is pressurized at 0.25 MPa.

[0030] Figure 8 This is a SEM image of the cross-sectional structure when the sintered metal layer is pressurized at 1 MPa.

[0031] Fig. 9 This is a SEM image of the cross-sectional structure when the sintered metal layer is pressurized at 5 MPa.

[0032] Fig.10 This is a SEM image of the cross-sectional structure when the sintered metal layer is pressurized at 7.5 MPa.

[0033] Fig.11 This is a SEM image of the cross-sectional structure when the sintered metal layer is pressurized at 30 MPa.

[0034] Fig.12 This is a SEM image of the cross-sectional structure when the sintered metal layer is pressurized at 50 MPa.

[0035] Fig.13 This is a graph showing the relationship between the tensile strength of a sintered metal layer and the pressure.

[0036] Fig.14 This is a graph showing the relationship between the sintering density of the sintered metal layer and the pressurization.

[0037] Fig.15 This is a graph showing the relationship between the tensile strength and the sintered density of a sintered metal layer.

[0038] Fig.16 This is a graph showing the relationship between the sintering density and the compression rate of the sintered metal layer.

[0039] Fig.17 This is a graph showing the relationship between the tensile strength and the compression rate of the sintered metal layer.

[0040] Fig.18 This is a graph showing the relationship between the tensile strength and thickness of a sintered metal layer.

[0041] Fig.19 This is a table showing the tensile strength characteristics of the Al metal layer and the Al alloy layer used for the semiconductor element electrode of the semiconductor device according to the first embodiment.

[0042] Fig. 20 This is a schematic cross-sectional view showing another example of the through hole in the metal plate according to the first embodiment.

[0043] Fig.21 This is a schematic cross-sectional view showing still another example of the through hole in the metal plate according to the first embodiment.

[0044] Fig. 22 This is a schematic cross-sectional view showing an example of a pressurizing step in the method for manufacturing the semiconductor device according to the first embodiment.

[0045] Fig.23 It is a schematic cross-sectional view showing another example of the pressurizing step in the method for manufacturing the semiconductor device according to the first embodiment.

[0046] Fig.24 It is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the second embodiment.

[0047] Fig.25 yes Fig.24 Magnified view of part D in FIG.

[0048] Fig.26 This is a schematic plan view showing an example of a metal plate according to the second embodiment.

[0049] Fig. 27 It is from along Fig.26 Cross-sectional view observed in the direction of line EE.

[0050] Fig.28 It is a schematic cross-sectional view showing another example of the metal plate according to the second embodiment. DETAILED DESCRIPTION

[0051] Below, the first and second embodiments of the present invention are described with reference to the accompanying drawings. In the description of the drawings, the same or similar parts are marked with the same or similar marks, and repeated descriptions are omitted. Among them, the drawings are schematic, and the relationship between thickness and plane size, the ratio of thickness of each layer, etc. are sometimes different from the actual. In addition, the drawings may also include parts with different dimensional relationships and ratios. In addition, the embodiments shown below are used to illustrate the devices and methods for concretizing the technical ideas of the present invention. The technical ideas of the present invention do not specify the material, shape, structure, configuration, etc. of the structural components as the following materials, shapes, structures, configurations, etc.

[0052] In addition, the definitions of up and down directions in the following description are simply selected for convenience of description and are not intended to limit the technical concept of the present invention. For example, if the object is rotated 90° to observe, up and down are converted to left and right to read, and if the object is rotated 180° to observe, up and down are reversed to read, which is self-evident. Similarly, if the relationship between "front" and "back" is also rotated 180°, the definition of the reversed terms is used.

[0053] (First Embodiment)

[0054] The semiconductor device of the present invention comprises: a first semiconductor chip having a metal layer on its surface; a first wiring member arranged opposite to the metal layer; a sintered metal layer arranged between the metal layer and the first wiring member, the sintered metal layer comprising a first region and a plurality of second regions arranged inside the first region, wherein the tensile strength of each second region is lower than the tensile strength of the first region; and a metal material arranged inside the sintered metal layer, wherein the tensile strength of the second region of the sintered metal layer is lower than the tensile strength of the metal layer of the first semiconductor chip. Figure 1 As shown, the semiconductor device according to the first embodiment of the present invention includes a semiconductor chip (first semiconductor chip) 1, a joint portion 2, 2a, an insulating circuit substrate 8, and a wiring member 7. The insulating circuit substrate 8 includes an insulating plate 81, conductor layers (wiring layers) 82a, 82b formed by patterning on the upper surface of the insulating plate 81, and a conductor layer (heat dissipation layer) 83 provided on the lower surface of the insulating plate 81. The upper surface of the semiconductor chip 1 is electrically connected to one end of the wiring member 7 via the joint portion 2. The lower surface of the semiconductor chip 1 is electrically connected to the conductor layer 82a of the insulating circuit substrate 8 via the joint portion 2a. The other end of the wiring member 7 is electrically connected to the conductor layer 82b of the insulating circuit substrate 8 via the joint portion 6. The conductor layer 83 of the insulating circuit substrate 8 is connected to the heat dissipation base 10 via the joint portion 9.

[0055] As power semiconductor elements forming the semiconductor chip 1, there are 3-terminal elements such as IGBT and MOSFET, 2-terminal elements such as freewheeling diodes (FWD) and Schottky barrier diodes (SBD), etc. As wiring members 7, lead frames, metal plates, metal foils, etc. formed of copper (Cu) or aluminum (Al) with a plating layer of silver (Ag) or gold (Au) on the surface are used. For example, the insulating circuit substrate 8 can be a ceramic copper-clad (DCB) substrate obtained by eutectic bonding copper on the surface of a ceramic substrate, an AMB substrate obtained by configuring a metal on the surface of a ceramic substrate by an active metal brazing (AMB) method, etc. The material of the ceramic substrate can be, for example, silicon nitride (Si3N4), aluminum nitride (AlN), aluminum oxide (Al2O3), etc. In addition, as described later, considering the bonding using Ag nanoparticles, etc., it is preferred to set a plating layer of Ag, Au, etc. on the surface of the conductor layer 82a, 82b, 83 of the insulating circuit substrate 8.

[0056] Figure 2 yes Figure 1 FIG. 1 is an enlarged view of the portion A in FIG. 1 , i.e., the bonding portion between the semiconductor chip 1 and the wiring member 7. Figure 2 As shown, the semiconductor chip 1 includes an electrode layer (1B, 1C) and a semiconductor layer 1A of SiC or the like. The electrode layer (1B, 1C) includes an electrode metal layer 1B of Al or an Al alloy or the like and an outer plated metal layer 1C of silver (Ag) or gold (Au) or the like. The joint 2 includes a sintered metal layer 4a arranged on the outer plated metal layer 1C, a sintered metal layer 4b arranged on the sintered metal layer 4a and under the wiring member 7, and a metal plate 3 arranged between the sintered metal layer 4a and the sintered metal layer 4b, the metal plate 3 having a plurality of through holes 5. In the through hole 5, the portion filled with the sintered metal layer 4a is the first groove portion 15a, and the portion filled with the sintered metal layer 4b is the second groove portion 15b. As shown in FIG. Figure 3 As shown in FIG. 1 , a plurality of circular through holes 5 are arranged in a matrix on the metal plate 3 when viewed from above. Figure 4 As shown, the through holes 5 have the same diameter on the upper and lower surfaces of the metal plate 3. The arrangement of the through holes 5 is not limited to a matrix, but may be a strip arrangement or a random arrangement. In addition, the shape of the through holes 5 is not limited to a circular shape, but may be an elliptical shape, a rectangular shape, a polygonal shape, etc.

[0057] The first sintered metal layer 4a has a plurality of regions with different tensile strengths. The second sintered metal layer 4b has a plurality of regions with different tensile strengths. The metal plate 3 (metal material) is arranged between a portion of the first sintered metal layer 4a having a high tensile strength region and a portion of the second sintered metal layer 4b having a high tensile strength region.

[0058] The sintered metal layers (4a, 4b) include a first sintered metal layer 4a disposed on the first semiconductor chip 1 side of the metal material 3 and a second sintered metal layer 4b disposed on the first wiring member 7 side of the metal material 3. The metal material 3 is a first metal plate 3 having a plurality of first grooves 15a on the lower surface and a plurality of second grooves 15b on the upper surface. The metal material 3 has an area of ​​a planar portion 3e where the first grooves 15a and the second grooves 15b are not formed.

[0059] Figure 5 yes Figure 1 The enlarged view of the C portion in FIG. 1 , i.e., the bonding portion between the semiconductor chip 1 and the insulating circuit substrate 8. Figure 5 As shown, the semiconductor chip 1 has an electrode layer (1D, 1E) and a semiconductor layer 1A such as SiC. The electrode layer (1D, 1E) has an electrode metal layer 1D such as Al or Al alloy and an outer plated metal layer 1E such as silver (Ag) or gold (Au). The joint 2a has a sintered metal layer 4c arranged under the outer plated metal layer 1E, a sintered metal layer 4d arranged under the sintered metal layer 4c and on the conductor layer 82a of the insulating circuit substrate 8, and a metal plate 3a arranged between the sintered metal layers 4c and 4d, the metal plate 3a having a plurality of through holes 5a. Figure 3 and Figure 4 Similarly, in the metal plate 3 shown in the figure, a plurality of circular through holes 5a are arranged in a matrix on the metal plate 3a when viewed from above. In addition, the shape of the through holes 5a is not limited to a circular shape, and may also be an elliptical shape, a rectangular shape, a polygonal shape, etc. In addition, the arrangement of the through holes 5a is not limited to a matrix shape, and may also be a staggered arrangement, a strip arrangement, or a random arrangement.

[0060] As the material of the sintered metal layers 4a, 4b, 4c, 4d, nano-sized Ag nanoparticles are used. Alternatively, as the material of the sintered metal layers 4a, 4b, 4c, 4d, a composite material containing Ag powder of micron size in Ag nanoparticles may be used. As the material of the metal plate 3, in consideration of the bonding with the sintered metal layers 4a, 4b, metals such as Ag and Au are preferred. In addition, as the metal plate 3, a metal plate whose surface is plated with Ag or Au, such as copper (Cu), Al, or Al alloy may be used. In addition, regarding Figure 1 The bonding portions 6 and 9 shown in FIG. 1 are preferably made of sintered metal, but since they are away from the semiconductor chip 1 which is a heat source, a bonding member such as ordinary solder may also be used.

[0061] Compared with conventional solder bonding materials, sintered metal can increase tensile strength (hereinafter referred to as strength) and yield stress (hereinafter referred to as yield stress) by about 3 to 4 times, for example, expressed as 0.2% yield strength. In addition, compared with Al or Al alloys used as electrode materials for semiconductor elements, the yield stress can be increased by about 5 times. For example, Figure 6 As shown, similar to conventional semiconductor devices, the semiconductor chip 1 can be bonded to the wiring member 7 such as a lead frame by using the sintered metal layer 4z formed of Ag nanoparticles. In a semiconductor device bonded by using the high-strength sintered metal layer 4z, during the power-on cycle test, the wiring member 7 as a whole repeatedly expands and contracts thermally, causing the sintered metal layer 4z as the bonding portion to be repeatedly strained. The sintered metal layer 4z as the bonding portion has a strength sufficient to withstand the repeatedly applied stress, so the crack Ca is likely to extend in the electrode metal layer 1B formed of Al or Al alloy with low strength. In addition, it is believed that there is also a possibility that the generated crack Cb extends to the semiconductor layer 1A of the semiconductor chip 1. As a result, it is believed that there is a possibility that the electrode of the semiconductor chip 1 deteriorates and fails in advance.

[0062] In the semiconductor device according to the first embodiment, the strength of the sintered metal layers 4a and 4b is controlled by using the metal plate 3 having the through hole 5 between the sintered metal layers 4a and 4b. Figure 7 to Figure 12 To illustrate the relationship between the cross-sectional structure of the joint and the pressurization of the sintered metal. The Ag nanopaste obtained by dispersing Ag nanoparticles in a solvent is deposited on a flat base layer of metal or the like by a printing method. After deposition, the solvent is removed by drying. The sintered metal layer formed by the Ag nanoparticles after the solvent is dried is about 1 / 2 of the thickness of the Ag nanopaste deposited. Here, the thickness of the sintered metal layer after the solvent is dried is defined as the "supply thickness". In addition, a sheet-shaped or preformed sintered metal layer formed by Ag nanoparticles can also be used. In this case, the solvent drying process can be omitted. The sintered metal layer formed in this way is heated by a punch at a temperature in the range of 200°C to 300°C, for example, 250°C, while being pressurized to perform the joining of the sintered metal layer and the base layer. The cross-sectional structure of the joints of the sintered metal layers stacked with the pressurization varying in the range of 0.25MPa to 50MPa is observed by a scanning electron microscope (SEM). Here, the thickness of the sintered metal layer after pressurization is defined as the "stacked thickness".

[0063] Figure 7 to Figure 12 The cross-sectional SEM images of the sintered metal layers laminated by pressure change in the range of 0.25 MPa to 50 MPa are shown. Figure 7 to Figure 12In the SEM image shown, the bright part is the sintered metal layer, and the dark part is the void. Figure 7 and Figure 8 As shown in the figure, the larger the size of the voids, the lower the sintered density of the sintered metal. When the pressure is increased to 5MPa to 7.5MPa, Fig. 9 and Fig.10 As shown in FIG. 1 , the size of the voids decreases dramatically. Furthermore, when the pressure is increased to 30 MPa to 50 MPa, as shown in FIG. Fig.11 and Fig.12 As shown, the size of the voids is extremely small and the sintered metal layer is densified.

[0064] Fig.13 and Fig.14 The relationship between the tensile strength and sintered density of the sintered metal layer and the pressure applied is shown in the figure. Fig.13 As shown in FIG. 1 , the yield stress and the maximum stress expressed as the 0.2% yield strength increase sharply when the pressure increases from 0 to about 10 MPa, and increase slowly when the pressure is in the range of 10 MPa to 50 MPa. Fig.14 As shown in FIG. 1 , the sintered density also increases sharply when the pressure is increased from 0 to about 10 MPa, and increases slowly when the pressure is in the range of 10 MPa to 50 MPa. Figure 7 to Figure 12 As also observed in the SEM image of , it is shown that, by increasing the pressure, the sintered powders of the sintered metal layer come closer together, so that the sintered density increases, and the tensile strength of the sintered metal layer increases.

[0065] Fig.15 It represents the relationship between the sintering density and tensile strength of the sintered metal layer. Fig.15 As shown in FIG. 1 , the yield stress of the sintered metal layer depends on the sintered density. Here, the percentage of the change in the stacking thickness in the thickness direction relative to the supply thickness of the sintered metal layer is defined as the "compression rate". Specifically, if it is considered that the compression of the sintered metal layer by pressurization occurs almost in the pressurization direction, that is, the thickness direction, the "compression rate" can be calculated based on the change in the sintered density. Fig.16 It represents the relationship between compression rate and sintered density. Fig.16 As shown, when the compression rate is about 0%, the sintered metal layer contains about 60% of voids, and when the compression rate is about 50%, the voids in the sintered metal layer almost disappear. Fig.17 It represents the relationship between compression rate and tensile strength. As the compression rate of the sintered metal layer increases, the tensile strength increases. In addition, if it is considered that the compression of the sintered metal layer is almost one-dimensionally generated in the pressurized direction, the stacking thickness of the sintered metal layer can be calculated using the compression rate or sintering density. Fig.18 The relationship between stack thickness and tensile strength is shown. Fig.18 As shown in FIG. 1 , as the stacking thickness of the sintered metal layer increases, the tensile strength decreases. As described above, the strength of the sintered metal layer corresponding to the yield stress can be controlled by the pressure of the press using the punch. Alternatively, the strength of the yield stress of the sintered metal layer can be detected based on the sintering density, compression rate and stacking thickness of the sintered metal layer.

[0066] In the first embodiment, the sintering density of the sintered metal layers 4a and 4b is controlled so that the strength of the sintered metal layers 4a and 4b is equal to or less than the strength of the electrode metal layer 1B of the semiconductor chip 1, so that the stress generated when the semiconductor device is energized is dispersed in the joint 2. Figure 1 to Figure 4 As shown, a metal plate 3 having a through hole 5 is provided between the sintered metal layer 4 a and the sintered metal layer 4 b to control the yield stress of the sintered metal layers 4 a and 4 b of the joint portion 2 . Fig.19 The following table shows the results of tensile strength tests of Al metal with a purity of 99.99% (4N) and Al alloy containing 1.0% Si (Al-1.0% Si alloy) used as electrode metal layer 1B using a test piece with a diameter of 6 mm and a gauge length of 30 mm. Fig.19 As shown in FIG. 1 , the yield stress of Al metal is about 27 MPa, and the yield stress of Al-1.0% Si alloy is about 35 MPa. Therefore, in order to prevent cracks from occurring in the electrode metal layer 1B, the strength of the sintered metal layers 4a and 4b is controlled to be equal to or less than the tensile strength of Al or Al alloy, for example, within the range of 20 MPa to 40 MPa. Fig.15 As shown in FIG. 1 , in order to make the strength of the sintered metal layers 4a and 4b in the range of 20 MPa to 40 MPa, it is sufficient to make the sintered density in the range of 72% to 78%. Fig.17 As shown, in order to make the strength of the sintered metal layers 4a and 4b within the range of 20 MPa to 40 MPa, the compression rate only needs to be within the range of 10% to 20%.

[0067] In addition, it is preferred that the thickness Tm of the metal plate 3 is less than 50% of the supply thickness or less than 63% of the stacking thickness. When the thickness Tm of the metal plate 3 is thicker than 50% of the supply thickness, the area of ​​the through hole 5 may be insufficiently pressurized due to the increase in the compression rate of the sintered metal layers 4a and 4b in the upper and lower areas of the metal plate 3. In this case, the contact area with the semiconductor chip 1 and the insulating circuit substrate 8 is reduced, the bonding strength is reduced or the thermal resistance is increased. In addition, when a metal plate is not used, the heating and pressurizing method of the sintered metal layer is used as in the past. For example, when using multiple semiconductor chips with different thicknesses or when using a semiconductor chip with warping or tilt, excessive or insufficient pressurization occurs depending on the position, so the sintering density cannot be controlled. Therefore, the metal plate 3 needs to have a certain thickness Tm.

[0068] In the first embodiment, when the semiconductor chip 1 and the wiring member 7 are bonded together, Figure 2 The strength of the sintered metal layers 4a and 4b in the region of the through hole 5 shown in FIG. 1 is controlled to be in the range of 20 MPa to 40 MPa, for example, about 35 MPa. At this time, the sintered density is about 76% and the compression rate is about 18%. For example, the supply thickness of the sintered metal layers 4a and 4b in the region of the through hole 5 is about 100 μm. Figure 2 The stacking thickness Ts shown in is about 82 μm, that is, the deformation caused by compression is about 18 μm. In this case, the sintering density of the sintered metal layers 4a and 4b at the upper and lower regions of the metal plate 3 is in the range of more than 76% and less than 90%. In addition, it is preferred that the supply thickness of the sintered metal layers 4a and 4b is in the range of more than 50 μm and less than 1000 μm, and the stacking thickness is in the range of more than 41 μm and less than 820 μm.

[0069] In the semiconductor device according to the first embodiment, Figure 2 As shown in FIG. 1 , a metal plate 3 having a through hole 5 is provided between a sintered metal layer 4a and a sintered metal layer 4b to disperse stress generated when electricity is applied to the joint 2. The strength of the sintered metal layers 4a and 4b in the upper and lower regions of the metal plate 3 is higher than the strength of the sintered metal layers 4a and 4b in the region of the through hole 5. The region of the through hole 5 where the strength of the sintered metal layers 4a and 4b is low is surrounded by the upper and lower regions of the metal plate 3 where the strength of the sintered metal layers 4a and 4b is high and exists locally. Therefore, even if cracks occur in the sintered metal layers 4a and 4b in the region of the through hole 5, it is possible to prevent the cracks from extending to the entire sintered metal layers 4a and 4b including the upper and lower regions of the metal plate 3. As a result, it is possible to prevent the semiconductor chip 1 from being deteriorated, thereby improving the reliability of the semiconductor device.

[0070] In addition, it is preferred that the thickness Tb of the sintered metal layer 4b between the metal plate 3 and the wiring member 7 is thicker than the thickness Ta of the sintered metal layer 4a between the metal plate 3 and the semiconductor chip 1. By making the sintered metal layer 4b thicker, the strength of the sintered metal layer 4b is made smaller than that of the sintered metal layer 4a, and cracks can be prevented from being generated in the sintered metal layer 4b on the wiring member 7 side of the metal plate 3 and extending to the semiconductor chip 1 side.

[0071] Preferably, in the planar pattern, the area occupied by the opening of the through hole 5 is greater than 25% and less than 75% relative to the entire area including the surface of the metal plate 3 and the opening of the through hole 5. If the area occupied by the through hole 5 is less than 25%, the ratio of the high-strength portion in the sintered metal layers 4a, 4b increases, and the possibility of cracks in the electrode metal layers 1B, 1D increases. If the area occupied exceeds 75%, the ratio of the low-strength portion in the sintered metal layers 4a, 4b increases, and the possibility of cracks in the sintered metal layers 4a, 4b increases. In addition, in order to make the strength of the sintered metal layer 4b on the wiring member 7 side smaller than the sintered metal layer 4a on the semiconductor chip 1 side, it is also possible as shown in the example. Fig. 20 The occupied area of ​​the opening of the through hole 5b of the metal plate 3b is adjusted as shown. In the through hole 5b, the opening size w1 of the first groove 55a on the semiconductor chip side is smaller than the opening size w2 of the second groove 55b on the wiring member 7 side. Therefore, the strength of the sintered metal layer 4b on the wiring member 7 side can be made smaller than the sintered metal layer 4a on the semiconductor chip 1 side. Fig.21 In the example shown, a metal plate 3 c having a through hole 5 c with an opening size w2 on the wiring member 7 side being smaller than an opening size w1 on the semiconductor chip 1 side and having an inclined side wall is used.

[0072] Similarly, in the bonding between the semiconductor chip 1 and the wiring layer 82a of the insulating circuit substrate 8, Figure 5 The strength of the sintered metal layers 4c and 4d in the region of the through hole 5a shown in FIG. 1 is controlled to be within a range of 20 MPa to 40 MPa, for example, about 35 MPa. For example, the thickness of the sintered metal layer is about 100 μm. Figure 5 The stacking thickness Ts shown in is about 82 μm, that is, the deformation caused by compression is about 9 μm. At this time, the sintering density is about 76% and the compression rate is about 18%. In addition, it is preferred that the thickness Tm of the metal plate 3a is less than 50% of the supply thickness.

[0073] In addition, if Figure 5As shown in FIG. 1 , the thickness Td of the sintered metal layer 4d between the metal plate 3a and the wiring layer 82a of the insulating circuit substrate 8 is preferably thinner than the thickness Tc of the sintered metal layer 4c between the metal plate 3a and the semiconductor chip 1. By making the sintered metal layer 4d thin, the strength of the sintered metal layer 4d is made smaller than that of the sintered metal layer 4c, and cracks can be prevented from being generated in the sintered metal layer 4d on the wiring layer 82a side of the metal plate 3a and extending to the semiconductor chip 1 side. In addition, in order to make the strength of the sintered metal layer 4d on the insulating circuit substrate 8 side smaller than that of the sintered metal layer 4c on the semiconductor chip 1 side, a Fig. 20 and Fig.21 As shown, the metal plate has opening sizes different between the semiconductor chip 1 side and the insulating circuit board 8 side.

[0074] Next, refer to Figure 1 and Figure 2 The manufacturing method of the semiconductor device involved in the first embodiment is described. First, a sintered metal paste obtained by dispersing Ag nanoparticles in a solvent is applied to the upper surface of the electrode layer (1B, 1C) of the semiconductor chip 1 bonded to the wiring layer 82a of the insulating circuit substrate 8 by printing, dispensing, etc. The applied sintered metal paste is dried in a temperature range of 100°C to 150°C where sintering of the sintered metal does not occur to remove the solvent, thereby stacking the sintered metal layer 4a. A metal plate 3 having a plurality of through holes 5 is arranged on the sintered metal layer 4a. A sintered metal paste obtained by dispersing Ag nanoparticles in a solvent is applied to the metal plate 3 by printing, dispensing, etc. The applied sintered metal paste is dried in a temperature range of 100°C to 150°C to remove the solvent, thereby stacking the sintered metal layer 4b. In this way, a joint 2 having a sintered metal layer 4a, a metal plate 3, and a sintered metal layer 4b is formed on the upper surface of the semiconductor chip 1. The sintered metal layers 4 a and 4 b are physically connected to each other in the through hole 5 .

[0075] A wiring member 7 such as a lead frame is arranged on the bonding portion 2, and the sintered metal layers 4a and 4b are pressed from the wiring member 7 while being heated at a temperature in the range of 200°C to 300°C, for example, 250°C, by a press forming device such as a punch. The pressure is applied so that the compression rate of the sintered metal layers 4a and 4b in the region of the through hole 5 is in the range of 10% to 20%. By pressing, the semiconductor chip 1 and the sintered metal layer 4a are bonded, and the sintered metal layer 4b and the wiring member 7 are bonded. In the through hole 5, the sintered metal layers 4a and 4b are metallurgically connected, and the sintered density of the sintered metal layers 4a and 4b is in the range of 72% to 78%. On the other hand, the sintered density of each of the sintered metal layers 4a and 4b in the region on the metal plate 3 is higher than that of the sintered metal layers 4a and 4b in the region of the through hole 5. In this way, a semiconductor device is produced in which the semiconductor chip 1 is bonded to the insulating circuit substrate 8 and the wiring member 7 via the sintered metal layers 4 a and 4 b .

[0076] In addition, in the above description, sintered metal paste is used in the stacking of sintered metal layers 4a and 4b, but a sheet-shaped or preformed sintered metal layer formed of Ag nanoparticles may also be used. In addition, as the joint 2, a multilayer plate (metal clad member) obtained by pre-arranging a sintered metal layer on the front and back of a metal plate having a through hole may also be used.

[0077] In addition, the case of bonding one semiconductor chip 1 is described above, but it can also be applied to multiple semiconductor chips. When the thicknesses of the multiple semiconductor chips are different, the difference in thickness can be adjusted by using a buffer member such as heat-resistant rubber disposed between the stamping die of the press molding device and the semiconductor device. For example, Fig. 22 As shown, as the semiconductor device, a semiconductor chip (first semiconductor chip) 1 such as IGBT, MOSFET, etc. and a semiconductor chip (second semiconductor chip) 21 such as FWD, SBD, etc. are used. The semiconductor chip 1 is bonded to the wiring layer 82a via the bonding portion 2a. One end of the wiring member 7 is bonded to the semiconductor chip 1 via the bonding portion 2. The other end of the wiring member 7 is bonded to the wiring layer 82b via the bonding portion 6. Similarly, the semiconductor chip 21 is bonded to the wiring layer 82a via the bonding portion 22a. One end of the wiring member 27 is bonded to the semiconductor chip 21 via the bonding portion 22. The other end of the wiring member 27 is bonded to the wiring layer 82c via the bonding portion 26. The bonding portions 22, 22a and Figure 2 and Figure 5The bonding parts 2 and 2a shown in FIG. 1 have a structure in which a metal plate having a through hole is sandwiched between sintered metal layers. For example, when the semiconductor chip 21 is thicker than the semiconductor chip 1, the portion of the buffer member 32 disposed on the press surface of the press die 31 that contacts the wiring member 27 of the semiconductor chip 21 is made thinner than the portion that contacts the wiring member 7 of the semiconductor chip 1. In this way, the buffer member 32 can be used to perform bonding at the same time by using the press die 31 of the press molding device.

[0078] In addition, the difference in thickness of the semiconductor chips can also be adjusted by using the metal plate used in the bonding portion. Fig.23 As shown, the joint 2 includes a sintered metal layer 4a, a sintered metal layer 4b and a metal plate 3. The metal plate 3 is arranged between the sintered metal layer 4a and the sintered metal layer 4b, and the metal plate 3 has a through hole (not shown in the figure). The joint 22 includes a sintered metal layer 24a, a sintered metal layer 24b and a metal plate 23. The metal plate 23 is arranged between the sintered metal layer 24a and the sintered metal layer 24b, and the metal plate 23 has a through hole (not shown in the figure). The thickness Tm2 of the metal plate 23 is made thinner than the thickness Tm1 of the metal plate 3 to make the upper surfaces of the wiring component 7 of the semiconductor chip 1 and the wiring component 27 of the semiconductor chip 21 at the same level. As a result, as shown in FIG. Fig.23 As shown, the buffer member 32 disposed on the press surface of the stamping die 31 can contact the wiring members 7 and 27 with a flat surface and can be joined together. In addition, the level of the upper surface of the wiring members 7 and 27 can be adjusted by the thickness of the metal plate used for the joint portion 2a of the semiconductor chip 1 and the joint portion 22a of the semiconductor chip 21. Alternatively, the level of the upper surface of the wiring members 7 and 27 can be adjusted by the sum of the thickness of the metal plate of the joint portion 2 and 2a and the sum of the thickness of the metal plate of the joint portion 22 and 22a.

[0079] (Second Embodiment)

[0080] like Fig.24 As shown, the semiconductor device according to the second embodiment includes a semiconductor chip 1, a bonding portion 2c bonding the semiconductor chip 1 to an insulating circuit substrate 8, and a bonding portion 2b bonding the semiconductor chip 1 to a wiring member 7. Fig.24 The enlarged view of part D Fig.25As shown, the joint 2b is arranged between the electrode layer (1B, 1C) and the wiring member 7. The joint 2b includes a sintered metal layer 4e arranged on the outer metal plating layer 1C, a sintered metal layer 4f arranged under the wiring member 7, and a metal plate 3d arranged between the sintered metal layers 4e and 4f. The metal plate 3d has a plurality of first grooves 15a and a plurality of second grooves 15b independently on the lower surface and the upper surface, respectively. The plurality of first grooves 15a are provided on the side of the metal plate 3d facing the semiconductor chip 1. The plurality of second grooves 15b are provided on the side of the metal plate 3d facing the wiring member 7. The second embodiment differs from the first embodiment in that it has a metal plate 3d, and the metal plate 3d has a plurality of first grooves 15a and a plurality of second grooves 15b independently on the lower surface and the upper surface, respectively. The other structures are the same as those of the first embodiment, so repeated descriptions are omitted.

[0081] like Fig.26 As shown, in a plan view, a plurality of circular first grooves 15a are arranged in a matrix on the lower surface of the metal plate 3d, and a plurality of circular second grooves 15b are arranged in a matrix on the upper surface of the metal plate 3d. The shapes of the first and second grooves 15a, 15b are not limited to circular shapes, but may also be elliptical, rectangular, polygonal, etc. In addition, the arrangement of the first and second grooves 15a, 15b is not limited to a matrix, but may also be a strip arrangement or a random arrangement. Fig. 27 As shown, a plurality of first grooves 15a are provided on the side of the metal plate 3d facing the semiconductor chip 1, and have a depth Da. A plurality of second grooves 15b are provided on the side of the metal plate 3d facing the wiring member 7, and have a depth Db. The depth Da and the depth Db may be the same or different. As the material of the metal plate 3d, in consideration of the bonding with the sintered metal layers 4a and 4b containing Ag particles, Ag powder, etc., it is preferably a metal such as Ag or Au. In addition, as the metal plate 3d, it may also be a metal plate obtained by plating the surface of Cu, Al, Al alloy, etc. with Ag or Au.

[0082] In the semiconductor device according to the second embodiment, the strength of the sintered metal layers 4e and 4f is controlled by using a metal plate 3d having first and second grooves 15a and 15b between the sintered metal layers 4e and 4f. The sintering density of the sintered metal layers 4e and 4f is controlled so that the strength of the sintered metal layers 4e and 4f is equal to or less than the strength of the electrode metal layer 1B of the semiconductor chip 1, so that the stress generated when the semiconductor device is energized is dispersed in the joint 2b. Fig.19 As shown in FIG. 1 , the yield stress of Al metal is about 27 MPa, and the yield stress of Al-1.0% Si alloy is about 35 MPa. Therefore, the strength of the sintered metal layers 4e and 4f is controlled to be within the range of 20 MPa to 40 MPa. Fig.15 As shown in FIG. 1 , in order to make the strength of the sintered metal layers 4e and 4f within the range of 20 MPa to 40 MPa, the sintered density can be within the range of 72% to 78%. Fig.17 As shown, in order to make the strength of the sintered metal layers 4e and 4f within the range of 20 MPa to 40 MPa, the compression rate only needs to be within the range of 10% to 20%.

[0083] The thickness Tm of the metal plate 3d is preferably less than 50% of the supplied thickness. When the thickness Tm of the metal plate 3d is thicker than 50% of the supplied thickness, the compression rate of the sintered metal layers 4e and 4f in the upper and lower regions of the metal plate 3d may increase, resulting in insufficient pressure on the respective regions of the first and second grooves 15a and 15b. In this case, the contact area with the semiconductor chip 1 and the insulating circuit substrate 8 is reduced, the bonding strength is reduced or the thermal resistance is increased. In addition, when the metal plate is not used, the heating and pressurizing method of the sintered metal layer in the past is used. For example, when a plurality of semiconductor chips with different thicknesses are used or when a semiconductor chip with warping or tilt is used, excessive or insufficient pressure may occur depending on the position, so the sintering density cannot be controlled. Therefore, the metal plate 3d needs to have a certain degree of thickness Tm. In addition, it is preferred that the depths Da and Db of the first and second grooves 15a and 15b are respectively in the range greater than 0 and less than the thickness Tm of the metal plate 3d.

[0084] In the second embodiment, when the semiconductor chip 1 and the wiring member 7 are bonded together, Fig.25 The strength of the sintered metal layers 4e and 4f in the first and second grooves 15a and 15b shown in FIG. 1 is controlled to be within a range of 20 MPa to 40 MPa, for example, about 35 MPa. At this time, the sintered density is about 76% and the compression rate is about 18%. For example, the supply thickness of the sintered metal layers 4e and 4f is about 100 μm. Fig.25 The stacking thickness Tsa of the sintered metal layer 4e and the stacking thickness Tsb of the sintered metal layer 4f shown in the figure are respectively about 82 μm, that is, the deformation amount caused by compression is about 18 μm. When the depths Da and Db of the first and second grooves 15a and 15b are respectively in the range of greater than 0 and less than the thickness Tm of the metal plate 3d, the sintering density of the sintered metal layers 4e and 4f in the upper and lower regions of the metal plate 3d is in the range of greater than 76% and less than 90%.

[0085] In the semiconductor device according to the second embodiment, Fig.25As shown, a metal plate 3d having first and second grooves 15a and 15b is provided between the sintered metal layer 4e and the sintered metal layer 4f to disperse the stress generated when power is applied to the joint 2b. The strength of the sintered metal layers 4e and 4f in the area on the metal plate 3d is higher than the strength of the sintered metal layers 4e and 4f in the area on the first and second grooves 15a and 15b. The area on the first and second grooves 15a and 15b where the strength of the sintered metal layers 4e and 4f is low is surrounded by the area on the first and second grooves 15a and 15b where the strength of the sintered metal layers 4e and 4f is high and exists locally. Therefore, even if cracks occur in the area of ​​the sintered metal layers 4e and 4f on the first and second grooves 15a and 15b, it is possible to prevent the cracks from extending to the entire sintered metal layers 4e and 4f.

[0086] It is preferred that the depth Db of the second groove 15b of the metal plate 3d is deeper than the depth Da of the first groove 15a of the metal plate 3d. By making the first groove 15b deeper, the strength of the sintered metal layer 4f becomes smaller than that of the sintered metal layer 4e, and it is possible to prevent cracks from being generated in the sintered metal layer 4f on the wiring member 7 side of the metal plate 3d and the cracks from extending to the semiconductor chip 1 side. As a result, it is possible to prevent the semiconductor chip 1 from being deteriorated, thereby improving the reliability of the semiconductor device.

[0087] Preferably, in the planar pattern, the occupied area of ​​each of the first groove portion 15a and the second groove portion 15b is 25% or more and 75% or less of the entire area of ​​the metal plate 3d including the surface of the metal plate 3d and the opening of the first groove portion 15a or the opening of the second groove portion 15b. In addition, it is preferred that the thickness Tb of the sintered metal layer 4f between the metal plate 3d and the wiring member 7 is thicker than the thickness Ta of the sintered metal layer 4e between the metal plate 3d and the semiconductor chip 1. By making the sintered metal layer 4f thicker, the strength of the sintered metal layer 4f is made smaller than that of the sintered metal layer 4e, and cracks can be prevented from being generated in the sintered metal layer 4f on the wiring member 7 side of the metal plate 3d and extending to the semiconductor chip 1 side.

[0088] In order to make the strength of the sintered metal layer 4f on the wiring member 7 side smaller than that of the sintered metal layer 4e on the semiconductor chip 1 side, Fig.28 The opening areas of the first and second grooves 15a and 15b of the metal plate 3d are adjusted as shown. In the first groove 15a, the opening size Wa of the first groove 15a on the semiconductor chip side is smaller than the opening size Wb of the second groove 15b on the wiring member 7 side. Therefore, the strength of the sintered metal layer 4f on the wiring member 7 side can be made smaller than the sintered metal layer 4e on the semiconductor chip 1 side.

[0089] Likewise, in Fig.24 In the bonding between the semiconductor chip 1 and the wiring layer 82a of the insulating circuit substrate 8 shown in FIG. Fig.25The structure of the metal plate having the first and second grooves 15a and 15b is arranged between the sintered metal layers. The strength of the sintered metal layer in the region of the first and second grooves 15a and 15b is controlled to be within the range of 20 MPa to 40 MPa, for example, about 35 MPa. For example, the supply thickness of the sintered metal layer is set to about 100 μm. Fig.25 The stacking thicknesses Tsa and Tsb shown in are about 82 μm, respectively, that is, the deformation caused by compression is about 18 μm. At this time, the sintering density is about 76% and the compression rate is about 18%. In addition, it is preferred that the thickness Tm of the metal plate is less than 50% of the supply thickness.

[0090] In addition, it is preferred Fig.24 The thickness of the sintered metal layer between the metal plate of the joint 2c and the wiring layer 82a of the insulating circuit substrate 8 shown in the figure is thinner than the thickness of the sintered metal layer between the metal plate and the semiconductor chip 1. By making the sintered metal layer on the insulating circuit substrate 8 side thinner, the strength of the sintered metal layer on the insulating circuit substrate 8 side is made smaller than that of the sintered metal layer on the semiconductor chip 1 side, and cracks can be prevented from being generated in the sintered metal layer on the wiring layer 82a side of the joint 2c and extending to the semiconductor chip 1 side. In addition, in the first and second embodiments described above, the metal plates 3, 3d (metal material) may be any one of metal particles, metal fibers, and metal meshes.

[0091] (Other embodiments)

[0092] The present invention is described through the above-disclosed embodiments, but it should not be understood that the discussion and drawings constituting a part of the present disclosure are used to limit the present invention. It should be considered that, based on the disclosure of the specification and drawings of the present invention, various alternative embodiments, examples and application technologies will be clear to those skilled in the art. Alternatively, it goes without saying that the present invention includes various embodiments not described herein, such as structures that arbitrarily apply the various structures described in the above-mentioned embodiments and various modifications. Therefore, the technical scope of the present invention is determined only by the inventive technical features involved in the appropriate claims based on the above-mentioned illustrative description.

[0093] Description of Reference Numerals

[0094] 1, 21: semiconductor chip; 1A: semiconductor layer; 1B, 1D: electrode metal layer; 1C, 1E: outer metal plating layer; 2, 2a, 2b, 2c, 6, 9, 22, 22a, 26: joining portion; 3, 3a, 3b, 3c, 3d, 23: metal plate; 3e: plane portion; 4a, 4b, 4c, 4d, 4e, 4f, 24a, 24b: sintered metal layer; 5, 5a, 5b, 5c: through hole; 7, 27: wiring component; 8: insulating circuit substrate; 10: heat dissipation base; 15a, 55a: first groove portion; 15b, 55b: second groove portion; 31: stamping die; 32: buffer component; 81: insulating plate; 82a, 82b, 82c: conductor layer (wiring layer); 83: conductor layer (heat dissipation layer).

Claims

1. A semiconductor device, characterized in that: have: A first semiconductor chip having a metal layer on a surface thereof; a first wiring member disposed opposite to the metal layer; a sintered metal layer disposed between the metal layer and the first wiring member, comprising a first region and a plurality of second regions disposed inside the first region, wherein the tensile strength of each second region is lower than the tensile strength of the first region; and a metal material disposed inside the sintered metal layer, The tensile strength of the second region of the sintered metal layer is lower than the tensile strength of the metal layer of the first semiconductor chip, and the first region includes regions of the sintered metal layer located above and below the metal material.

2. The semiconductor device according to claim 1, wherein: The sintered metal layer includes a first sintered metal layer disposed on the first semiconductor chip side of the metal material and a second sintered metal layer disposed on the first wiring member side of the metal material. The metal material is a first metal plate having a plurality of first grooves on a lower surface and a plurality of second grooves on an upper surface, and has a region of a planar portion where the first grooves and the second grooves are not formed.

3. The semiconductor device according to claim 2, wherein: The plurality of first grooves and the plurality of second grooves are connected to each other to form a plurality of through holes.

4. The semiconductor device according to claim 2 or 3, characterized in that The sintering density of the first sintered metal layer and the second sintered metal layer in each region of the plurality of first groove portions and the plurality of second groove portions is in a range of 72% to 78%.

5. The semiconductor device according to claim 2 or 3, characterized in that: The sintering density of the first sintered metal layer in the region of the lower surface of the first metal plate is higher than the sintering density of the first sintered metal layer in the region of the plurality of first grooves. The sintering density of the second sintered metal layer in the region of the upper surface of the first metal plate is higher than the sintering density of the second sintered metal layer in the region of the plurality of second groove portions.

6. The semiconductor device according to claim 2 or 3, characterized in that: The sintering density of the first sintered metal layer in the region of the plurality of first groove portions is higher than the sintering density of the second sintered metal layer in the region of the plurality of second groove portions.

7. The semiconductor device according to claim 2 or 3, characterized in that: In the planar pattern, each of the plurality of first groove portions and the plurality of second groove portions occupies an area of ​​not less than 25% and not more than 75% of a surface area of ​​the first metal plate.

8. The semiconductor device according to claim 2 or 3, characterized in that: In the planar pattern, an occupied area of ​​the plurality of first groove portions is smaller than an occupied area of ​​the plurality of second groove portions.

9. The semiconductor device according to claim 2 or 3, characterized in that: The thickness of the first metal plate is within a range of greater than 0% and not more than 63% of the thickness of the first sintered metal layer from the surface of the first semiconductor chip to the bottom of the first groove.

10. The semiconductor device according to claim 2 or 3, characterized in that: A thickness of the first sintered metal layer from the upper surface of the first semiconductor chip to the bottom of the first groove is thinner than a thickness of the second sintered metal layer from the lower surface of the first wiring member to the bottom of the second groove.

11. The semiconductor device according to claim 1, wherein: Also available: a second semiconductor chip; a second metal plate disposed above the second semiconductor chip, having a plurality of third grooves on a lower surface of the second metal plate and a plurality of fourth grooves on an upper surface of the second metal plate; a second wiring member disposed above the second metal plate; a third sintered metal layer disposed between the second semiconductor chip and the second metal plate in a manner of filling the plurality of third grooves; as well as a fourth sintered metal layer disposed between the second metal plate and the second wiring member so as to fill the plurality of fourth grooves; Here, a height level of an upper surface of the first wiring member is the same as a height level of an upper surface of the second wiring member.

12. The semiconductor device according to claim 11, wherein: The sintered metal layer includes a first sintered metal layer disposed on the first semiconductor chip side of the metal material and a second sintered metal layer disposed on the first wiring member side of the metal material. The metal material is a first metal plate having a plurality of first grooves on a lower surface and a plurality of second grooves on an upper surface, and has a planar region where the first grooves and the second grooves are not formed. The thickness of the first metal plate is different from the thickness of the second metal plate.

13. The semiconductor device according to claim 1 or 2, characterized in that: Also available: a third metal plate disposed below the first semiconductor chip, having a plurality of fifth grooves on an upper surface of the third metal plate and a plurality of sixth grooves on a lower surface of the third metal plate; an insulating circuit substrate, which is arranged below the third metal plate and has a wiring layer on the upper surface of the insulating circuit substrate; a fifth sintered metal layer disposed between the first semiconductor chip and the third metal plate in a manner of filling the plurality of fifth grooves; as well as A sixth sintered metal layer is disposed between the third metal plate and the wiring layer so as to fill the plurality of sixth grooves.

14. The semiconductor device according to claim 1 or 2, characterized in that: The metal material is any one of metal particles, metal fibers and metal meshes.

15. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: bonding a first semiconductor chip to a wiring layer disposed on an upper surface of an insulating circuit substrate; Applying a sintered metal paste on the upper surface of the first semiconductor chip and drying the paste to laminate a first sintered metal layer; disposing a first metal plate having a plurality of first grooves on a lower surface and a plurality of second grooves on an upper surface on the first sintered metal layer in such a manner that the lower surface of the first metal plate is in contact with the first sintered metal layer; Applying a sintered metal paste on the upper surface of the first metal plate and drying the paste to laminate a second sintered metal layer; disposing a first wiring member on the second sintered metal layer; as well as The first sintered metal layer and the second sintered metal layer are heated and pressurized, and the first sintered metal layer is joined between the lower surface of the first metal plate and the first semiconductor chip in a manner that fills the plurality of first grooves, and the second sintered metal layer is joined between the upper surface of the first metal plate and the first wiring member in a manner that fills the plurality of second grooves, The sintered metal layer composed of the first sintered metal layer and the second sintered metal layer comprises a first region and a plurality of second regions arranged inside the first region, wherein the tensile strength of each second region is lower than the tensile strength of the first region, and the tensile strength of the second region is lower than the tensile strength of the metal layer on the surface of the first semiconductor chip, The first region includes a region of the first sintered metal layer located below the first metal plate and a region of the second sintered metal layer located above the first metal plate.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The plurality of first grooves and the plurality of second grooves are connected to each other to form a plurality of through holes.

17. The method for manufacturing a semiconductor device according to claim 15 or 16, wherein: The pressing of the first sintered metal layer and the second sintered metal layer is performed at a compression rate in a range of 10% to 20% with respect to a supply thickness of the first sintered metal layer and the second sintered metal layer after the sintered metal paste is dried.

18. The method for manufacturing a semiconductor device according to claim 15 or 16, wherein: The following steps are involved: forming a third sintered metal layer on the upper surface of the second semiconductor chip bonded to the insulating circuit substrate; disposing a second metal plate having a plurality of third grooves on a lower surface and a plurality of fourth grooves on an upper surface on the third sintered metal layer in such a manner that the lower surface of the second metal plate is in contact with the third sintered metal layer; forming a fourth sintered metal layer on the upper surface of the second metal plate; disposing a second wiring member on the fourth sintered metal layer; as well as The third sintered metal layer and the fourth sintered metal layer are heated and pressurized, and the third sintered metal layer is joined between the lower surface of the second metal plate and the second semiconductor chip in a manner that fills the plurality of third grooves, and the fourth sintered metal layer is joined between the upper surface of the second metal plate and the second wiring member in a manner that fills the plurality of fourth grooves, The pressurizing of the third sintered metal layer and the fourth sintered metal layer is performed simultaneously with the pressurizing of the first sintered metal layer and the second sintered metal layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The thickness of the first metal plate is different from the thickness of the second metal plate, and the height level of the upper surface of the first wiring member is the same as the height level of the upper surface of the second wiring member.

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