Device for generating analog signals

Abstract

A device for generating an analog signal, comprising: a digital-to-analog converter, which includes at least one digital input and one analog output; a circuit for generating a first clock signal with a frequency of fs; and a digital register, which is configured to receive and store N bits representing the analog output signal from the digital-to-analog converter at an input, N being an integer greater than or equal to 1, and to receive the first clock signal, the register including two complementary digital outputs for each bit; the device is characterized in that it also includes: a circuit for generating a second clock signal with a frequency of m×fs, wherein m is an integer greater than 1; and N multiplexer circuits, the N multiplexer circuits are placed between the output of the digital register and the input of the digital-to-analog converter, and are configured so that they receive the second clock signal at the control input respectively, and so that they receive signals from the two digital outputs of the register corresponding to the same input bit of the register at the data input respectively, so that the frequency of the signal leaving the multiplexer circuit is 2×m×fs.

Description

Technical Field

[0001] The present invention relates to generating analog signals from digital codes at high output frequencies, particularly output frequencies greater than the sampling frequency, while maintaining performance close to the first Nyquist zone and limiting the number of components in the signal processing chain. Background Art

[0002] In general, practical digital-to-analog converters have step outputs or provide pulses of finite width. The spectral response of the converter is reflected by a sinusoidal basis function. Therefore, the power response of the converter allows the generation of signals with a wide dynamic range in the first and second Nyquist zones, in other words, between 0 and fs / 2 and between fs / 2 and fs, where fs is the sampling frequency of the digital signal. Once one wishes to synthesize a signal exceeding the sampling frequency fs (e.g., 2fs or higher), the signal is severely attenuated.

[0003] To remedy this, a multiplier placed at the output of the converter can be used, which will convert the frequency of the generated signal by means of a convolution with the frequency fm. The analog system coming from the converter will then be converted around the frequency fm, which will allow the frequency of the signal coming from the converter to be raised (iffm>fs / 2) with the same dynamic range as that of the converter in the first Nyquist zone. However, this solution requires additional active components, in particular a radio frequency source, in order to generate the signal frequency fm. This increases the noise, distortion and power consumption of the converter. In addition, the use of two independent analog sources between the converter and the multiplier means that reconfigurability is poor.

[0004] To avoid this, fm can be chosen so that fm=fs; this allows the signal used to sample the digital data to be used to increase the frequency at the converter output (US 7796971). As a result, the analog signal output by the converter will be converted around the sampling frequency fs, and its dynamic range will always be equal to the dynamic range of the first Nyquist zone. However, we cannot always generate a signal with a frequency greater than 2fs, because this signal will always be strongly attenuated by the sinusoidal base response of the converter, thus reducing the system performance. Moreover, this solution is only applicable to current converters.

[0005] It is also possible to increase the sampling frequency fs. This allows increasing the dynamic range in the first and second Nyquist zones, but obtaining a converter with a wide Nyquist zone and a strong dynamic range is complicated because to achieve a high sampling frequency fs, the DAC cores must be interleaved, which generates additional spurious signals that degrade the performance.

[0006] There is also a possibility to perform multiple zeroing of the analog output signal from the converter (US 8659458). If N zeroings are performed, where N is an integer, the signal will be generated around N × fs with little attenuation. This requires a fast clock signal setup with a frequency of fs on the quantization clock and to apply zeroing that is shorter and shorter as N increases. This is only applicable to current converters. Summary of the invention

[0007] The object of the present invention is to overcome the above mentioned drawbacks and limitations of the prior art. More specifically, the object of the present invention is to propose a device for generating analog signals capable of optimizing the output power of a digital-to-analog converter and the digital bit rate at the input of the converter.

[0008] Therefore, the object of the present invention is a device for generating an analog signal, the device comprising: a digital-to-analog converter, which comprises at least one digital input and one analog output; a circuit for generating a first clock signal with a frequency of fs; and a digital register, which is configured so as to receive and store N bits representing the analog output signal from the digital-to-analog converter at an input, N being an integer greater than or equal to 1, and to receive the first clock signal, the register comprising two complementary digital outputs for each bit, the device being characterized in that it also comprises: a circuit for generating a second clock signal with a frequency of m×fs, wherein m is an integer greater than 1; and N multiplexer circuits, the N multiplexer circuits being placed between the output of the digital register and the input of the digital-to-analog converter and being configured so that they respectively receive the second clock signal at a control input, and so that they respectively receive signals from the two digital outputs of the register corresponding to the same input bit of the register at a data input, so that the frequency of the signal leaving the multiplexer circuit is 2×m×fs.

[0009] According to a specific embodiment of the invention:

[0010] - combining the circuit for generating the first clock signal and the circuit for generating the second clock signal;

[0011] - the circuit for generating the first clock signal and the second clock signal comprises a clock configured to generate a clock signal with a frequency of m×fs; and a frequency divider circuit configured such that the signal at the output of the frequency divider circuit is a clock signal with a frequency of fs;

[0012] - The converter is a digital-to-analog current converter or a digital-to-analog voltage converter.

[0013] - The multiplexer circuit comprises at least one bipolar multiplexer.

[0014] Another object of the present invention is a method for generating an analog signal, comprising the following steps:

[0015] a) providing N bits representing an analog signal at an input of a digital register, N being an integer greater than or equal to 1, and applying a first clock signal of frequency fs to the digital register, the register comprising two complementary digital outputs for each input bit;

[0016] b) applying a second clock signal having a frequency of 2×m×fs to N multiplexer circuits, m being an integer greater than or equal to 1, and providing signals from two complementary digital outputs of the register at the inputs of the N multiplexer circuits, the multiplexer circuit n receiving two outputs originating from the same input bit n, n being an integer between 1 and N;

[0017] c) providing output signals from said N multiplexer circuits at said inputs of a digital-to-analog converter;

[0018] d) recovering a signal at the output of the converter, the signal being derived from a current or voltage value, the spectral response of which is centered around a frequency m×fs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Other characteristics, details and advantages of the invention will become apparent from a reading of the description given with reference to the accompanying drawings, which are provided by way of example and are respectively:

[0020] Figure 1 is a device according to a first embodiment of the present invention;

[0021] Figure 2 is a device according to a second embodiment of the present invention.

[0022] Figure 3 is a device according to a third embodiment of the present invention; and

[0023] Figure 4 is a method for generating an analog signal according to the present invention. DETAILED DESCRIPTION

[0024] Figure 1 A device for generating an analog signal according to a first embodiment of the present invention is shown. The device comprises a digital register REG, which receives digital data to be converted at an input IN. The digital data is, for example, a binary word comprising three bits B1, B2 and B3. The register REG comprises two complementary outputs for each bit, namely a first output for providing the bit and a second output for providing its complement. Figure 1In the embodiment shown, only three inputs for three bits (B1, B2, B3) and six outputs (B1, B2. B3, ), but more generally, the register can receive N bits at its input, where N is an integer greater than or equal to 1, and will therefore have N inputs and 2N outputs.

[0025] The first circuit C1 for generating a clock signal sends a clock signal Clk1 with a frequency fs to the register REG so that these bits and their complements (B1, B2. B3, ) leaves register REG with frequency fs.

[0026] There is a second circuit C2 for generating a clock signal Clk2. This circuit sends a clock signal Clk2 with a frequency of m×fs to the control inputs of the multiplexer circuits M1, M2 and M3, where m is an integer greater than 1. The multiplexer circuits M1, M2 and M3 are placed at the output of the register REG. Each multiplexer circuit (M1, M2, M3) receives at its input two output signals from the register REG, more specifically a bit and its complement, so that the two output signals correspond to the same input bit in the register REG. Thus, the multiplexer circuit M1 receives (B1, ), circuit M2 receives (B2, ), circuit M3 receives (B3, ). With the help of the second clock signal Clk2 with a frequency of m×fs, each multiplexer circuit will have the bit B1, B2 or B3 or its complement at the output according to the rising or falling edge of the clock signal Clk2 or This makes it possible to obtain these bits or their complement at the output of the multiplexer circuit (M1, M2, M3) with a frequency of 2×m×fs.

[0027] The output of the multiplexer circuit (M1, M2, M3) is then sent to a digital-to-analog converter DAC, which includes three digital inputs IN_DAC and one digital output OUT. Only three inputs IN_DAC are shown in the figure, because there are 3 bits at the input of the register REG: bit 1, bit 2 and bit 3, but more generally, the number of inputs is as many as the number of bits at the input of the register REG.

[0028] These bits are converted into analog data in the converter DAC, and the spectral response of the analog signal obtained at the output OUT of the converter is centered at a frequency m×fs with a maximum width of fs / 2. This allows sufficient power levels to be maintained at high frequencies (m×fs) by means of a fast clock signal.

[0029] Figure 2 FIG. 2 shows a device for generating an analog signal according to a second embodiment of the present invention. Figure 1 Similarly, only three bits are shown at the input IN of the digital register REG: bit 1, bit 2 and bit 3, but there may be N bits at the input of the register REG, where N is an integer greater than or equal to 1. Unlike the first embodiment, the circuits for generating the two clock signals are combined. Only one circuit C generates the clock signal Clkat with a frequency of m×fs, where m is an integer greater than or equal to 1. The clock signal Clk is sent directly to the multiplexer circuits M1, M2 and M3, thereby following the clock signal Clk. Figure 1 Likewise, these bits and their complement are available at the output of the multiplexer circuits M1, M2 and M3 with a frequency 2×m×fs. However, before being sent to the register REG, the clock signal Clkfirst passes through a frequency divider circuit D which divides the frequency of the clock signal by m, thus allowing to have a clock signal Clk1 with a frequency of fs at the input of the register.

[0030] Figure 3 A third embodiment of the invention is shown. An exemplary device and a digital-to-analog converter structure according to the invention are described. The register REG receives two bits at input: bit 1 and bit 2, which are clocked at the frequency fs of the clock signal Clk1 as (B1, ) and (B2, ) appears from the register. Next, (B1, ) and (B2, ) enters the multiplexer circuits M1 and M2 and emerges at a frequency 2×m×fs with the aid of a clock signal Clk2 with a frequency m×fs sent to the two multiplexer circuits. At the converter input, the register REG_DAC receives a clock signal Clk2 with a frequency m×fs, for example from a second circuit C2 for generating a clock signal, or from another circuit for generating a clock signal. For each input bit (B1, B2. ), the register REG_DAC provides the bit or its complement at the output. The register REG_DAC includes two outputs for one input: an even output (PAIR1, PAIR2) that provides the complement of the bit; an odd output (IMP1, IMP2) that provides the bit. The combination of two even and odd outputs for the same input bit is called a differential branch. Two differential branches BD1 and BD2 are shown in this embodiment. Two current sources S1 and S2 allow two differential branches BD1 and BD2 to be provided. According to the value of the bit (0 or 1) in the register REG_DAC, the transistors (T1, T2, T3, T4) present in the two differential branches BD1 and BD2 are made conductors. For example, if bit 1 appears on the odd branch IMP1, transistor T1 will become a conductor, and if bit 0 appears on the odd branch IMP1, transistor T2 will be blocked. For branch PAIR, the opposite is true, the output bit must be 0 to make transistor T2 a conductor, or the output bit must be 1 to make transistor T2 in a blocking state. The same principle applies to the even and odd outputs of the second differential branch BD2.

[0031] The output currents of the odd branches are added in an adder circuit, which in this embodiment is a resistor R1. The output currents of the even branches are likewise added in an adder circuit, which in this embodiment is likewise a resistor R2. The voltage difference between the voltages at the resistor terminals R1 and R2 represents the digital value of the binary word to be converted, which digital value is provided at the input IN of the device via bit 1 and bit 2. This voltage difference is provided at the output OUT of the converter DAC. Depending on the type of converter, in other words, whether it is a current converter or a voltage converter, the output OUT will be a current value or a voltage value.

[0032] According to another embodiment of the invention, the multiplexer circuit (M1, M2, M3) comprises at least one bipolar multiplexer.

[0033] According to another embodiment, the DAC converter comprises bipolar transistors. According to another embodiment, the DAC converter comprises MOSFET transistors, in other words insulated gate field effect transistors.

[0034] According to another embodiment, the DAC converter is a voltage converter. According to various embodiments, the DAC converter is more specifically:

[0035] - a digital-to-analog converter with a switching function, the switch of which is controlled according to the bit value at the converter input;

[0036] - a digital-to-analog converter with a resistor network R / 2R; or

[0037] -Digital-to-analog converter with weighted resistors.

[0038] These three converters typically operate at lower frequencies than the digital-to-analog current converters.

[0039] Figure 4 A method for generating an analog signal according to the present invention is shown. The first step (step a) involves providing N bits representing the analog signal at the input of a digital register, N being an integer greater than or equal to 1, and applying a first clock signal of a frequency fs to the digital register, the register comprising two complementary digital outputs for each input bit. The following step b involves applying a second clock signal of a frequency of 2×m×fs to N multiplexer circuits, m being an integer greater than or equal to 1, and providing signals from the two complementary digital outputs of the register at the input of N multiplexer circuits, the multiplexer circuit n receiving two outputs originating from the same input bit n, n being an integer between 1 and N. Then in step c, the output signals of the N multiplexer circuits are provided at the input of a digital-to-analog converter, and finally, in the last step (step d), the output signal from the converter corresponding to a voltage or current value is recovered, the spectral response of the signal being centered on the frequency m×fs.

[0040] This method of generating an analog signal can be implemented on a device according to the invention, such as the device described previously.

Claims

1. A device for generating an analog signal, comprising: - a digital-to-analog converter comprising at least one digital input and one analog output; - a circuit for generating a first clock signal with a frequency fs; as well as a digital register configured so as to receive and store at input N bits representing the analog output signal from said digital-to-analog converter, N being an integer greater than or equal to 1, and receiving said first clock signal, said register comprising for each bit two complementary digital outputs; The device is characterized in that it further comprises: a circuit for generating a second clock signal with a frequency of m×fs, wherein m is an integer greater than 1; and N multiplexer circuits, which are placed between the output of the digital register and the input of the digital-to-analog converter and are configured so that they receive the second clock signal at their control inputs, respectively, and so that they receive signals from two digital outputs of the register corresponding to the same input bit of the register, respectively, at their data inputs, so that the frequency of the signal leaving the multiplexer circuit is m×fs.

2. The apparatus for generating an analog signal according to claim 1, wherein the circuit for generating the first clock signal and the circuit for generating the second clock signal are combined.

3. The device for generating an analog signal according to claim 2, wherein the circuit for generating the first clock signal and the second clock signal comprises: A clock configured to generate a clock signal having a frequency of m×fs; and a frequency divider circuit configured such that the signal at the output of the frequency divider circuit is a clock signal with a frequency of fs.

4. The device for generating an analog signal according to any of the preceding claims, wherein the converter is a digital to analog current converter.

5. The device for generating an analog signal according to any one of claims 1 to 3, wherein the converter is a digital-to-analog voltage converter.

6. The device for generating an analog signal according to any one of claims 1 to 3, wherein the multiplexer circuit comprises at least one bipolar multiplexer.

7. A method for generating an analog signal, comprising the steps of: a) providing N bits representing an analog signal at an input of a digital register, N being an integer greater than or equal to 1, and applying a first clock signal of frequency fs to the digital register, the register comprising two complementary digital outputs for each input bit; b) applying a second clock signal having a frequency of m×fs to control inputs of N multiplexer circuits, m being an integer greater than or equal to 1, and providing signals from two complementary digital outputs of the register at the inputs of the N multiplexer circuits, the multiplexer circuit n receiving two outputs originating from the same input bit n, n being an integer between 1 and N; c) providing output signals from said N multiplexer circuits at said inputs of a digital-to-analog converter; d) recovering a signal at the output of the converter, the signal being derived from a current or voltage value, the spectral response of which is centered around a frequency m×fs.

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