Pin control circuit and integrated chip

Abstract

The present application discloses a pin control circuit and an integrated chip, which are used to increase the functions of the pins in the integrated chip so that it can meet the needs of multiple application scenarios. The pin control circuit includes: a processing unit, a function control unit and a function selection unit; wherein the processing unit is connected to the function control unit and the function selection unit, and is used to receive a signal from an input port and generate a communication signal based on the received signal; the function control unit is connected to the function selection unit, and is used to receive a communication signal and generate a power on / off signal or a data transmission signal according to the communication signal; the function selection unit is used to receive the power on / off signal or the data transmission signal, and based on the power on / off signal, the pin realizes the power on / off function, and based on the data transmission signal, the pin realizes the data communication function.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, and in particular to a pin control circuit and an integrated chip. Background Art

[0002] In today's electronic technology field, integrated chips are widely used in multiple scenarios due to their full functionality and small size. With the development of technology, the functions they can achieve are increasing. Integrated chips are connected to external devices through pins, and external devices are connected to integrated chips through pins to achieve specific functions.

[0003] In the application development process of integrated chips, most pins can only realize a single function. Once the pin is occupied, the integrated chip cannot realize the corresponding function. In order to solve this problem, a pin reuse method that uses fuses to burn and blow to determine the function of the pin has emerged. However, this reuse method has the problem that the function cannot be changed once it is determined, or it needs to be changed in conjunction with the internal software system. If there is no software system, the function of the pin cannot be changed.

[0004] In order to achieve low power consumption during pin reuse, the enable pin of an integrated chip can usually only realize a single function. If you want to add functions, you need to add additional pins for communication or control, or use a new chip to replace the original chip. In this case, the layout of the original system circuit board needs to be re-planned, resulting in low development efficiency, high development cost, and low portability.

[0005] Based on the above situation, the pin functions of existing integrated chips are single and are not applicable in multi-functional application scenarios. Summary of the invention

[0006] The embodiments of the present invention provide a pin control circuit and an integrated chip, which are used to increase the functions of the integrated chip pins so as to meet the requirements of multiple application scenarios.

[0007] In the first aspect, the embodiment of the present application provides a pin control circuit, including: a processing unit, a function control unit and a function selection unit. The processing unit is connected to the function control unit and the function selection unit, and is used to receive a signal from an input port and generate a communication signal based on the received signal; the function control unit is connected to the function selection unit, and is used to receive a communication signal sent by the processing unit, and generate a power on / off signal or a data transmission signal according to the communication signal; the function selection unit is used to receive the power on / off signal or the data transmission signal, and based on the power on / off signal, the pin implements the power on / off function, and based on the data transmission signal, the pin implements the data communication function.

[0008] By adopting the pin control circuit provided in the first aspect, multiple functional units can be configured for the multifunctional pin, and according to the communication signal received by the input port of the processing unit, it is determined whether the pin needs to switch functions (power-on function, power-off function and communication function). When it is determined that the pin needs to switch functions, a power-on / off signal is sent through the data control unit to realize the power-on function or the power-off function, or the data selection unit is used to realize data transmission between the integrated chip and the external device connected to the input port, so that the pin in the integrated chip realizes multiple functions. Therefore, the pin can realize multiple functions and meet the needs of multiple application scenarios.

[0009] In summary, by adopting the pin control circuit provided in the embodiment of the present application, multiple functions can be realized through one pin, so that when other pins of the integrated chip are occupied, the corresponding functions can be realized through this pin, thereby meeting the needs of multiple application scenarios.

[0010] In a possible implementation, the processing unit includes: a detection module and a driving module. The detection module is connected to the input port of the pin and is used to detect the signal of the input port and generate a communication signal according to the signal; the driving module is connected to the function selection unit and is used to implement the communication function.

[0011] In a possible implementation, the driving module includes: a first metal oxide semiconductor field effect transistor MOS tube and a second MOS tube. The source of the first MOS tube is connected to the power supply, the gate of the first MOS tube is connected to the function selection unit, the drain of the first MOS tube is connected to the drain of the second MOS tube and the input port; the gate of the second MOS tube is connected to the function selection unit, and the source of the second MOS tube is connected to the ground line.

[0012] In a possible implementation, the detection module includes: a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a first capacitor and a first inverter. Wherein, the source of the third MOS tube is connected to the power supply, the gate of the third MOS tube is connected to the function selection unit, and the drain of the third MOS tube is connected to the drain of the fourth MOS tube; the gate of the fourth MOS tube is connected to the input port, the source of the fourth MOS tube is connected to the drain of the fifth MOS tube; the gate of the fifth MOS tube is connected to the drain, and the source of the fifth MOS tube is connected to the ground line; the drain of the sixth MOS tube is connected to the drain of the fifth MOS tube, the gate of the sixth MOS tube is connected to the function selection unit, and the source of the sixth MOS tube is connected to the ground line; the source of the seventh MOS tube is connected to the power supply, the gate of the seventh MOS tube is connected to the function selection unit, and the drain of the seventh MOS tube is connected to the drain of the third MOS tube; the first end of the first capacitor is connected to the power supply, and the second end of the first capacitor is connected to the source of the seventh MOS tube; the input end of the first inverter is connected to the second end of the first capacitor, and the output end of the first inverter outputs the communication signal.

[0013] In a possible implementation, the function control unit includes: a clock unit, a communication unit, a power on / off unit, and a register logic unit. The clock unit is connected to the power on / off unit, the communication unit, and the register logic unit, and is used to generate a clock signal with a preset period, and send the clock signal to the communication unit, the power on / off unit, and the register logic unit, so that the communication unit, the power on / off unit, and the register logic unit are synchronized based on the clock signal; the power on / off unit is connected to the processing unit, and is used to receive the communication signal as a clock signal, and generate the power on / off signal according to the level value of the communication signal and the duration of the level value; the communication unit is connected to the processing unit and the register logic unit, and is used to receive the communication signal, and when it is determined that the power on / off unit is in the power on state, and the level value of the communication signal is the preset level for a duration less than a preset threshold, it generates a data transmission signal, and writes data to the register logic unit or reads data from the register logic unit according to the communication information carried in the communication signal; the register logic unit is used to perform data writing or data reading operations.

[0014] The pin control circuit provided in the first aspect is adopted to generate a power-on / off signal according to the level maintenance time of the communication signal received by the processing unit to control the pin to realize the power-on function or the power-off operation, and when it is determined that the power-on / off unit is in the power-on state and the level value of the communication signal is a preset level for a duration less than a preset threshold, the control circuit communicates with the device connected to the outside of the pin, so that the pin realizes the power-on function, the power-off function and the communication function.

[0015] In a possible implementation, the clock unit includes: an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a second capacitor, and a comparator. Among them, the source of the eighth MOS tube is connected to the power supply, the gate of the eighth MOS tube is connected to the second end of the second capacitor, the drain of the eighth MOS tube is connected to the drain of the ninth MOS tube and the drain of the tenth MOS tube; the gate of the ninth MOS tube is connected to the output end of the comparator, the source of the ninth MOS tube is connected to the first end of the second capacitor and the drain of the eleventh MOS tube; the gate of the tenth MOS tube is connected to the output end of the comparator, the source of the tenth MOS tube is connected to the second end of the second capacitor and the first input end of the comparator; the gate of the eleventh MOS tube is connected to the output end of the comparator, and the gate of the eleventh MOS tube is connected to the output end of the comparator. The source of the S tube is connected to the ground line; the drain of the twelfth MOS tube is connected to the second end of the second capacitor, the gate of the twelfth MOS tube is connected to the output end of the comparator, and the source of the twelfth MOS tube is connected to the ground line; the source of the thirteenth MOS tube is connected to the power supply, the gate of the thirteenth MOS tube is connected to the second end of the second capacitor, the drain of the thirteenth MOS tube is connected to the drain of the fourteenth MOS tube and the second input end of the comparator; the gate and drain of the fourteenth MOS tube are connected, and the source of the fourteenth MOS tube is connected to the ground line; the output end of the comparator is connected to the switch unit, the communication unit and the register logic unit.

[0016] In a possible implementation, the switch unit includes: a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a time detection unit, a first resistor, a second resistor, a second inverter, and a third capacitor. Among them, the input end of the time detection unit receives the communication signal, and the output end of the time detection unit is connected to the gate of the fifteenth MOS tube; the source of the fifteenth MOS tube is connected to the power supply, and the drain of the fifteenth MOS tube is connected to the first resistor and the gate of the nineteenth MOS tube; the drain of the sixteenth MOS tube is connected to the second end of the first resistor and the drain of the seventeenth MOS tube, the gate of the sixteenth MOS tube is connected to the second end of the first capacitor, and the source of the sixteenth MOS tube is connected to the ground line; the gate of the seventeenth MOS tube is connected to the output end of the first inverter, and the source of the seventeenth MOS tube is connected to the ground line; the source of the eighteenth MOS tube is connected to the power supply, and the gate of the eighteenth MOS tube is connected to the input of the first inverter. The output end of the first inverter is connected, the drain of the eighteenth MOS tube is connected to the first end of the second resistor; the drain of the nineteenth MOS tube is connected to the second end of the second resistor and the drain of the twentieth MOS tube, the gate of the nineteenth MOS tube is connected to the first end of the first resistor, and the source of the nineteenth MOS tube is connected to the ground line; the drain of the twentieth MOS tube is connected to the second end of the second resistor, the gate of the twentieth MOS tube is connected to the output end of the first inverter, and the source of the twentieth MOS tube is connected to the ground line; the first end of the third capacitor is connected to the power supply, and the second end of the third capacitor is connected to the second end of the second resistor; the input end of the second inverter is connected to the second end of the second resistor, and the output switch signal of the second inverter is sent to the function selection unit.

[0017] In a second aspect, an embodiment of the present application provides an integrated chip, which includes the pin control circuit provided by the above-mentioned first aspect and any possible implementation manner thereof.

[0018] By using the integrated chip provided in the second aspect, the pins of the integrated chip and the control circuit of the pins can be connected in the integrated chip in an integrated manner, thereby reducing the volume of the pin control circuit provided in the embodiment of the first aspect.

[0019] In addition, the technical effects brought about by any possible implementation in the second aspect can refer to the technical effects brought about by different implementations in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0021] Figure 1 A schematic diagram of the structure of the pin control circuit provided in the embodiment of the present invention Figure 1 ;

[0022] Figure 2 A schematic diagram of the structure of the pin control circuit provided in the embodiment of the present invention Figure 2 ;

[0023] Figure 3 A schematic diagram of the circuit structure of a processing unit provided in an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of the circuit structure of a function control unit provided in an embodiment of the present invention;

[0025] Figure 5 A schematic diagram of pin status provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application.

[0027] The following describes a specific implementation of a pin control circuit and an integrated chip provided by an embodiment of the present invention in conjunction with the accompanying drawings.

[0028] Most of the current integrated chips have 8-24 pins, each of which is connected to a fixed external device for receiving signals sent by the external device and implementing corresponding functions according to the received signals. However, in actual applications, for some application scenarios, for example, when the pins used for communication in the integrated chip are occupied, if the external device needs to communicate with the integrated chip at this time, the integrated chip cannot realize the communication function, unless another integrated chip is added to enable the external device to communicate with the newly added integrated chip, thereby realizing the communication function. It can be seen from this that the existing integrated chips have the problem that when the pins of the integrated chip are occupied, the function corresponding to the pins cannot be realized, and the needs of multiple application scenarios cannot be met.

[0029] Based on this, the embodiment of the present application provides a pin control circuit and an integrated chip, which are used to solve the problem in the prior art that when the pin in the integrated chip is occupied, the function corresponding to the pin cannot be realized, thereby failing to meet the requirements of the application scenario. Among them, the pin control circuit and the integrated chip are based on the same inventive concept. Since the principles of solving the problem by the multifunctional pin and the integrated chip are similar, the implementation of the method, the multifunctional pin and the integrated chip can refer to each other, and the repeated parts will not be repeated.

[0030] In the specific introduction of the following embodiments, it should be noted that the multiple involved in this application refers to two or more. The term "or" involved in this application describes the association relationship of associated objects, indicating that three relationships may exist. For example, A or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The connection involved in this application describes the connection relationship between two objects and can represent two connection relationships. For example, A and B are connected, which can represent: A is directly connected to B, and A is connected through C and B. In addition, it should be understood that in the description of this application, words such as "first", "second", "third"... are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0031] See also Figure 1 , is a schematic diagram of the structure of a pin control circuit provided in an embodiment of the present application. Figure 1 The pin control circuit 100 shown includes a processing unit 101, a function control unit 102 and a function selection unit 103. The processing unit 101 is connected to the function control unit 102 and the function selection unit 103, and the function selection unit 103 is connected to the function control unit 102.

[0032] Among them, the processing unit 101 can be used to receive the signal of the input port of the multi-function pin control circuit 100, and generate a communication signal based on the received signal; the function control unit 102 can be used to receive the communication signal sent by the processing unit 101, and generate a power on / off signal or a data transmission signal according to the communication signal; the function selection unit 103 can be used to receive the power on / off signal or the data transmission signal, and enable the pin to realize the power on / off function based on the power on / off signal, and enable the pin to realize the data communication function based on the data transmission signal.

[0033] Among them, the above-mentioned pins can be pins in the integrated chip used for turning on and off the machine, and of course can also be other pins in the integrated chip, which is not limited in this application.

[0034] For ease of understanding, the implementation of the pin control circuit 100 is described by taking the pin as a pin for powering on and off in an integrated chip and using the pin to implement power on, power off and communication as an example.

[0035] For example, the structure of the pin control circuit provided in the embodiment of the present application can be as follows: Figure 2 In the pin control circuit 100 provided in the embodiment of the present application, the processing unit 101 includes a detection unit and a driving unit, and the function control unit 102 includes a clock unit, a communication unit, a power on / off unit and a register unit. The working principle of the circuit is as follows:

[0036] In the pin control circuit provided in the embodiment of the present application, an external device transmits a signal through the pin input port, a detection unit converts the signal received at the pin input port into a communication signal, and outputs the communication signal to the switch unit and the communication unit, the switch unit detects the level value of the communication signal and the maintenance time of the level value, and generates a switch signal according to the level value of the communication signal and the maintenance time of the level value, and the communication unit generates a data transmission signal when it is determined that the switch unit is in the power-on state and the duration of the level value of the communication signal being a preset level is less than a preset threshold, writes data to the register logic unit or reads data from the register logic unit according to the communication information carried in the communication signal, and realizes the data communication function through the data transmission signal.

[0037] Specifically, if the communication signal is a high level value, a power-on signal is generated when it is determined that the current integrated chip is in a power-off state and the high level value of the communication signal is maintained for a time greater than or equal to a preset threshold; if the communication signal is a low level, a power-off signal is generated when it is determined that the integrated chip is in a power-on state and the low level value of the communication signal is maintained for a time greater than or equal to a preset threshold.

[0038] Specifically, when it is determined that the integrated chip is in the power-on state and the maintenance time of the low-level value of the communication signal is less than a preset threshold, the communication signal is sent to the communication unit, and the communication unit writes the communication information carried in the communication signal to the register logic unit or reads data from the register unit, and generates a data transmission signal, and the data communication function is realized through the function selection unit based on the data transmission signal.

[0039] Next, the specific structures of the processing unit 101 , the function control unit 102 and the function selection unit 103 in the pin control circuit 100 are introduced.

[0040] 1. Processing Unit 101

[0041] The processing unit 101 may include a detection module and a driving module. Specifically, the detection module is connected to the input port of the pin, and the driving module is connected to the function selection unit 103. The detection module is configured to detect the signal of the input port and generate a communication signal according to the signal. The driving module is configured to realize the communication function.

[0042] The driving module may include: a first metal oxide semiconductor field effect transistor (MOS) transistor and a second MOS transistor.

[0043] Specifically, the source of the first MOS tube is connected to the power supply, the gate of the first MOS tube is connected to the function selection unit 103, the drain of the first MOS tube is connected to the drain of the second MOS tube and the input port; the gate of the second MOS tube is connected to the function selection unit, and the source of the second MOS tube is connected to the ground line.

[0044] The detection module may include: a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a first capacitor and a first inverter.

[0045] Specifically, the source of the third MOS tube is connected to the power supply, the gate of the third MOS tube is connected to the function selection unit, and the drain of the third MOS tube is connected to the drain of the fourth MOS tube; the gate of the fourth MOS tube is connected to the input port, and the source of the fourth MOS tube is connected to the drain of the fifth MOS tube; the gate of the fifth MOS tube is connected to the drain, and the source of the fifth MOS tube is connected to the ground line; the drain of the sixth MOS tube is connected to the drain of the fifth MOS tube, the gate of the sixth MOS tube is connected to the function selection unit, and the source of the sixth MOS tube is connected to the ground line; the source of the seventh MOS tube is connected to the power supply, the gate of the seventh MOS tube is connected to the function selection unit, and the drain of the seventh MOS tube is connected to the drain of the third MOS tube; the first end of the first capacitor is connected to the power supply, and the second end of the first capacitor is connected to the drain of the seventh MOS tube; the input end of the first inverter is connected to the second end of the first capacitor, and the output end of the first inverter outputs the communication signal.

[0046] It should be understood that the MOS tube provided in the embodiment of the present application is a device that can realize the switching function, and other devices that can realize the function may also be used, such as: bipolar junction transistor (bipolar junction transistor, BJT), which is not limited in the present application.

[0047] To facilitate understanding, a specific example of the structure of the processing unit 101 is given below. Figure 3 A schematic diagram of the structure of a processing unit 101 provided in an embodiment of the present application. Figure 3 In the figure, Q1 can be regarded as the first MOS tube as a PMOS tube, Q2 can be regarded as the second MOS tube as an NMOS tube, Q3 can be regarded as the third MOS tube as a PMOS tube, Q4 can be regarded as the fourth MOS tube as an NMOS tube, and Q5 can be regarded as the fifth MOS tube as an NMOS tube. Q6 can be regarded as the sixth MOS tube as an NMOS tube, Q7 can be regarded as the seventh MOS tube as a PMOS tube, Y1 represents the first inverting unit, and C1 can be regarded as the first capacitor. A is used as the input end of the processing unit 101 to receive the signal input from the input port of the pin control circuit 100, and B is used as the output end of the processing unit 101 to output the communication signal.

[0048] pass Figure 3 When the processing unit 101 shown detects the input signal, A serves as the input terminal to receive the signal sent by the input port. Q3 and Q7 have a pull-up effect. At the initial moment, Q3 is turned off, Q7 is turned on, and the input port is grounded. Since the capacitor voltage cannot change suddenly, the output signal of the output terminal B is a low level. When the input port is connected to a high level (such as greater than 1.4V), Vcc, C1, Q4 and Q5 constitute a charging path for the capacitor C1. C1 is charged. As the charging process proceeds, the input terminal potential of Y1 gradually decreases, and the output signal B corresponds to a high level. After a certain period of time, the power-on function is realized. After the power-on is completed, Q7 is turned off and enters the shutdown state. After Q3 is reset, Q7 is turned on. In order to reduce power consumption, the power consumption of the circuit is determined by Q3, which is about 5nA.

[0049] When A receives a low-level signal and is currently in the shutdown state, the function selection unit has no level output, Q7 is turned on, the potential of the Y1 input terminal is high, Y1 outputs a low-level signal, and the output communication signal is low. When A receives a high-level signal, the output level of the function selection unit changes, at this time Q7 is cut off, Vcc, C1, Q4 and Q5 form a charging path for capacitor C1, and as the charging process proceeds, the potential of the Y1 input terminal gradually decreases. When the negative electrode of C1 decreases to a fixed value, Y1 reverses and outputs a high-level signal, that is, the communication signal changes.

[0050] It should be noted that when the pin input port receives a low-level signal, if it is in a shutdown state, no device in the processing unit is powered on and the circuit consumes no energy, thereby reducing the energy consumption of the pin control circuit.

[0051] 2. Function Control Unit 102

[0052] The function control unit 102 includes: a clock unit, a communication unit, a power on / off unit and a register logic unit; specifically, it can be: a clock unit, a communication unit, a power on / off unit and a register logic unit. The structure of the pin control circuit provided in the embodiment of the present application can be as follows: Figure 3 shown.

[0053] The clock unit is connected to the power on / off unit, the communication unit and the register logic unit, and the function of the clock unit is to generate a clock signal with a preset period, and send the clock signal to the communication unit, the power on / off unit and the register logic unit, so that the communication unit, the power on / off unit and the register logic unit are synchronized based on the clock signal. The preset period can be set according to actual needs, and this application does not limit it here.

[0054] It should be noted that the clock unit can also be a timer set inside the integrated chip, or of course it can also be other devices inside the integrated chip that can achieve the above functions, or a timing device in an external device connected to the integrated chip. This application does not limit this here.

[0055] The clock unit may include an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a second capacitor and a comparator.

[0056] Specifically, the source of the eighth MOS tube is connected to the power supply, the gate of the eighth MOS tube is connected to the second end of the second capacitor, and the drain of the eighth MOS tube is connected to the drain of the ninth MOS tube and the drain of the tenth MOS tube; the gate of the ninth MOS tube is connected to the output end of the comparator, the source of the ninth MOS tube is connected to the first end of the second capacitor and the drain of the eleventh MOS tube; the gate of the tenth MOS tube is connected to the output end of the comparator, the source of the tenth MOS tube is connected to the second end of the second capacitor and the first input end of the comparator; the gate of the eleventh MOS tube is connected to the output end of the comparator, and the source of the eleventh MOS tube is connected to the second end of the second capacitor and the first input end of the comparator; The source of the twelfth MOS tube is connected to the ground line; the drain of the twelfth MOS tube is connected to the second end of the second capacitor, the gate of the twelfth MOS tube is connected to the output end of the comparator, and the source of the twelfth MOS tube is connected to the ground line; the source of the thirteenth MOS tube is connected to the power supply, the gate of the thirteenth MOS tube is connected to the second end of the second capacitor, the drain of the thirteenth MOS tube is connected to the drain of the fourteenth MOS tube and the second input end of the comparator; the gate and drain of the fourteenth MOS tube are connected, and the source of the fourteenth MOS tube is connected to the ground line; the output end of the comparator is connected to the switch unit, the first communication unit and the first register logic unit.

[0057] Among them, the power on / off unit is connected to the processing unit and the register logic unit. The function of the power on / off unit is to receive the communication signal, generate the power on / off signal according to the level value of the communication signal and the duration of the level value, so that the pin can realize the power on / off function.

[0058] Specifically, when it is determined that the switch unit is in the power-on state and the duration of the communication signal being in the low level value is greater than or equal to a preset threshold, a shutdown signal is generated to enable the pin to implement a shutdown function.

[0059] Specifically, when it is determined that the switch unit is in the shutdown state and the duration of the communication signal being at a high level value is greater than or equal to a preset threshold, a power-on signal is generated to enable the pin to implement a power-on function.

[0060] It should be noted that the preset threshold can be set according to the actual situation. For example, the preset threshold can be set to 200 microseconds, and of course it can also be set to other values. The embodiment of the present application does not limit this. The switch unit determines the switch state of the integrated chip according to the communication signal output by the received detection unit. Specifically, when the integrated chip is in the shutdown state, if the signal is a continuous high level (if the high level is maintained for a time greater than or equal to 200us), the power-on signal is set to perform the power-on operation; if the signal is a continuous high level time that is not long enough (such as the high level is maintained for less than 200us), the power-on signal is not set to maintain the shutdown state. When the integrated chip is in the power-on state, if the signal is a continuous low level (such as a time greater than 200us), the power-on signal is reset to enter the shutdown state; if the signal is a continuous high level (the time is long enough such as a time greater than or equal to 200us), the power-on signal is not reset to maintain the power-on state. The switch unit uses nanoampere bias current to ensure low power consumption in the power-on state.

[0061] Among them, the switch unit may include: a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a time detection unit, a first resistor, a second resistor, a second inverter and a third capacitor.

[0062] Specifically, the time detection unit can be a rising / falling edge time detection unit, which is used to detect the duration of high and low values ​​of the level in the communication signal, and its input end receives the communication signal, and the output end of the time detection unit is connected to the gate of the fifteenth MOS tube; the source of the fifteenth MOS tube is connected to the power supply, and the drain of the fifteenth MOS tube is connected to the first resistor and the gate of the nineteenth MOS tube; the drain of the sixteenth MOS tube is connected to the second end of the first resistor and the drain of the seventeenth MOS tube, the gate of the sixteenth MOS tube is connected to the second end of the first capacitor, and the source of the sixteenth MOS tube is connected to the ground line; the gate of the seventeenth MOS tube is connected to the output end of the first inverter, and the source of the seventeenth MOS tube is connected to the ground line; the source of the eighteenth MOS tube is connected to the power supply, The gate of the eighteenth MOS tube is connected to the output end of the first inverter, and the drain of the eighteenth MOS tube is connected to the first end of the second resistor; the drain of the nineteenth MOS tube is connected to the second end of the second resistor and the drain of the twentieth MOS tube, the gate of the nineteenth MOS tube is connected to the first end of the first resistor, and the source of the nineteenth MOS tube is connected to the ground line; the drain of the twentieth MOS tube is connected to the second end of the second resistor, the gate of the twentieth MOS tube is connected to the output end of the first inverter, and the source of the twentieth MOS tube is connected to the ground line; the first end of the third capacitor is connected to the power supply, and the second end of the third capacitor is connected to the second end of the second resistor; the input end of the second inverter is connected to the second end of the second resistor, and the second inverter outputs a switch signal to the function selection unit 103.

[0063] Among them, the communication unit is connected to the processing unit 101 and the register logic unit. The function of the communication unit is to receive the communication signal, and when it is determined that the switch unit is in the power-on state and the level value of the communication signal is a preset level for a duration less than a preset threshold, generate a data transmission signal, and write data to the register logic unit or read data from the register logic unit according to the communication information carried in the communication signal.

[0064] To facilitate understanding, a specific example of the structure of the function control unit 102 is given below. Figure 4 This is a schematic diagram of the structure of a function control unit 102 provided in an embodiment of the present application. Figure 4 In the figure, Q8 can be regarded as the eighth MOS tube, Q9 can be regarded as the ninth MOS tube, Q10 can be regarded as the tenth MOS tube, Q11 can be regarded as the eleventh MOS tube, and so on, Q20 can be regarded as the twentieth MOS tube, C2 can be regarded as the second capacitor, C3 can be regarded as the third capacitor, R1 can be regarded as the first resistor, R2 can be regarded as the second resistor, Y2 can be regarded as the second inverter, Z can be regarded as the time detection unit, and U can be regarded as the comparator. A is used as the input end of the function control unit 102 to receive the communication signal output by the processing unit 101, and B is used as the output end of the function control unit 102 to output the selection signal.

[0065] Figure 4 The function control circuit shown, A as an input terminal, receives the communication signal output by the processing unit 101. When it is determined that the integrated chip where the pin is located is in the power-on state and the low-level duration of the communication signal is less than the preset threshold, according to the communication information carried in the communication signal, write data to the register logic unit or read data from the register unit, and generate a transmission signal, and the data to be transmitted is sent to the function selection unit through the transmission signal to communicate with the function selection unit. If the communication signal is a low-level value, when it is determined that the integrated chip where the pin is located is in the power-on state, and the duration of the low-level value is greater than or equal to the preset threshold, the time detection unit outputs a low-level signal, Y2 is reversed, and it is determined to be converted to a shutdown function, and the shutdown signal is output to enable the pin to realize the shutdown function. If the communication signal is a high-level value, when it is determined that the integrated chip where the pin is located is in the power-off state, and the maintenance time of the high-level value is greater than or equal to the preset threshold, the time detection unit outputs a high-level signal, Y2 is reversed, and it is determined to perform a power-on function, and a power-on signal is generated to enable the pin to realize the power-on function.

[0066] Specifically, the power-on signal and the power-off signal are used to be output to a power-on / off control circuit in the integrated chip, and the power-on / off circuit implements a power-on function or a power-off function through the power-on signal or the power-off signal.

[0067] 3. Function Selection Unit 103

[0068] The function selection unit 103 may include a transmission unit and a storage unit. The transmission unit is connected to the processing unit 101, the function control unit 102 and the storage unit, and is used to receive the data transmission signal sent by the function control unit 102, and write data to the storage unit or read data from the storage unit. The storage unit can be used to perform data writing or data reading operations. The function selection unit 103 can be used to implement data communication with an external device connected to the pin input port.

[0069] Specifically, the storage unit can also be connected to the integrated chip through a communication line to transmit data received through the pin input port to the integrated chip, receive signals sent by the integrated chip to the pin input port, and output them to the pin input port through the transmission unit to enable the integrated chip to communicate with an external device connected to the pin input port, so that the pin can realize the communication function.

[0070] When the communication unit determines that the integrated chip is in the power-on state and the level maintenance time of the communication signal is less than the preset threshold, the communication unit receives the communication signal, and writes data to the register logic unit or reads data from the register logic unit according to the communication information carried in the communication signal, and generates a data transmission signal, which includes data that needs to be transmitted to the function selection unit. The register logic unit is used to perform data writing or data reading operations.

[0071] The transmission unit in the function selection unit receives the data transmission signal sent by the communication unit, and writes the data carried in the data transmission signal into the storage unit, or reads the data from the storage unit and sends it to the driving signal, and then sends it to the pin input port through the driving signal to realize data communication with the external device connected to the pin input port.

[0072] In one example, the communication signals and pin function states are as follows: Figure 5 As shown, when the input pin is in the shutdown state, when the communication signal is at a high level value, and the high level value continues to be greater than or equal to the power-on time, a power-on signal is generated to enable the pin to realize the power-on function. In the power-on state, when the level value of the received communication signal is continuously less than the preset threshold (power-on time or power-off time), the externally connected device establishes data communication with the integrated chip through the pin, and when it is determined that the maintenance time of the low level value of the received communication signal is greater than or equal to the power-off time, the control pin realizes the power-off function. The static power consumption is determined by the power consumption in the detection unit and the power-on and power-off unit, which consumes a total current of about 10nA. The power-on and power-off waveform is as follows Figure 5 shown.

[0073] The pin control circuit in the embodiment of the present invention can cooperate with the single-line communication protocol to realize the communication function, realize the purpose of register control, dynamic adjustment, mass production adjustment, etc. At the same time, in the power-on state, the internal function register is configured in conjunction with the communication function so that this port can be used as a normal input / output (Input / Output, I / O) port, that is, it is switched to a general-purpose input / output (General-purpose input / out, GPIO) interface to realize the general functions of GPIO such as digital / analog, input / output, and can automatically restore the original function after a set time. It can support a wide voltage range and can work normally within the pin level range of 1.8 to 5V. It greatly improves the pin utilization rate, enhances integration, and reduces the layout area and packaging volume.

[0074] Based on the same technical concept, the embodiment of the present application further provides an integrated chip, which includes a plurality of pins and a plurality of the aforementioned pin control circuits 100 .

[0075] The system structure and business scenarios provided in the embodiments of the present application are mainly intended to explain some possible implementation methods of the technical solution of the present application and should not be interpreted as a unique limitation on the technical solution of the present application. A person of ordinary skill in the art can know that with the evolution of the system and the emergence of newer business scenarios, the technical solution provided in the present application can still be applicable to the same or similar technical problems.

Claims

1. A pin control circuit, characterized in that: include: processing unit, function control unit and function selection unit; wherein, The processing unit is connected to the function control unit and the function selection unit, and is used to receive a signal from an input port and generate a communication signal based on the received signal; The function control unit is connected to the function selection unit, and is used to receive the communication signal sent by the processing unit, and generate a power on / off signal or a data transmission signal according to the communication signal; The function selection unit is used to receive the power on / off signal or the data transmission signal, and enable the pin to realize the power on / off function based on the power on / off signal, and enable the pin to realize the data communication function based on the data transmission signal; The function control unit includes: a clock unit, a communication unit, a power on / off unit and a register logic unit; The clock unit is connected to the switch unit, the communication unit and the register logic unit, and is used to generate a clock signal with a preset period, and send the clock signal to the communication unit, the switch unit and the register logic unit, so that the communication unit, the switch unit and the register logic unit are synchronized based on the clock signal; The on / off unit is connected to the processing unit and is used to receive the communication signal and generate an on / off signal according to the level value of the communication signal and the duration of the level value; The communication unit is connected to the processing unit and the register logic unit, and is used to receive the communication signal, and when it is determined that the switch unit is in the power-on state and the level value of the communication signal is a preset level for a duration less than a preset threshold, generates a data transmission signal, and writes data to the register logic unit or reads data from the register logic unit according to the communication information carried in the communication signal; The register logic unit is used to perform data writing or data reading operations.

2. The control circuit according to claim 1, characterized in that: The processing unit includes: a detection module and a driving module; The detection module is connected to the input port of the pin, and is used to detect the signal of the input port and generate a communication signal according to the signal; The driving module is connected to the function selection unit to realize the communication function.

3. The control circuit according to claim 2, characterized in that: The driving module includes: a first MOS tube and a second MOS tube; The source of the first MOS tube is connected to the power supply, the gate of the first MOS tube is connected to the function selection unit, and the drain of the first MOS tube is connected to the drain of the second MOS tube and the input port; The gate of the second MOS tube is connected to the function selection unit, and the source of the second MOS tube is connected to the ground line.

4. The control circuit according to claim 3, characterized in that: The detection module includes: a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a first capacitor and a first inverter; The source of the third MOS tube is connected to the power supply, the gate of the third MOS tube is connected to the function selection unit, and the drain of the third MOS tube is connected to the drain of the fourth MOS tube; The gate of the fourth MOS tube is connected to the input port, and the source of the fourth MOS tube is connected to the drain of the fifth MOS tube; The gate and drain of the fifth MOS tube are connected, and the source of the fifth MOS tube is connected to the ground line; The drain of the sixth MOS tube is connected to the drain of the fifth MOS tube, the gate of the sixth MOS tube is connected to the function selection unit, and the source of the sixth MOS tube is connected to the ground line; The source of the seventh MOS tube is connected to the power supply, the gate of the seventh MOS tube is connected to the function selection unit, and the drain of the seventh MOS tube is connected to the drain of the third MOS tube; The first end of the first capacitor is connected to the power supply, and the second end of the first capacitor is connected to the drain of the seventh MOS transistor; The input end of the first inverter is connected to the second end of the first capacitor, and the output end of the first inverter outputs the communication signal.

5. The control circuit according to claim 4, characterized in that: The switch unit includes: a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a time detection unit, a first resistor, a second resistor, a second inverter and a third capacitor; The input end of the time detection unit receives the communication signal, and the output end of the time detection unit is connected to the gate of the fifteenth MOS tube; The source of the fifteenth MOS tube is connected to the power supply, and the drain of the fifteenth MOS tube is connected to the first resistor and the gate of the nineteenth MOS tube; The drain of the sixteenth MOS tube is connected to the second end of the first resistor and the drain of the seventeenth MOS tube, the gate of the sixteenth MOS tube is connected to the second end of the first capacitor, and the source of the sixteenth MOS tube is connected to the ground line; The gate of the seventeenth MOS tube is connected to the output end of the first inverter, and the source of the seventeenth MOS tube is connected to the ground line; The source of the eighteenth MOS tube is connected to the power supply, the gate of the eighteenth MOS tube is connected to the output end of the first inverter, and the drain of the eighteenth MOS tube is connected to the first end of the second resistor; The drain of the nineteenth MOS tube is connected to the second end of the second resistor and the drain of the twentieth MOS tube, the gate of the nineteenth MOS tube is connected to the first end of the first resistor, and the source of the nineteenth MOS tube is connected to the ground line; The drain of the 20th MOS transistor is connected to the second end of the second resistor, the gate of the 20th MOS transistor is connected to the output end of the first inverter, and the source of the 20th MOS transistor is connected to the ground line; A first end of the third capacitor is connected to the power supply, and a second end of the third capacitor is connected to the second end of the second resistor; The input end of the second inverter is connected to the second end of the second resistor, and the second inverter outputs a power-on / off signal to the function selection unit.

6. The control circuit according to claim 3, characterized in that: The clock unit includes: an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a second capacitor and a comparator; The source of the eighth MOS tube is connected to the power supply, the gate of the eighth MOS tube is connected to the second end of the second capacitor, and the drain of the eighth MOS tube is connected to the drain of the ninth MOS tube and the drain of the tenth MOS tube; The gate of the ninth MOS tube is connected to the output end of the comparator, and the source of the ninth MOS tube is connected to the first end of the second capacitor and the drain of the eleventh MOS tube; The gate of the tenth MOS transistor is connected to the output end of the comparator, and the source of the tenth MOS transistor is connected to the second end of the second capacitor and the first input end of the comparator; The gate of the eleventh MOS tube is connected to the output end of the comparator, and the source of the eleventh MOS tube is connected to the ground line; The drain of the twelfth MOS tube is connected to the second end of the second capacitor, the gate of the twelfth MOS tube is connected to the output end of the comparator, and the source of the twelfth MOS tube is connected to the ground line; The source of the thirteenth MOS tube is connected to the power supply, the gate of the thirteenth MOS tube is connected to the second end of the second capacitor, and the drain of the thirteenth MOS tube is connected to the drain of the fourteenth MOS tube and the second input end of the comparator; The gate and drain of the fourteenth MOS tube are connected, and the source of the fourteenth MOS tube is connected to the ground line; The output end of the comparator is connected to the switch unit, the communication unit and the register logic unit.

7. An integrated chip, characterized in that: The invention comprises the pin control circuit according to any one of claims 1 to 6.

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