Multilayer electronic device including high precision inductor

Abstract

A multilayer electronic device may include a plurality of dielectric layers, and a signal path having an input and an output. An inductor may include a conductive layer formed on one of the plurality of dielectric layers, and may be electrically connected to the signal path at a first location and to at least one of the signal path or ground at a second location. The inductor may include a periphery, the periphery including a first straight edge facing outward in a first direction, and a second straight edge parallel to the first straight edge and facing outward in the first direction. The second straight edge may be offset from the first straight edge by an offset distance, the offset distance being less than 500 microns and less than about 90% of a first width of the inductor in the first direction at the first straight edge.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application Serial No. 62 / 782,501 filed on December 20, 2018 and U.S. Provisional Application Serial No. 62 / 850,106 filed on May 20, 2019, the entire contents of which are incorporated by reference into this application. Background Art

[0003] Multilayer electronic devices often include inductors. For example, a multilayer filter often includes one or more inductors that are designed to provide a specific inductance value. However, precise control of the inductance of such an inductor can be difficult to achieve because it involves precisely controlling the size of the inductor.

[0004] Filtering of high frequency signals, such as filtering of high frequency radio signal communications, has become increasingly popular recently. The demand for increasing data transmission speeds for wireless connections has driven the need for high frequency components, including components configured to operate at high frequencies including 5G spectrum frequencies. High frequency applications typically require inductors with very low but precise inductance values. Achieving smaller inductance values ​​requires smaller inductors, which further increases the difficulty associated with precisely controlling the inductance value. Therefore, multilayer filters including high precision inductors would be welcome in the art. Summary of the invention

[0005] According to one embodiment of the present disclosure, a multilayer electronic device may include a plurality of dielectric layers and a signal path having an input and an output. The multilayer electronic device may include an inductor, the inductor including a conductive layer covering one of the plurality of dielectric layers. The inductor may be electrically connected to the signal path at a first position and electrically connected to at least one of the signal path or ground at a second position. The inductor may have a periphery, the periphery including a first straight edge facing outward in a first direction, and a second straight edge parallel to the first straight edge and facing outward in the first direction. The second straight edge may be offset from the first straight edge by an offset distance, the offset distance being less than about 500 microns and less than about 90% of the first width of the inductor at the first straight edge in the first direction.

[0006] According to another embodiment of the present disclosure, a method for forming a multilayer electronic device may include providing a plurality of dielectric layers and forming a plurality of conductive layers on at least some of the plurality of dielectric layers to form a signal path having an input and an output. The signal path may include an inductor electrically connected to the signal path at a first position and electrically connected to at least one of the signal path or ground at a second position. The inductor may have a periphery including a first straight edge facing outward in a first direction, and a second straight edge parallel to the first straight edge and facing outward in the first direction. The second straight edge may be offset from the first straight edge by an offset distance that is less than about 500 microns and less than about 90% of a first width of the inductor at the first straight edge in the first direction.

[0007] According to another embodiment of the present disclosure, a method for designing an inductor for a multilayer electronic device may include: selecting an effective length and width for the inductor based on a target inductance value for the inductor. The method may include: setting the size of an offset distance associated with a protrusion of the inductor. The offset distance may be between a first straight edge of the inductor periphery and a second straight edge of the inductor periphery. The offset distance may be less than 500 microns and less than about 90% of a first width of the inductor at the first straight edge in a first direction. The first straight edge may face outward in the first direction, and the second straight edge may be parallel to the first straight edge and may face outward in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the remainder of this specification, a full and enabling disclosure of the invention, including the best mode thereof, is more particularly set forth to one of ordinary skill in the art, and with reference to the accompanying drawings, in which:

[0009] Figure 1 is a simplified schematic diagram of a bandpass filter according to aspects of the present disclosure;

[0010] Figure 2 is a simplified schematic diagram of another bandpass filter according to aspects of the present disclosure;

[0011] Figure 3A and Figure 3B is a perspective view of an exemplary bandpass filter according to aspects of the present disclosure;

[0012] Figure 3C yes Figure 3A and Figure 3B A side view of the filter;

[0013] FIG. 4A to FIG. 4E yes Figure 3A and Figure 3B A series of sequential filter top views of a filter of the invention, wherein additional layers are shown in each sequential view;

[0014] Figure 5A The above reference FIG. 3A to FIG. 4E a top view of a third inductor of the described filter;

[0015] Figure 5B is a top view of an embodiment of an inductor including a pair of protrusions according to aspects of the present disclosure;

[0016] Figure 5C is a top view of an embodiment of an inductor including a protrusion according to aspects of the present disclosure;

[0017] Figure 5D is a top view of another embodiment of an inductor including a pair of protrusions according to aspects of the present disclosure;

[0018] Fig. 6A and Figure 6B is a perspective view of another embodiment of a multilayer filter according to aspects of the present disclosure;

[0019] Figure 6C yes Fig. 6A and Figure 6B A side view of the filter;

[0020] FIG. 7A to FIG. 7D yes Fig. 6A and Figure 6B A series of sequential top views of a filter of FIG. 1 , wherein additional layers are shown in each sequential view;

[0021] Fig. 8A is a perspective view of another embodiment of a multilayer filter according to aspects of the present disclosure;

[0022] Figure 8B yes Fig. 8A A side view of the filter;

[0023] FIG. 9A to FIG. 9D yes Fig. 8A and Figure 8B A series of sequential top views of a filter of FIG. 1 , wherein additional layers are shown in each sequential view;

[0024] Fig. 10A is a perspective view of another embodiment of a multilayer filter according to aspects of the present disclosure;

[0025] Fig. 10B yes Fig. 10A A side view of the filter;

[0026] FIG. 11A to FIG. 11D yes Fig. 10A and Fig. 10B A series of sequential top views of a filter of FIG. 1 , wherein additional layers are shown in each sequential view;

[0027] Fig.12 is a test data graph including measured insertion loss values ​​and return loss values ​​for a filter constructed according to aspects of the present disclosure;

[0028] Fig.13 is a test data graph including measured insertion loss values ​​and return loss values ​​for a filter constructed according to aspects of the present disclosure;

[0029] Fig.14 is a test data graph including measured insertion loss values ​​and return loss values ​​for a filter constructed according to aspects of the present disclosure;

[0030] Fig.15 is a simulated data graph including insertion loss values ​​and return loss values ​​from a computer analysis of a filter according to aspects of the present disclosure;

[0031] Fig.16 is a simulated data graph including insertion loss values ​​and return loss values ​​from a computer analysis of a filter according to aspects of the present disclosure;

[0032] Fig.17 is a graph of simulated data including insertion loss values ​​and return loss values ​​from a computer analysis of a filter according to aspects of the present disclosure; and

[0033] Fig.18 is a perspective view of a test assembly including a filter according to aspects of the present disclosure.

[0034] Repeat use of reference characters in the present specification and drawings is intended to represent the same or analogous features or elements of the present disclosure. DETAILED DESCRIPTION

[0035] Those skilled in the art will appreciate that the present discussion is merely a description of exemplary embodiments and is not intended to limit the broader aspects of the present disclosure, which are implemented in the exemplary configurations.

[0036] In general, the present disclosure relates to a multilayer electronic device including a plurality of dielectric layers and a signal path having an input and an output. The multilayer electronic device includes an inductor including a conductive layer formed on one of the plurality of dielectric layers. The inductor can be electrically connected to the signal path at a first location and electrically connected to at least one of the signal path or ground at a second location.

[0037] The inductor may have an outer periphery including a first straight edge facing outward in a first direction, and a second straight edge parallel to the first straight edge and facing outward in the first direction. The second straight edge may be offset from the first straight edge by an offset distance that is less than about 500 microns and less than about 90% of a first width of the inductor at the first straight edge in the first direction.

[0038] The protrusion may be associated with an offset distance. The protrusion may slightly increase the average width of the inductor and reduce the inductance of the inductor. Inductance is generally proportional to the length of the inductor, but inversely proportional to the width of the inductor. In other words, the inductance may be proportional to the ratio of the length of the inductor element to the average width. Therefore, small adjustments to the width and length of the inductor element may be used to finely adjust the inductance. Therefore, such a protrusion may provide a more precise adjustment of the inductance of the inductor than adjusting the entire width of the inductor.

[0039] The multilayer filter may include one or more dielectric materials. In some embodiments, one or more dielectric materials may have a low dielectric constant. The dielectric constant may be less than about 100, less than about 75 in some embodiments, less than about 50 in some embodiments, less than about 25 in some embodiments, less than about 15 in some embodiments, and less than about 5 in some embodiments. For example, in some embodiments, the dielectric constant may range from about 1.5 to 100, from about 1.5 to about 75 in some embodiments, and from about 2 to about 8 in some embodiments. The dielectric constant may be determined according to IPCTM-6502.5.5.3 at an operating temperature of 25°C and a frequency of 1 MHz. The dielectric loss tangent may range from about 0.001 to about 0.04, and in some embodiments from about 0.0015 to about 0.0025.

[0040] In some embodiments, one or more dielectric materials may include an organic dielectric material. Example organic dielectrics include polyphenylene ether (PPE) based materials such as LD621 from Polyclad and the N6000 series from Park / Nelco, liquid crystal polymers (LCPs) such as those from Rogers or WL Gore & Associates, Inc., hydrocarbon composites such as the 4000 series from Rogers, and epoxy-based laminates such as the N4000 series from Park / Nelco. For example, examples include epoxy resin system N4000-13, bromide-free materials laminated to LCP, organic layers with high-K materials, unfilled high-K organic layers, Rogers 4350, Rogers 4003 materials and other thermoplastic materials, such as polyphenylene sulfide resin, polyethylene terephthalate resin, polybutylene terephthalate resin, polysulfide resin, polyether ketone resin, polytetrafluoroethylene resin and grafted resin, or similar low dielectric constant, low loss organic materials.

[0041] In some embodiments, the dielectric material can be a ceramic filled epoxy resin. For example, the dielectric material can include an organic compound such as a polymer (e.g., epoxy resin) and can contain particles of a ceramic dielectric material such as barium titanate, calcium titanate, zinc oxide, aluminum oxide with low fire glass, or other suitable ceramic or glass bonding materials.

[0042] However, other materials may be used, including N6000, epoxy resin system N4000-13, bromine-free materials laminated to LCP, organic layers with high-K materials, unfilled high-K organic layers, Rogers 4350, Rogers 4003 materials (from Rogers Corporation), and other thermoplastic materials, such as hydrocarbons, Teflon, FR4, epoxy resins, polyamides, polyimides and acrylates, polyphenylene sulfide resins, polyethylene terephthalate resins, polybutylene terephthalate resins, polysulfide resins, polyether ketone resins, polytetrafluoroethylene resins, BT resin composites (e.g., Speedboard C), thermosetting plastics (e.g., Hitachi MCL-LX-67F) and grafted resins, or similar low dielectric constant, low loss organic materials.

[0043] In addition, in some embodiments, non-organic dielectric materials including ceramics, semiconductors or insulating materials may be used, such as but not limited to barium titanate, calcium titanate, zinc oxide, aluminum oxide with low-fire glass or other suitable ceramic or glass bonding materials. Alternatively, the dielectric material may be an organic compound, such as epoxy resin (with or without mixed ceramics, with or without glass fiber) commonly used as a circuit board material or other plastics commonly used as dielectrics. In these cases, the conductor is usually a copper foil that is chemically etched to provide a pattern. In further embodiments, the dielectric material may include a material with a relatively high dielectric constant (K), such as one of NPO (COG), X7R, X5R, X7S, Z5U, Y5V and strontium titanate. In this example, the dielectric material may have a dielectric constant greater than 100, such as a dielectric constant in the range of about 100 to about 4000, and in some embodiments a dielectric constant in the range of about 1000 to about 3000.

[0044] One or more conductive layers may be formed directly on the dielectric layer. Alternatively, a coating or intermediate layer may be positioned between the conductive layer and the corresponding dielectric layer. As used herein, "formed on" may refer to a conductive layer formed directly on a dielectric layer, or a conductive layer overlying a dielectric layer with an intermediate layer or coating between the dielectric layer and the conductive layer.

[0045] The conductive layer may include a variety of conductive materials. For example, the conductive layer may include copper, nickel, gold, silver or other metals or alloys.

[0046] In some embodiments, a multilayer electronic device may include a signal path having an input and an output. The signal path may include one or more conductive layers overlying one or more of the dielectric layers and connected to one or more vias.

[0047] Vias can be formed in one or more dielectric layers. For example, a via can electrically connect a conductive layer on one dielectric layer to a conductive layer on another dielectric layer. Vias can include a variety of conductive materials such as copper, nickel, gold, silver, or other metals or alloys. Vias can be formed by drilling (e.g., mechanical drilling, laser drilling, etc.) through holes and electroplating the through holes with conductive materials, such as using chemical plating or seeded copper. The vias can be filled with conductive material so that a solid column of conductive material is formed. Alternatively, the inner surface of the through hole can be electroplated so that the via is hollow.

[0048] A multilayer electronic device may include an inductor. The inductor may include a conductive layer formed on one of a plurality of dielectric layers. The inductor may be electrically connected to a signal path at a first location and electrically connected to at least one of the signal path or a ground at a second location. For example, the inductor may form a portion of the signal path or may be connected between the signal path and the ground.

[0049] In some embodiments, the inductor may include at least one corner. The corner may have an angle greater than about 20 degrees (e.g., 90 degrees). The inductor may have one to nine corners, or more, and in some embodiments the inductor may have less than six corners, in some embodiments less than four corners, in some embodiments less than three corners, and in some embodiments less than two corners. In some embodiments, the inductor may not have any corners. In some embodiments, the inductor may define a complete "loop" or less. For example, the inductor may define less than half a "loop".

[0050] In some embodiments, at least some of the dielectric layers may have a thickness of less than about 180 microns, in some embodiments less than about 120 microns, in some embodiments less than about 100 microns, in some embodiments less than about 80 microns, in some embodiments less than 60 microns, in some embodiments less than about 50 microns, in some embodiments less than about 40 microns, in some embodiments less than about 30 microns, and in some embodiments less than about 20 microns. For example, a conductive layer of an inductor may be formed on a dielectric layer having a thickness of less than about 180 microns, in some embodiments less than about 100 microns, and in some embodiments less than about 80 microns.

[0051] One or more vias may be formed in the dielectric layer. The vias may electrically connect different conductive layers. For example, a via may be formed in a dielectric layer, on which a conductive layer of an inductor is formed. Such a via may connect the inductor to another portion of the filter, such as to a portion of a signal path or to ground (e.g., a ground plane). In some embodiments, the length of such a via in the Z direction may be equal to the thickness of the dielectric layer forming such a via. For example, the length of such a via may be less than about 180 microns, less than about 100 microns in some embodiments, and less than about 80 microns in some embodiments.

[0052] In some embodiments, a series of vias and intermediate layers can be arranged vertically to connect the inductor to another conductive layer such as a ground plane or a portion of a signal path. The total vertical length of the series of vias and intermediate layers in the Z direction can range from about 10 microns to about 500 microns, in some embodiments from about 30 microns to about 300 microns, in some embodiments from about 40 microns to about 200 microns, and in some embodiments from about 60 microns to about 150 microns.

[0053] The vias can have a variety of suitable widths. For example, in some embodiments, the width of the vias can range from about 20 microns to about 200 microns, in some embodiments from about 40 microns to about 180 microns, in some embodiments from about 60 microns to about 140 microns, and in some embodiments from about 80 microns to about 120 microns.

[0054] In some embodiments, the multilayer electronic device can be configured as a multilayer filter. The multilayer filter can be configured to operate at high frequencies. The multilayer filter can have a characteristic frequency greater than 6 GHz (e.g., a low-pass frequency, a high-pass frequency, an upper limit of a bandpass frequency, or a lower limit of a bandpass frequency). In some embodiments, the characteristic frequency that the filter has can be greater than about 6 GHz, greater than about 10 GHz in some embodiments, greater than about 15 GHz in some embodiments, greater than about 20 GHz in some embodiments, greater than about 25 GHz in some embodiments, greater than about 30 GHz in some embodiments, greater than about 35 GHz in some embodiments, greater than about 40 GHz in some embodiments, greater than about 45 GHz in some embodiments, greater than about 50 GHz in some embodiments, greater than about 60 GHz in some embodiments, greater than about 70 GHz in some embodiments, and greater than about 80 GHz in some embodiments.

[0055] The multilayer filter can exhibit excellent performance characteristics, such as low insertion loss for frequencies within the passband frequency range of the multilayer filter. For example, the average insertion loss for frequencies within the passband frequency range can be greater than -15dB, greater than -10dB in some embodiments, greater than -5dB in some embodiments, and greater than -2.5dB or more in some exemplary embodiments.

[0056] In addition, the multilayer filter can exhibit excellent suppression of frequencies outside the passband frequency range. In some embodiments, the insertion loss for frequencies outside the passband frequency range can be less than about -15dB, in some embodiments less than about -25dB, in some embodiments less than about -35dB, and in some embodiments less than about -40dB.

[0057] In addition, the multilayer filter can exhibit a steep roll-off from the passband frequency range to frequencies outside the passband. For example, for frequencies immediately outside the passband frequency range, the insertion loss can decrease at a rate of about 0.1 dB / MHz, in some embodiments at a rate greater than about 0.2 dB / MHz, in some embodiments at a rate greater than about 0.3 dB / MHz, and in some embodiments at a rate greater than about 0.4 dB / MHz.

[0058] The multilayer filter can also exhibit consistent performance characteristics (e.g., insertion loss, return loss, etc.) over a wide temperature range. In some embodiments, the insertion loss of the multilayer filter can vary by less than 5 dB or less over a large temperature range. For example, the multilayer filter can exhibit a first insertion loss at about 25°C and a first frequency. The multilayer filter can exhibit a second insertion loss at a second temperature and about a first frequency. The temperature difference between the first temperature and the second temperature can be about 70°C or higher, about 60°C or higher in some embodiments, about 50°C or higher in some embodiments, about 30°C or higher in some embodiments, and about 20°C or higher in some embodiments. As an example, the first temperature can be 25°C and the second temperature can be 85°C. As another example, the first temperature can be 25°C and the second temperature can be -55°C. The difference between the second insertion loss and the first insertion loss can be about 5 dB or less, in some embodiments about 2 dB or less, in some embodiments about 1 dB or less, in some embodiments about 0.75 dB or less, in some embodiments about 0.5 dB or less, and in some embodiments about 0.2 dB or less.

[0059] However, it should be understood that in other embodiments, the multilayer electronic device can be any suitable type of device including an inductor. For example, the multilayer electronic device can be a multilayer inductor, a multilayer inductor array, a multilayer transformer (eg, a balun), etc.

[0060] In some embodiments, the device can have an overall length ranging from about 0.5 mm to about 30 mm, in some embodiments ranging from about 1 mm to about 15 mm, and in some embodiments ranging from about 2 mm to about 8 mm.

[0061] In some embodiments, the device can have an overall width ranging from about 0.2 mm to about 20 mm, in some embodiments ranging from about 0.5 mm to about 15 mm, in some embodiments ranging from about 1 mm to about 10 mm, and in some embodiments ranging from about 2 mm to about 8 mm.

[0062] The device can be generally low profile or thin. For example, in some embodiments, the device can have a total thickness ranging from about 100 microns to about 2 mm, in some embodiments a total thickness ranging from about 150 microns to about 1 mm, and in some embodiments a total thickness ranging from about 200 microns to about 300 microns.

[0063] Regardless of the specific configuration employed, the inventors have discovered that by selectively controlling the shape of the conductive layers of an inductor of a multilayer electronic device, precise control of the inductance of the inductor can be achieved. More specifically, one or more protrusions can be used to finely adjust the average width of the inductor. The protrusions can provide excellent control of the ratio of the length to the average width of the inductor, which allows for fine control of the inductance value of the inductor.

[0064] Multilayer electronic devices may include a conductive layer. The conductive layer may be formed using a variety of suitable techniques. A subtractive process, a semi-additive process, or a fully additive process may be used with a panel or pattern plating of a conductive material, followed by a printing and etching step to define a patterned conductive layer. The conductive layer may be formed using photolithography, electroplating (e.g., electrolysis), sputtering, vacuum deposition, printing, or other techniques. For example, a thin layer of conductive material (e.g., foil) may be adhered (e.g., laminated) to the surface of a dielectric layer. A mask and photolithography may be used to selectively etch a thin layer of conductive material to produce a desired pattern of conductive material on the surface of a dielectric material.

[0065] Any such process may achieve limited resolution. "Minimum line width" may be defined as the smallest feature size that can be accurately produced by the process employed. In some embodiments, the minimum line width may be about 100 microns or less, in some embodiments, about 75 microns or less, in some embodiments, about 50 microns or less, in some embodiments, about 20 microns or less, in some embodiments, about 10 microns or less, and in some embodiments, about 5 microns or less. "Minimum area unit" may be defined as the square of the minimum line width. The minimum area unit may be about 0.01 mm. 2 or less, in some embodiments about 0.005 mm 2 or less, in some embodiments about 0.0025 mm 2 or less, and in some embodiments about 0.0001 mm 2 or smaller.

[0066] In some embodiments, short and / or wide inductors may be used to achieve very low inductance values. Such low inductance values ​​may be desirable for high frequency applications. The ratio of length to average width may be defined as the length of the inductor divided by the average width of the inductor. In some embodiments, the ratio of length to average width may be less than about 60, in some embodiments less than about 20, in some embodiments less than about 10, in some embodiments less than about 8, in some embodiments less than about 6, in some embodiments less than about 4, in some embodiments less than about 2, in some embodiments less than about 1, and in some embodiments less than about 0.5.

[0067] The inductor may have an average width of less than about 1000 microns, in some embodiments less than about 500 microns, in some embodiments less than about 300 microns, in some embodiments less than about 200 microns, and in some embodiments less than about 100 microns.

[0068] In some embodiments, the inductor may have an effective length between the first position and the second position. The effective length may be defined as the length along the conductive layer between the first position and the second position. For example, the effective length may be equal to the sum of the lengths of the respective straight line portions (e.g., in the XY plane) of the inductor connected between the first position and the second position. The effective length of the inductor may be less than about 5 mm, less than about 3 mm in some embodiments, less than about 2 mm in some embodiments, less than about 1 mm in some embodiments, less than about 800 microns in some embodiments, less than about 500 microns in some embodiments, less than about 300 microns in some embodiments, less than about 200 microns in some embodiments, and less than about 100 microns in some embodiments.

[0069] The inductor may include a feature (e.g., a protrusion) that slightly increases the width of the inductor, which may slightly reduce the inductance of the inductor. More specifically, the inductor may have a periphery that includes a first straight edge facing outward in a first direction, and a second straight edge parallel to the first straight edge and facing outward in the first direction. The second straight edge may be offset from the first straight edge by an offset distance. The protrusion may be formed by offsetting the second straight edge from the first straight edge.

[0070] The offset distance may be less than about 500 microns, in some embodiments less than about 400 microns, in some embodiments less than about 300 microns, in some embodiments less than about 200 microns, in some embodiments less than about 100 microns, in some embodiments less than about 75 microns, and in some embodiments less than about 50 microns. The offset distance may be about 8 minimum line widths or less, in some embodiments about 4 minimum line widths or less, in some embodiments about 2 minimum line widths or less, and in some embodiments about 1 minimum line width.

[0071] The offset distance may be about 90% or less, in some embodiments 80% or less, in some embodiments 70% or less, in some embodiments 60% or less, in some embodiments 50% or less, in some embodiments 40% or less, in some embodiments 30% or less, in some embodiments 20% or less, in some embodiments 10% or less, in some embodiments 5% or less, and in some embodiments 2% or less of a first width of the inductor at the first straight edge in the first direction. The protrusion may reduce the ratio of the length to the average width of the inductor by 30% or less, in some embodiments 20% or less, in some embodiments 10% or less, in some embodiments 5% or less, and in some embodiments 2% or less.

[0072] Thus, the ratio of the second width of the inductor at the second straight edge to the first width of the inductor at the first straight edge can be less than about 1.9, in some embodiments less than about 1.8, in some embodiments less than about 1.7, in some embodiments less than about 1.6, in some embodiments less than about 1.5, in some embodiments less than about 1.4, in some embodiments less than about 1.3, in some embodiments less than about 1.2, in some embodiments less than about 1.1, in some embodiments less than about 1.05, and in some embodiments less than about 1.02. In some embodiments, the ratio of the second width of the inductor at the second straight edge to the first width of the inductor at the first straight edge can be greater than about 1.02, in some embodiments greater than about 1.05, in some embodiments greater than about 1.1, and in some embodiments greater than about 1.2. Such dimensions can allow the protrusion to finely adjust the width of the inductor at the protrusion, thereby finely adjusting the inductance of the inductor.

[0073] In some embodiments, the protrusion or tab can have an effective length of about 70 microns or greater, in some embodiments greater than about 100 microns, in some embodiments greater than about 120 microns, in some embodiments greater than about 150 microns, in some embodiments greater than about 200 microns, and in some embodiments greater than about 220 microns.

[0074] In some embodiments, the inductor may include a plurality of protrusions. For example, the inductor may include a pair of protrusions. The pair of protrusions may be symmetrical about a centerline of the inductor, the centerline extending from a first position to a second position along the inductor. In some embodiments, the pair of protrusions may be symmetrical about a transverse centerline.

[0075] The width discontinuous edge may extend between the first straight edge and the second straight edge. The width discontinuous edge may be perpendicular to the first straight edge and the second straight edge. The width discontinuous edge may be spaced apart from a corner of the longitudinal centerline of the inductor by at least about 30 microns, in some embodiments at least 50 microns, in some embodiments at least 80 microns, in some embodiments at least 100 microns, in some embodiments at least 200 microns, in some embodiments at least 300 microns, in some embodiments at least 500 microns.

[0076] I. Multilayer Filter

[0077] Figure 1 1 is a simplified schematic diagram of a multilayer filter 100 according to aspects of the present disclosure. The filter 100 may include one or more inductors 102, 104, 106 and one or more capacitors 108, 110, 112. The input voltage (at Figure 1 V i ) can be input to the filter 100, and the output voltage (in Figure 1 V o denoted) can be output by the filter 100. The bandpass filter 100 can significantly reduce low frequencies and high frequencies while allowing frequencies within the passband frequency range to be transmitted substantially unaffected by the filter 100. It should be understood that the simplified filter 100 described above is only a simplified example of a bandpass filter, and aspects of the present disclosure can be applied to more complex bandpass filters. In addition, aspects of the present disclosure can be applied to filters including other types such as low-pass filters or high-pass filters.

[0078] Figure 2 2 is a schematic diagram of an exemplary embodiment of a bandpass filter 200 according to aspects of the present disclosure. A signal path 201 may be defined between an input 202 and an output 204 of the filter 200. An input voltage (at Figure 1 V i denoted) can be input to the filter 200 between the input 202 of the filter 200 and ground 206. The output voltage (at Figure 1 V o denoted) can be output by the filter 200 between the output 204 and the ground 206.

[0079] The filter 200 may include a first inductor 208 and a first capacitor 210 electrically connected in parallel to each other. The first inductor 208 and the first capacitor 210 may be electrically connected between the signal path 201 and the ground 206. The filter 200 may include a second inductor 212 and a second capacitor 214 electrically connected in parallel to each other. The second inductor 212 and the second capacitor 214 may be connected in series with the signal path 201 (e.g., may form a portion of the signal path 201). The filter 200 may include a third inductor 210 and a third capacitor 214 electrically connected in parallel to each other. The third inductor 210 and the third capacitor 214 may be electrically connected between the signal path 201 and the ground 206. The third inductor 210 and the third capacitor 214 may be connected in series with the signal path 201 (e.g., may form a portion of the signal path 201). The filter 200 may include a fourth inductor 220 and a fourth capacitor 222 electrically connected in parallel to each other. The fourth inductor 220 and the fourth capacitor 222 may be electrically connected between the signal path 201 and the ground 206 .

[0080] The inductance values ​​of inductors 208, 212, 216, 220 and the capacitance values ​​of capacitors 210, 214, 218, 222 may be selected to produce a desired passband frequency range for bandpass filter 200. Bandpass filter 200 may significantly reduce frequencies outside of the passband frequency range while allowing frequencies within the passband frequency range to pass through filter 200 substantially unaffected.

[0081] Figure 3A and Figure 3B is a perspective view of an example bandpass filter 300 according to aspects of the present disclosure. Figure 3C yes Figure 3A and Figure 3B A side view of the filter 300 is shown. FIG. 3A to FIG. 3C , the bandpass filter 300 may include multiple dielectric layers (transparent for clarity). Figure 3C, a first dielectric layer 304, a second dielectric layer 306, and a third dielectric layer 308 may be stacked to form a monolithic structure. The filter 300 may be mounted to a mounting surface 302 such as a printed circuit board. Conductive layers 303, 305, 307, 309 may be formed on dielectric layers 304, 306, 308. Conductive layer 303 may be formed on the bottom surface of the first dielectric layer 304. Conductive layers 305, 307 may be formed on the top and bottom surfaces of the second dielectric layer 306, respectively. Grounding may include a ground plane 312 exposed and / or terminated along the bottom surface of the filter 300 (the bottom surface of the conductive layer 303). The mounting surface may include one or more terminals 310 for connecting to the ground plane 312.

[0082] FIG. 4A to FIG. 4E 3 is a series of sequential top views of filter 300, wherein additional layers are shown in each figure. More specifically, Figure 4A A mounting surface 302 and a first conductive layer 303 are shown. Figure 4B A ground plane 312 formed on the bottom surface of the first dielectric layer 304 is shown. Figure 4C Additionally shown is a conductive layer 305 formed on a top surface of the first dielectric layer 304 . Figure 4D Additionally shown is a conductive layer 307 formed on the second dielectric layer 306 . Figure 4E A conductive layer 309 is shown formed on the third layer 308. The dielectric layers 304, 306, 308 are transparent to illustrate the relative repositioning of the various patterned conductive layers 303, 305, 307, 309.

[0083] The bandpass filter 300 may include a signal path 316 having an input 318 and an output 320. The signal path 316 may electrically connect the input 318 and the output 320. More specifically, the signal path 316 may include a plurality of dielectric layers and / or vias formed in and on the plurality of dielectric layers 304, 306, 308 and electrically connected between the input 318 and the output 320. The signal path 316 may include one or more vias 322 that may electrically connect the input 318 to an intermediate conductive layer 324 disposed between the first layer 304 and the second layer 306. The signal path 316 may include one or more vias 326 that electrically connect the intermediate layer 324 to a conductive layer 328 formed on the second dielectric layer 306.

[0084] The first capacitor may be formed between a portion 336 of the signal path 316 formed on the upper surface of the second layer 360 and a conductive layer 330 formed on the lower surface of the second layer 306 of dielectric material. The conductive layer 330 may be electrically connected to the ground plane 312. The first capacitor of the filter 300 may correspond to Figure 2 The first capacitor 210 of the circuit diagram 200. The conductive layer 330 can be capacitively coupled with the portion 336 of the signal path 316. The conductive layer 330 can be spaced apart from the portion 336 of the signal path 316 in the Z direction. The conductive layer 330 can be electrically connected to the ground plane 312 through one or more vias 334.

[0085] The first capacitor may be insensitive to relative misalignment of the electrodes of the first capacitor, which may be described as "self-aligning". Figure 4D As best seen in , portion 336 of signal path 316 can generally be smaller in size than conductive layer 330 of first capacitor (e.g., in the X and Y directions). Additionally, portion 336 of signal path 316 can define connections in the XY plane with other elements and other portions of signal path 316. Such connections can be sized such that slight misalignment in the X or Y directions does not change the capacitive area of ​​the first capacitor. More specifically, the size of the effective overlap area (e.g., in the XY plane) between conductive layer 330 and portion 336 of signal path 316 can be insensitive to slight misalignment of second layer 304 and third layer 306 in the X or Y directions.

[0086] For example, portion 336 of signal path 316 may include tab 337 (e.g., extending in the X direction) having a width (e.g., in the Y direction) equal to a width (e.g., in the Y direction) of connector portion 338 on an opposite side of portion 336. Similarly, connection 340 may extend from an opposite side of portion 336 (e.g., in the Y direction) that may have an equal width. As a result, relative misalignment in the Y direction may not change the overlap area between conductive layer 330 and portion 336 of signal path 316.

[0087] The filter 300 may include a first inductor 342 electrically connected to the signal path 316 and the ground plane 312. The first inductor 342 of the filter 300 may correspond to Figure 2 The first inductor 342 may be connected to the portion 336 of the signal path 316 that forms the first capacitor via the connector portion 338. The first inductor 342 may be electrically connected to the ground plane 312 via one or more vias 344 (best seen at Figure 3B ).

[0088] The signal path 316 of the filter 300 may include a second inductor 346, which may correspond to Figure 2 The second inductor 212 of the circuit diagram 200. The second inductor 346 can be formed on the third layer 308 (best seen at Figure 3C). The second inductor 346 may be electrically connected to the signal path 316 at each of the first location 349 and the second location 351. In other words, the second inductor 346 may form a portion of the signal path 316 between the input 318 and the output 320.

[0089] One or more vias 348 may connect the second inductor 346 to a portion 354 of the signal path 316 on the second layer 306 at a first location 349 (best seen at Figure 3B , Figure 4D and Figure 4E ). One or more vias 348 may connect the first inductive element 346 to each of the portions 369 of the signal path 316 on the top surface of the second layer 306 and to the conductive layer 352 on the bottom surface of the second layer 306 (the second layer forms a second capacitor with the portion 354 of the signal path 316, as described below) at the second location 351. Figure 3A and Figure 4E , the inductor 346 may have four corners. Therefore, the first inductor 346 may form a "loop" that is greater than half.

[0090] A second capacitor may be formed between conductive layer 352 and portion 354 of signal path 316. The second capacitor may correspond to Figure 2 The second capacitor 214 of the circuit diagram 200. The second capacitor may be a self-aligned capacitor.

[0091] The third inductor 356 of the filter 300 may correspond to Figure 2 200. The third inductor 356 may be connected to a portion 369 of the signal path 316 at a first location 357, the portion being connected to the second inductor 346, through one or more vias 360. The third inductor 356 may be connected to a portion 361 of the signal path 316 at a second location 359, the portion being connected to the output 320, through one or more vias 360. The portion 361 of the signal path 316 may be electrically connected to the output 320 through one or more vias 366 and / or an intermediate layer 368. In other words, the third inductor 356 may form a portion of the signal path 316 between the second inductor 346 and the output 320. The third inductor 356 may have a greater width at the protrusion 364 than along other portions of the third inductor 356.

[0092] A third capacitor may be formed in parallel with the third inductor 356. The third capacitor may correspond to Figure 2 The third capacitor 214 of the circuit diagram 200 of FIG. 300 may include a conductive layer 367 capacitively coupled to a portion 369 of the signal path 316 .

[0093] The fourth inductor 370 may be electrically connected to the signal path 316 at a first position 371 and to the ground plane 312 at a second position 373 through a via 374. The via 374 may be connected through an intermediate layer 376. The fourth inductor 370 of the filter 300 may correspond to Figure 2 The fourth inductor 220 of the circuit diagram 200 of FIG. The fourth inductor 370 of the filter 300 may be connected to the signal path 316 at a portion 361 of the signal path 316 electrically connected to the output 320. The fourth inductor 370 may have three corners 372 and form approximately a quarter loop.

[0094] The fourth capacitor may include a conductive layer 380 capacitively coupled to a portion 361 of the signal path 316 connected to the output 320. The conductive layer 380 of the fourth capacitor may be electrically connected to the ground plane 312 through a via 382. The fourth capacitor may correspond to Figure 2 The fourth capacitor 222 of the circuit diagram 200 .

[0095] II. Example Inductor

[0096] Inductance is generally proportional to the length of the inductive element, but inversely proportional to the width of the inductive element. In other words, the inductance may be proportional to the ratio of the length of the inductive element to the average width. Therefore, small adjustments to the width and length of the inductive element may be used to finely tune the inductance. This may be particularly useful for inductors designed to exhibit very low inductance, such as those used in high frequency applications.

[0097] As above FIG. 3A to FIG. 4E As stated, Figure 5A 3 is a top view of the third inductor 356 of the filter 300. As described above, the inductor 356 may be connected to the via 360 at the first location 357 and the second location 359.

[0098] The inductor 356 can have a perimeter 502. The perimeter 502 can define the boundary of the conductive layer forming the inductor 356. The perimeter 502 can include a first straight edge 504 facing outward in a first direction (e.g., the positive Y direction). The perimeter 502 can include a second straight edge 506 that is parallel to the first straight edge 504 and faces outward in the first direction (e.g., the positive Y direction). The second straight edge 506 can be offset from the first straight edge 504 by an offset distance 508. The offset distance 508 can be less than about 500 microns. In some embodiments, the offset distance 508 can be less than about 90% of the first width 510 of the inductor at the first straight edge 504. In some embodiments, the offset distance 508 can be approximately equal to a single minimum line width 510 (e.g., about 50 microns). The minimum line width 510 (given by Figure 5A The grid points in the image (represented by the grid points in the image) can be defined as the minimum feature size that can be accurately patterned.

[0099] The perimeter 502 can include a width discontinuous edge 509 extending between the first straight edge 504 and the second straight edge 506. The width discontinuous edge 509 can be perpendicular to the first straight edge 504 and the second straight edge 506.

[0100] The inductor 356 may have a first width 510 at the first straight edge 504 (e.g., near the width discontinuous edge 509). The first width 510 may be defined in a local width direction (e.g., Y direction) perpendicular to the first straight edge 504. The inductor 356 may have a second width 512 at the second straight edge 506 (e.g., near the width discontinuous edge 509). The second width 512 may be defined in a local width direction (e.g., Y direction). The second width 512 may be greater than the first width 510. The offset distance 508 may be equal to the second width 512 minus the first width 510.

[0101] As mentioned above FIG. 3A to FIG. 4E As described, the inductor 356 can be connected to the via at a first position 537 and a second position 538. The longitudinal centerline 514 can extend along the inductor 356 between the first position 537 and the second position 538. The longitudinal centerline 514 can have a length equal to the effective length of the inductor 356. The longitudinal centerline 514 can include one or more corners 516. The width discontinuous edge 509 can be spaced apart from the corners 516 of the longitudinal centerline 514 of the inductor 356 by a distance 518. The distance 518 can be at least 30 microns. In this example, the distance 518 corresponds to the effective length of the tab or protrusion 364 for increasing the width of the inductor 356.

[0102] Inductor 356 may have various widths defined in respective local width directions perpendicular to longitudinal centerline 514 of inductor 356. Inductor 356 may have an average width that is an average of the widths of inductor 356 weighted by the lengths associated with each length along longitudinal centerline 514. A ratio of the length of inductor 356 to the average width may be defined as the effective length of inductor 356 divided by the average width of inductor 356.

[0103] Adjusting the dimensions of one or more of protrusions 364 (e.g., offset distance 508, effective length 518) can be used to fine tune the average width, and the ratio of length to average width, of inductor 356, and thus the inductance of inductor 356. Example average widths, and ratios of length to average width are provided in the "Examples" section.

[0104] Reference Figure 5B ,Apart from Figure 5B In addition to the offset edges shown in the inductor 530 according to aspects of the present disclosure, the inductor 530 may be similar to the inductor 530 described below with reference to 8A to 9D The third inductor 820 of the filter 800 is depicted.

[0105] Inductor 530 may have a perimeter 532. Perimeter 532 may define the boundaries of the conductive layer forming inductor 530. Perimeter 502 may include a first straight edge 534 facing outward in a first direction (e.g., positive Y direction). Perimeter 532 may include a second straight edge 536 that is parallel to first straight edge 534 and faces outward in the first direction (e.g., positive Y direction). Second straight edge 536 may be offset from first straight edge 534 by an offset distance 538. Offset distance 538 may be less than about 500 microns. In some embodiments, offset distance 538 may be approximately equal to single minimum line width 510 (e.g., about 50 microns).

[0106] The perimeter 532 may include a width discontinuous edge 539 extending between the first straight edge 534 and the second straight edge 536 (eg, in the Y direction). The width discontinuous edge 539 may be perpendicular to the first straight edge 534 and the second straight edge 536.

[0107] Inductor 530 may have a third straight edge 540 and a second discontinuous edge 542 extending between second straight edge 536 and third straight edge 540. Third straight edge 540 may be parallel and aligned with first straight edge 534 so as to form a tab or protrusion 544. Protrusion 544 may have a length 546 in a direction parallel to second straight edge 536.

[0108] Inductor 530 may be connected to the via at a first location 550 and a second location 552. A longitudinal centerline 554 may extend along inductor 530 between first location 550 and second location 552. Longitudinal centerline 554 may have a length 556 equal to an effective length of inductor 530.

[0109] Inductor 530 can include additional protrusions 558. Additional protrusions 558 can be defined relative to straight edges 560 and width discontinuous edges 561 of periphery 532 of inductor 530 in the same manner as protrusions 544. An offset distance 562 associated with additional protrusions 558 can be defined between straight edges 560 in the same manner as protrusions 544.

[0110] Additional protrusion 558 (including associated width discontinuous edge 561) can be symmetrical with protrusion 554 (including associated discontinuous edges 539, 542) about longitudinal centerline 554 and / or transverse centerline 563. The entire inductor 540 can be symmetrical about longitudinal centerline 554 and / or transverse centerline 563.

[0111] Inductor 530 may have a first width 564 at a first straight edge 534. First width 564 may be defined in a local width direction (e.g., Y direction) perpendicular to first straight edge 534. Inductor 530 may have a second width 566 at a second straight edge 536 (e.g., near width discontinuous edge 539). Second width 566 may be defined in a local width direction (e.g., Y direction). Second width 566 may be greater than first width 564. In this example, the difference between second width 566 and first width 564 may be equal to the sum of offset distances 542, 561.

[0112] Inductor 530 can have a first length 570 along longitudinal centerline 554 associated with first width 564. Inductor 530 can have a length along second width 566 that is equal to length 546 of protrusions 554, 558. Inductor 530 can have an average width that can be a weighted average of widths 564, 566 of inductor 530 according to lengths 546, 570 associated with widths 564, 566. A ratio of the length to the average width of inductor 530 can be defined as the effective length 556 of inductor 530 divided by the average width of inductor 530.

[0113] Adjusting the size and / or position of one or more of protrusions 558 can be used to fine tune the average width, and the ratio of length to average width, of inductor 530, thereby fine tuning the inductance of inductor 530. Example average widths, and ratios of length to average width are provided in the "Examples" section.

[0114] Figure 5C 572 is a top view of an inductor 572 according to aspects of the present disclosure. In addition to the inductor 572 including a first straight edge 576 and a second straight edge 577 (the second straight edge is shown in FIG. Figure 5A and Figure 5B In addition to being offset from the first straight edge 576 by an offset distance 575 in the manner described above, the inductor 572 can be similar to the following reference FIG. 10A to FIG. 11D1. The third inductor 1020 of the filter 1000 described above. The first straight edge 576 can be perpendicular to the second straight edge 577. The width discontinuous edge 578 can be connected between the straight edges 576, 577. The width discontinuous edge 578 can be perpendicular to the straight edges 576, 577. The offset distance 575 can be defined in a direction perpendicular to the straight edges 576, 577. The inductor 572 can include a protrusion 574 associated with the width discontinuous edge 578.

[0115] The inductor 572 may be connected to the via at a first location 581 and a second location 583. The longitudinal centerline 571 may be defined between the first location 581 and the second location 583. The effective length 579 of the inductor 572 may be defined along the longitudinal centerline 571 between the first location 581 and the second location 583. The inductor 572 may have a first width 580 and a second width 582, and the second width may be similar to the above reference. Figure 5A and Figure 5B The same is defined with respect to edges 576, 577. Inductor 572 can have a first length 584 and a second length 585 associated with first width 580 and second width 582, respectively.

[0116] The inductor 572 may have an average width that is a weighted average of the widths 580, 582 of the inductor 572 according to respective associated lengths 584, 585 along the longitudinal centerline 571. The ratio of the length to the average width of the inductor 572 may be defined as the effective length 579 of the inductor 572 divided by the average width of the inductor 572. Adjusting the size and / or position of the protrusion 574 may be used to fine tune the average width, and the ratio of the length to the average width, of the inductor 572, and thus the inductance of the inductor 572. Example average widths, and ratios of length to average width are provided in the "Examples" section.

[0117] Reference Figure 5D , the inductor 587 may include two protrusions 588, the two protrusions being referred to as Figure 5A and Figure 5B The described manner is defined with respect to each corresponding straight edge 589, length 596, offset distance 597 and discontinuous edge 596. In addition to the inductor 587 including two protrusions 588, the inductor 587 can be similar to the following reference FIG. 10A to FIG. 10B The fourth inductor 1024 of the filter 1000 is depicted.

[0118] Inductor 587 may have an effective length equal to the sum of first length 590 and second length 591 along longitudinal centerline 592 between first location 593 and second location 594. First length 590 and second length 591 may be defined parallel to longitudinal centerline 592. Inductor 587 and longitudinal centerline 592 may include corner 595.

[0119] Inductor 587 may have various widths measured perpendicular to straight edge 589. Various widths may be defined along longitudinal centerline 592. Inductor 587 may have various widths as described above with reference to Figure 5A Adjusting the size and / or position of one or more of the protrusions 586 can be used to fine tune the average width of the inductor 587, and the ratio of the length to the average width, thereby fine tuning the inductance of the inductor 587. Example average widths, and ratios of the length to the average width are provided in the "Examples" section.

[0120] III. Additional Example Implementations

[0121] Fig. 6A A perspective view of another embodiment of a multilayer filter 600 according to aspects of the present disclosure is shown. Figure 6B Shows Fig. 6A Filter 600 can be generally configured similarly to that described above with reference to FIG. 3A to FIG. 5D Filter 600 may include an input 602, an output 604, and a signal path 606 connecting input 602 and output 604. Filter 600 may also include a ground plane 608 electrically connected to one or more ground electrodes 610.

[0122] The filter 600 may include a first inductor 612 electrically connected to the ground plane 608. The first inductor 612 may correspond to the first inductor 612 described above with reference to Figure 2 The filter 600 may include a first capacitor 614 electrically coupled to the ground plane 608. The first capacitor 614 may correspond to the first inductor 208 of the circuit diagram 200 described above. Figure 2 The first capacitor 210 of the circuit diagram 200 is depicted.

[0123] The filter 600 may include a second inductor 616 and a second capacitor 618 connected in parallel to each other. The second inductor 616 and the second capacitor 618 may correspond to the above reference numerals. Figure 2The filter 600 may include a second inductor 212 and a second capacitor 214 of the circuit diagram 200 described above. The second inductor 616 and the second capacitor 618 may form a portion of the signal path 606 between the input 602 and the output 604. The filter 600 may include a third inductor 620 and a third capacitor 622, which are connected in parallel with each other and may form a portion of the signal path 606 between the input 602 and the output 604. The third inductor 620 and the third capacitor 622 may correspond to the third inductor 620 and the third capacitor 622 described above, respectively. Figure 2 Finally, the filter 600 may include a fourth inductor 624 and a fourth capacitor 626 connected in parallel with each other and connected between the signal path 606 and the ground plane 608. The fourth inductor 624 and the fourth capacitor 626 may correspond to the above reference numerals. Figure 2 The fourth inductor 220 and the fourth capacitor 222 of the circuit diagram 200 are depicted.

[0124] Inductors 612, 616, 620, 624 and capacitors 614, 618, 622, 626 may be configured similarly to those described above with reference to FIG. 3A to FIG. 5D The inductors 612, 616, 620, 624 are connected in the manner described above through vias 627. Each of the inductors 612, 616, 620, 624 can be connected to the signal path 606 at a corresponding first position and connected to the signal path 606 or the ground plane 608 at a corresponding second position. Each of the inductors 612, 616, 620, 624 can have a respective effective length between the first position and the second position (e.g., in the XY plane). In addition, each of the inductors 612, 616, 620, 624 can have a respective width along its respective effective length.

[0125] Figure 6C yes Fig. 6A and Figure 6B 600. The bandpass filter 600 may include multiple dielectric layers (for clarity, the Fig. 6A and Figure 6B is transparent). Figure 6C , the first layer 632, the second layer 636, and the third layer 640 may be stacked to form a monolithic structure. Conductive layers 630, 634, 638, 642 may be formed on dielectric layers 632, 636, 640. Conductive layer 630 may be formed on the bottom surface of the first dielectric layer 632. Conductive layers 634, 638 may be formed on the top and bottom surfaces of the second dielectric layer 636, respectively. Conductive layer 642 may be formed on the top surface of the third dielectric layer 640.

[0126] FIG. 7A to FIG. 7D yes FIG. 6A to FIG. 6C 600, wherein an additional dielectric layer is shown in each figure. More specifically, Fig. 7A A mounting surface 628, such as a printed circuit board, is shown. The first conductive layer 630 may include a ground plane 608, which may be formed on the bottom and top surfaces of the first layer 632. Figure 7B Additionally shown is a second conductive layer 634 formed on the first dielectric layer 632. The second conductive layer 634 may include a first capacitor 614, a second capacitor 618, a third capacitor 622, and a fourth capacitor 626. Figure 7C Additionally shown is a third conductive layer 638 formed on the second dielectric layer 636. The third conductive layer 638 can include portions of the signal path 606 and the first inductor 612. Fig.7D A fourth conductive layer 642 is shown formed on the fourth dielectric layer 640. The fourth conductive layer 642 may include the second inductor 616, the third inductor 622, and the fourth inductor 624. The dielectric layers 632, 636, 640 are transparent to illustrate the relative repositioning of the various patterned conductive layers 630, 634, 638, 642.

[0127] Fig. 8A 800 according to aspects of the present disclosure. The filter 800 may generally be constructed in a manner similar to that described above with reference to FIG. FIG. 3A to FIG. 5D Filter 800 may include an input 802, an output 804, and a signal path 806 connecting input 802 and output 804. Filter 800 may also include a ground plane 808 electrically connected to one or more ground electrodes 810.

[0128] The filter 800 may include a first inductor 812 electrically connected to the ground plane 808. The first inductor 812 may correspond to the first inductor 812 described above with reference to Figure 2 The filter 800 may include a first capacitor 814 electrically coupled to the ground plane 808. The first capacitor 814 may correspond to the first inductor 208 of the circuit diagram 200 described above. Figure 2 The filter 800 may include a second inductor 816 and a second capacitor 818 connected in parallel to each other. The second inductor 816 and the second capacitor 818 may correspond to the above reference numerals. Figure 2800. The second inductor 812 and the second capacitor 814 of the circuit diagram 200 described above. The second inductor 816 and the second capacitor 818 can form a portion of the signal path 806 between the input 802 and the output 804. The filter 800 can include a third inductor 820 and a third capacitor 822, which are connected in parallel with each other and can form a portion of the signal path 806 between the input 802 and the output 804. The third inductor 820 and the third capacitor 822 can correspond to the above reference numerals, respectively. Figure 2 Finally, the filter 800 may include a fourth inductor 824 and a fourth capacitor 826 connected in parallel with each other and connected between the signal path 806 and the ground plane 808. The fourth inductor 824 and the fourth capacitor 826 may correspond to the above reference numerals. Figure 2 The fourth inductor 220 and the fourth capacitor 222 of the circuit diagram 200 are depicted.

[0129] Inductors 812, 816, 820, 824 and capacitors 814, 818, 822, 826 may be configured similarly to those described above with reference to FIG. 3A to FIG. 5D The inductors 812, 818, 820, 824 are connected in the manner described above through vias 827. Each of the inductors 812, 818, 820, 824 can be connected to the signal path 806 at a corresponding first position and connected to the signal path 806 or the ground plane 808 at a corresponding second position. Each of the inductors 812, 818, 820, 824 can have a respective effective length between the first position and the second position (e.g., in the XY plane). In addition, each of the inductors 812, 818, 820, 824 can have a respective width along its respective effective length.

[0130] Figure 8B yes Fig. 8A 800. The bandpass filter 800 may include multiple dielectric layers (for clarity, the Fig. 8A is transparent). Figure 8B , the first layer 832, the second layer 836, and the third layer 840 may be stacked to form a monolithic structure. Conductive layers 830, 834, 838, 842 may be formed on dielectric layers 832, 836, 840. Conductive layer 830 may be formed on the bottom surface of the first dielectric layer 832. Conductive layers 834, 838 may be formed on the top and bottom surfaces of the second dielectric layer 836, respectively. Conductive layer 842 may be formed on the top surface of the third dielectric layer 840.

[0131] FIG. 9A to FIG. 9D yes Fig. 8A and Figure 8B600, wherein an additional dielectric layer is shown in each figure. More specifically, Fig. 9A A mounting surface 828, such as a printed circuit board, is shown. The first conductive layer 830 may include a ground plane 808, which may be formed on the bottom and top surfaces of the first layer 832. Fig. 9B Additionally shown is a second conductive layer 834 formed on the first dielectric layer 832. The second conductive layer 834 may include a first capacitor 814, a second capacitor 818, a third capacitor 822, and a fourth capacitor 826. Fig. 9C Additionally shown is a third conductive layer 838 formed on the second dielectric layer 836. The third conductive layer 838 can include portions of the signal path 806 and the first inductor 812. Fig.9D A fourth conductive layer 842 is illustrated formed on the fourth dielectric layer 840. The fourth conductive layer 842 may include the second inductor 816, the third inductor 822, and the fourth inductor 824. The dielectric layers 832, 836, 840 are transparent to illustrate the relative repositioning of the various patterned conductive layers 830, 834, 838, 842.

[0132] Fig. 10A A perspective view of another embodiment of a multilayer filter 1000 according to aspects of the present disclosure is shown. Fig. 10B Shows Fig. 10A Filter 1000 can be generally constructed in a manner similar to that described above with reference to FIG. 3A to FIG. 5D Filter 1000 may include an input 1002, an output 1004, and a signal path 1006 connecting input 1002 and output 1004. Filter 1000 may also include a ground plane 1008 electrically connected to one or more ground electrodes 1010.

[0133] The filter 1000 may include a first inductor 1012 electrically connected to the ground plane 1008. The first inductor 1012 may correspond to the first inductor 1012 described above with reference to Figure 2 The filter 1000 may include a first capacitor 1014 electrically coupled to the ground plane 1008. The first capacitor 1014 may correspond to the first inductor 208 of the circuit diagram 200 described above. Figure 2 The filter 1000 may include a second inductor 1016 and a second capacitor 1018 connected in parallel to each other. The second inductor 1016 and the second capacitor 1018 may correspond to the first capacitor 210 of the circuit diagram 200 described above. Figure 21004. The filter 1000 may include a third inductor 1020 and a third capacitor 1022, which are connected in parallel to each other and may form a portion of the signal path 1006 between the input 1002 and the output 1004. The third inductor 1020 and the third capacitor 1022 may correspond to the third inductor 1020 and the third capacitor 1022 described above, respectively. Figure 2 Finally, the filter 1000 may include a fourth inductor 1024 and a fourth capacitor 1026 connected in parallel with each other and connected between the signal path 1006 and the ground plane 1008. The fourth inductor 1024 and the fourth capacitor 1026 may correspond to the above reference 1006, respectively. Figure 2 The fourth inductor 220 and the fourth capacitor 222 of the circuit diagram 200 are depicted.

[0134] Inductors 1012, 1016, 1020, 1024 and capacitors 1014, 1018, 1022, 1026 may be configured similarly to those described above. FIG. 3A to FIG. 5D The inductors 1012, 10110, 1020, 1024 are connected in the manner described by vias 1027. Each of the inductors 1012, 10110, 1020, 1024 can be connected to the signal path 1006 at a corresponding first position and connected to the signal path 1006 or the ground plane 1008 at a corresponding second position. Each of the inductors 1012, 10110, 1020, 1024 can have a respective effective length between the first position and the second position (e.g., in the XY plane). In addition, each of the inductors 1012, 10110, 1020, 1024 can have a respective width along its respective effective length.

[0135] Fig. 10B yes Fig. 10A and Fig. 10B 1000. The bandpass filter 1000 may include multiple dielectric layers (for clarity, the Fig. 10A is transparent). Fig. 10B, the first layer 1032, the second layer 1036, and the third layer 1040 may be stacked to form a monolithic structure. Conductive layers 1030, 1034, 1038, and 1042 may be formed on dielectric layers 1032, 1036, and 1040. Conductive layer 1030 may be formed on the bottom surface of the first dielectric layer 1032. Conductive layers 1034 and 1038 may be formed on the top and bottom surfaces of the second dielectric layer 1036, respectively. Conductive layer 1042 may be formed on the top surface of the third dielectric layer 1040.

[0136] FIG. 11A to FIG. 11D yes Fig. 10A and Fig. 10B 600, wherein an additional dielectric layer is shown in each figure. More specifically, Fig.11A A mounting surface 1028 such as a printed circuit board is shown. The first conductive layer 1030 may include a ground plane 1008, which may be formed on the bottom and top surfaces of the first layer 1030. Fig. 11B Additionally shown is a second conductive layer 1034 formed on the first dielectric layer 1032. The second conductive layer 1034 may include a first capacitor 1014, a second capacitor 1018, a third capacitor 1022, and a fourth capacitor 1026. Fig. 11C Additionally shown is a third conductive layer 1038 formed on the second dielectric layer 1036. The third conductive layer 1038 can include portions of the signal path 1006 and the first inductor 1012. Fig.11D A fourth conductive layer 1042 is shown formed on the fourth dielectric layer 1040. The fourth conductive layer 1042 may include the second inductor 1016, the third inductor 1022, and the fourth inductor 1024. The dielectric layers 1032, 1036, 1040 are transparent to illustrate the relative repositioning of the various patterned conductive layers 1030, 1034, 1038, 1042.

[0137] IV. Application

[0138] Various embodiments of the filters described herein may find application in any suitable type of electrical component. The filters may find particular application in devices that receive, transmit, or otherwise use high frequency radio signals. Exemplary applications include smartphones, signal repeaters (e.g., small base stations), relay stations, and radars.

[0139] V. Testing and Simulation Data

[0140] Computer modeling was used to simulate a multilayer filter according to aspects of the present disclosure. In addition, a filter was built and tested.

[0141] The thickness of the dielectric layer can generally be less than about 180 microns ("microns"). For example, in some embodiments, the first layer 304, 632, 832, 1032 can be about 60 microns thick. The second layer 306, 636, 836, 1036 can be about 20 microns thick. The third layer 308, 640, 840, 1040 can be about 60 microns thick.

[0142] In some embodiments, the total length of the filter can be 4.3 mm. The total width can be about 4 mm. The total thickness can be about 230 microns.

[0143] Figures 12 to 17 Test results and simulation data for various filters are shown. Fig.12 , a multilayer filter according to aspects of the present disclosure was constructed and tested. The measured insertion loss (S 21 ) value and the measured return loss (S 11 ) values ​​are plotted from 0 GHz to 45 GHz. The simulated insertion loss (S 21 ) value and simulated return loss (S 11 ) values ​​are plotted in the range of 0 GHz to 35 GHz. The measured passband is from about 13.2 GHz to about 15.8 GHz.

[0144] Reference Fig.13 , a multilayer filter according to aspects of the present disclosure was constructed and tested. The measured insertion loss (S 21 ) value and the measured return loss (S 11 ) values ​​are plotted from 0 GHz to 45 GHz. The simulated insertion loss (S 21 ) value and simulated return loss (S 11 ) values ​​are plotted in the range of 0 GHz to 35 GHz. The passband is from about 16.1 GHz to about 18.2 GHz.

[0145] Reference Fig.14 , simulated, built and physically tested the above reference FIG. 3A to FIG. 4E The multilayer filter 300 is described. The measured insertion loss (S 21 ) value and the measured return loss (S 11 ) values ​​are plotted from 0 GHz to 45 GHz. The simulated insertion loss (S 21 ) value and simulated return loss (S 11 ) values ​​are plotted in the range of 0 GHz to 35 GHz. The passband is from about 17.0 GHz to about 21.2 GHz.

[0146] Reference Fig.15 , simulating the above reference FIG. 6A to FIG. 7D The multilayer filter 600 is described. The simulated insertion loss (S21 ) value and simulated return loss (S 11 ) values ​​are plotted in the range of 0 GHz to 50 GHz. The passband is from about 24.6 GHz to about 27.8 GHz.

[0147] Reference Fig.16 , simulating the above reference FIG. 8A to FIG. 9D The multilayer filter 800 is described. The simulated insertion loss (S 21 ) value and simulated return loss (S 11 ) values ​​are plotted in the range of 0 GHz to 55 GHz. The passband is from about 34.6 GHz to about 37.4 GHz.

[0148] Reference Fig.17 , simulating the above reference FIG. 10A to FIG. 11D The multilayer filter 1000 is described. The simulated insertion loss (S 21 ) value and simulated return loss (S 11 ) values ​​are plotted in the range of 0 GHz to 70 GHz. The passband is from about 42.9 GHz to about 46.6 GHz.

[0149] Example

[0150] It should be understood that the following dimensions and ratios are given as examples only and do not limit the scope of the present disclosure. For example, in some embodiments, a process that can achieve higher precision in shaping the conductive layer can be used, resulting in a smaller minimum line width.

[0151] Refer again Figure 5A , the inductor 356 may have dimensions as shown, where each minimum line width 510 (in the X and Y directions) is approximately 51 microns. In other words, for the purposes of this example section, Figure 5A It can be considered to be drawn to scale. Inductor 356 has an average width of about 5.36 minimum line widths 501 (e.g., about 272 microns). The total effective length is 14 minimum line widths 501 (e.g., about 711 microns). Therefore, the ratio of the length to the average width of inductor 356 is about 2.61.

[0152] In contrast, a similar inductor without protrusion 364 would have an average width of about 5.14 minimum line widths 501 (e.g., about 261 microns) and a length-to-average-width ratio of about 2.72. Thus, protrusion 364 increases the average width by about 4% and decreases the length-to-average-width ratio by about 4%. Furthermore, increasing the distance 518 (e.g., length) associated with protrusion 364 by a single minimum line width 501 (e.g., about 51 microns) would increase the average width of inductor 534 by only about 1.3% and decrease the length-to-average-width ratio by only about 1.3%. Thus, adjusting the size of protrusion 364 can be used to fine-tune the length-to-average-width ratio, and thus the inductance of inductor 356.

[0153] Refer again Figure 5B , the inductor 530 may have dimensions as shown, where each minimum line width 510 (in the X and Y directions) is approximately 51 microns. In other words, for the purposes of this example section, Figure 5B Can be considered to be drawn to scale. Inductor 530 can have an average width of about 5.29 minimum line widths 501 (e.g., about 269 microns) and a length to average width ratio of about 1.32. In contrast, a similar inductor without protrusions 588 will have an average width of 4 minimum line widths 501 (e.g., about 203 microns) and a length to average width ratio of about 1.75. Therefore, protrusions 544, 558 increase the average width by about 32% and reduce the length to average width ratio by about 24%. In addition, increasing the length 546 of any protrusion 558 by a single minimum line width 510 will increase the average width of inductor 530 by only about 8.1% and reduce the length to average width ratio by only about 8.8%. Therefore, adjusting the size of one or more of the protrusions 544, 558 can be used to finely adjust the length to average width ratio, thereby finely adjusting the inductance of inductor 530.

[0154] Refer again Figure 5C , the inductor 572 may have dimensions as shown, where each minimum line width 510 (in the X and Y directions) is approximately 51 microns. In other words, for the purposes of this example section, Figure 5C can be considered to be drawn to scale. Inductor 572 can have an average width of about 6.8 minimum line widths 501 (e.g., about 345 microns) and a length to average width ratio of about 0.88. In contrast, a similar inductor without protrusion 574 would have an average width of 6 minimum line widths 501 (e.g., about 305 microns) and a length to average width ratio of about 1. Thus, protrusion 574 increases the average width by about 14% and decreases the length to average width ratio by about 12%.

[0155] Furthermore, reducing the effective length (second length 585) of protrusion 574 by a single minimum line width 510 (e.g., about 51 microns) will increase the average width of inductor 572 by only about 2.5% and reduce the length-to-average width ratio by only about 2.44%. Thus, adjusting the size of protrusion 574 can be used to fine-tune the length-to-average width ratio, and thus the inductance of inductor 572.

[0156] Refer again Figure 5D , inductor 587 may have an average width of about 4.8 minimum line widths 501 (e.g., about 244 microns) and a length to average width ratio of about 2.08. In contrast, a similar inductor without protrusion 588 would have an average width of 4.4 minimum line widths 510 (e.g., about 224 microns) and a length to average width ratio of about 2.27. Thus, protrusion 588 increases the average width by about 9.1% and decreases the length to average width ratio by about 8.3%.

[0157] Furthermore, increasing the effective length 596 of any protrusion 588 by a single minimum line width 510 (e.g., about 51 microns) will only increase the average width of the inductor 587 by about 2.08% and reduce the length-to-average width ratio by about 2.04%. Thus, adjusting the size of one or more of the protrusions 588 can be used to fine tune the length-to-average width ratio, and thus the inductance of the inductor 587.

[0158] Test Method

[0159] Reference Fig.18 , the test assembly 1800 can be used to test the performance characteristics of the multilayer filter 1802 according to aspects of the present disclosure, such as insertion loss and return loss. The filter 1802 can be mounted to a test board 1804. The input line 1806 and the output line 1808 are both connected to the test board 1804. The test board 1804 can include microstrip lines 1810 that electrically connect the input line 1806 to the input of the filter 1802 and the output line 1808 to the output of the filter 1802. An input signal is applied to the input line using a source signal generator (e.g., a 1806 Keithley 2400 series source measurement unit (SMU) such as a Keithley 2410-C SMU), and the resulting output of the filter 1802 is measured at the output line 1808 (e.g., using a source signal generator). This operation is repeated for various configurations of the filter.

[0160] Without departing from the spirit and scope of the present disclosure, those of ordinary skill in the art may practice these and other modifications and variations of the present disclosure. In addition, it should be understood that the aspects of the various embodiments may be interchangeable in whole and in part. In addition, those of ordinary skill in the art will appreciate that the foregoing description is only by way of example and is not intended to limit the disclosure further described in such appended claims.

Claims

1. A multilayer electronic device, comprising: multiple dielectric layers; a signal path having an input and an output; as well as an inductor comprising a conductive layer overlying one of the plurality of dielectric layers, and wherein the inductor is electrically connected to the signal path at a first location of the conductive layer and is electrically connected to at least one of the signal path or ground at a second location of the conductive layer, and wherein: The inductor has an outer periphery including a first straight edge facing outward in a first direction, and a second straight edge parallel to the first straight edge and facing outward in the first direction, the second straight edge is offset from the first straight edge in the first direction by an offset distance that is less than 500 microns and less than 90% of a first width of the inductor in the first direction at the first straight edge, and The inductor has an effective length, the effective length being a length along the conductive layer between the first location and the second location.

2. The multilayer electronic device according to claim 1, wherein: The inductor has a second width at the second straight edge in the first direction, and wherein a ratio of the second width to the first width ranges from 1.02 to 1.

9.

3. The multilayer electronic device according to claim 1, wherein: The perimeter includes a width discontinuous edge extending between the first straight edge and the second straight edge.

4. The multilayer electronic device according to claim 3, wherein: The width discontinuous edge is perpendicular to the first straight edge and the second straight edge.

5. The multilayer electronic device according to claim 3, wherein: The inductor has a longitudinal centerline extending from the first position to the second position, wherein the longitudinal centerline is non-linear and includes at least one corner, and wherein the width discontinuous edge is spaced at least 30 microns from the corner of the longitudinal centerline of the inductor.

6. The multilayer electronic device according to claim 1, wherein: The offset distance is equal to the minimum line width.

7. The multilayer electronic device according to claim 1, wherein: The inductor has a length to average width ratio of less than 10.

8. The multilayer electronic device according to claim 1, wherein: The inductor has an average width of less than 1 mm.

9. The multilayer electronic device according to claim 1, wherein: The effective length is less than 2 mm.

10. The multilayer electronic device according to claim 3, wherein: The inductor includes an additional width discontinuous edge, and wherein the additional width discontinuous edge and the width discontinuous edge are symmetrical about at least one of a longitudinal centerline or a lateral centerline of the inductor.

11. The multilayer electronic device according to claim 1, wherein: The multilayer electronic device is configured as a filter.

12. The multilayer electronic device according to claim 11, wherein: The filter has a characteristic frequency greater than 6 GHz.

13. The multilayer electronic device according to claim 12, wherein: The characteristic frequency includes at least one of a low-pass frequency, a high-pass frequency, or an upper limit of a band-pass frequency.

14. The multilayer electronic device according to claim 1, wherein: The conductive layer is a first conductive layer, and the multilayer electronic device further comprises: a second conductive layer covering a corresponding one of the plurality of dielectric layers, The second conductive layer and the first conductive layer are spaced apart by less than 100 micrometers in the Z direction. 15 . The multilayer electronic device of claim 14 , further comprising a ground plane and a via electrically connecting at least one of the first conductive layer or the second conductive layer to the ground plane.

16. The multilayer electronic device of claim 1, further comprising a dielectric material having a dielectric constant less than 100 determined according to IPC TM-650 2.5.5.3 at an operating temperature of 25°C and at a frequency of 1 MHz.

17. The multilayer electronic device of claim 1, further comprising a dielectric material having a dielectric constant greater than 100 determined according to IPC TM-650 2.5.5.3 at an operating temperature of 25°C and at a frequency of 1 MHz.

18. The multilayer electronic device according to claim 1, further comprising: A dielectric material comprising epoxy resin.

19. The multilayer electronic device of claim 1, further comprising an organic dielectric material.

20. The multilayer electronic device according to claim 19, wherein The organic dielectric material includes at least one of a liquid crystal polymer or polyphenylene ether.

21. A method of forming a multilayer electronic device, the method comprising: providing a plurality of dielectric layers; forming a plurality of conductive layers to form a signal path having an input and an output, the plurality of conductive layers overlying at least some of the plurality of dielectric layers; wherein the signal path comprises an inductor, the inductor comprising a corresponding one of the plurality of conductive layers, the inductor being electrically connected to the signal path at a first position of the conductive layer and being electrically connected to at least one of the signal path or ground at a second position of the conductive layer, wherein the inductor has an outer periphery, the outer periphery comprising a first straight edge facing outward in a first direction, and a second straight edge parallel to the first straight edge and facing outward in the first direction, wherein the second straight edge is offset from the first straight edge by an offset distance, the offset distance being less than 500 microns and less than 90% of a first width of the inductor in the first direction at the first straight edge, and wherein the inductor has an effective length, the effective length being a length along the conductive layer between the first position and the second position.

22. A method of designing an inductor for a multilayer electronic device, the method comprising: selecting an effective length and width of the inductor based on a target inductance value for the inductor, the effective length being a length along a conductive layer of the inductor between a first location on the conductive layer and a second location on the conductive layer; An offset distance associated with a protrusion of the inductor is sized between a first straight edge of a perimeter of the inductor and a second straight edge of the perimeter of the inductor, the offset distance being less than 500 microns and less than 90% of a first width of the inductor in a first direction at the first straight edge, wherein The first straight edge faces outward in the first direction, and the second straight edge is parallel to the first straight edge and faces outward in the first direction.

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