IGBT device

Abstract

The application discloses an IGBT device, which is formed by a plurality of cells in parallel, each of the cells is formed in an active region on a wafer, and a gate structure of each of the cells adopts a trench gate, the trench gate comprises a gate dielectric layer formed on an inner surface of a gate trench and a polysilicon gate filled in the gate trench; when the polysilicon gate completely fills the gate trench, a corresponding first stress is generated on the wafer; in a top view, the active region is divided into two or more area blocks, the gate trench in each of the area blocks is in a strip structure and is arranged in parallel, the strip structures of the gate trenches in two adjacent area blocks are not parallel and have an included angle, so that the directions of the first stress on the wafer generated by the polysilicon gates in the two adjacent area blocks are different, and the resultant stress generated by each of the polysilicon gates on the wafer is reduced or disappears. The application can improve the uniformity of IGBT device parameters on the same wafer, and thereby improves the product yield.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit, and in particular to an insulated gate bipolar transistor (IGBT) device. BACKGROUND

[0002] IGBT is the mainstream power device in the market, especially in the high-voltage and high-power field. As a voltage-controlled bipolar power device, IGBT has a high share in the low-frequency and high-power market, and IGBT module has considerable potential in the new energy field.

[0003] The mainstream IGBT devices in the market basically adopt trench gate field stop structure design. This structure design balances the on and off of the device and the parameters of the switch to the best. The current IGBT manufacturing technology is developing towards reducing the cell size, thereby increasing the channel density per unit area and reducing the chip area. At the same time, the area of the wafer is developing towards larger and larger to reduce the manufacturing cost.

[0004] So far, the size of a single cell has been reduced to a few microns or even close to one micron, so improving the uniformity of IGBT chip parameters on the same wafer is crucial to product yield. SUMMARY

[0005] The technical problem to be solved by the present application is to provide an IGBT device that can improve the uniformity of IGBT device parameters on the same wafer and thereby improve product yield.

[0006] To solve the above technical problems, the IGBT device provided by the present application is formed by a plurality of cells in parallel, each of the cells is formed in an active region on a wafer, and the wafer is composed of a semiconductor substrate.

[0007] The gate structure of each of the cells adopts a trench gate, which includes a gate dielectric layer formed on the inner side surface of a gate trench and a polysilicon gate filled in the gate trench; when the polysilicon gate completely fills the gate trench, it will generate a corresponding first stress on the wafer.

[0008] In the top view, the active region is divided into two or more area blocks, the gate trench in each of the area blocks has a strip structure and is arranged in parallel, the strip structures of the gate trenches in adjacent two of the area blocks are not parallel but have an included angle, so that the directions of the first stress on the wafer generated by the polysilicon gates in adjacent two of the area blocks are different, thereby reducing or eliminating the resultant stress on the wafer generated by each of the polysilicon gates.

[0009] Further improvement is that the strip structure of the gate trench in two adjacent area blocks has an included angle of 90 degrees.

[0010] Further improvement is that the top view of the active region is a rectangular structure.

[0011] Further improvement is that each area block is formed by dividing the length or width of the active region.

[0012] Further improvement is that each area block has the same length and the same width.

[0013] Further improvement is that the number of each area block is an even number.

[0014] Further improvement is that the number of each area block is 4, the length of each area block is equal to the length of the active region, and the width of each area block is equal to 1 / 4 of the width of the active region.

[0015] Further improvement is that the number of each area block is 8, the length of each area block is equal to 1 / 2 of the length of the active region, and the width of each area block is equal to 1 / 4 of the width of the active region.

[0016] Further improvement is that the IGBT device further comprises an N-type doped drift region.

[0017] A P-type well region is formed on the surface of the drift region, and the depth of the trench gate is greater than the depth of the P-type well region.

[0018] The channel region is composed of selected areas of the P-type well region, and an N+ doped source region is formed on the front surface of the channel region, and the surface of the channel region covered by the polysilicon gate is used to form a channel; the top of the source region is connected to an emitter composed of a front metal layer through a contact hole passing through an interlayer film, and the bottom of the top contact hole of the source region also passes through the source region and contacts the channel region.

[0019] The floating P-type doped region is composed of selected areas of the P-type well region, and the front surface of the floating P-type doped region does not form the source region and does not form the contact hole, thereby forming a floating structure not connected to an electrode.

[0020] The hole flow-through channel region is composed of selected areas of the P-type well region, and the front surface of the hole flow-through channel region does not form the source region, and the top of the hole flow-through channel region is connected to the emitter through a contact hole passing through an interlayer film.

[0021] A P+ doped collector region is formed on the back surface of the drift region.

[0022] A collector electrode is formed on the back surface of the collector region by a back surface metal layer.

[0023] A further improvement is that the top of each of the polysilicon gates is connected to a gate electrode formed by a front surface metal layer through a contact hole.

[0024] A further improvement is that part of the top of each of the polysilicon gates is connected to a gate electrode formed by a front surface metal layer through a contact hole, and the remaining part of the top of each of the polysilicon gates is connected to the source electrode through a contact hole to adjust the capacitance of the IGBT device.

[0025] A further improvement is that an N-type doped carrier storage layer (CS) is formed between the front surface of the drift region and the back surface of the P-type well region, and the doping concentration of the carrier storage layer is greater than that of the drift region.

[0026] A further improvement is that an N-type doped field stop layer is further formed between the back surface of the drift region and the front surface of the collector region, and the doping concentration of the field stop layer is greater than that of the drift region.

[0027] A further improvement is that the width of the unit cell is several microns or close to 1 micron.

[0028] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0029] The gate dielectric layer is a gate oxide layer.

[0030] An epitaxial layer is further formed on the surface of the semiconductor substrate, the drift region is formed in the epitaxial layer, and the collector region is formed in the semiconductor substrate after back thinning.

[0031] The gate structure of the IGBT device of the present application adopts a trench gate. As the size of the unit cell becomes smaller and smaller, the stress generated by the trench gate has a greater and greater impact on the parameters of the wafer and the IGBT device formed on the wafer, such as the uniformity of the parameters. The present application takes into account the adverse effect of the stress of the trench gate on the uniformity of the parameters of the IGBT device, and specially sets the extension direction of the trench gate, i.e. the layout structure on the top view. By setting the strip structure of the gate trench in the adjacent two region blocks to be a structure with an included angle, such as a perpendicular structure, the first stress direction of the polysilicon gate in the adjacent two region blocks is different, so that the resultant stress of the polysilicon gate on the wafer is reduced or eliminated, i.e. the stress of the wafer is released, and finally the uniformity of the parameters of the IGBT device on the same wafer is improved, and the product yield is improved.

[0032] The technical scheme of the present application breaks through the limitation of the structure of the trench gate in the IGBT, and by setting the layout structure of the trench gate, the cell size of the IGBT device of the present application can be further reduced or the performance of the IGBT device with the cell width of several microns or even close to 1 micron can be improved, so that the present application can achieve unexpected technical effects. BRIEF DESCRIPTION OF DRAWINGS

[0033] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0034] Figure 1 is a cross-sectional structure schematic diagram of the first embodiment IGBT device of the present application;

[0035] Figure 2 is the layout of the trench gate of the first preferred embodiment of the first embodiment IGBT device of the present application;

[0036] Figure 3 is the layout of the trench gate of the second preferred embodiment of the first embodiment IGBT device of the present application;

[0037] Figure 4 is a cross-sectional structure schematic diagram of the second embodiment IGBT device of the present application. DETAILED DESCRIPTION

[0038] The first embodiment IGBT device of the present application:

[0039] As shown in Figure 1 , it is a cross-sectional structure schematic diagram of the first embodiment IGBT device of the present application; the first embodiment IGBT device of the present application is formed by a plurality of cells connected in parallel, each of the cells is formed in an active region 201 on a wafer, and the wafer is composed of a semiconductor substrate.

[0040] The gate structure of each of the cells adopts a trench gate, the trench gate includes a gate dielectric layer such as a gate oxide layer 3 formed on the inner side surface of a gate trench 101 and a polysilicon gate 4 filled in the gate trench 101; when the polysilicon gate 4 completely fills the gate trench 101, a corresponding first stress will be generated on the wafer.

[0041] In the top view, the active region 201 is divided into two or more area blocks, the gate trench 101 in each of the area blocks has a strip structure and is arranged in parallel, the strip structures of the gate trenches 101 in the adjacent two area blocks are not parallel but have an included angle, so that the first stresses on the wafer generated by the polysilicon gates 4 in the adjacent two area blocks are different, and the resultant stress on the wafer generated by each of the polysilicon gates 4 is reduced or disappears.

[0042] Preferably, the strip structure of the gate trench 101 in two adjacent region blocks has an included angle of 90 degrees. The top view of the active region 201 is in a rectangular structure. Each region block is formed by dividing the length or width of the active region 201. The length of each region block is the same and the width of each region block is also the same. The number of each region block is an even number.

[0043] As shown in FIG. 1, it is a top view of the IGBT device of the first embodiment of the present application. The number of each region block is 4, which is respectively indicated by the marks 201a, 201b, 201c and 201d. The length of each region block is equal to the length of the active region 201, and the width of each region block is equal to 1 / 4 of the width of the active region 201. Figure 2 As shown in FIG. 2, it is a top view of the IGBT device of the second embodiment of the first embodiment of the present application. The number of each region block is 8, which is respectively indicated by the marks 201a, 201b, 201c, 201d, 201e, 201f, 201g and 201h. The length of each region block is equal to 1 / 2 of the length of the active region 201, and the width of each region block is equal to 1 / 4 of the width of the active region 201.

[0044] Figure 3 The IGBT device further comprises an N-type doped drift region 1.

[0045] A P-type well region 2 is formed on the surface of the drift region 1, and the depth of the trench gate is greater than the depth of the P-type well region 2.

[0046] A channel region is composed of the P-type well region 2 in the selected region such as the region indicated by the dashed box 102, and an N+ doped source region 6 is formed on the front surface of the channel region. The surface of the channel region covered by the polysilicon gate 4 is used to form a channel. The top of the source region 6 is connected to an emitter composed of a front metal layer 9 through a contact hole 8 passing through an interlayer film 7. The bottom of the top contact hole 8 of the source region 6 also passes through the source region 6 and contacts the channel region.

[0047] A floating P-type doped region is composed of the P-type well region 2 in the selected region such as the region indicated by the dashed box 104. The front surface of the floating P-type doped region is not formed with the source region 6 and the contact hole 8, and thus is a floating structure not connected to an electrode.

[0048] A hole flow passage region is composed of the P-type well region 2 in the selected region such as the region indicated by the dashed box 103. The front surface of the hole flow passage region is not formed with the source region 6. The top of the hole flow passage region is connected to the emitter through the contact hole 8 passing through the interlayer film 7.

[0049] A hole flow passage region is composed of the P-type well region 2 in the selected region such as the region indicated by the dashed box 103. The front surface of the hole flow passage region is not formed with the source region 6. The top of the hole flow passage region is connected to the emitter through the contact hole 8 passing through the interlayer film 7. ​

[0050] A P+ doped collector region 11 is formed on the back surface of the drift region 1.

[0051] A collector electrode composed of a back surface metal layer 12 is formed on the back surface of the collector region 11.

[0052] Each of the polysilicon gates 4 is connected to a gate electrode composed of a front surface metal layer 9 through a contact hole 8.

[0053] An N-type doped carrier storage layer 5 is formed between the front surface of the drift region 1 and the back surface of the P-type well region 2, and the doping concentration of the carrier storage layer 5 is greater than that of the drift region 1.

[0054] An N-type doped field stop layer 10 is also formed between the back surface of the drift region 1 and the front surface of the collector region 11, and the doping concentration of the field stop layer 10 is greater than that of the drift region 1.

[0055] The width of the unit cell is several microns or close to 1 micron.

[0056] The semiconductor substrate comprises a silicon substrate.

[0057] The gate dielectric layer 3 is a gate oxide layer.

[0058] An epitaxial layer is also formed on the surface of the semiconductor substrate, and the drift region 1 is formed in the epitaxial layer; the collector region 11 is formed in the semiconductor substrate after back thinning.

[0059] The gate structure of the IGBT device of the first embodiment of the present application adopts a trench gate. With the size of the unit cell becoming smaller and smaller, the stress generated by the trench gate has a greater and greater impact on the parameters of the wafer and the IGBT device formed on the wafer, such as the impact on the parameter uniformity. The first embodiment of the present application combines the adverse impact of the stress of the trench gate on the parameter uniformity of the IGBT device, and specially sets the layout structure in the extension direction of the trench gate, i.e. the layout structure on the top view. By setting the strip structure of the gate trench 101 in the adjacent two region blocks to a structure with an included angle, such as a perpendicular structure, the direction of the first stress of the polysilicon gate 4 in the adjacent two region blocks on the wafer is different, so that the resultant stress of each polysilicon gate 4 on the wafer is reduced or eliminated, i.e. the stress of the wafer is released, and finally the parameter uniformity of the IGBT device on the same wafer is improved, and the product yield is improved.

[0060] The technical solution of the first embodiment of the present invention breaks through the limitation of the trench gate structure in IGBT. By setting the layout structure of the trench gate, the cell size of the IGBT device of the first embodiment of the present invention can be further reduced or the performance of the IGBT device with a cell width of several micrometers or even close to 1 micrometer can be improved. Therefore, the first embodiment of the present invention can achieve unexpected technical effects.

[0061] The difference between the IGBT device of the second embodiment of the present invention and the IGBT device of the first embodiment of the present invention is as follows:

[0062] like Figure 4 The diagram shown is a cross-sectional view of an IGBT device according to a second embodiment of the present invention. In the second embodiment of the present invention, the top of a portion of the polysilicon gate 4 is connected to the gate composed of the front metal layer 9 through contact holes 8. As shown in the area corresponding to the dashed box 105, the top of the remaining portion of the polysilicon gate 4 is connected to the source through contact holes 8a to adjust the capacitance of the IGBT device. Figure 4 The contact hole connected to the source is marked separately with symbol 8a. The capacitance of an IGBT device typically includes Cgs, Ggd, and Csd, where Cgs is the parasitic capacitance between the gate and the source (i.e., emitter), Cgd is the parasitic capacitance between the gate and the drain (i.e., collector), and Csd is the parasitic capacitance between the emitter and the collector. By connecting a portion of the polysilicon gate 4 to the source, the coverage area of ​​the polysilicon gate 4 and the drift region 1 between the gate and the collector can be reduced, while the coverage area of ​​the polysilicon gate 4 and the drift region 1 between the source and the collector can be increased. This allows adjustment of Cgs, Ggd, and Csd, and thus, the performance of the device can be adjusted as needed.

[0063] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An IGBT device, characterized in that: IGBT devices are composed of multiple unit cells connected in parallel, each of which is formed in an active region on a wafer composed of a semiconductor substrate; Each unit cell employs a trench gate structure, the trench gate comprising a gate dielectric layer formed on the inner surface of the gate trench and a polysilicon gate filling the gate trench; when the polysilicon gate completely fills the gate trench, it generates a corresponding first stress on the wafer; On the top view, the active area is divided into two or more regions. The gate trenches in each region are strip-shaped and arranged in parallel. The strip-shaped structures of the gate trenches in two adjacent regions are not parallel but have an angle, so that the direction of the first stress of the polysilicon gate on the wafer in the two adjacent regions is different, thereby reducing or eliminating the combined stress generated by each polysilicon gate on the wafer. The top view of the active region has a rectangular structure; Each of the aforementioned region blocks is formed by dividing the length or width of the active region; All of the aforementioned regions have the same length and the same width, and the length of each region is greater than its width. The IGBT device also includes an N-type doped drift region; A P-type well region is formed on the surface of the drift region, and the depth of the trench gate is greater than the depth of the P-type well region; The channel region is composed of the selected area of ​​the P-type well region, and an N+ doped source region is formed on the front surface of the channel region. The surface of the channel region covered by the side of the polysilicon gate is used to form the channel. The top of the source region is connected to the emitter composed of the front metal layer through a contact hole through the interlayer film. The bottom of the top contact hole of the source region also passes through the source region and contacts the channel region. The floating P-type doped region is composed of the selected region of the P-type well region. The source region and the contact hole are not formed on the front surface of the floating P-type doped region, thus forming a floating structure that is not connected to the electrode. The hole flow channel region is composed of the selected P-type trap region. The source region is not formed on the front surface of the hole flow channel region. The top of the hole flow channel region is connected to the emitter through a contact hole passing through the interlayer membrane. A P+-doped collector region is formed on the back side of the drift region; A current collector electrode composed of a back metal layer is formed on the back side of the current collector region; In some cases, the top of the polysilicon gate is connected to the gate, which is composed of a front-side metal layer, via a contact hole; in the remaining cases, the top of the polysilicon gate is connected to the source via a contact hole to adjust the capacitance of the IGBT device.

2. The IGBT device as described in claim 1, characterized in that: The strip structure of the gate trench in two adjacent region blocks has an included angle of 90 degrees.

3. The IGBT device as described in claim 1, characterized in that: The number of each of the aforementioned region blocks is an even number.

4. The IGBT device as described in claim 3, characterized in that: The number of each region block is 4, the length of each region block is equal to the length of the active region, and the width of each region block is equal to 1 / 4 of the width of the active region.

5. The IGBT device as described in claim 3, characterized in that: The number of each region block is 8, the length of each region block is equal to 1 / 2 of the length of the active region, and the width of each region block is equal to 1 / 4 of the width of the active region.

6. The IGBT device as described in claim 1, characterized in that: An N-type doped carrier storage layer is formed between the front surface of the drift region and the back surface of the P-type well region, wherein the doping concentration of the carrier storage layer is greater than that of the drift region.

7. The IGBT device as described in claim 1, characterized in that: An N-type doped field stop layer is also formed between the back surface of the drift region and the front surface of the collector region, and the doping concentration of the field stop layer is greater than that of the drift region.

8. The IGBT device as described in claim 1, characterized in that: The width of the unit cell is several micrometers or close to 1 micrometer.

9. The IGBT device as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate; The gate dielectric layer is a gate oxide layer; An epitaxial layer is also formed on the surface of the semiconductor substrate, and the drift region is formed in the epitaxial layer; the collector region is formed in the semiconductor substrate after back-side thinning.

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