Spin-orbit moment magnetoresistive random access memory and manufacturing method thereof

Abstract

Disclosed herein is an improved SOT-MRAM device and a method for manufacturing the same. A memory device includes a first structure including a magnetic tunnel junction stack and a spin-orbit moment layer. The spin-orbit moment layer is formed on the magnetic tunnel junction stack. A dielectric cap layer is formed on top of the spin-orbit moment layer. A metal layer is formed on top of the first structure. The metal layer surrounds each of the spin-orbit moment layer and the dielectric cap layer. The metal layer is in direct contact with a sidewall of the spin-orbit moment layer.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to spin-orbit torque magnetoresistive random access memory (SOT-MRAM). Background Art

[0002] Magnetoresistive random access memory (MRAM) uses magnetic memory elements to store data. MRAM can take various forms, including spin transfer torque (STT) MRAM, in which a spin-polarized current is used to reverse the spin direction of electrons by using a magnetic tunnel junction (MTJ) stack. The spin-polarized current is applied to the STT-MRAM device in the in-plane or perpendicular direction relative to the MTJ stack. In contrast, spin-orbit torque (SOT) MRAM induces the switching of the spin direction of electrons by applying a current to a heavy metal layer (or spin-orbit torque (SOT) layer) adjacent to the MTJ stack. The current is applied to the SOT layer in the in-plane direction relative to the MTJ stack. The manufacture of SOT-MRAM devices can be challenging because conventional SOT-MRAM structures have poor thermal stability and current loss due to the size mismatch between the MTJ stack and the SOT layer.

[0003] Therefore, there remains a need in the art for more robust SOT-MRAM devices and methods of fabricating the same. Summary of the invention

[0004] Examples of the present disclosure provide improved SOT-MRAM devices and methods of manufacturing the same. In one example, a memory device includes a first structure including a magnetic tunnel junction stack and a spin-orbit moment layer. The spin-orbit moment layer is formed on the magnetic tunnel junction stack. A dielectric cap layer is formed on the spin-orbit moment layer. A metal layer is formed on top of the first structure. The metal layer surrounds each of the spin-orbit moment layer and the dielectric cap layer. The metal layer is in direct contact with a sidewall of the spin-orbit moment layer.

[0005] In another example, a memory device includes a magnetic tunnel junction stack having a first intermediate layer and a second intermediate layer. A spin-orbit moment layer is formed on the magnetic tunnel junction stack. A dielectric cover layer is formed on the spin-orbit moment layer. A cladding layer is disposed on the magnetic tunnel junction stack and in direct contact with the magnetic tunnel junction stack. A metal layer is formed on top of the cladding layer, the metal layer surrounding each of the spin-orbit moment layer and the dielectric cover layer. The metal layer is in direct contact with a sidewall of the spin-orbit moment layer. The first intermediate layer is formed on a substrate and in contact with the substrate. The second intermediate layer is formed below the spin-orbit moment layer and in contact with the spin-orbit moment layer.

[0006] In another example, a method of forming a memory device includes: depositing a cladding layer on a first structure. The first structure includes a magnetic tunnel junction stack. The first structure includes a spin-orbit moment layer formed on the magnetic tunnel junction stack and a dielectric cap layer formed on the spin-orbit moment layer. A dielectric layer is deposited on the cladding layer. A trench is formed in the dielectric layer by removing a portion of the dielectric layer and a portion of the cladding layer. A metal layer is deposited in the trench via at least one of chemical vapor deposition (CVD) or physical vapor deposition (PVD). The metal layer is deposited on top of the dielectric layer. The metal layer surrounds the spin-orbit moment layer and the dielectric cap layer. The metal layer is in direct contact with a sidewall of the spin-orbit moment layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] A more detailed description of the present disclosure briefly summarized above can be obtained by reference to some of the examples illustrated in the accompanying drawings, and the manner in which the above-mentioned features of the present disclosure can be understood in detail. However, it should be noted that the accompanying drawings illustrate only exemplary examples of the present disclosure and are therefore not to be considered as limiting the scope of the present disclosure, as the present disclosure may admit to other equally effective examples.

[0008] Figure 1 is a cross-sectional view of a bottom-pinned spin-orbit torque MRAM device fabricated according to an example of the present disclosure.

[0009] FIG. 2A to FIG. 2D A top view of a SOT-MRAM device fabricated according to an example of the present disclosure is illustrated.

[0010] Figure 3 is a flow chart of a method of manufacturing a SOT-MRAM according to an example of the present disclosure.

[0011] 4A to 4F is a diagram of a structure resulting from a manufacturing method according to an example of the present disclosure.

[0012] Figure 5 is a flow chart of a method of manufacturing a SOT-MRAM according to an example of the present disclosure.

[0013] 6A to 6H A structure resulting from a manufacturing method according to an example of the present disclosure is described.

[0014] To facilitate understanding, identical reference numerals have been used, wherever possible, to designate identical elements that are common to the figures. It is contemplated that elements and features disclosed in one example may be beneficially incorporated in other examples without repetition. DETAILED DESCRIPTION

[0015] Examples of the present disclosure generally include bottom-pinned spin-orbit moment magnetoresistive random access memory (SOT-MRAM) and methods for manufacturing the same. Top-pinned SOT-MRAM devices may have poor thermal stability during manufacturing operations (e.g., annealing), which may negatively impact the magnetic and electrical properties of the SOT-MRAM devices. In addition, due to the width difference between the MTJ stack and the SOT layer, the top-pinned SOT-MRAM component suffers from current loss, which reduces the switching efficiency of the SOT-MRAM device. In addition, the top-pinned structure uses the SOT layer as an etch stop layer, which may negatively impact the quality of the SOT layer. Conventional methods for manufacturing bottom-pinned SOT-MRAM may be challenging, for example, because defects may occur in the free layer of the magnetic tunnel junction (MTJ) stack. Defects can occur in the free layer because, for example, the free layer is exposed to the surrounding air during the patterning process of the MTJ stack before the SOT layer is deposited. Defects in the free layer can cause challenges in the deposition of subsequent layers on the free layer, including a spin-orbit moment (SOT) layer. Therefore, defects in the free layer may negatively impact the performance of a SOT-MRAM device.

[0016] Using the systems and methods discussed herein, a bottom pinned SOT-MRAM device is manufactured by in-situ depositing an MTJ stack and an SOT layer without breaking vacuum to form a high-quality interface between the MTJ stack and the SOT layer. The MTJ stack and the SOT layer can be formed in a single processing chamber or in an integrated tool including multiple processing chambers. The substrate transferred between the processing chambers of the integrated tool is kept under vacuum. The high-quality interface between the SOT layer and the MTJ stack can promote a strong pinning anisotropy field (Hk) and high thermal stability at high temperatures of up to 450°C. The bottom pinned SOT-MRAM structure manufactured herein electrically couples metal lines to two or more sides of the SOT layer to transmit current through the SOT layer without the possibility of the metal line contacting the top of the SOT layer, which may cause current loss.

[0017] Figure 1 is a cross-sectional view of a bottom-pinned spin-orbit torque MRAM (SOT-MRAM) device 100 fabricated according to an example of the present disclosure. Figure 1The SOT-MRAM device 100 in the embodiment includes an MTJ stack 110 formed on a metal contact 102, and a dielectric layer such as an oxide layer 104 is formed to surround the metal contact 102. The MTJ stack 110 includes a pinning layer 112 formed on the metal contact 102, which also contacts a reference layer 114. The pinning layer 112 can be formed as a single layer or multiple intermediate layers, and can be formed of a material such as cobalt (Co) on a single seed layer (not shown here) or multiple seed layers. In other examples of the pinning layer 112, platinum (Pt) can be used alone or in combination with other materials. The reference layer 114 is formed below a tunnel barrier layer 116. The tunnel barrier layer 116 can be formed as a single layer or multiple intermediate layers, and can be formed of one or more oxides, such as magnesium oxide (MgO). The reference layer 114 can be formed as a single layer or multiple intermediate layers. The reference layer 114 can include one or more of CoFe, CoFeB, FeB, Ta, Mo, ruthenium (Ru), or a combination of the foregoing materials. The MTJ stack 110 further includes an outermost layer, which is a free layer 118 in direct contact with the SOT layer 124 and the tunnel barrier layer 116. The free layer 118 can be formed as a single layer or multiple intermediate layers. The free layer 118 can be formed to include CoFeB and / or other magnetic materials. Depending on the example, each of the free layer 118, the tunnel barrier layer 116, the reference layer 114, and the pinned layer 112 can be a single layer or can include an intermediate layer. In some examples of the MTJ stack 110, additional layers can be included between the pinned layer 112 and the free layer 118. The reference layer 114, the tunnel barrier layer 116, and the free layer 118 are arranged so that when the directions of the electron spin polarizations of the reference layer 114 and the free layer 118 are aligned parallel, the current through the tunnel barrier layer 116 is high, resulting in a low resistance state of the MTJ stack 110. When the polarization directions of the reference layer 114 and the free layer 118 are antiparallel, the resistance of the MTJ stack 110 becomes large (increased). The SOT layer 124 is deposited on top of the MTJ stack 110, and the dielectric cap layer 122 is deposited on the SOT layer 124. The SOT layer 124 can be formed of tungsten (W), tantalum (Ta), platinum (Pt), or a combination of the above materials or an alloy of the above materials. Depending on the example, the thickness 130 of the SOT layer 124 can be about 3 mm thick to about 10 mm thick. The MTJ stack 110 and the SOT layer 124 are formed in a series of operations performed under vacuum as discussed below. The dielectric cap layer 122 can be formed of oxide, nitride, or a combination of oxide and nitride, and can vary in thickness depending on the application. In various examples, the dielectric cap layer 122 can be formed in-situ when the SOT layer 124 is formed.In another example, the dielectric cap layer 122 can be formed in a different processing chamber (ex-situ) than the processing chamber used to form the SOT layer 124. The dielectric cap layer 122 is formed in part by etching a target stack including the MTJ stack 110, the SOT layer 124, and the dielectric cap layer 122. Figure 1 The structure in .

[0018] Further, in the SOT-MRAM device 100, the cladding layer 106 extends around the MTJ stack 110 and along the oxide layer 104. The cladding layer 106 can be formed of one or more dielectric materials, such as SiN, SiCN, SiON, Al2O3, or other materials. The cladding layer 106 is formed to cover the sidewalls 110A of the MTJ stack 110, the sidewalls 126 of the SOT layer 124, and the dielectric cap layer 122. The cladding layer 106 further extends along the top surface 128 of the dielectric cap layer 122 and the sidewalls 132 of the dielectric cap layer 122. In one example, the cladding layer 106 extends along the sidewalls 126 of the SOT layer 124 by a distance that is about 1% to about 60% of the thickness 130 of the SOT layer 124. The cladding layer 106 extends along a portion of the sidewall 126 of the SOT layer 124 to protect the free layer 118 from the patterning process. The cladding layer 106 further serves to separate the metal contact 102 from the dielectric filling layer 108 .

[0019] The dielectric fill layer 108 is formed to surround the cladding layer 106. The dielectric fill layer 108 can be formed as one or more oxides and / or nitrides with a thickness of about 10 nm to about 100 nm. In one example, the dielectric fill layer 108 is formed of silicon dioxide (SiO2). The metal layer 120 surrounds the dielectric cap layer 122 and the SOT layer 124. The metal layer 120 can be formed of copper (Cu), W, Ta, tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or a combination of the above materials. The metal layer 120 can refer to a metal line or a plurality of metal lines because the metal layer 120 is electrically coupled to the SOT layer 124 and is used to transmit current through the SOT layer 124. In one example, the metal layer 120 does not contact the top surface 134 of the SOT layer 124, thereby preventing current loss during device operation. In various examples, metal layer 120 can contact two or more areas along sidewalls 126 of SOT layer 124, depending on factors including the cross-sectional geometry of the top view of SOT layer 124. In one example, metal layer 120 contacts less than all of sidewalls 126 of SOT layer 124.

[0020] FIG. 2A to FIG. 2D A top view illustrating an example of a SOT-MRAM device fabricated according to an example of the present disclosure. FIG. 2A to FIG. 2CThe top view shown in FIG. 1 is a polygonal shape similar to a square, but it is considered that in other examples, the cross-sectional geometry of the top view including the SOT layer 124 can be a circle (eg, Figure 2D ), elliptical, triangular, or other shapes or combinations of shapes that can be aligned with the metal layer 120 in various ways. FIG. 2A to FIG. 2D The dielectric cover layer 122 is formed on Figure 1 On top of the SOT layer 124 shown in FIG. Figures 2A-2D 1 is used to illustrate the position of the SOT layer 124 relative to the metal layer 120 and the dielectric fill layer 108. Conventionally, current loss may occur if the SOT layer 124 is not aligned with the metal layer 120. However, in the example of the SOT-MRAM device discussed herein, the misalignment does not have a similar effect at least because of how the metal layer 120 electrically couples two or more portions of the sidewall 126 of the SOT layer 124.

[0021] Figure 2A An exemplary SOT-MRAM device fabricated according to an example of the present disclosure is shown having a SOT layer 124 aligned along a central axis 202 shared with a metal layer 120. Depending on the example, the metal layer 120 can be in direct contact with two parallel sidewall portions 126A and 126B or 126C and 126D of the SOT layer 124. Figure 2A , the third sidewall portion 126C and the fourth sidewall portion 126D are aligned with the side surfaces (120A, 120B) of the metal layer 120. In contrast to conventional devices in which the sidewalls of the SOT layer 124 are not aligned with the metal layer 120, in Figure 2A The metal layer 120 in the SOT layer 124 is aligned with two sidewalls ( 126C, 126D). Figure 1 The sidewall 126 of the SOT layer 124 is shown in FIG. Figure 2A The sidewall 126 of the SOT layer 124 is further shown as a first sidewall portion 126A, a second sidewall portion 126B, a third sidewall portion 126C, and a fourth sidewall portion 126D. The first sidewall portion 126A is opposite and parallel to the second sidewall portion 126B. The third sidewall portion 126C is opposite and parallel to the fourth sidewall portion 126D.

[0022] Figure 2B Show similar Figure 2A But with Figure 2A A contrasting structure. Figure 2B The SOT layer 124 in FIG. 1 is offset from the central axis 202 , and at least one sidewall portion, such as the fourth sidewall portion 126D, can be in direct contact with the dielectric fill layer 108 . Figure 2C Displays something like Figure 2A and Figure 2B The structure, however, is similar to Figure 2A and Figure 2B In contrast, the SOT layer 124 is further offset (misaligned) from the central axis 202 , such that a portion of the SOT layer 124 overhangs the metal layer 120 along the fourth sidewall portion 126D. Figure 2D Displays something like Figure 2A The structure has a circular cross-sectional shape defined by the sidewalls 126. In this example, the metal layer 120 can be in contact with all of the sidewalls 126 or with less than all of the sidewalls 126, for example, 10%-90% of the circumference of the sidewalls 126.

[0023] exist FIG. 2A to FIG. 2D In any example, the SOT-MRAM device transmits current through the SOT layer 124 via a metal line (electrically coupled to the SOT layer 124) formed by the metal layer 120. As discussed below, the metal layer 120 is not disposed on the SOT layer 124, which reduces current loss and increases the switching efficiency of the SOT-MRAM device.

[0024] Some examples are as follows: Figure 3 and 4A to 4F As shown and discussed, the third sidewall portion 126C and the fourth sidewall portion 126D contact the dielectric fill layer 108. In other examples, as described below, Figure 5 and 6A to 6H As shown and discussed in FIG. 1 , the third sidewall portion 126C and the fourth sidewall portion 126D do not contact the dielectric fill layer 108. In other examples, such as Figure 5 and 6A to 6H As shown and discussed in , the metal layer 120 can be in direct contact with all of the sidewall portions 126A, 126B, 126C, 126D of the SOT layer 124 .

[0025] The bottom pinned SOT-MRAM devices discussed herein can be fabricated in a variety of ways. Exemplary methods and structures resulting from these methods are discussed below. Various elements of the methods below can be combined and utilized to form the SOT-MRAM structures discussed herein. Depending on the example, the metal layer 120 for forming a metal line electrically coupling the SOT layer 124 can be configured to contact two or more sidewall portions of the SOT layer 124. Figures 3 to 6H Various fabrication operations and sub-operations for fabricating bottom-pinned SOT-MRAM structures, and the resulting structures, are discussed. It is contemplated that elements of the methods discussed herein can be combined to form SOT-MRAM devices having high-quality MTJ stack / SOT layer interfaces and commercially viable magnetic and electrical properties.

[0026] Figure 3is a flow chart of a method 300 for manufacturing a SOT-MRAM according to an example of the present disclosure. 4A to 4F The structure resulting from the operations of the manufacturing method 300 is described. Figure 3 and 4A to 4F ,and Figure 3 and 4A to 4F It is aimed at forming Figure 1 Therefore, in the following, Figure 3 and Figure 4 discussed in Figure 1 In the manufacturing method 300, in operations 302 and 304, Figure 4A The structure in is formed in multiple sub-operations, which include forming a target stack and patterning the target stack.

[0027] In operation 302, a target stack is formed, which includes an MTJ stack 110 formed on a metal contact 102, an SOT layer 124 formed on the MTJ stack 110, and a dielectric cap layer 122 formed on the SOT layer. The MTJ stack 110 can be formed in operation 302 in a series of physical vapor deposition (PVD) sputtering sub-operations without breaking vacuum between the formation of the layers. Therefore, each of the pinned layer 112, the reference layer 114, the tunnel barrier layer 116, and the free layer 118 is formed in a processing chamber maintained at a vacuum pressure. One or more sputtering targets can be used in the PVD sputtering operation to form the pinned layer 112 (e.g., formed of Co and / or Pt) and the reference layer 114 is formed of CoFe, CoFeB, ruthenium (Ru), or a combination of the above materials. Furthermore, in the sub-operation of operation 302, the tunnel barrier layer 116 is formed via PVD sputtering of magnesium oxide (MgO) or PVD sputtering of magnesium (Mg) followed by oxidation, and the free layer 118 is formed by sputtering one or more targets to form a CoFeB layer.

[0028] Further in a sub-operation of operation 302, a SOT layer 124 is deposited on the MTJ stack 110 via PVD sputtering. As discussed above, the SOT layer 124 is formed of tungsten (W), tantalum (Ta), platinum (Pt), or a combination of the above materials or an alloy of the above materials to a thickness of 3 mm to 10 mm. A vacuum pressure is maintained in one or more processing chambers used to form the MTJ stack 110 between forming the outermost layer (free layer 118) of the MTJ stack 110 and forming the SOT layer 124. Maintaining a vacuum between the fabrication of the layers of the MTJ stack 110 and the SOT layer 124 facilitates the formation of high-quality interfaces between the layers of the MTJ stack and between the free layer 118 and the SOT layer 124. The high-quality interface formed between the free layer 118 and the SOT layer 124 under vacuum results in improved performance of the SOT-MRAM device.

[0029] Further, in operation 302, a dielectric capping layer 122 can be formed in-situ or ex-situ (with or without breaking the vacuum) in operation 302 using PVD, CVD, or other methods or a combination of the above methods. In one example, the dielectric capping layer 122 is formed on the SOT layer 124 without breaking the vacuum. In another example, the dielectric capping layer 122 is formed ex-situ on the SOT layer 124, wherein the vacuum is broken after the SOT layer 124 is formed, and the vacuum may or may not be re-established for forming the dielectric capping layer 122. Further, a sub-operation of operation 302 can include depositing one or more optional hard mask layers on the dielectric capping layer 122 (not shown here), and the hard mask layer can be used for patterning in operation 304. The target stack formed in the sub-operation of operation 302 is patterned (etched) in operation 304 to form a plurality of structures, and in Figure 4A One of the structures is shown in FIG. Each structure formed by the target stack includes an MTJ stack 110, a SOT layer 124, and a dielectric cap layer 122. Each structure is in contact with a metal contact 102. FIG. 2A to FIG. 2C As shown, each structure formed by the target stack during operation 302 can have a top-view cross-section that is polygonal (including rectangular or square), circular, elliptical, triangular, or a combination of the above shapes.

[0030] In operation 306, Figure 4A A cladding layer 106 is formed around the patterned structure to cover the MTJ stack 110, the SOT layer 124 and the dielectric cap layer 122, thereby forming Figure 4BThe structure shown. The cladding layer 106 can be formed using CVD, atomic layer deposition (ALD), or PVD at step 306. The cladding layer 106 protects the MTJ stack 110 during manufacturing, for example, by preventing the MTJ stack from oxidizing. The cladding layer 106 can be formed of SiN, SiCN, SiON, Al2O3, or other materials or combinations thereof to various thicknesses, for example, from 5 nm to 30 nm.

[0031] At operation 308, a dielectric fill layer 108 is deposited on the cladding layer 106 and the dielectric fill layer 108 is planarized. The dielectric fill layer 108 can be deposited using CVD at operation 308. During the planarization at operation 308, a portion of the dielectric fill layer 108 can be removed using chemical mechanical polishing (CMP) to form a top portion 404 of the dielectric fill layer 108 that is substantially coplanar with the top portion 402 of the cladding layer 106, as shown in FIG. Figure 4C shown.

[0032] At operation 310, SOT metal line lithography is performed to form a plurality of metal lines that electrically couple the SOT layer 124 to pass current through the SOT layer 124. Operation 310 includes sub-operations 312-316. At sub-operation 312, a photoresist is disposed on Figure 4C , and then patterning the photoresist. In operation 314, the recess is etched using the photoresist formed and patterned in sub-operation 312. The etching in operation 314 is a selective etching operation that removes the dielectric filling layer 108 and the cladding layer 106, but does not etch the dielectric cap layer 122 in the same amount. During the etching in operation 314, a portion of the dielectric filling layer 108 and a portion of the cladding layer 106 are removed, and a trench 410 is formed. The formation of the trench 410 exposes all or a portion of the four sidewalls 126 of the SOT layer 124. Figure 4D The structure resulting from operation 314 is shown. Figure 4F show Figure 4D , which illustrates a trench 410 formed through the dielectric fill layer 108. In particular, Figure 4D A structure is shown in which a portion of the dielectric fill layer 108 and a portion of the cladding layer 106 have been removed. The formation of the trench 410 exposes the top of the dielectric cap layer 122 and two or more portions of the sidewalls 126 of the SOT layer 124. As discussed above, the cladding layer 106 may not be completely removed from the sidewalls 126 of the SOT layer 124. During the etching of operation 314, the portion of the cladding layer 106 that remains on the sidewalls 126 of the SOT layer 124 protects the free layer 118 below. In one example, at operation 314, about 10% to about 90% of the height of the sidewalls 126 of the SOT layer 124 can be exposed.

[0033] In operation 316, a metal layer 120 is deposited in the trench 410 formed in operation 314 to form a metal line electrically coupled to the sidewall 126 of the SOT layer 124. In operation 316, the metal layer 120 can be deposited via CVD or PVD. Further, in operation 318, the metal layer 120 can be planarized via CMP to remove a portion so that the top surface 406 of the dielectric cap layer 122 is coplanar with the top surface 408 of the metal layer 120, as shown in FIG. Figure 4E At operation 320, further operations can be performed on the SOT-MRAM device, including an annealing operation. Figure 4F The structure shown is fabricated to withstand further processing at temperatures on the order of 400°C while maintaining commercially viable electrical and magnetic properties.

[0034] The SOT-MRAM device discussed in this article can be used as Figure 3 and 4A to 4F As shown and discussed in , a trench is formed and filled with a metal material to form a metal line electrically coupling the SOT layer. In other examples, as described below in Figure 5 and 6A to 6H As shown and discussed in , recesses can be formed in the dielectric fill layer (rather than trenches), thereby exposing additional surface area of ​​the SOT layer for coupling to metal lines formed from the metal layer.

[0035] Figure 5 is a flow chart of a method 500 for fabricating a SOT-MRAM device according to an example of the present disclosure. FIG. 6A to FIG. 6G The structure resulting from the operations of the manufacturing method 500 is described. In the manufacturing method 500, operations 302, 304, and 306 are performed as discussed above with respect to the manufacturing method 300 to form the MTJ stack 110 and the SOT layer 124 under vacuum. Also, as discussed above, the dielectric cap layer 122 is formed on the SOT layer 124, and the MTJ stack 110 is patterned to form a plurality of structures. Fig. 6A An exemplary structure is shown in FIG. In operation 306, the coating layer 106 is coated Fig. 6A The resulting structure is shown in Figure 6B In operation 308, a dielectric fill layer 108 is formed on the cladding layer 106. The dielectric fill layer 108 can include oxide, nitride, or alternating layers of oxide and nitride. Further, in operation 308, the dielectric fill layer 108 is planarized by CMP. After planarization in operation 308, the top 402 of the cladding layer 106 is coplanar with the top 404 of the dielectric fill layer 108, as shown in FIG. Figure 6C shown.

[0036] In operation 502, a recess 610 is formed in the dielectric fill layer 108. Fig.6D is the cross section, and Fig. 6E The figure is a perspective view. Fig.6D and Fig. 6E As shown, a recess 610 in the dielectric filling layer 108 is formed around the entire SOT layer 124 (all four sides thereof) and the dielectric cap layer 122. The recess 610 can be formed using etching in operation 502 without photolithography. Forming the recess in operation 502 removes a portion of the dielectric filling layer 108 and a portion of the capping layer 106. The recess 610 is formed to expose at least a portion (sidewall portion) of all four sides of the sidewall 126 of the SOT layer 124. In contrast, in some examples, the trench 410 formed in operation 308 of the manufacturing method 300 is formed so that two parallel sidewalls of the SOT layer 124 are exposed, and the remaining two sidewalls are not exposed, thereby maintaining contact with the dielectric filling layer 108. In other examples, the trench 410 formed in operation 308 can expose more than two sidewall portions.

[0037] In operation 504, a metal layer 120 is deposited using CVD or PVD and then patterned via photolithography. The metal layer 120 is formed to contact and electrically couple with one or more portions of the sidewalls 126 of the SOT layer 124 exposed in operation 502. Fig. 6F The structure resulting from operation 504 is shown, Fig. 6F The metal layer 120 can further be shown in contact with a top surface 608 of the dielectric cap layer 122 . Fig. 6F The metal layer 120 is shown to include two portions. A first portion 120A of the metal layer 120 is formed on the dielectric fill layer 108. A second portion 120B of the metal layer 120 is formed on the dielectric cap layer 122 and extends beyond the first portion 120A by a distance 120C. At operation 506, the patterned surface (not shown in the cross-sectional view herein) resulting from the metal lithography at operation 504 is filled with a dielectric material 602, such as Figure 6G As shown. In operation 506, dielectric material 602 can be deposited by using CVD. In another example, in operation 506, dielectric material 602 can be deposited by using PVD. Dielectric material 602 can include one or more oxides, nitrides, or other dielectric materials, or multiple layers of dielectric materials. In one example, dielectric material 602 includes multiple alternating oxide and nitride layers.

[0038] At operation 508, CMP is used to remove at least a portion of the dielectric material 602 to planarize the surface of the structure. Figure 6HAs shown, the planarization at operation 508 causes the top surface 608 of the dielectric cap layer 122 to be coplanar with the top surface 604 of the dielectric material 602. The planarization at operation 508 also causes the top surface 608 of the dielectric cap layer 122 to be coplanar with the top surface 606 of the metal layer 120. Although Figure 6H A portion 602A of dielectric material 602 is shown remaining after the CMP of operation 508, but it is contemplated that in other examples, operation 508 removes substantially all of dielectric material 602 to expose metal layer 120. At operation 510, further operations can be performed on the SOT-MRAM device, including an annealing operation. Figure 6H The structure shown is fabricated to withstand further processing at temperatures up to 450° C. while maintaining commercially viable electrical and magnetic properties. At operation 510 , the SOT-MRAM device formed at operations 302 - 308 and 502 - 508 can undergo further processing including thermal processing.

[0039] The bottom pinned SOT-MRAM device discussed herein is manufactured to form an MTJ stack and a SOT layer under vacuum to establish a high-quality interface between the free layer and the SOT layer of the MTJ stack. Further, a SOT-MRAM device manufactured according to an example of the present disclosure is formed to couple a metal line to one or more sides of the SOT layer without contacting the top of the SOT layer. In contrast to the top pinned structure using the SOT layer as an etch stop layer, a cladding layer is used as a protective layer to protect the free layer of the MTJ stack. The cladding layer is further configured to protect a portion of the free layer and the SOT layer of the MTJ stack to prevent etching of the free layer. In addition, the bottom pinned SOT-MRAM device can be configured to have an improved coverage margin for the MTJ stack and the SOT layer to reduce current loss and improve switching efficiency.

[0040] While the foregoing is directed to examples of the present disclosure, other and further examples of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is to be determined by the claims that follow.

Claims

1. A method of forming a memory device, comprising: depositing a cladding layer on a first structure, the first structure comprising a magnetic tunnel junction stack, a spin-orbit moment layer formed on the magnetic tunnel junction stack, and a dielectric cap layer formed on the spin-orbit moment layer; depositing a dielectric layer on the cladding layer; forming a trench in the dielectric layer by removing a portion of the dielectric layer and a portion of the cladding layer; and depositing a metal layer in the trench via at least one of chemical vapor deposition (CVD) or physical vapor deposition (PVD), the metal layer being deposited on top of the dielectric layer and surrounding the spin-orbit moment layer and the dielectric cap layer, the metal layer being in direct contact with the sidewalls of the spin-orbit moment layer, The magnetic tunnel junction stack and the spin-orbit moment layer are deposited in situ without breaking the vacuum.

2. The method of claim 1, wherein the spin-orbit moment layer is formed of tungsten (W), tantalum (Ta), platinum (Pt), or a combination of the above materials, or an alloy of the above materials, and is formed to a thickness of from 3 mm to 10 mm.

3. The method of claim 1 , wherein forming the trench exposes the dielectric cap layer and a first sidewall portion of the sidewall of the spin-orbit moment layer, wherein: After forming the trench, the cladding layer directly contacts a second sidewall portion of the spin-orbit moment layer, the second sidewall portion being adjacent to the magnetic tunnel junction stack.

4. The method of claim 1 , wherein forming the trench comprises: The portion of the dielectric layer and the portion of the cladding layer are removed from at least two sides of the spin-track moment layer.

5. The method of claim 1, further comprising: Forming a target stack, wherein forming the target stack comprises: Depositing the magnetic tunnel junction stack under vacuum pressure on a substrate positioned in a processing chamber, wherein forming the magnetic tunnel junction stack comprises: depositing a pinning layer on the substrate; depositing a reference layer on the pinned layer; depositing a tunnel barrier layer on the reference layer; and depositing a free layer on the tunnel barrier layer; depositing the spin-orbit moment layer on the free layer of the magnetic tunnel junction stack while maintaining the magnetic tunnel junction stack at a vacuum pressure; and The dielectric cap layer is deposited on the spin-orbit moment layer.

6. The method of claim 5, further comprising: The target stack is patterned to form a plurality of structures including the first structure.

7. A method of forming a memory device, comprising: Depositing a first dielectric layer on a cladding layer formed on a first structure, wherein the first structure includes a magnetic tunnel junction stack, a spin-orbit moment layer formed on the magnetic tunnel junction stack, and a dielectric cap layer formed on the spin-orbit moment layer; forming a trench in the first dielectric layer by removing a portion of the first dielectric layer and a portion of the cladding layer; Depositing a metal layer in the trench via at least one of chemical vapor deposition (CVD) or physical vapor deposition (PVD), the metal layer being deposited on top of the first dielectric layer and surrounding the spin-orbit moment layer and the dielectric cap layer, the metal layer being in direct contact with a sidewall of the spin-orbit moment layer; and depositing a second dielectric filling layer on the metal layer, The magnetic tunnel junction stack and the spin-orbit moment layer are deposited in situ without breaking the vacuum.

8. The method of claim 7, wherein depositing the metal layer in the trench comprises: The metal layer is deposited to include a first portion of the metal layer and a second portion of the metal layer, the second portion extending beyond the first portion a predetermined distance. 9 . The method of claim 8 , wherein the first portion is formed on the second dielectric filling layer and the second portion is formed on the dielectric capping layer, the first portion further being in contact with the spin-track moment layer.

10. The method of claim 7, further comprising: The second dielectric layer is planarized to expose the dielectric cap layer, wherein after planarizing the second dielectric layer, a first top surface of the second dielectric layer is coplanar with a second top surface of the dielectric cap layer. 11 . The method of claim 10 , wherein planarizing the second dielectric layer further comprises exposing a portion of the metal layer, the portion of the metal layer being adjacent to the dielectric cap layer.

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