Semiconductor Package

Abstract

A semiconductor package is provided. The semiconductor package may include a package substrate, a semiconductor chip, a signal bump, and a first heat dissipation bump and a second heat dissipation bump. The semiconductor chip may be stacked on the upper surface of the package substrate, with a first region and a second region having different heat dissipation efficiencies. The second temperature may be higher than the first temperature. The signal bump may be arranged between the semiconductor chips. The first heat dissipation bump may be arranged between the semiconductor chips in the first region at a first pitch. The second heat dissipation bump may be arranged between the semiconductor chips in the second region at a second pitch narrower than the first pitch. The heat generated from the second region of the semiconductor chip may be dissipated by the second heat dissipation bumps that may be arranged relatively closely to each other.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2020-0023342 filed on February 26, 2020 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Some example embodiments relate to a semiconductor package and / or a method of manufacturing the semiconductor package. More specifically, some example embodiments relate to a semiconductor package including stacked high bandwidth memory (HBM) chips and / or a method of manufacturing the semiconductor package. Background Art

[0003] Typically, a high bandwidth memory (HBM) chip may be stacked on the upper surface of a package substrate. The HBM chip may be electrically connected to the package substrate via a signal bump. In addition, in order to dissipate the heat generated from the HBM chip, a heat dissipation bump may be arranged between the HBM chips.

[0004] According to the related art, for example, during operation, the central portion of the stacked HBM chip may have a higher temperature than the edge portion of the stacked HBM chip. However, the heat dissipation bumps may be arranged to be spaced apart from each other at the same pitch. Therefore, the central portion of the stacked HBM chip having a relatively high temperature may have a low heat dissipation effect. Summary of the invention

[0005] Some example embodiments provide a semiconductor package having improved heat dissipation characteristics.

[0006] Some example embodiments also provide a method of manufacturing the above-mentioned stack package.

[0007] According to some example embodiments, a semiconductor package may include a package substrate, a plurality of semiconductor chips, a plurality of signal bumps, a plurality of first heat dissipation bumps, and a plurality of second heat dissipation bumps. The plurality of semiconductor chips may be stacked on an upper surface of the package substrate. The semiconductor chip may have a first region and a second region. The plurality of signal bumps may be arranged between the semiconductor chips. The plurality of first heat dissipation bumps may be arranged between the plurality of semiconductor chips in the first region at a first pitch. The plurality of second heat dissipation bumps may be arranged between the plurality of semiconductor chips in the second region at a second pitch narrower than the first pitch, so that the second region has a higher heat dissipation efficiency than the first region.

[0008] According to some example embodiments, a semiconductor package may include a package substrate, a plurality of semiconductor chips, a plurality of signal bumps, and a plurality of heat dissipation bumps. The plurality of semiconductor chips may be stacked on an upper surface of the package substrate. The plurality of signal bumps may be arranged between the plurality of semiconductor chips. The plurality of heat dissipation bumps may be arranged between the plurality of semiconductor chips at a gradually decreasing pitch from edge portions of the plurality of semiconductor chips to a central portion of the plurality of semiconductor chips.

[0009] According to some example embodiments, a semiconductor package may include a package substrate, a plurality of high bandwidth memory (HBM) chips, a plurality of signal bumps, a plurality of first heat dissipation bumps, a plurality of second heat dissipation bumps, and an underfill layer. The plurality of HBM chips may be stacked on an upper surface of the package substrate. The plurality of HBM chips may have an edge region and a central region. Each of the plurality of HBM chips may include a plurality of signal pillars, a plurality of first heat dissipation pillars arranged in the edge region at a first pitch, and a plurality of second heat dissipation pillars arranged in the central region at a second pitch not greater than 1 / 2 times the first pitch. The plurality of signal bumps may be arranged between the plurality of HBM chips. The plurality of signal bumps may be electrically connected to the plurality of signal pillars. The plurality of first heat dissipation bumps may be arranged in the edge region at a first pitch. The plurality of first heat dissipation bumps may be connected to the plurality of first heat dissipation pillars. The plurality of second heat dissipation bumps may be arranged in the central region at a second pitch. The plurality of second heat dissipation bumps may be connected to the plurality of second heat dissipation pillars so that the central portion may have a heat dissipation efficiency higher than that of the edge portion. The bottom filling layer may be between the plurality of HBM chips and may surround the plurality of signal bumps, the plurality of first heat dissipation bumps, and the plurality of second heat dissipation bumps.

[0010] According to some example embodiments, a method for manufacturing a semiconductor package may be provided. In the method for manufacturing a semiconductor package, a plurality of semiconductor chips may be stacked on an upper surface of a package substrate. The plurality of semiconductor chips may have a first region and a second region. A plurality of signal bumps may be arranged between the plurality of semiconductor chips. A plurality of first heat dissipation bumps may be arranged between the plurality of semiconductor chips in the first region at a first pitch. A plurality of second heat dissipation bumps may be arranged between the plurality of semiconductor chips in the second region at a second pitch narrower than the first pitch, so that the second region may have a heat dissipation efficiency higher than that of the first region.

[0011] According to some example embodiments, the second pitch of the second heat dissipation bumps in the high temperature region of the stacked semiconductor chips may be narrower than the first pitch of the first heat dissipation bumps in the low temperature region of the stacked semiconductor chips, so that the number of the second heat dissipation bumps in the high temperature region of the stacked semiconductor chips may be increased. Therefore, the heat generated from the high temperature region of the stacked semiconductor chips may be effectively dissipated by the second heat dissipation bumps that are arranged relatively closely to each other. As a result, the semiconductor package may have low heat resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Some example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 13 represents non-limiting examples of some example embodiments as described herein.

[0013] Figure 1 is a cross-sectional view illustrating a semiconductor package according to some example embodiments;

[0014] Figure 2 It is shown Figure 1 A cross-sectional view of a signal bump of a semiconductor package in FIG.

[0015] Figure 3 It is shown Figure 1 a plan view of a first semiconductor chip of a semiconductor package in;

[0016] Figures 4 to 6 It shows the manufacturing Figure 1 A cross-sectional view of a method for a semiconductor package in FIG.

[0017] Figure 7 is a cross-sectional view illustrating a semiconductor package according to some example embodiments;

[0018] Figure 8 It is shown Figure 7 a plan view of a first semiconductor chip of a semiconductor package in;

[0019] Fig. 9 is a cross-sectional view illustrating a semiconductor package according to some example embodiments;

[0020] Fig.10 It is shown Fig. 9 a plan view of a first semiconductor chip of a semiconductor package in;

[0021] Fig.11 is a cross-sectional view illustrating a semiconductor package according to some example embodiments;

[0022] Fig.12 is a cross-sectional view illustrating a semiconductor package according to some example embodiments; and

[0023] Fig.13is a cross-sectional view illustrating a semiconductor package according to some example embodiments. DETAILED DESCRIPTION

[0024] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the boundaries of the shape are within the disclosed range. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value or shape.

[0025] Hereinafter, some example embodiments will be explained in detail with reference to the accompanying drawings.

[0026] Figure 1 is a cross-sectional view illustrating a semiconductor package according to some example embodiments, Figure 2 It is shown Figure 1 A cross-sectional view of a signal bump of a semiconductor package in FIG. Figure 3 It is shown Figure 1 A plan view of a first semiconductor chip in a semiconductor package.

[0027] Reference Figures 1 to 3 The semiconductor package 100 of the present example embodiment may include a package substrate 110, a plurality of semiconductor chips (e.g., a plurality of semiconductor chips such as first to fourth semiconductor chips 120, 130, 140, and 150), a signal bump 190, a signal column 192, a first heat dissipation bump 170, a second heat dissipation bump 172, a first heat dissipation column 180, a second heat dissipation column 182, a bottom filling layer 200, a molding member 210, and an external terminal 220.

[0028] The package substrate 110 may include a signal post. Each signal post may correspond to a through silicon via (TSV, also referred to as a "Through Silicon Via"). The signal post may be vertically arranged in the package substrate 110. Specifically, the signal post may be arranged at the central portion of the package substrate 110. Each signal post may include an upper end exposed through the upper surface of the package substrate 110 and a lower end exposed through the lower surface of the package substrate 110. The package substrate 110 may be referred to as a buffer substrate.

[0029] The first to fourth semiconductor chips 120, 130, 140, and 150 may be sequentially stacked on the central portion of the upper surface of the package substrate 110. Each of the first to third semiconductor chips 120, 130, and 140 may include a signal column 192. The signal column 192 may be vertically arranged in each of the first to third semiconductor chips 120, 130, and 140. Specifically, the signal column 192 may be arranged at the central portion of the first to third semiconductor chips 120, 130, and 140. Each signal column 192 may include an upper end exposed through the upper surface of each of the first to third semiconductor chips 120, 130, and 140, and a lower end exposed through the lower surface of each of the first to third semiconductor chips 120, 130, and 140.

[0030] Because the signal column 192 can be concentrated on the central portion of the first to third semiconductor chips 120, 130 and 140, the central portion of the first to fourth semiconductor chips 120, 130, 140 and 150 can have a second temperature, and the edge portions of the first to fourth semiconductor chips 120, 130, 140 and 150 can have a first temperature lower than the second temperature.

[0031] In some example embodiments, the edge portions of the first to fourth semiconductor chips 120, 130, 140, and 150 may be defined as a first region R1 having a first temperature. The central portions of the first to fourth semiconductor chips 120, 130, 140, and 150 may be defined as a second region R2 having a second temperature. The first to fourth semiconductor chips 120, 130, 140, and 150 may be capable of having a first temperature in the first region R1 (e.g., during operation), and may be capable of having a second temperature in the second region R2 (e.g., during operation). Here, the first temperature of the first region R1 may be an average value of the temperature in the first region R1. The second temperature of the second region R2 may be an average value of the temperature in the second region R2. Therefore, since the second region R2 may correspond to the high temperature region of the first to fourth semiconductor chips 120, 130, 140, and 150, the first region R1 and the second region R2 may be changed according to the temperature distribution of the first to fourth semiconductor chips 120, 130, 140, and 150. That is, the first region R1 may not be limited within edge portions of the first to fourth semiconductor chips 120 , 130 , 140 , and 150 , and the second region R2 may not be limited within central portions of the first to fourth semiconductor chips 120 , 130 , 140 , and 150 .

[0032] In some example embodiments, the first semiconductor chip to the fourth semiconductor chip 120, 130, 140 and 150 may include a high bandwidth memory (HBM) chip. In some embodiments, the HBM chip may include a stack of interconnected semiconductor chips (e.g., DRAM). In some embodiments, the HBM chip may comply with the high bandwidth memory (HBM) standard issued by JEDEC (Joint Electron Device Engineering Committee), as well as future evolutions / versions of the HBM standard. The first semiconductor chip to the third semiconductor chip 120, 130 and 140 may be referred to as the first intermediate core to the third intermediate core, respectively. The top fourth semiconductor chip 150 may be referred to as the top core. However, the first semiconductor chip to the fourth semiconductor chip 120, 130, 140 and 150 may include other types of semiconductor chips in addition to the HBM chip.

[0033] The first to fourth semiconductor chips 120, 130, 140, and 150 may have substantially the same width. The widths of the first to fourth semiconductor chips 120, 130, 140, and 150 may be narrower than the width of the package substrate 110. Therefore, an edge portion of the upper surface of the package substrate 110 may be exposed upward. Alternatively, the widths of the first to fourth semiconductor chips 120, 130, 140, and 150 may be substantially the same as the width of the package substrate 110. In addition, the first to fourth semiconductor chips 120, 130, 140, and 150 may have different widths.

[0034] The first to third semiconductor chips 120, 130, and 140 may have substantially the same thickness. In contrast, the fourth semiconductor chip 150 may have a thickness thicker than that of the first to third semiconductor chips 120, 130, and 140. Therefore, the first to third semiconductor chips 120, 130, and 140 may have substantially the same size. Figure 3 Only the first semiconductor chip 120 may be shown among the first to third semiconductor chips 120, 130, and 140. Alternatively, the thickness of the fourth semiconductor chip 150 may be substantially the same as that of the first to third semiconductor chips 120, 130, and 140. In addition, the first to fourth semiconductor chips 120, 130, 140, and 150 may have different thicknesses.

[0035] The signal bumps 190 may be configured to electrically connect the first to fourth semiconductor chips 120, 130, 140, and 150 to the package substrate 110. Specifically, the signal bumps 190 may be placed between the package substrate 110 and the first semiconductor chip 120, between the first semiconductor chip 120 and the second semiconductor chip 130, between the second semiconductor chip 130 and the third semiconductor chip 140, and between the third semiconductor chip 140 and the fourth semiconductor chip 150. In some example embodiments, the signal bumps 190 may be arranged in two rows. However, the signal bumps 190 may be arranged in one row or at least three rows.

[0036] The signal bump 190 between the package substrate 110 and the first semiconductor chip 120 may be electrically connected between the signal column of the package substrate 110 and the signal column 192 of the first semiconductor chip 120. The signal bump 190 between the first semiconductor chip 120 and the second semiconductor chip 130 may be electrically connected between the signal column 192 of the first semiconductor chip 120 and the signal column 192 of the second semiconductor chip 130. The signal bump 190 between the second semiconductor chip 130 and the third semiconductor chip 140 may be electrically connected between the signal column 192 of the second semiconductor chip 130 and the signal column 192 of the third semiconductor chip 140. The signal bump 190 between the third semiconductor chip 140 and the fourth semiconductor chip 150 may be electrically connected between the signal column 192 of the third semiconductor chip 140 and the fourth semiconductor chip 150.

[0037] As mentioned above, since the signal pillars 192 may be concentrated on the central portions of the first to fourth semiconductor chips 120, 130, 140, and 150, the signal bumps 190 may also be concentrated on the central portions of the first to fourth semiconductor chips 120, 130, 140, and 150. Therefore, heat generated from the signal bumps 190 configured to transmit signals may be generated from the central portions (e.g., the second region R2) of the first to fourth semiconductor chips 120, 130, 140, and 150, so that the second temperature of the second region R2 may be higher than the first temperature of the first region R1.

[0038] The first and second heat dissipation bumps 170 and 172 may be configured to dissipate heat from the first to fourth semiconductor chips 120, 130, 140, and 150. Therefore, the first and second heat dissipation bumps 170 and 172 may correspond to dummy bumps through which signals may not be transmitted.

[0039] In some example embodiments, the first heat dissipation bump 170 and the second heat dissipation bump 172 may be arranged in two rows. Alternatively, the first heat dissipation bump 170 and the second heat dissipation bump 172 may be arranged in one row or at least three rows. In addition, the first heat dissipation bump 170 and the second heat dissipation bump 172 may be arranged at both sides of the signal bump 190. However, the first heat dissipation bump 170 and the second heat dissipation bump 172 may be positioned at one side of the signal bump 190. In addition, the first heat dissipation bump 170 and the second heat dissipation bump 172 may be arranged in a direction substantially parallel to the arrangement direction of the signal bump 190. Alternatively, the first heat dissipation bump 170 and the second heat dissipation bump 172 may be arranged in a direction inclined to the arrangement direction of the signal bump 190.

[0040] The first heat dissipation bumps 170 may be configured to dissipate heat from the first to fourth semiconductor chips 120, 130, 140, and 150 in the first region R1. Specifically, the first heat dissipation bumps 170 may be arranged between the package substrate 110 and the first semiconductor chip 120 in the first region R1, between the first semiconductor chip 120 and the second semiconductor chip 130 in the first region R1, between the second semiconductor chip 130 and the third semiconductor chip 140 in the first region R1, and between the third semiconductor chip 140 and the fourth semiconductor chip 150 in the first region R1. Specifically, the first heat dissipation bumps 170 may be arranged in the first region R1 at a first pitch P1.

[0041] The first heat dissipation column 180 may be vertically arranged in each of the first to third semiconductor chips 120, 130, and 140. Specifically, the first heat dissipation column 180 may be positioned in the first region R1 of the first to third semiconductor chips 120, 130, and 140. The first heat dissipation column 180 may be configured to connect the first heat dissipation bumps 170 to each other in a vertical direction. That is, the first heat dissipation column 180 may also be arranged at a first pitch P1. Therefore, the heat generated from the first region R1 of the first to third semiconductor chips 120, 130, and 140 may be quickly dissipated from the semiconductor package 100 through the first heat dissipation column 180 and the first heat dissipation bump 170.

[0042] The second heat dissipation bumps 172 may be configured to dissipate heat from the first to fourth semiconductor chips 120, 130, 140, and 150 in the second region R2. Specifically, the second heat dissipation bumps 172 may be arranged between the package substrate 110 and the first semiconductor chip 120 in the second region R2, between the first semiconductor chip 120 and the second semiconductor chip 130 in the second region R2, between the second semiconductor chip 130 and the third semiconductor chip 140 in the second region R2, and between the third semiconductor chip 140 and the fourth semiconductor chip 150 in the second region R2. Specifically, the second heat dissipation bumps 172 may be arranged in the second region R2 at a second pitch P2.

[0043] In some example embodiments, the second pitch P2 may be narrower than the first pitch P1. The second pitch P2 may be no greater than about 1 / 2 times the first pitch P1. For example, when the first pitch P1 may be about 60 μm, the second pitch P2 may be no greater than about 30 μm. Therefore, the number of second heat dissipation bumps 172 located in the second region R2 at the second pitch P2 may be greater than the number of second heat dissipation bumps 172 located in the second region R2 at the first pitch P1. For example, the density of the second heat dissipation bumps 172 in a row in the second region R2 (e.g., the number of bumps per row or length of the area region) may be greater than the density of the first heat dissipation bumps 170 in a row in the first region R1. As a result, the heat dissipation efficiency of the second region R2 may be greatly improved by the second heat dissipation bumps 172. The heat dissipation efficiency of the second region R2 may be greater than the heat dissipation efficiency of the first region R1.

[0044] The second heat dissipation column 182 may be vertically arranged in each of the first semiconductor chip to the third semiconductor chip 120, 130 and 140. Specifically, the second heat dissipation column 182 may be positioned in the second region R2 of the first semiconductor chip to the third semiconductor chip 120, 130 and 140. The second heat dissipation column 182 may be configured to connect the second heat dissipation bumps 172 to each other in the vertical direction. That is, the second heat dissipation column 182 may also be arranged at a second pitch P2. Therefore, the heat generated from the second region R2 of the first semiconductor chip to the third semiconductor chip 120, 130 and 140 can be quickly dissipated from the semiconductor package 100 by the second heat dissipation column 182 and the second heat dissipation bump 172. Alternatively, the signal column 192, the first heat dissipation column 180 and the second heat dissipation column 182 may be arranged in the fourth semiconductor chip 150.

[0045] The bottom filling layer 200 may be configured to fill the space between the package substrate 110 and the first semiconductor chip 120, the space between the first semiconductor chip 120 and the second semiconductor chip 130, the space between the second semiconductor chip 130 and the third semiconductor chip 140, and the space between the third semiconductor chip 140 and the fourth semiconductor chip 150. Therefore, the signal bump 190, the first heat dissipation bump 170, and the second heat dissipation bump 172 may be surrounded by the bottom filling layer 200. Specifically, because the number of the second heat dissipation bumps 172 in the second region R2 can be increased, the area of ​​the bottom filling layer 200 with low thermal conductivity can be relatively reduced. Therefore, the heat dissipation characteristics of the semiconductor package 100 can be improved. In some example embodiments, the bottom filling layer 200 may include a non-conductive film (NCF).

[0046] The molding member 210 may be formed on an exposed edge portion of the upper surface of the package substrate 110 to surround the side surfaces of the first to fourth semiconductor chips 120, 130, 140, and 150. In contrast, the molding member 210 may not be formed on the upper surface of the fourth semiconductor chip 150 to expose the upper surface of the fourth semiconductor chip 150. Therefore, heat in the first region R1 and the second region R2 may be quickly dissipated through the exposed upper surface of the fourth semiconductor chip 150 via the first and second heat dissipation bumps 170 and 172. The molding member 210 may include an epoxy molding compound (EMC).

[0047] The external terminal 220 may be mounted on the lower surface of the package substrate 110. The external terminal 220 may be electrically connected to the lower end of the signal pillar in the package substrate 110. The external terminal 220 may include a solder ball.

[0048] Figures 4 to 6 It shows the manufacturing Figure 1 A cross-sectional view of a method for a semiconductor package in FIG.

[0049] Reference Figure 4 , first to fourth semiconductor chips 120 , 130 , 140 , and 150 may be sequentially stacked on an upper surface of a package substrate 110 .

[0050] Signal bumps 190 may be inserted between the package substrate 110 and the first semiconductor chip 120, between the first semiconductor chip 120 and the second semiconductor chip 130, between the second semiconductor chip 130 and the third semiconductor chip 140, and between the third semiconductor chip 140 and the fourth semiconductor chip 150. The signal bumps 190 may be electrically connected to signal pillars 192.

[0051] The first heat dissipation bump 170 may be inserted between the package substrate 110 and the first semiconductor chip 120 in the first region R1, between the first semiconductor chip 120 and the second semiconductor chip 130 in the first region R1, between the second semiconductor chip 130 and the third semiconductor chip 140 in the first region R1, and between the third semiconductor chip 140 and the fourth semiconductor chip 150 in the first region R1. The first heat dissipation bump 170 may be electrically connected to the first heat dissipation column 180.

[0052] The second heat dissipation bumps 172 may be inserted between the package substrate 110 and the first semiconductor chip 120 in the second region R2, between the first semiconductor chip 120 and the second semiconductor chip 130 in the second region R2, between the second semiconductor chip 130 and the third semiconductor chip 140 in the second region R2, and between the third semiconductor chip 140 and the fourth semiconductor chip 150 in the second region R2. The second heat dissipation bumps 172 may be electrically connected to the second heat dissipation pillars 182.

[0053] Reference Figure 5 , an underfill layer 200 may be formed in the space between the package substrate 110 and the first semiconductor chip 120, the space between the first semiconductor chip 120 and the second semiconductor chip 130, the space between the second semiconductor chip 130 and the third semiconductor chip 140, and the space between the third semiconductor chip 140 and the fourth semiconductor chip 150. Therefore, the signal bump 190, the first heat dissipation bump 170, and the second heat dissipation bump 172 may be surrounded by the underfill layer 200.

[0054] Reference Figure 6 , a molding member 210 may be formed on an exposed edge portion of an upper surface of the package substrate 110 to surround side surfaces of the first to fourth semiconductor chips 120 , 130 , 140 , and 150 .

[0055] The external terminal 220 may be mounted on the lower surface of the package substrate 110 to complete the Figure 1 A semiconductor package 100 is provided in FIG.

[0056] Figure 7 is a cross-sectional view illustrating a semiconductor package according to some example embodiments, Figure 8 It is shown Figure 7 A plan view of a first semiconductor chip in a semiconductor package.

[0057] In addition to the heat dissipation bumps and the heat dissipation pillars, the semiconductor package 100a of the present example embodiment may include Figure 1The elements of the semiconductor package 100 in FIG. 1 are substantially the same elements. Therefore, the same reference numerals may refer to the same elements, and any further illustrations regarding the same elements may be omitted for the sake of brevity.

[0058] Reference Figure 7 and Figure 8 , the first to fourth semiconductor chips 120 , 130 , 140 , and 150 may be divided into a first region R1 , a second region R2 , and a third region R3 . Figure 7 and Figure 8 The first region R1 and the second region R2 in Figure 1 The first region R1 and the second region R2 in the embodiment are substantially the same. Therefore, for the sake of brevity, any further illustrations of the first region R1 and the second region R2 may be omitted herein.

[0059] The third region R3 may be positioned in the second region R2. Thus, the third region R3 may be surrounded by the second region R2. The third region R3 may be capable of having a third temperature (eg, during operation) that is higher than the second temperature of the second region R2.

[0060] The heat dissipation bumps may include a first heat dissipation bump 170 , a second heat dissipation bump 172 , and a third heat dissipation bump 174 . Figure 7 and Figure 8 The first heat dissipation bump 170 and the second heat dissipation bump 172 in the Figure 1 The first heat dissipation bump 170 and the second heat dissipation bump 172 in the embodiment are substantially the same. Therefore, for the sake of brevity, any further illustrations of the first heat dissipation bump 170 and the second heat dissipation bump 172 may be omitted herein.

[0061] The third heat dissipation bumps 174 may be configured to dissipate heat from the first to fourth semiconductor chips 120, 130, 140, and 150 in the third region R3. Specifically, the third heat dissipation bumps 174 may be arranged between the package substrate 110 and the first semiconductor chip 120 in the third region R3, between the first semiconductor chip 120 and the second semiconductor chip 130 in the third region R3, between the second semiconductor chip 130 and the third semiconductor chip 140 in the third region R3, and between the third semiconductor chip 140 and the fourth semiconductor chip 150 in the third region R3. Specifically, the third heat dissipation bumps 174 may be arranged in the third region R3 at a third pitch P3.

[0062] In some example embodiments, the third pitch P3 may be narrower than the second pitch P2. The third pitch P3 may be no greater than about 1 / 2 times the second pitch P2. For example, when the second pitch P2 may be about 30 μm, the third pitch P3 may be no greater than about 15 μm. Therefore, the number of third heat dissipation bumps 174 located in the third region R3 at the third pitch P3 may be increased. For example, the density of the third heat dissipation bumps 174 in a row in the third region R3 (e.g., the number of bumps per length of a row or area region) may be greater than the density of the second heat dissipation bumps 172 in a row in the second region R2. As a result, the heat dissipation efficiency of the third region R3 may be greatly improved by the third heat dissipation bumps 174. The heat dissipation efficiency of the third region R3 may be greater than the heat dissipation efficiency of the second region R2.

[0063] The third heat dissipation column 184 may be vertically arranged in each of the first semiconductor chip to the third semiconductor chip 120, 130 and 140. Specifically, the third heat dissipation column 184 may be positioned in the third region R3 of the first semiconductor chip to the third semiconductor chip 120, 130 and 140. The third heat dissipation column 184 may be configured to connect the third heat dissipation bumps 174 to each other in the vertical direction. That is, the third heat dissipation column 184 may also be arranged at a third pitch P3. Therefore, the heat generated from the third region R3 of the first semiconductor chip to the third semiconductor chip 120, 130 and 140 can be quickly dissipated from the semiconductor package 100 through the third heat dissipation column 184 and the third heat dissipation bump 174.

[0064] In some example embodiments, the first to fourth semiconductor chips 120, 130, 140, and 150 may be divided into two or three regions. Alternatively, the first to fourth semiconductor chips 120, 130, 140, and 150 may be divided into at least four regions.

[0065] Fig. 9 is a cross-sectional view illustrating a semiconductor package according to some example embodiments, Fig.10 It is shown Fig. 9 A plan view of a first semiconductor chip in a semiconductor package.

[0066] In addition to the heat dissipation bumps and the heat dissipation pillars, the semiconductor package 100b of this example embodiment may include Figure 1 The elements of the semiconductor package 100 in FIG. 1 are substantially the same elements. Therefore, the same reference numerals may refer to the same elements, and any further illustrations regarding the same elements may be omitted for the sake of brevity.

[0067] As mentioned above, since the signal bump 190 may be arranged at the central portion of the first to fourth semiconductor chips 120, 130, 140, and 150, the central portion of the first to fourth semiconductor chips 120, 130, 140, and 150 may have the highest temperature. In contrast, the edge portion of the first to fourth semiconductor chips 120, 130, 140, and 150 may have the lowest temperature. Therefore, the temperature may gradually increase from the edge portion of the first to fourth semiconductor chips 120, 130, 140, and 150 toward the central portion of the first to fourth semiconductor chips 120, 130, 140, and 150.

[0068] Reference Fig. 9 and Fig.10 , the heat dissipation bumps 176 may be arranged with a gradually decreasing pitch from the edge portion of the first semiconductor chip to the fourth semiconductor chip 120, 130, 140 and 150 to the central portion of the first semiconductor chip to the fourth semiconductor chip 120, 130, 140 and 150. That is, the pitch between the outermost heat dissipation bump 176 and the next heat dissipation bump 176 may be the widest. On the contrary, the pitch between the central heat dissipation bump 176 and the next heat dissipation bump 176 may be the narrowest. In some embodiments, the signal bump 190 may be as shown in FIG. Fig.10 The first to fourth semiconductor chips 120, 130, 140, and 150 may be arranged with a gradually decreasing pitch from the edge portion to the center portion as shown in FIG. Figure 3 Arranged evenly as shown in .

[0069] Therefore, the heat dissipation columns 186 configured to vertically connect the heat dissipation bumps 176 to each other may be arranged with a pitch substantially the same as the pitch between the heat dissipation bumps 176. That is, the heat dissipation columns 186 may also be arranged with a gradually decreasing pitch from the edge portions of the first to fourth semiconductor chips 120, 130, 140, and 150 to the central portions of the first to fourth semiconductor chips 120, 130, 140, and 150. In other embodiments, the signal columns 192 and the heat dissipation columns 186 may be arranged (or not arranged) in the fourth semiconductor chip 150 as needed.

[0070] Fig.11 is a cross-sectional view illustrating a semiconductor package according to some example embodiments.

[0071] In addition to the number of semiconductor chips, the semiconductor package 100c of this example embodiment may include Figure 1The elements of the semiconductor package 100 in FIG. 1 are substantially the same elements. Therefore, the same reference numerals may refer to the same elements, and any further illustrations regarding the same elements may be omitted for the sake of brevity.

[0072] Reference Fig.11 , the semiconductor package 100 c of the present example embodiment may include a plurality of (at least two) semiconductor chips, such as first to eighth semiconductor chips 122 , 132 , 142 , 152 , 124 , 134 , 144 , and 154 , which are sequentially stacked.

[0073] In some example embodiments, the first to eighth semiconductor chips 122, 132, 142, 152, 124, 134, 144, and 154 may include HBM chips. However, the first to eighth semiconductor chips 122, 132, 142, 152, 124, 134, 144, and 154 may include other kinds of semiconductor chips besides HBM chips.

[0074] In some example embodiments, the first to eighth semiconductor chips 122, 132, 142, 152, 124, 134, 144 and 154 may have substantially the same width. The widths of the first to eighth semiconductor chips 122, 132, 142, 152, 124, 134, 144 and 154 may be narrower than the width of the package substrate 110. Therefore, the edge portion of the upper surface of the package substrate 110 may be exposed upward. Optionally, the widths of the first to eighth semiconductor chips 122, 132, 142, 152, 124, 134, 144 and 154 may be substantially the same as the width of the package substrate 110. In addition, the first to eighth semiconductor chips 122, 132, 142, 152, 124, 134, 144 and 154 may have different widths.

[0075] In some example embodiments, the first to seventh semiconductor chips 122, 132, 142, 152, 124, 134 and 144 may have substantially the same thickness. On the contrary, the eighth semiconductor chip 154 ​​may have a thickness thicker than the thickness of the first to seventh semiconductor chips 122, 132, 142, 152, 124, 134 and 144. Therefore, the first to seventh semiconductor chips 122, 132, 142, 152, 124, 134 and 144 may have substantially the same size. Optionally, the thickness of the eighth semiconductor chip 154 ​​may be substantially the same as the thickness of the first to seventh semiconductor chips 122, 132, 142, 152, 124, 134 and 144. In addition, the first to eighth semiconductor chips 122, 132, 142, 152, 124, 134, 144 and 154 may have different thicknesses.

[0076] Optionally, Figure 7 The heat dissipation bumps 170, 172 and 174 in Fig. 9 The heat dissipation bump 176 in FIG. 1 may be applied to the semiconductor package 100 c of the present example embodiment.

[0077] Fig.12 is a cross-sectional view illustrating a semiconductor package according to some example embodiments.

[0078] In addition to the number of semiconductor chips, the semiconductor package 100d of the present example embodiment may include Figure 1 The elements of the semiconductor package 100 in FIG. 1 are substantially the same elements. Therefore, the same reference numerals may refer to the same elements, and any further illustrations regarding the same elements may be omitted for the sake of brevity.

[0079] Reference Fig.12 , the semiconductor package 100 d of the present example embodiment may include first to twelfth semiconductor chips 122 , 132 , 142 , 152 , 124 , 134 , 144 , 154 , 126 , 136 , 146 , and 156 sequentially stacked.

[0080] In some example embodiments, the first to twelfth semiconductor chips 122, 132, 142, 152, 124, 134, 144, 154, 126, 136, 146, and 156 may include HBM chips. However, the first to twelfth semiconductor chips 122, 132, 142, 152, 124, 134, 144, 154, 126, 136, 146, and 156 may include other kinds of semiconductor chips besides HBM chips.

[0081] In some example embodiments, the first to twelfth semiconductor chips 122, 132, 142, 152, 124, 134, 144, 154, 126, 136, 146 and 156 may have substantially the same width. The widths of the first to twelfth semiconductor chips 122, 132, 142, 152, 124, 134, 144, 154, 126, 136, 146 and 156 may be narrower than the width of the package substrate 110. Therefore, an edge portion of the upper surface of the package substrate 110 may be exposed upward. Alternatively, the widths of the first to twelfth semiconductor chips 122, 132, 142, 152, 124, 134, 144, 154, 126, 136, 146 and 156 may be substantially the same as the width of the package substrate 110. In addition, the first to twelfth semiconductor chips 122 , 132 , 142 , 152 , 124 , 134 , 144 , 154 , 126 , 136 , 146 , and 156 may have different widths.

[0082] In some example embodiments, the first to eleventh semiconductor chips 122, 132, 142, 152, 124, 134, 144, 154, 126, 136, and 146 may have substantially the same thickness. In contrast, the twelfth semiconductor chip 156 may have a thickness thicker than that of the first to eleventh semiconductor chips 122, 132, 142, 152, 124, 134, 144, 154, 126, 136, and 146. Therefore, the first to eleventh semiconductor chips 122, 132, 142, 152, 124, 134, 144, 154, 126, 136, and 146 may have substantially the same size. Alternatively, the thickness of the twelfth semiconductor chip 156 may be substantially the same as the thickness of the first to eleventh semiconductor chips 122, 132, 142, 152, 124, 134, 144, 154, 126, 136, and 146. In addition, the first to twelfth semiconductor chips 122, 132, 142, 152, 124, 134, 144, 154, 126, 136, 146, and 156 may have different thicknesses.

[0083] Optionally, Figure 7 The heat dissipation bumps 170, 172 and 174 in Fig. 9 The heat dissipation bump 176 in FIG. 1 may be applied to the semiconductor package 100 d of the present example embodiment.

[0084] In some example embodiments, the semiconductor package may include four layers, eight layers, and twelve layers, but is not limited thereto.Alternatively, the semiconductor package may have a structure including a semiconductor chip having at least two layers.

[0085] Fig.13 is a cross-sectional view illustrating a semiconductor package according to some example embodiments.

[0086] In addition to including a heat sink, the semiconductor package 100e of this example embodiment may include Figure 1 The elements of the semiconductor package 100 in FIG. 1 are substantially the same elements. Therefore, the same reference numerals may refer to the same elements, and any further illustrations regarding the same elements may be omitted for the sake of brevity.

[0087] Reference Fig.13 The heat sink 230 may be attached to the exposed upper surface of the fourth semiconductor chip 150. The heat sink 230 may be configured to dissipate heat transferred to the fourth semiconductor chip 150 through the heat dissipation bumps 170 and 172 and the heat dissipation pillars 180 and 182 to the outside of the semiconductor package 100e.

[0088] Therefore, the heat sink 230 may include a material having high thermal conductivity such as metal. However, the heat sink 230 may include other materials not limited to metal.

[0089] In addition, the heat sink 230 may be applied to Figure 7 The semiconductor package 100a, Fig. 9 The semiconductor package 100b in Fig.11 The semiconductor package 100c or Fig.12 The semiconductor package 100d in FIG.

[0090] According to some example embodiments, the second pitch of the second heat dissipation bumps in the high temperature region of the stacked semiconductor chips may be narrower than the first pitch of the first heat dissipation bumps in the low temperature region of the stacked semiconductor chips, so that the number of the second heat dissipation bumps in the high temperature region of the stacked semiconductor chips may be increased. Therefore, the heat generated from the high temperature region of the stacked semiconductor chips may be effectively dissipated by the second heat dissipation bumps that are arranged relatively closely to each other. As a result, the semiconductor package may have low heat resistance.

[0091] The foregoing is an illustration of some example embodiments and is not to be construed as limiting thereof. Although several example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are possible without materially departing from the novel teachings and effects of the inventive concept. Therefore, all such modifications are intended to be included within the scope of some example embodiments defined in the claims.

Claims

1. A semiconductor package, the semiconductor package include: Package substrate; A plurality of semiconductor chips are stacked on an upper surface of the package substrate, wherein the plurality of semiconductor chips include a first region and a second region; a plurality of signal bumps arranged between the plurality of semiconductor chips; a plurality of first heat dissipation bumps arranged at a first pitch between the plurality of semiconductor chips in the first region; as well as A plurality of second heat dissipation bumps are arranged between the plurality of semiconductor chips in the second region at a second pitch, the second pitch being narrower than the first pitch so that the second region has a higher heat dissipation efficiency than the first region.

2. The semiconductor package according to claim 1, in, The second region corresponds to a central portion of the plurality of semiconductor chips, The first region corresponds to edge portions of the plurality of semiconductor chips, and The first area surrounds the second area.

3. The semiconductor package according to claim 1, in, The second pitch is no greater than 1 / 2 times the first pitch.

4. The semiconductor package according to claim 3, in, The first pitch is 60 μm, and The second pitch is not greater than 30 μm.

5. The semiconductor package according to claim 1, in, The plurality of first heat dissipation bumps and the plurality of second heat dissipation bumps are located at both sides of the plurality of signal bumps.

6. The semiconductor package according to claim 1, wherein the semiconductor package further comprises: include: A heat sink is located on an upper surface of an uppermost semiconductor chip among the plurality of semiconductor chips.

7. The semiconductor package according to claim 1, wherein the semiconductor package further comprises: include: The third heat dissipation bump, wherein The plurality of semiconductor chips further include a third region, The third heat dissipation bumps are arranged between the plurality of semiconductor chips in the third region at a third pitch narrower than the second pitch, so that the third region has a higher heat dissipation efficiency than that of the second region.

8. The semiconductor package according to claim 7, in, The third region corresponds to a central portion of the plurality of semiconductor chips, the first region corresponds to an edge portion of the plurality of semiconductor chips, and The second area is located between the first area and the third area.

9. The semiconductor package according to claim 1, in, The plurality of signal bumps are also located between the package substrate and a lowermost semiconductor chip among the plurality of semiconductor chips.

10. The semiconductor package according to claim 1, in, The plurality of first heat dissipation bumps and the plurality of second heat dissipation bumps are also located between the package substrate and a lowermost semiconductor chip among the plurality of semiconductor chips.

11. The semiconductor package according to claim 1, in, Each corresponding semiconductor chip among the plurality of semiconductor chips comprises: a signal column located in the corresponding semiconductor chip and connected to vertically adjacent signal bumps among the plurality of signal bumps; a first heat dissipation column located in the corresponding semiconductor chip and connected to first heat dissipation bumps adjacent in the vertical direction among the plurality of first heat dissipation bumps; and The second heat dissipation column is located in the corresponding semiconductor chip and connected to the heat dissipation bumps adjacent in the vertical direction among the plurality of second heat dissipation bumps.

12. The semiconductor package according to claim 1, further comprising: include: The bottom filling layer is located between the plurality of semiconductor chips, wherein the bottom filling layer surrounds the plurality of signal bumps, the plurality of first heat dissipation bumps and the plurality of second heat dissipation bumps.

13. The semiconductor package according to claim 1, further comprising: include: A molding member is located on the upper surface of the package substrate, and the molding member surrounds the side surfaces of the plurality of semiconductor chips.

14. The semiconductor package according to claim 1, further comprising: include: The external terminals are mounted on the lower surface of the package substrate.

15. A semiconductor package, the semiconductor package include: Package substrate; A plurality of semiconductor chips are stacked on the upper surface of the packaging substrate; a plurality of signal bumps arranged between the plurality of semiconductor chips; as well as A plurality of heat dissipation bumps are arranged between the plurality of semiconductor chips at a gradually decreasing pitch from edge portions of the plurality of semiconductor chips to central portions of the plurality of semiconductor chips.

16. The semiconductor package according to claim 15, wherein the semiconductor package further comprises: include: A heat sink is arranged on an upper surface of an uppermost semiconductor chip among the plurality of semiconductor chips.

17. The semiconductor package according to claim 15, in, The plurality of signal bumps are also located between the package substrate and a lowermost semiconductor chip among the plurality of semiconductor chips.

18. The semiconductor package according to claim 15, in, The plurality of heat dissipation bumps are also located between the package substrate and a lowermost semiconductor chip among the plurality of semiconductor chips.

19. The semiconductor package according to claim 15, in, Each corresponding semiconductor chip among the plurality of semiconductor chips comprises: a signal column located in the corresponding semiconductor chip and connected to vertically adjacent signal bumps among the plurality of signal bumps; and The heat dissipation column is located in the corresponding semiconductor chip and is connected to the heat dissipation bumps adjacent in the vertical direction among the plurality of heat dissipation bumps.

20. The semiconductor package according to claim 15, wherein the semiconductor package further comprises: include: A bottom filling layer is located between the plurality of semiconductor chips, wherein: The underfill layer surrounds the plurality of signal bumps and the plurality of heat dissipation bumps.

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