3D Flash Memory with Air Gap and Method for Manufacturing the Same

Abstract

A 3D flash memory and a method of manufacturing the same are disclosed. The 3D flash memory has a structure that reduces interference between adjacent cells in an oxide-nitride-oxide (ONO) layer, which is a charge storage layer. According to one embodiment, the 3D flash memory is characterized by including: at least one channel layer formed to extend in a first direction; a plurality of electrode layers formed to extend in a second direction perpendicular to the first direction, so as to be vertically stacked with respect to the at least one channel layer; a plurality of air gaps interposed between the plurality of electrode layers to separate the plurality of electrode layers from each other; and at least one ONO layer including a first oxide layer, a nitride layer, and a second oxide layer, and formed to extend in the first direction so as to connect the at least one channel layer and the plurality of electrode layers, wherein the 3D flash memory has a structure that reduces interference between cells in the at least one ONO layer that are in contact with the plurality of electrode layers.

Description

Technical Field

[0001] The embodiments relate to 3-dimensional (3D) flash memories and methods of manufacturing the same, and more particularly, to techniques for improving vertical scaling of 3D flash memories. Background Art

[0002] A flash memory device is an electrically erasable programmable read-only memory (EEPROM) and can generally be used, for example, in computers, digital cameras, MP3 players, game systems, memory sticks, etc. The flash memory device controls data input / output electrically through Fowler-Nordheim tunneling or hot electron injection.

[0003] Specifically, referring to Figure 1 that shows a 3D flash memory array of the related art, the array of the 3D flash memory may include a common source line CSL, bit lines BL, and a plurality of cell strings CSTR disposed between the common source line CSL and the bit lines BL.

[0004] The bit lines are arranged two-dimensionally, and the plurality of cell strings CSTR are connected in parallel to each bit line. The cell strings CSTR may be commonly connected to the common source line CSL. That is, the plurality of cell strings CSTR may be disposed between a plurality of bit lines and one common source line CSL. In this regard, there may be a plurality of common source lines CSL, and the plurality of common source lines CSL may be arranged two-dimensionally. In this case, the same voltage may be electrically applied to the plurality of common source lines CSL, or each of the plurality of common source lines CSL may be electrically controlled.

[0005] Each cell string CSTR may include a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. In addition, the ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

[0006] The common source line CSL may be commonly connected to the source of the ground selection transistor GST. In addition, a ground selection line GSL, a plurality of word lines WL0-WL3, and a plurality of string selection lines SSL disposed between the common source line CSL and the bit lines BL may be used as electrode layers of the ground selection transistor GST, the memory cell transistors MCT, and the string selection transistor SST, respectively. In addition, each memory cell transistor MCT includes a memory element.

[0007] The related art 3D flash memory has improved integration due to cells being vertically stacked, thereby achieving excellent performance and low price required by consumers.

[0008] For example, referring toFigure 2 , a 3D flash memory can be fabricated to include an electrode structure 215, in which an interlayer insulating layer 211 and a horizontal structure 250 are alternately and repeatedly formed on a substrate 200. The interlayer insulating layer 211 and the horizontal structure 250 may extend in a first direction. The interlayer insulating layer 211 may be, for example, a silicon oxide layer, and the lowermost interlayer insulating layer 211a in the interlayer insulating layer 211 may have a thickness smaller than that of the remaining interlayer insulating layers 211. Each horizontal structure 250 may include a first barrier insulating layer 242, a second barrier insulating layer 243, and an electrode layer 245. A plurality of electrode structures 215 may be provided, and the plurality of electrode structures 215 may be arranged to face each other in a second direction intersecting the first direction. The first direction and the second direction may correspond to Figure 2 the x-axis and the y-axis, respectively. A trench 240 may extend between the plurality of electrode structures 215 in the first direction to separate the plurality of electrode structures 215 from each other. An impurity region doped at a high concentration may be formed such that a common source line CSL can be formed in the substrate 200 exposed by the trench 240. Although not shown, an isolation insulating layer filled in the trench 240 may be further provided.

[0009] A vertical structure 230 may be provided to pass through the electrode structure 215. For example, the vertical structures 230 may be arranged in a matrix form by being arranged along the first direction and the second direction in a top view. As another example, the vertical structures 230 may be aligned in the second direction while being arranged in a zigzag pattern in the first direction. Each vertical structure 230 may include a protective layer 224, a charge storage layer 225, a tunnel insulating layer 226, and a channel layer 227. For example, the channel layer 227 may be provided in a hollow tubular shape, and in this case, a buried layer 228 filled inside the channel layer 227 may be further provided. A drain region D may be provided on the channel layer 227, and a conductive pattern 229 may be formed on the drain region D to be connected to a bit line BL. The bit line BL may extend in a direction intersecting the horizontal electrode 250 (e.g., in the second direction). For example, the vertical structures 230 aligned in the second direction may be connected to one bit line BL.

[0010] The first barrier insulating layer 242 and the second barrier insulating layer 243 included in the horizontal structure 250 and the charge storage layer 225 and the tunnel insulating layer 226 included in the vertical structure 230 may be defined as an oxide-nitride-oxide (ONO) layer, which is an information storage element. That is, some of the information storage elements may be included in the vertical structure 230, while the remaining information storage elements may be included in the horizontal structure 250. For example, among the information storage elements, the charge storage layer 225 and the tunnel insulating layer 226 may be included in the vertical structure 230, and the first barrier insulating layer 242 and the second barrier insulating layer 243 may be included in the horizontal structure 250.

[0011] The epitaxial pattern 222 may be disposed between the substrate 200 and the vertical structure 230. The epitaxial pattern 222 connects the substrate 200 and the vertical structure 230. The epitaxial pattern 222 may contact at least one layer of the horizontal structure 250. That is, the epitaxial pattern 222 may be arranged to contact the bottommost horizontal structure 250a. According to another embodiment, the epitaxial pattern 222 may be arranged to contact the horizontal structure 250 of multiple layers (e.g., two layers). When the epitaxial pattern 222 is arranged to contact the bottommost horizontal structure 250a, the bottommost horizontal structure 250a may be thicker than the remaining horizontal structures 250. The bottommost horizontal structure 250a contacting the epitaxial pattern 222 may correspond to the ground selection line GSL of the array of the 3D flash memory described with reference to Figure 1 The remaining horizontal structures 250 contacting the vertical structure 230 may correspond to the multiple word lines WL0 to WL3.

[0012] Each epitaxial pattern 222 has a recessed sidewall 222a. Accordingly, the bottommost horizontal structure 250a contacting the epitaxial pattern 222 is disposed along the contour of the recessed sidewall 222a. That is, the bottommost horizontal structure 250a may be disposed in an inwardly convex shape along the recessed sidewall 222a of the epitaxial pattern 222.

[0013] In the 3D flash memory of the related art having such a structure, the vertical scaling problem due to the increase in the number of vertically stacked layers is important. However, among the vertical scaling methods, the method of reducing the thickness of the multiple electrode layers 245 has the disadvantage that the characteristics of the storage device itself are affected, and the method of reducing the thickness of the multiple interlayer insulating layers 211 (the method of reducing the space between the multiple electrode layers 245) has the disadvantage that an interference phenomenon occurs between adjacent cells on the charge storage layer 225.

[0014] Therefore, in order to overcome the above disadvantages, a technique for improving vertical scaling according to the increase in the number of vertically stacked stages is required. SUMMARY OF THE INVENTION

[0015] TECHNICAL PROBLEM

[0016] The present invention provides a three-dimensional (3D) flash memory and a method of manufacturing the same, which overcome the disadvantages of the vertical scaling method of the related art by applying a structure that reduces the space between the multiple electrodes by means of multiple air gaps between the multiple electrode layers while reducing the interference phenomenon between cells (adjacent cells) in the charge storage layer (oxide-nitride-oxide (ONO) layer) that are in contact with each other in the multiple electrode layers.

[0017] SOLUTION TO THE PROBLEM

[0018] According to one aspect of the present invention, there is provided a three-dimensional (3D) flash memory, comprising: at least one channel layer formed to extend in a first direction; a plurality of electrode layers formed to extend in a second direction orthogonal to the first direction so as to be vertically stacked with respect to the at least one channel layer; a plurality of air gaps interposed between the plurality of electrode layers to separate the plurality of electrode layers from each other; and at least one oxide-nitride-oxide (ONO) layer, each comprising a first oxide layer, a nitride layer, and a second oxide layer and formed to extend in the first direction to connect the at least one channel layer and the plurality of electrode layers, wherein the 3D flash memory includes a structure for reducing an interference phenomenon between cells respectively contacting the plurality of electrode layers in the at least one ONO layer.

[0019] The 3D flash memory may include a structure for reducing an interference phenomenon between cells respectively contacting the plurality of electrode layers in the at least one ONO layer by etching the first oxide layer and the nitride layer among the at least one ONO layer in a region contacting the plurality of air gaps.

[0020] The second oxide layer of the at least one ONO layer may be etched in a region contacting the plurality of air gaps.

[0021] The 3D flash memory may include a structure for reducing an interference phenomenon between cells respectively contacting the plurality of electrode layers in the at least one ONO layer by forming barrier material layers on upper and lower portions of each of the plurality of electrode layers.

[0022] The 3D flash memory may further include a plurality of electrode protection layers for protecting the plurality of electrode layers in a process of generating the plurality of air gaps.

[0023] According to another aspect of the present invention, a method of manufacturing a 3D flash memory is provided, the method comprising: preparing a molded structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers for electrodes are alternately stacked on a substrate; forming at least one string hole that penetrates the molded structure and exposes the substrate, and extending the at least one string hole in a first direction; depositing a first oxide layer, a nitride layer, and a second oxide layer in the at least one string hole, and forming at least one oxide-nitride-oxide (ONO) layer including an internal vertical hole in the first direction and extending it in the first direction; forming at least one channel layer in the vertical hole of the at least one ONO layer, and extending the at least one channel layer in the first direction; removing the plurality of sacrificial layers for electrodes, forming a plurality of electrode layers in the space from which the plurality of sacrificial layers for electrodes have been removed, and extending the plurality of electrode layers in a second direction orthogonal to the first direction; etching the plurality of interlayer insulating layers to produce a plurality of air gaps interposed between the plurality of electrode layers and separating the plurality of electrode layers from each other; and etching the first oxide layer and the nitride layer of the at least one ONO layer in a region in contact with the plurality of air gaps, thereby reducing the interference phenomenon between cells in the at least one ONO layer that are in contact with the plurality of electrode layers respectively.

[0024] The etching of the first oxide layer and the nitride layer of the at least one ONO layer in the region in contact with the plurality of air gaps may include etching the second oxide layer of the at least one ONO layer in the region in contact with the plurality of air gaps.

[0025] The molded structure may include a structure in which a plurality of horizontal regions of a plurality of electrode protection layers for protecting the plurality of electrode layers during the process of generating the plurality of air gaps are stacked on upper and lower portions of the plurality of sacrificial layers for electrodes.

[0026] The formation and extension of the at least one oxide-nitride-oxide (ONO) layer in the first direction may include depositing vertical regions of the plurality of electrode protection layers in the at least one string hole.

[0027] The molded structure may include a structure in which a barrier material layer for reducing the interference phenomenon between cells in the at least one ONO layer that are in contact with the plurality of electrode layers respectively is stacked on upper and lower portions of each of the plurality of sacrificial layers for electrodes.

[0028] According to another aspect of the present invention, there is provided a method of manufacturing a 3D flash memory, the method comprising: preparing a molded structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers for electrodes are alternately stacked on a substrate, and a barrier material layer is stacked in the molded structure on each of the upper and lower portions of the plurality of sacrificial layers for electrodes; forming at least one string hole that penetrates the molded structure and exposes the substrate, and causing the at least one string hole to extend in a first direction; depositing a first oxide layer, a nitride layer, and a second oxide layer in the at least one string hole, and forming at least one oxide-nitride-oxide (ONO) layer including an internal vertical hole in the first direction and causing it to extend in the first direction; forming at least one channel layer in the vertical hole of the at least one ONO layer, and causing the at least one channel layer to extend in the first direction; removing the plurality of sacrificial layers for electrodes, forming a plurality of electrode layers in the space from which the plurality of sacrificial layers for electrodes have been removed, and causing the plurality of electrode layers to extend in a second direction orthogonal to the first direction; and etching the plurality of interlayer insulating layers to produce a plurality of air gaps interposed between the plurality of electrode layers and separating the plurality of electrode layers from each other.

[0029] According to another aspect of the present invention, there is provided a 3D flash memory, the 3D flash memory comprising: at least one channel layer formed to extend in a first direction; a plurality of electrode layers formed to extend in a second direction orthogonal to the first direction so as to be vertically stacked with respect to the at least one channel layer; a plurality of air gaps interposed between the plurality of electrode layers to separate the plurality of electrode layers from each other; and at least one charge storage layer formed to extend in the first direction to connect the at least one channel layer and the plurality of electrode layers, wherein the 3D flash memory includes a structure for reducing an interference phenomenon between cells in the at least one charge storage layer that respectively contact the plurality of electrode layers.

[0030] The 3D flash memory may include a structure for reducing an interference phenomenon between cells in the at least one charge storage layer that respectively contact the plurality of electrode layers by etching the at least one charge storage layer in a region in contact with the plurality of air gaps.

[0031] The 3D flash memory may include a structure for reducing an interference phenomenon between cells in the at least one charge storage layer that respectively contact the plurality of electrode layers by forming a barrier material layer on each of the upper and lower portions of the plurality of electrode layers.

[0032] According to another aspect of the present invention, there is provided a method of manufacturing a 3D flash memory, the method comprising: preparing a molded structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers for electrodes are alternately stacked on a substrate; forming at least one string hole that penetrates the molded structure and exposes the substrate, and extending the at least one string hole in a first direction; forming at least one charge storage layer including internal vertical holes in the at least one string hole and extending the at least one charge storage layer in the first direction; forming at least one channel layer in the vertical holes of the at least one charge storage layer and extending the at least one channel layer in the first direction; removing the plurality of sacrificial layers for electrodes, forming a plurality of electrode layers in a space from which the plurality of sacrificial layers for electrodes have been removed, and extending the plurality of electrode layers in a second direction orthogonal to the first direction; etching the plurality of interlayer insulating layers to generate a plurality of air gaps interposed between the plurality of electrode layers and separating the plurality of electrode layers from each other; and etching the at least one charge storage layer in a region in contact with the plurality of air gaps to reduce interference phenomena between cells in the at least one charge storage layer that are respectively in contact with the plurality of electrode layers.

[0033] The molded structure may include a structure in which a plurality of horizontal regions of a plurality of electrode protection layers that protect the plurality of electrode layers are stacked on upper and lower portions of the plurality of sacrificial layers for electrodes during a process of generating the plurality of air gaps.

[0034] The formation and extension of the at least one charge storage layer in the first direction includes depositing vertical regions of the plurality of electrode protection layers in the at least one string hole.

[0035] The molded structure may include a structure in which a barrier material layer for reducing interference phenomena between cells in the at least one charge storage layer that are respectively in contact with the plurality of electrode layers is stacked on upper and lower portions of each of the plurality of sacrificial layers for electrodes.

[0036] According to another aspect of the present invention, there is provided a method of manufacturing a 3D flash memory, the method comprising: preparing a molded structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers for electrodes are alternately stacked on a substrate, and a barrier material layer is stacked in the molded structure above and below each of the plurality of sacrificial layers for electrodes; forming at least one string hole that penetrates the molded structure and exposes the substrate, and extending the at least one string hole in a first direction; forming at least one charge storage layer including internal vertical holes in the at least one string hole and extending the at least one charge storage layer in the first direction; forming at least one channel layer in the vertical holes of the at least one charge storage layer and extending the at least one channel layer in the first direction; removing the plurality of sacrificial layers for electrodes, forming a plurality of electrode layers in the space from which the plurality of sacrificial layers for electrodes have been removed, and extending the plurality of electrode layers in a second direction orthogonal to the first direction; and etching the plurality of interlayer insulating layers to produce a plurality of air gaps interposed between the plurality of electrode layers and separating the plurality of electrode layers from each other.

[0037] Technical effects of the present disclosure

[0038] Embodiments may provide a 3D flash memory and a method of manufacturing the same, which overcome the disadvantages of the vertical scaling method of the related art by applying a structure that reduces the space between the plurality of electrodes by means of a plurality of air gaps interposed between the plurality of electrode layers to achieve vertical scaling while reducing interference phenomena between cells (adjacent cells) that are in contact with each other in the plurality of electrode layers in a charge storage layer (oxide-nitride-oxide (ONO) layer). Description of the drawings

[0039] Figure 1 is a schematic circuit diagram showing an array of 3D flash memories of the related art.

[0040] Figure 2 is a perspective view showing the structure of a 3D flash memory of the related art.

[0041] Figure 3 is a cross-sectional view showing a 3D flash memory to which an air gap is applied according to an embodiment.

[0042] Figures 4a to 4b shows Figure 3 a cross-sectional view of another embodiment of the 3D flash memory shown.

[0043] Figure 5 shows Figure 3 a cross-sectional view of an embodiment of a structure in which a second oxide layer is etched in the 3D flash memory shown.

[0044] Figure 6 shows Figure 3Cross-sectional view of a case where a 3D flash memory further includes a plurality of electrode protection layers as shown.

[0045] Figure 7 Cross-sectional view showing a 3D flash memory to which a barrier material layer is applied according to an embodiment.

[0046] Figure 8 Cross-sectional view showing a 3D flash memory to which both an air gap and a barrier material layer are applied according to an embodiment.

[0047] Figure 9 Flowchart showing a method of manufacturing a 3D flash memory to which an air gap is applied according to an embodiment.

[0048] Figures 10a to 10g Cross-sectional view showing a method of manufacturing a 3D flash memory to which an air gap is applied according to an embodiment.

[0049] Figure 11 Flowchart showing a method of manufacturing a 3D flash memory to which a barrier material layer is applied according to an embodiment.

[0050] Figures 12a to 12f Cross-sectional view showing a method of manufacturing a 3D flash memory to which a barrier material layer is applied according to an embodiment. Detailed Description of the Embodiment

[0051] Hereinafter, embodiments will be described in detail with reference to the drawings. However, the present invention is not limited or restricted by the embodiments. In addition, the same reference numerals shown in each drawing denote the same components.

[0052] In addition, the terms used in this specification are terms for appropriately expressing the preferred embodiments of the present invention, and may vary according to the intention or habit of users and operators in the field to which the present invention pertains. Therefore, the definitions of these terms should be based on the descriptions throughout this specification.

[0053] Figure 3 Cross-sectional view showing a 3D flash memory to which an air gap is applied according to an embodiment. Figures 4a to 4b Shows Figure 3 Cross-sectional view of another embodiment of the 3D flash memory shown. Figure 5 Shows in Figure 3 Cross-sectional view of an embodiment of a structure in which a second oxide layer is etched in the 3D flash memory shown. Figure 6 Shows in Figure 3 Cross-sectional view of a case where the 3D flash memory shown further includes a plurality of electrode protection layers.

[0054] Refer to Figures 3 to 6, A 3D flash memory 300 applying an air gap according to an embodiment includes at least one channel layer 310, a plurality of electrode layers 320, a plurality of air gaps 330, and at least one oxide-nitride-oxide (ONO) layer 340.

[0055] At least one channel layer 310 may be formed to extend in a first direction (e.g., Figure 2 the z-axis direction in ) and may use single-crystalline silicon as a material.

[0056] A plurality of electrode layers 320 may be formed to extend in a second direction perpendicular to the first direction (e.g., Figure 2 the y-axis direction in ) so as to be vertically stacked with respect to at least one channel layer 310, and may use a conductive material such as tungsten, titanium, and tantalum as a material.

[0057] A plurality of air gaps 330 are components interposed between the plurality of electrode layers 320 to separate the plurality of electrode layers 320 from each other. A stand (not shown) for preventing a short circuit between the plurality of electrode layers 320 as needed may pass through the plurality of air gaps 330 and be connected to the plurality of electrode layers 320.

[0058] At least one ONO layer 340 may be formed to extend in a first direction (e.g., Figure 2 the z-axis direction in ) to connect the plurality of air gaps 330, at least one channel layer 310, and the plurality of electrode layers 320, and may include a first oxide layer (tunnel oxide layer) 341, a nitride layer (charge trap layer) 342, and a second oxide layer (internal oxide layer) 343.

[0059] Here, since the plurality of air gaps 330 are formed to have a thickness thinner than that of the interlayer insulating layer included in a 3D flash memory of the related art, the space between the plurality of electrode layers 320 in the 3D flash memory 300 according to an embodiment may be smaller than the space between the plurality of electrode layers in the 3D flash memory of the related art. Therefore, compared with the 3D flash memory of the related art, the 3D flash memory 300 according to an embodiment may have improved integration.

[0060] Specifically, according to an embodiment, a structure for reducing interference phenomena between cells that are respectively in contact with the plurality of electrode layers 320 in at least one ONO layer 340 is applied to the 3D flash memory 300, so that the disadvantage of interference phenomena occurring between adjacent cells on at least one ONO layer 340 can be overcome.

[0061] More specifically, a structure for reducing interference phenomena between cells in at least one ONO layer 340 that are in contact with a plurality of electrode layers 320, respectively, can be applied by etching a first oxide layer 341 and a nitride layer 342 among at least one ONO layer 340 in a region where a plurality of air gaps 330 are in contact. That is, among the first oxide layer 341, the nitride layer 342, and the second oxide layer 343 that constitute at least one ONO layer 340, the first oxide layer 341 and the nitride layer 342 may exist only in a region in contact with each of the plurality of electrode layers 320, and may have a structure in which the first oxide layer 341 and the nitride layer 342 are isolated between vertically adjacent cells.

[0062] Thus, the structure in which the first oxide layer 341 and the nitride layer 342 among at least one ONO layer 340 are etched in a region where a plurality of air gaps 330 are in contact is not limited to or restricted to Figure 3 the structure shown. Instead, as Figures 4a to 4b shown, the first oxide layer 341 and the nitride layer 342 can be variously implemented with a structure in which the first oxide layer 341 and the nitride layer 342 are isolated between vertically adjacent cells.

[0063] In addition, the 3D flash memory 300 according to an embodiment is not limited to or restricted to having a structure in which the first oxide layer 341 and the nitride layer 342 are etched in a region where a plurality of air gaps 330 are in contact to be isolated between vertically adjacent cells, and may have a structure in which the second oxide layer 343 is etched as Figure 5 shown.

[0064] In addition, as Figure 6 shown, the 3D flash memory 300 may further include a plurality of electrode protection layers 350 that protect the plurality of electrode layers 320 in a process of generating a plurality of air gaps 330. The plurality of electrode protection layers 350 may include a material (e.g., nitrogen oxide) having an etching ratio different from that of a process of etching a plurality of interlayer insulating layers and a process of removing a sacrificial layer for the plurality of electrodes among operations of a method for manufacturing a 3D flash memory to be described later. However, the present invention is not limited or restricted thereto, and the plurality of electrode protection layers 350 may include a material (e.g., nitride) having an etching ratio the same as that of the process of removing the sacrificial layer for the plurality of electrodes, and may be formed with a thickness that can be partially retained during the process of removing the sacrificial layer for the plurality of electrodes.

[0065] As described above, although a structure for reducing interference phenomena between cells respectively contacting a plurality of electrode layers 320 by etching a first oxide layer 341 and a nitride layer 342 among at least one ONO layer 340 in a region contacting a plurality of air gaps 330 has been described as being applied to the 3D flash memory 300, a structure for reducing interference phenomena between cells respectively contacting a plurality of electrode layers 320 in at least one ONO layer 340 can be applied to the 3D flash memory 300 by using a barrier material layer. A detailed description thereof will be given with reference to Figure 7 as follows.

[0066] In addition, although the 3D flash memory 300 when at least one ONO layer 340 is used as a charge storage layer has been described above, when a charge storage layer different from at least one ONO layer 340 is used, a 3D flash memory according to an embodiment may include: at least one channel layer formed to extend in a first direction; a plurality of electrode layers formed to extend in a second direction orthogonal to the first direction so as to be vertically stacked with respect to the at least one channel layer; a plurality of air gaps interposed between the plurality of electrode layers to separate the plurality of electrode layers from each other; and at least one charge storage layer formed to extend in the first direction so as to connect the at least one channel layer and the plurality of electrode layers, and similar to those Figures 3 to 6 described, may have a structure for reducing interference phenomena between cells respectively contacting a plurality of electrode layers in the at least one charge storage layer by etching the at least one charge storage layer in a region contacting a plurality of air gaps.

[0067] Figure 7 FIG. is a cross-sectional view showing a 3D flash memory to which a barrier material layer is applied according to an embodiment, Figure 8 FIG. is a cross-sectional view showing a 3D flash memory to which both an air gap and a barrier material layer are applied according to an embodiment.

[0068] Referring to Figure 7 , a 3D flash memory 700 to which a barrier material layer is applied according to an embodiment includes at least one channel layer 710, a plurality of electrode layers 720, a plurality of air gaps 730, a barrier material layer 740, and at least one ONO layer 750.

[0069] At least one channel layer 710 is formed to extend in a first direction (e.g., Figure 2 the z-axis direction in

[0070] ), and single-crystalline silicon may be used as a material. Figure 2 A plurality of electrode layers 720 may be formed to extend in a second direction perpendicular to the first direction (e.g., the y-axis direction in ), so as to be vertically stacked with respect to at least one channel layer 710, and a conductive material such as tungsten, titanium, and tantalum may be used as a material.

[0071] A plurality of air gaps 730 are components interposed between a plurality of electrode layers 720 to separate the plurality of electrode layers 720 from each other. A bracket (not shown) for preventing short circuits between the plurality of electrode layers 720 as needed may pass through the plurality of air gaps 330 and be connected to the plurality of electrode layers 720.

[0072] At least one ONO layer 750 may be formed to extend in a first direction (e.g., Figure 2 the z-axis direction in ) to connect the plurality of air gaps 730 and at least one channel layer 710 and the plurality of electrode layers 720, and may include a first oxide layer (tunnel oxide layer) 751, a nitride layer (charge trap layer) 752, and a second oxide layer (internal oxide layer) 753.

[0073] Here, since the plurality of air gaps 730 are formed to have a thickness thinner than that of the interlayer insulating layer included in the 3D flash memory of the related art, the space between the plurality of electrode layers 720 in the 3D flash memory 700 according to one embodiment may be smaller than the space between the plurality of electrode layers in the 3D flash memory of the related art. Therefore, compared with the 3D flash memory of the related art, the 3D flash memory 700 according to one embodiment may have improved integration.

[0074] Specifically, according to one embodiment, a structure for reducing the interference phenomenon between the cells respectively contacting the plurality of electrode layers 720 in at least one ONO layer 750 is applied to the 3D flash memory 700, so that the disadvantage of the interference phenomenon occurring between adjacent cells on at least one ONO layer 750 can be overcome.

[0075] More specifically, a structure for reducing the interference phenomenon between the cells respectively contacting the plurality of electrode layers 720 in at least one ONO layer 750 may be applied by forming barrier material layers 740 on the upper and lower portions of each of the plurality of electrode layers 720. That is, the barrier material layers 740 formed on the upper and lower portions of each of the plurality of electrode layers 720 isolate the regions respectively contacting the plurality of electrode layers 720 in at least one ONO layer 750, and thus, a structure for reducing the interference phenomenon between the cells respectively contacting the plurality of electrode layers 720 in at least one ONO layer 750 may be applied. As the barrier material layer 740, any material having non-conductive characteristics may be used. For example, silicon nitride, silicon oxynitride, silicon oxide, or metal oxide may be used.

[0076] In addition, the 3D flash memory 700 may further include a plurality of electrode protection layers (not shown) to protect the plurality of electrode layers 720 in the process of generating the plurality of air gaps 730. The positions and materials of the plurality of electrode protection layers (not shown) are the same as those described above with reference to Figure 6 those, and thus, a detailed description thereof is omitted.

[0077] As described above, although a structure in which a barrier material layer 740 formed on the upper and lower portions of each of the plurality of electrode layers 720 isolates regions that respectively contact the plurality of electrode layers 720 in at least one ONO layer 750, and thus reduces the interference phenomenon between cells that respectively contact the plurality of electrode layers 720 in at least one ONO layer 750, can be applied to the 3D flash memory 700. In addition, as referred to above Figure 3 as described, a structure that reduces the interference phenomenon between cells that respectively contact the plurality of electrode layers 720 in at least one ONO layer 750 can be applied to the 3D flash memory 700 by etching a first oxide layer 751 and a nitride layer 752 in a region of at least one ONO layer 750 that contacts the plurality of air gaps 730. In this case, as Figure 8 shown, the 3D flash memory 800 can have a structure in which a barrier material layer 820 is formed on the upper and lower portions of each of the plurality of electrode layers 810, and at the same time, a first oxide layer 831 and a nitride layer 832 in at least one ONO layer 830 are etched in a region that contacts the plurality of air gaps 840.

[0078] In addition, although the 3D flash memory 700 when at least one ONO layer 750 is used as a charge storage layer has been described above, when a charge storage layer different from at least one ONO layer 750 is used, a 3D flash memory according to an embodiment may include: at least one channel layer formed to extend in a first direction; a plurality of electrode layers formed to extend in a second direction orthogonal to the first direction so as to be vertically stacked with respect to the at least one channel layer; a plurality of air gaps interposed between the plurality of electrode layers to separate the plurality of electrode layers from each other; and at least one charge storage layer formed to extend in the first direction so as to connect the at least one channel layer and the plurality of electrode layers, and similar to those Figure 7 described, may have a structure that reduces the interference phenomenon between cells that respectively contact the plurality of electrode layers in the at least one charge storage layer by forming a barrier material layer on the upper and lower portions of each of the plurality of electrode layers.

[0079] Figure 9 is a flowchart showing a method of manufacturing a 3D flash memory to which air gaps are applied according to an embodiment, Figures 10a to 10g is a cross-sectional view showing a method of manufacturing a 3D flash memory to which air gaps are applied according to an embodiment.

[0080] Hereinafter, the 3D flash memory manufactured by the method of manufacturing a 3D flash memory has the structure described above with reference to Figure 3 description. In addition, hereinafter, an automated and mechanized manufacturing system can be used as the main body for implementing the manufacturing method of the 3D flash memory.

[0081] Refer to Figures 9 to 10g, a molded structure 1020 is prepared by a manufacturing system according to an embodiment, wherein a plurality of interlayer insulating layers 1021 and a plurality of sacrificial layers 1022 for electrodes are alternately stacked on a substrate 1010 as Figure 10a shown, and the molded structure 1020 is prepared in operation S910. Here, the plurality of interlayer insulating layers 1021 may include oxides, and the plurality of sacrificial layers 1022 for electrodes may include nitrides.

[0082] Subsequently, in operation S920, as Figure 10b shown, the manufacturing system forms at least one string hole 1023 passing through the molded structure 1020 in a first direction to expose the substrate 1010 and extends it in the first direction.

[0083] Then, in operation S930, the manufacturing system deposits a first oxide layer 1031, a nitride layer 1032, and a second oxide layer 1033 in at least one string hole 1023 as Figure 10c shown to form at least one ONO layer 1030 including an internal vertical hole 1034 in the first direction and extends it in the first direction.

[0084] Next, in operation S940, as Figure 10d shown, the manufacturing system forms at least one channel layer 1040 in the vertical hole 1034 of at least one ONO layer 1030 in the first direction and extends it in the first direction. In this regard, the at least one channel layer 1040 may include single crystal silicon.

[0085] Next, in operation S950, as Figure 10e shown, the manufacturing system removes the plurality of sacrificial layers 1022 for electrodes and forms a plurality of electrode layers 1050 in a space 1024 from which the plurality of sacrificial layers 1022 for electrodes have been removed in a second direction orthogonal to the first direction and extends them in the second direction. Here, as a method of removing the plurality of sacrificial layers 1022 for electrodes, various chemical etching methods and physical etching methods can be used, and the plurality of electrode layers 1050 may include conductive materials such as tungsten, titanium, tantalum, etc.

[0086] Next, in operation S960, as Figure 10f shown, the manufacturing system etches the plurality of interlayer insulating layers 1021 to generate a plurality of air gaps 1060 interposed between the plurality of electrode layers 1050 and separating the plurality of electrode layers 1050 from each other. In this regard, various chemical etching methods and physical etching methods can be used as the method of etching the plurality of interlayer insulating layers 1021.

[0087] Hereinafter, in operation S970, as Figure 10gAs shown, in order to reduce the interference phenomenon between cells in at least one ONO layer 1030 that contact multiple electrode layers 1050, the manufacturing system etches the first oxide layer 1031 and the nitride layer 1032 of at least one ONO layer 1030 in the region that contacts multiple air gaps 1060. Through operation S970, among the first oxide layer 1031, the nitride layer 1032, and the second oxide layer 1033 that constitute at least one ONO layer 1030, the first oxide layer 1031 and the nitride layer 1032 can exist only in the region that contacts each of the multiple electrode layers 1050, and can have a structure in which adjacent upper and lower cells are isolated from each other.

[0088] Therefore, the 3D flash memory manufactured through operations S910 to S970 can have the structure described above with reference to Figure 3 FIG. 4.

[0089] In addition, in operation S970, the manufacturing system can etch the second oxide layer 1033 of at least one ONO layer 1030 in the region that contacts multiple air gaps 1060. In this case, a 3D flash memory having the structure described above with reference to Figure 5 can be manufactured.

[0090] As described above, the 3D flash memory manufactured through the above operations (S910 to S970) includes multiple air gaps 1060, which are formed to have a thickness thinner than the thickness of the interlayer insulating layer included in the 3D flash memory of the related art, so that it has improved integration compared to the 3D flash memory of the related art, and the structure that reduces the interference phenomenon between cells that respectively contact multiple electrode layers 1050 in at least one ONO layer 1030 can be applied to the 3D flash memory by etching the first oxide layer 1031 and the nitride layer 1032 among at least one ONO layer 1030 in the region that contacts multiple air gaps 1060, thereby overcoming the drawback of the interference phenomenon occurring between adjacent cells on at least one ONO layer 1030.

[0091] In addition, the manufacturing system can prepare a molded structure 1020 having a structure in which multiple horizontal regions 1071 of multiple electrode protection layers 1070 that protect multiple electrode layers 1050 are stacked on the upper and lower parts of multiple sacrificial layers 1022 for electrodes during the process of generating multiple air gaps 1060 in operation S910, and the vertical regions 1072 of multiple electrode protection layers 1070 are deposited in at least one string hole 1023 before forming at least one ONO layer 1030 in operation S930, thereby manufacturing a structure including the above with reference to Figure 6A 3D flash memory with a plurality of electrode protection layers 1070 described. In this case, during the process of etching the plurality of interlayer insulating layers 1021 in operation S950 or during the process of etching the first oxide layer 1031 and the nitride layer 1032 of at least one ONO layer 1030 in the region contacting the plurality of air gaps 1060 in operation S970, the region of the vertical region 1072 of the plurality of electrode protection layers 1070 contacting the plurality of air gaps 1060 is removed.

[0092] In addition, the manufacturing system may use a molding structure 1020 having a structure in which a barrier material layer (not shown) for reducing the interference phenomenon between cells respectively contacting the plurality of electrode layers 1050 in at least one ONO layer 1030 is stacked on the upper and lower portions of each of the plurality of sacrificial layers 1022 for electrodes in operation S910, thereby manufacturing the 3D flash memory described above with reference to Figure 8 the description.

[0093] Although the method of manufacturing a 3D flash memory when at least one ONO layer 1030 is used as a charge storage layer is described above, when a charge storage layer different from at least one ONO layer 1030 is used, the method of manufacturing a 3D flash memory according to an embodiment is as follows.

[0094] 1. Prepare a molding structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers for electrodes are alternately stacked on a substrate.

[0095] 2. Form at least one string hole that penetrates the molding structure and exposes the substrate to extend in its first direction.

[0096] 3. Form at least one charge storage layer including internal vertical holes to extend along the first direction in the at least one string hole.

[0097] 4. Form at least one channel layer to extend along the first direction in the vertical holes of the at least one charge storage layer.

[0098] 5. Remove the plurality of sacrificial layers for electrodes, and form a plurality of electrode layers in the space from which the plurality of sacrificial layers for electrodes have been removed to extend in a second direction orthogonal to the first direction.

[0099] 6. Etch the plurality of interlayer insulating layers to produce a plurality of air gaps interposed between the plurality of electrode layers and separating the plurality of electrode layers from each other.

[0100] 7. Etch the at least one charge storage layer in the region contacting the plurality of air gaps, thereby reducing the interference phenomenon between cells respectively contacting the plurality of electrode layers in the at least one charge storage layer.

[0101] Each process of such a manufacturing method is the same as that described above with reference toFigures 9 to 10g Each of the described operations is similar or identical, and thus its detailed description is omitted.

[0102] Figure 11 is a flowchart showing a method of manufacturing a 3D flash memory to which a barrier material layer is applied according to an embodiment, Figures 12a to 12f is a cross-sectional view showing a method of manufacturing a 3D flash memory to which a barrier material layer is applied according to an embodiment.

[0103] Hereinafter, the 3D flash memory manufactured by the method of manufacturing a 3D flash memory has the structure described above with reference to Figure 7 In addition, hereinafter, an automated and mechanized manufacturing system can be used as the main body for implementing the method of manufacturing a 3D flash memory.

[0104] Referring to Figures 11 to 12f , a molding structure 1220 is prepared by a manufacturing system according to an embodiment, in which a plurality of interlayer insulating layers 1221 and a plurality of sacrificial layers 1222 for electrodes are alternately stacked on a substrate 1010 as Figure 12a shown, and the molding structure 1220 is prepared in operation S1110. Here, the plurality of interlayer insulating layers 1221 may include oxides, and the plurality of sacrificial layers 1222 for electrodes may include nitrides. Specifically, in the molding structure 1220, a barrier material layer 1223 is stacked on the upper and lower portions of each of the plurality of sacrificial layers 1222 for electrodes.

[0105] Subsequently, in operation S1120, as Figure 12b shown, the manufacturing system forms at least one string hole 1223 that penetrates the molding structure 1220 in a first direction to expose the substrate 1210 and extends it in the first direction.

[0106] Then, in operation S1130, the manufacturing system deposits a first oxide layer 1231, a nitride layer 1232, and a second oxide layer 1233 in at least one string hole 1223 as Figure 12c shown to form at least one ONO layer 1230 including an internal vertical hole 1234 in the first direction and extend it in the first direction.

[0107] Next, in operation S1140, as Figure 12d shown, the manufacturing system forms at least one channel layer 1240 in the vertical hole 1234 of at least one ONO layer 1230 in the first direction and extends it in the first direction. In this case, the at least one channel layer 1240 may include single-crystalline silicon.

[0108] Next, in operation S1150, as Figure 12eAs shown, the manufacturing system removes a plurality of sacrificial layers 1222 for electrodes and forms a plurality of electrode layers 1250 in a space 1224 from which the plurality of sacrificial layers 1222 for electrodes have been removed in a second direction orthogonal to the first direction and extends them in the second direction. Here, as a method for removing the plurality of sacrificial layers 1222 for electrodes, various chemical etching methods and physical etching methods can be used, and the plurality of electrode layers 1250 can include conductive materials such as tungsten, titanium, tantalum, etc.

[0109] Next, in operation S1160, as Figure 12f shown, the manufacturing system etches a plurality of interlayer insulating layers 1221 to produce a plurality of air gaps 1260 interposed between the plurality of electrode layers 1250 and separating the plurality of electrode layers 1250 from each other. In this regard, various chemical etching methods and physical etching methods can be used as a method for etching the plurality of interlayer insulating layers 1221.

[0110] Therefore, the 3D flash memory manufactured through operations S1110 to S1160 can have the structure described above with reference to Figure 7 description.

[0111] As described above, the 3D flash memory manufactured through the above operations (S1110 to S1170) includes a plurality of air gaps 1260, which are formed to have a thickness thinner than the thickness of the interlayer insulating layer included in the 3D flash memory of the related art, so as to have improved integration compared with the 3D flash memory of the related art, and a structure in which regions in at least one ONO layer 1230 that respectively contact the plurality of electrode layers 1250 are isolated from each other by barrier material layers 1223 stacked on the upper and lower portions of each of the plurality of electrode layers 1250 can be applied to the 3D flash memory, thereby overcoming the drawback of interference phenomena occurring between adjacent cells on at least one ONO layer 1230.

[0112] In addition, the manufacturing system can prepare a molded structure 1220 having a structure in which a plurality of horizontal regions 1271 of a plurality of electrode protection layers 1270 that protect the plurality of electrode layers 1250 during the process of generating the plurality of air gaps 1260 in operation S1110 are stacked on the upper and lower portions of the plurality of sacrificial layers 1222 for electrodes, and vertical regions 1272 of the plurality of electrode protection layers 1270 are deposited in at least one string hole 1223 before forming at least one ONO layer 1230 in operation S1130, thereby manufacturing a 3D flash memory including the plurality of electrode protection layers 1270 described above with reference to Figure 6 description. In this case, during the process of etching the plurality of interlayer insulating layers 1221 in operation S1150, regions of the vertical regions 1272 of the plurality of electrode protection layers 1270 that contact the plurality of air gaps 1260 can be removed.

[0113] Although the method of manufacturing a 3D flash memory when at least one ONO layer 1230 is used as a charge storage layer has been described above, when a charge storage layer different from the at least one ONO layer 1230 is used, the method of manufacturing a 3D flash memory according to an embodiment is as follows.

[0114] 1. Prepare a molded structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers for electrodes are alternately stacked on a substrate. Specifically, a barrier material layer is stacked on the upper and lower portions of each of the plurality of sacrificial layers for electrodes in the molded structure.

[0115] 2. Form at least one string hole that penetrates the molded structure and exposes the substrate so as to extend in a first direction.

[0116] 3. Form at least one charge storage layer including internal vertical holes so as to extend in the at least one string hole in the first direction.

[0117] 4. Form at least one channel layer so as to extend in the vertical holes of the at least one charge storage layer in the first direction.

[0118] 5. Remove the plurality of sacrificial layers for electrodes, and a plurality of electrode layers are formed to extend in a second direction orthogonal to the first direction in the space from which the plurality of sacrificial layers for electrodes have been removed.

[0119] 6. Etch the plurality of interlayer insulating layers to create a plurality of air gaps interposed between the plurality of electrode layers and separating the plurality of electrode layers from each other.

[0120] Each process of such a manufacturing method is similar or identical to each of the operations described above with reference to Figures 11 to 12f description, and thus its detailed description is omitted.

[0121] As described above, although the embodiments have been described through limited embodiments and drawings, various modifications and variations are possible for those of ordinary skill in the art according to the above description. For example, even if the described technology is executed in an order different from the described method, and / or components such as the described system, structure, device, circuit, etc. are coupled or combined in a form different from the described method, or replaced or substituted by other components or equivalents, appropriate results can also be obtained.

[0122] Therefore, other implementations, other embodiments, and those equivalent to the claims also fall within the scope of the claims to be described below.

Claims

1. A three-dimensional flash memory, comprising: At least one channel layer formed to extend in a first direction; A plurality of electrode layers formed to extend in a second direction orthogonal to the first direction, so as to be vertically stacked relative to the at least one channel layer; A plurality of air gaps separating the plurality of electrode layers from each other between the plurality of electrode layers; At least one oxide-nitride-oxide layer including a first oxide layer, a nitride layer, and a second oxide layer and formed to extend in the first direction to connect the at least one channel layer and the plurality of electrode layers; And A barrier material layer formed on upper and lower portions of each of the plurality of electrode layers, Wherein the first oxide layer, the nitride layer, and the second oxide layer continuously extend in the first direction between the at least one channel layer and each of the plurality of electrode layers and the plurality of air gaps, and Wherein the first oxide layer contacts the plurality of air gaps, the barrier material layer, and the plurality of electrode layers.

2. The three-dimensional flash memory according to claim 1, further comprising: A plurality of electrode protection layers for protecting the plurality of electrode layers in a process of generating the plurality of air gaps.

3. A method of manufacturing a three-dimensional flash memory, the method comprising: Preparing a molded structure, wherein a plurality of interlayer insulating layers and a plurality of sacrificial layers for electrodes are alternately stacked on a substrate, and a barrier material layer is stacked in the molded structure on upper and lower portions of each of the plurality of sacrificial layers for electrodes; Forming at least one string hole and extending the at least one string hole in a first direction, the at least one string hole penetrating the molded structure and exposing the substrate; Depositing a first oxide layer, a nitride layer, and a second oxide layer in the at least one string hole, and forming at least one oxide-nitride-oxide layer including internal vertical holes in the first direction and extending the at least one oxide-nitride-oxide layer in the first direction; Forming at least one channel layer in the vertical holes of the at least one oxide-nitride-oxide layer and extending the at least one channel layer in the first direction; Removing the plurality of sacrificial layers for electrodes, forming a plurality of electrode layers in a space from which the plurality of sacrificial layers for electrodes have been removed so that the barrier material layer is stacked on upper and lower portions of each of the plurality of electrode layers, and extending the plurality of electrode layers in a second direction orthogonal to the first direction; And Etching the plurality of interlayer insulating layers to generate a plurality of air gaps interposed between the plurality of electrode layers and separating the plurality of electrode layers from each other, Wherein the first oxide layer, the nitride layer, and the second oxide layer continuously extend in the first direction between the at least one channel layer and each of the plurality of electrode layers and the plurality of air gaps, and Wherein the first oxide layer contacts the plurality of air gaps, the barrier material layer, and the plurality of electrode layers.

4. A three-dimensional flash memory, comprising: At least one channel layer formed to extend in a first direction; A plurality of electrode layers formed to extend in a second direction orthogonal to the first direction so as to be vertically stacked relative to the at least one channel layer; A plurality of air gaps to separate the plurality of electrode layers from each other therebetween; At least one charge storage layer formed to extend in the first direction to connect the at least one channel layer and the plurality of electrode layers; And A barrier material layer formed on upper and lower portions of each of the plurality of electrode layers, Wherein the at least one charge storage layer continuously extends in the first direction between the at least one channel layer and each of the plurality of electrode layers and the plurality of air gaps, and Wherein the at least one charge storage layer contacts the plurality of air gaps, the barrier material layer, and the plurality of electrode layers.

5. The three-dimensional flash memory according to claim 4, further comprising: A plurality of electrode protection layers to protect the plurality of electrode layers in a process of generating the plurality of air gaps.

6. A method of manufacturing a three-dimensional flash memory, the method comprising: Preparing a molded structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers for electrodes are alternately stacked on a substrate, and a barrier material layer is stacked on upper and lower portions of each of the plurality of sacrificial layers for electrodes in the molded structure; Forming at least one string hole and extending the at least one string hole in a first direction, the at least one string hole penetrating the molded structure and exposing the substrate; Forming at least one charge storage layer including internal vertical holes in the at least one string hole and extending the at least one charge storage layer in the first direction; Forming at least one channel layer in the vertical holes of the at least one charge storage layer and extending the at least one channel layer in the first direction; Removing the plurality of sacrificial layers for electrodes, forming a plurality of electrode layers in a space from which the plurality of sacrificial layers for electrodes have been removed such that the barrier material layer is stacked on upper and lower portions of each of the plurality of electrode layers, and extending the plurality of electrode layers in a second direction orthogonal to the first direction; And Etching the plurality of interlayer insulating layers to generate a plurality of air gaps interposed between the plurality of electrode layers to separate the plurality of electrode layers from each other, Wherein the at least one charge storage layer continuously extends in the first direction between the at least one channel layer and each of the plurality of electrode layers and the plurality of air gaps, and Wherein the at least one charge storage layer contacts the plurality of air gaps, the barrier material layer, and the plurality of electrode layers.

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