Display substrate to be cut, display substrate and display device thereof

Abstract

The embodiments of the present disclosure provide a display substrate to be cut, a display substrate and a display device thereof, which relate to the field of display technology and solve the problem of product defects caused by severe heating of large resistance test leads in the related art. The display substrate includes at least one binding portion, at least one testing portion, a plurality of residual test leads and a plurality of residual binding leads, the binding portion includes a plurality of binding pads arranged along a first direction, at least one testing portion is located on at least one side of at least one binding portion, the testing portion includes a plurality of test pads arranged along a first direction, and the test pads are configured to receive test signals transmitted by an external circuit during a test phase; a plurality of residual test leads are located on a side of at least one testing portion away from a display area, and the residual test leads are electrically connected to the test pads; a plurality of residual binding leads are located on a side of at least one binding portion away from a display area, and the residual binding leads are electrically connected to at least part of the binding pads. The present disclosure is used to manufacture a display device.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate to be cut, a display substrate and a display device thereof. Background Art

[0002] With the development of display technology, display devices have gradually become prevalent in people's lives. In the production process of display devices, after the circuits (e.g., pixel circuits, gate drive circuits) and signal lines (e.g., gate lines, data lines, power lines) in the display substrate are completed, it is necessary to use a test circuit to detect the circuits and signal lines in the display substrate to determine whether there are short circuits or open circuits in the display substrate. After the detection is completed, the display substrate is cut and the subsequent module process is performed to form a display device. Summary of the invention

[0003] The present invention provides a display substrate to be cut, a display substrate and a display device thereof, so as to solve the problem of product defects caused by severe heating of large resistance test leads in the related art, reduce ESD risks, and reduce the corrosion diffusion of active metal atoms on the test pad into the interior of the display substrate.

[0004] On the one hand, a display substrate is provided. The display substrate includes a base substrate, a plurality of sub-pixels, a plurality of data lines, at least one binding portion, a plurality of data connection lines, at least one testing portion, a plurality of residual test leads, and a plurality of residual binding leads, the base substrate includes a display area and a peripheral area at least partially surrounding the display area, the plurality of sub-pixels and the plurality of data lines are located in the display area, and the plurality of data lines are electrically connected to the plurality of sub-pixels; the at least one binding portion is located in the peripheral area, the binding portion includes a plurality of binding pads arranged along a first direction, the at least one binding portion is configured to be bound to a circuit board, the plurality of binding pads include a plurality of data pads; the plurality of data connection lines are located In the peripheral area, the data connection line is electrically connected to the data pad and the data line; the at least one testing part is located on at least one side of the at least one binding part along the first direction, the testing part includes a plurality of testing pads arranged along the first direction, and the testing pads are configured to receive a test signal transmitted by an external circuit during a testing phase; the plurality of residual test leads are located on a side of the at least one testing part away from the display area, and the residual test leads are electrically connected to the test pads; the plurality of residual binding leads are located on a side of the at least one binding part away from the display area, and the residual binding leads are electrically connected to at least part of the binding pads.

[0005] In some embodiments, the at least one test section includes a first test section and a second test section, and the first test section and the second test section are arranged on both sides of the at least one binding section along the first direction. The plurality of residual test leads include a plurality of first residual test leads and a plurality of second residual test leads, and the plurality of first residual test leads are electrically connected to a plurality of test pads of the first test section; and the plurality of second residual test leads are electrically connected to a plurality of test pads of the second test section.

[0006] In some embodiments, the at least one binding portion includes a first binding portion and a second binding portion; the at least one test portion also includes a third test portion and a fourth test portion; wherein the first test portion, the first binding portion, the third test portion, the fourth test portion, the second binding portion, and the second test portion are arranged in sequence along the first direction. The plurality of residual test leads also include a plurality of third residual test leads and a plurality of fourth residual test leads, the plurality of third residual test leads are electrically connected to a plurality of test pads of the third test portion; the plurality of fourth residual test leads are electrically connected to a plurality of test pads of the fourth test portion.

[0007] In some embodiments, the display substrate further includes a plurality of first connecting wires disposed on a side of the third test section and the fourth test section close to the display area, and the first connecting wires are electrically connected to the test pads of the third test section and the test pads of the fourth test section.

[0008] In some embodiments, the at least one binding part further includes a third binding part and a fourth binding part, and the at least one test part further includes a fifth test part, a sixth test part, a seventh test part and an eighth test part; wherein the first test part, the first binding part, the third test part, the fourth test part, the third binding part, the fifth test part, the sixth test part, the fourth binding part, the seventh test part, the eighth test part, the second binding part, and the second test part are arranged in sequence along the first direction. The plurality of residual test leads further include a plurality of fifth residual test leads, a plurality of sixth residual test leads, a plurality of seventh residual test leads and a plurality of eighth residual test leads, the plurality of fifth residual test leads are electrically connected to a plurality of test pads of the fifth test part; the plurality of sixth residual test leads are electrically connected to a plurality of test pads of the sixth test part; the plurality of seventh residual test leads are electrically connected to a plurality of test pads of the seventh test part; the plurality of eighth residual test leads are electrically connected to a plurality of test pads of the eighth test part.

[0009] In some embodiments, the display substrate further includes a plurality of second connecting wires, which are arranged on a side of the seventh test section and the eighth test section close to the display area, and the second connecting wires are electrically connected to the test pads of the seventh test section and the test pads of the eighth test section.

[0010] In some embodiments, the plurality of binding pads of the first binding part and the second binding part further include a plurality of gate pads; the plurality of test pads of the first test part and the second test part include a first test pad and a second test pad, the first test pad being configured to receive a control test signal transmitted by an external circuit for driving the test circuit to work during the test phase; the second test pad being configured to receive a control test signal transmitted by an external circuit for driving the gate drive circuit to work during the test phase. The display substrate further includes a plurality of gate lines, two gate drive circuits, a plurality of gate control signal lines and a plurality of gate connection lines, the plurality of gate lines being located in the display area and being electrically connected to the plurality of sub-pixels; the two gate drive circuits are respectively arranged in the peripheral areas on both sides of the display area along the first direction, each of the gate drive circuits being electrically connected to the plurality of gate lines; the plurality of gate control signal lines being located in the peripheral area and being electrically connected to the gate drive circuit; the plurality of gate connection lines being located in the peripheral area, the gate connection lines being electrically connected to the gate control signal lines and the gate pads.

[0011] In some embodiments, the binding residual wires include a plurality of first residual binding wires and a plurality of second residual binding wires, the plurality of first residual binding wires are electrically connected to the data pads, and the plurality of second residual binding wires are electrically connected to the gate pads.

[0012] In some embodiments, the multiple binding pads of the binding part also include multiple power pads; the display substrate also includes multiple power lines and multiple power connection lines, the multiple power lines are located in the display area and are electrically connected to the multiple sub-pixels; the multiple power connection lines are located in the peripheral area, and the power connection lines are electrically connected to the power lines and the power pads.

[0013] In some embodiments, the binding portion includes two groups of power pads, and the two groups of power pads are respectively located at two opposite sides of the data pad and the gate pad along the first direction.

[0014] In some embodiments, the display substrate further includes at least one first test circuit, and the at least one first test circuit is located on a side of the at least one binding portion close to the display area; each first test circuit corresponds to one binding portion; the data connection line includes a first sub-data connection line and a second sub-data connection line, the first sub-data connection line is electrically connected to the data line and the first test circuit, and the second sub-data connection line is electrically connected to the first test circuit and the data pad.

[0015] Some embodiments of the present disclosure provide a display substrate, wherein a plurality of residual test leads and a plurality of residual binding leads are partial leads remaining after the substrate to be cut in the front-end process is cut, and the leads are used to electrically connect the test pads, the cut-off test circuit (the second test circuit) and the corresponding binding pads to ensure that the test signal transmitted by the external circuit received during the test phase can detect the circuit and signal line to determine whether there is a short circuit or open circuit problem.

[0016] Among them, a plurality of residual test leads are located on a side of at least one test part away from the display area, and a plurality of residual binding leads are located on a side of at least one binding part away from the display area. In this way, the active metal atoms on the test pad will usually corrode and diffuse along the residual test leads to the side of the test pad away from the display area, which can reduce the corrosion and diffusion of the active metal atoms on the test pad to the inside of the display substrate, that is, the side of the test pad close to the display area, thereby reducing the defective rate of the product. In addition, there is no test lead connected to the test pad on the side of the binding part close to the display area, which can reduce the occupied area of ​​the metal, reduce the ESD risk, and reduce the size of the display substrate, which is conducive to the narrow frame design of the display device; at the same time, it avoids the overlap of the positive projection of the test lead on the substrate substrate and the positive projection of the signal line connection line on the substrate substrate, thereby solving the problem of serious heat generation of the large resistance test lead set in the transfer layer in the related art, resulting in product defects.

[0017] In another aspect, a display substrate to be cut is provided, comprising a substrate to be cut, a plurality of sub-pixels, a plurality of data lines, at least one binding portion, a plurality of data connection lines, at least one test portion, at least one second test circuit, a plurality of first test leads, and a plurality of second test leads.

[0018] The substrate to be cut includes a product area and an area to be cut that at least partially surrounds the product area, the product area includes a display area and a peripheral area that at least partially surrounds the display area; the multiple sub-pixels and the multiple data lines are located in the display area, and the multiple data lines are electrically connected to the multiple sub-pixels; the at least one binding portion is located in the peripheral area, the binding portion includes a multiple binding pads arranged along a first direction, the at least one binding portion is configured to be bound to a circuit board, and the multiple binding pads include a multiple data pads; the multiple data connection lines are located in the peripheral area, and the data connection lines are electrically connected to the data pads and the data lines; the at least one testing portion is located on at least one side of the at least one binding portion along the first direction, the testing portion includes a multiple test pads arranged along the first direction, and the test pads are configured to receive test signals transmitted by an external circuit during a test phase.

[0019] The at least one second test circuit is located in the area to be cut, and each of the second test circuits corresponds to a binding part; the multiple first test leads are located on a side of the at least one test part away from the display area, and the first test leads are electrically connected to the test pad and the binding pad; the multiple second test leads are located on a side of the at least one test part away from the display area, and the second test leads are electrically connected to the test pad and the second test circuit; the multiple third test leads are located on a side of the at least one test part away from the display area, and the third test leads are electrically connected to the binding pad and the second test circuit.

[0020] In some embodiments, the at least one binding part includes a first binding part, a second binding part, a third binding part and a fourth binding part; the at least one testing part includes a first testing part, a second testing part, a third testing part, a fourth testing part, a fifth testing part, a sixth testing part, a seventh testing part and an eighth testing part; wherein, the first testing part, the first binding part, the third testing part, the fourth testing part, the third binding part, the fifth testing part, the sixth testing part, the fourth binding part, the seventh testing part, the eighth testing part, the second binding part and the second testing part are arranged in sequence along the first direction.

[0021] The display substrate to be cut also includes a plurality of first connecting wires, a plurality of second connecting wires and a plurality of third connecting wires, the plurality of first connecting wires being arranged on a side of the third test section and the fourth test section close to the display area, and the first connecting wires being electrically connected to the test pads of the third test section and the test pads of the fourth test section; the plurality of second connecting wires being arranged on a side of the seventh test section and the eighth test section close to the display area, and the second connecting wires being electrically connected to the test pads of the seventh test section and the test pads of the eighth test section; the plurality of third connecting wires being arranged on a side of the fifth test section and the sixth test section away from the display area, and the third connecting wires being electrically connected to the test pads of the fifth test section and the test pads of the sixth test section.

[0022] In some embodiments, the multiple binding pads of the first binding part and the second binding part also include multiple gate pads; the multiple test pads of the first test part and the second test part include a first test pad and a second test pad, the first test pad is configured to receive a control test signal transmitted by an external circuit for driving the test circuit to work during the test phase; the second test pad is configured to receive a control test signal transmitted by an external circuit for driving the gate drive circuit to work during the test phase.

[0023] The display substrate to be cut also includes a plurality of gate lines, two gate driving circuits, a plurality of gate control signal lines, a plurality of gate connecting lines and a plurality of fourth test leads, wherein the plurality of gate lines are located in the display area and are electrically connected to the plurality of sub-pixels; the two gate driving circuits are respectively arranged in the peripheral areas on both sides of the display area along the first direction, and each of the gate driving circuits is electrically connected to the plurality of gate lines; the plurality of gate control signal lines are located in the peripheral area and are electrically connected to the two gate driving circuits; the plurality of gate connecting lines are located in the peripheral area, and the gate connecting lines are electrically connected to the gate control signal lines and the gate pads; the plurality of fourth test leads are located on a side of the at least one test portion away from the display area, and the fourth test leads are electrically connected to the second test pads and the gate pads.

[0024] In some embodiments, the display substrate to be cut also includes at least one first test circuit, and the at least one first test circuit is located on a side of the at least one binding portion close to the display area, and each first test circuit corresponds to one binding portion; the data connection line includes a first sub-data connection line and a second sub-data connection line, the first sub-data connection line is electrically connected to the data line and the first test circuit, and the second sub-data connection line is electrically connected to the first test circuit and the data pad.

[0025] In some embodiments of the present disclosure, a display substrate to be cut is provided, wherein a plurality of first test leads, a plurality of second test leads, and a plurality of third test leads are all located on a side of the test portion away from the display area, so that the active metal atoms on the test pad usually corrode and diffuse along the first test lead, the second test lead, and the third test lead to the side of the test pad away from the display area, which can reduce the corrosion and diffusion of the active metal atoms on the test pad to the side of the test pad close to the display area, thereby reducing the defective rate of the product. In addition, the second test circuit is located in the area to be cut, so that the first test lead, the second test lead, and the third test lead can all be designed for routing in the area to be cut to reduce the metal occupied area of ​​the product area, reduce the ESD risk, and reduce the space occupied by the product area, which is conducive to the narrow frame design of the display device; at the same time, the positive projection of the test lead on the substrate to be cut is prevented from overlapping with the positive projection of the signal line connection line on the substrate to be cut, thereby solving the problem of serious heating of the large resistance test lead set in the transfer layer in the related art, which leads to defective products.

[0026] In another aspect, a display device is provided, comprising the display substrate and a circuit board according to any one of the above embodiments, wherein the circuit board is bound and connected to the display substrate.

[0027] Compared with the prior art, the beneficial effects of the display device provided by the embodiment of the present disclosure are the same as the beneficial effects of the display substrate provided by any of the above embodiments, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0029] Figure 1 is a structural diagram of a display device according to some embodiments;

[0030] Figure 2 is an exploded view of a display device according to some embodiments;

[0031] Figure 3 for Figure 1 A cross-sectional view of the display device shown at II';

[0032] Figure 4 is a structural diagram of a display substrate to be cut according to some embodiments;

[0033] Figure 5 is a structural diagram of a display substrate according to some embodiments;

[0034] Figure 6 is a structural diagram of a binding circuit board of a display substrate according to some embodiments;

[0035] Figure 7 is a partially enlarged structural diagram of a display substrate to be cut according to some embodiments;

[0036] Figure 8 is a partially enlarged structural diagram of a display substrate according to some embodiments;

[0037] Fig. 9 is a structural diagram of a binding area and a to-be-cut area of ​​a display substrate to be cut according to some embodiments;

[0038] Fig.10 A structural diagram showing a binding area and a to-be-cut area of ​​a display substrate according to some embodiments;

[0039] Fig.11 is a structural diagram of a binding area and a to-be-cut area of ​​another to-be-cut display substrate according to some embodiments;

[0040] Fig.12 is a structural diagram of a binding area and a to-be-cut area of ​​another display substrate according to some embodiments;

[0041] Fig.13 is a structural diagram of a first test circuit according to some embodiments;

[0042] Fig.14 is a structural diagram of a second test circuit according to some embodiments. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0045] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0046] When describing some embodiments, the expressions "connected" and "electrically connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "electrically connected" may be used to indicate that two or more components are in direct electrical contact. However, the term "electrically connected" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0047] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0048] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0049] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0050] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0051] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0052] like Figure 1 As shown, some embodiments of the present disclosure provide a display device 100, which can be a television, a mobile phone, a computer, a laptop computer, a tablet computer, a personal digital assistant (PDA), a car computer, etc.

[0053] The display device 100 may be an electroluminescent display device or a photoluminescent display device. When the display device 100 is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot electroluminescent display device (QLED). When the display device 100 is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0054] In some embodiments, Figure 2 As shown, the display device 100 includes a display panel 1, a glass cover plate 2, and other electronic components such as a circuit board 3. The display panel 1 has a display area AA and a peripheral area BB located at least on one side of the display area AA. Figure 2 An example is given in which the peripheral area BB surrounds the display area AA.

[0055] Here, see Figure 2 and Figure 4The display area AA is an area for displaying an image, and the display area AA can be configured to set a sub-pixel P. The peripheral area BB is an area for not displaying an image, and the peripheral area BB can be configured to arrange a gate driving circuit 220 that outputs a scanning signal to the sub-pixel P of the display area AA and a gate control signal line 221 that transmits a control signal for driving the gate driving circuit 220 to work to the gate driving circuit 220.

[0056] In some embodiments, Figure 3 As shown, the display panel 1 includes a display substrate 11 and an encapsulation layer 12 for encapsulating the display substrate 11 .

[0057] Here, the encapsulation layer 12 may be an encapsulation film or an encapsulation substrate.

[0058] For example, Figure 3 As shown, the encapsulation layer 12 is an encapsulation film, and along a direction perpendicular to the display substrate 11 and away from the display substrate 11 , the encapsulation layer 12 includes a first inorganic encapsulation layer 121 , an organic encapsulation layer 122 and a second inorganic encapsulation layer 123 .

[0059] like Figure 2 , Figure 3 and Figure 4 As shown, each sub-pixel P of the display substrate 11 includes a light-emitting device and a pixel circuit 210 disposed on a substrate Sub, and the pixel circuit 210 includes a plurality of thin film transistors 111. The thin film transistor 111 includes an active layer 1111, a source 1112, a drain 1113 and a gate 1114, and the source 1112 and the drain 1113 are respectively in contact with the active layer 1111. The light-emitting device includes an anode 112, a light-emitting functional layer 113 and a cathode 114, and the anode 112 is electrically connected to the source 1112 or the drain 1113 of the thin film transistor 111 used as a driving transistor among the plurality of thin film transistors 111, Figure 3 In the figure, the anode 112 and the source 1112 of the thin film transistor 111 are electrically connected to each other.

[0060] It should be noted that the source 1112 and the drain 1113 can be interchanged. Figure 3 The 1112 in the figure represents the drain. Figure 3 The reference numeral 1113 indicates a source.

[0061] In some embodiments, Figure 3As shown, the display substrate 11 includes a semiconductor pattern, a first gate insulating film 115, a first gate pattern, a second gate insulating film 116, a second gate pattern, an interlayer insulating film 117 and a source-drain conductive layer which are stacked in sequence, the first gate pattern includes a gate 1114 of a thin film transistor 111, the source-drain conductive layer includes a source 1112 and a drain 1113 of the thin film transistor 111, and the semiconductor pattern includes an active layer 1111 of the thin film transistor 111.

[0062] On this basis, the first gate pattern further includes a first capacitor electrode 1115, and the second gate pattern includes a second capacitor electrode 1116. The orthographic projection of the first capacitor electrode 1115 on the substrate Sub at least partially overlaps with the orthographic projection of the second capacitor electrode 1116 on the substrate Sub, thereby forming a pixel circuit 210 (see Figure 4 ) storage capacitor.

[0063] The display substrate 11 further includes a pixel defining layer 118 . The pixel defining layer 118 includes a plurality of opening regions. One light emitting device is disposed in one opening region.

[0064] In some embodiments, the light-emitting functional layer 113 includes only a light-emitting layer. In other embodiments, the light-emitting functional layer 113 includes, in addition to the light-emitting layer, at least one of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0065] In some embodiments, Figure 3 As shown, the display substrate 11 further includes a spacer 119 , and the spacer 119 is disposed between the pixel defining layer 118 and the light emitting functional layer 113 .

[0066] In some embodiments, Figure 3 As shown, the display substrate 11 further includes a planar layer 120 disposed between the thin film transistor 111 and the anode 112 .

[0067] In some embodiments, Figure 3 As shown, the display substrate 11 further includes a passivation film 121 , which is disposed on a side of the source and drain conductive layer away from the substrate Sub, and the planarization layer 120 is located on a side of the passivation film 121 away from the substrate Sub.

[0068] In some embodiments, Figure 3As shown, the display substrate 11 further includes a buffer layer 122 , and the buffer layer 122 is disposed between the substrate Sub and the thin film transistor 111 .

[0069] In some related technologies, the display substrate to be tested and cut includes a test circuit, a test pad, a test lead, a pixel circuit, a binding pad and a signal line connection line arranged in a peripheral area, the test circuit and the test pad are electrically connected through the test lead, and the pixel circuit and the binding pad are electrically connected through the signal line connection line. Among them, the test lead and the signal line connection line are crossed in the routing of the display substrate, and the part where the test lead and the signal line connection line cross is located in a different film layer from the signal line connection line, and a large resistance routing is used.

[0070] However, the display substrate has a high risk of electrostatic discharge (ESD), and the active metal atoms on the test pads may corrode and diffuse into the interior of the display substrate in large quantities. In addition, during the test phase, some test leads with large resistors set in the transfer layer will heat up severely, which will damage other nearby film layers and cause product defects.

[0071] Based on this, some embodiments of the present disclosure provide a display substrate 200 to be cut. Figure 4 , having a product area MM and a to-be-cut area NN at least partially surrounding the product area MM, and the boundary line between the product area MM and the to-be-cut area NN is a cutting line L. Figure 5 After the display substrate 200 to be cut has the area NN to be cut cut along the cutting line L, a display substrate 11 is obtained. The display substrate 11 can be applied to the display device 100 of any of the above embodiments. Figure 4 The product area MM is illustrated with the area to be cut NN surrounding it.

[0072] See also Figure 4 In some embodiments, the product area MM includes a display area AA and a peripheral area BB at least partially surrounding the display area AA. Figure 4 The peripheral area BB is shown as surrounding the display area AA. The peripheral area BB includes a fan-out area CC located on one side of the display area AA along the second direction Y, and a binding area DD located on the side of the fan-out area CC away from the display area AA. Figure 6 ) is bound and connected to the display substrate 11 in the binding area DD.

[0073] Here, see Figure 4 , Figure 5 and Figure 6The fan-out area CC can be configured to set signal line connection lines (power connection line 254, data connection line 253, gate connection line 223, etc.); the binding area DD can be configured to set binding pads (for example: power pad 232, data pad 231 and gate pad 233).

[0074] In some embodiments, Figure 4 and Figure 7 As shown, the display substrate 200 to be cut includes a substrate Sub1 to be cut ( Figure 3 ), and at least one binding portion 230, at least one testing portion 240, a first testing circuit 250, a second testing circuit 260, a plurality of first testing leads 271, a plurality of second testing leads 272, and a plurality of third testing leads 273 are arranged on the substrate Sub1 to be cut.

[0075] Here, at least one binding portion 230 and at least one testing portion 240 are located in the binding area DD, and at least one testing portion 240 is located on at least one side of at least one binding portion 230 along the first direction X; at least one first test circuit 250 is located on a side of at least one binding portion 230 close to the display area AA, and each first test circuit 250 corresponds to a binding portion 230; and at least one second test circuit 260 is located in the area to be cut NN, and each second test circuit 260 corresponds to a binding portion 230.

[0076] Each binding portion 230 includes a plurality of binding pads arranged along the first direction X, and at least one binding portion 230 is configured to be connected to the circuit board 3 (see Figure 6 ) binding, each test section 240 includes a plurality of test pads arranged along a first direction X, and the test pads are configured to receive a test signal transmitted by an external circuit during a test phase.

[0077] On this basis, multiple first test leads 271, multiple second test leads 272 and multiple third test leads 273 are located on a side of at least one test part 240 away from the display area AA; the first test lead 271 is electrically connected to the test pad and the binding pad to provide a test signal for driving the first test circuit 250 to the first test circuit 250; the second test lead 272 is electrically connected to the test pad and the second test circuit 260 to provide a test signal for driving the second test circuit 260 to the second test circuit 260; the third test lead 273 is electrically connected to the binding pad and the second test circuit 260 to write a data signal to the pixel circuit 210.

[0078] From the above, it can be seen that the multiple first test leads 271, the multiple second test leads 272 and the multiple third test leads 273 are all located on the side of the test part 240 away from the display area AA, so that the active metal atoms on the test pad will usually corrode and diffuse along the first test lead 271, the second test lead 272 and the third test lead 273 to the side of the test pad away from the display area AA, which can reduce the corrosion and diffusion of the active metal atoms on the test pad to the side of the test pad close to the display area AA, thereby reducing the defective rate of the product. And the second test circuit 260 is located in the area to be cut NN. In this way, the first test lead 271, the second test lead 272 and the third test lead 273 can all be designed for routing in the area to be cut NN to reduce the metal occupied area of ​​the product area MM, reduce the ESD risk, and reduce the space occupied by the product area MM, which is beneficial to the narrow frame design of the display device 100; at the same time, it avoids the overlap of the orthographic projection of the test lead on the substrate to be cut Sub1 and the orthographic projection of the signal line connecting line on the substrate to be cut Sub1, thereby solving the problem of severe heat generation of the test lead with a large resistance set in the transfer layer in the related technology, resulting in defective products.

[0079] In some embodiments, Fig.13 As shown, the first test circuit 250 includes a first switch signal line SW1, a lighting control signal line D1, and a data control signal line PCD. The first switch signal line SW1 is configured to transmit a test signal for controlling a crack detection switch of the display substrate 11; the lighting control signal line D1 is configured to transmit a test signal for lighting a sub-pixel P; the data control signal line PCD is configured to be electrically connected to at least one column of sub-pixels P. When a crack appears on the display substrate 11, a bright line, such as a green bright line, will appear in at least one column of sub-pixels P.

[0080] In some embodiments, Fig.14 As shown, the second test circuit 260 includes a second switch signal line SW2, a first sub-pixel signal line DR, a second sub-pixel signal line DG, and a third sub-pixel signal line DB. The second switch signal line SW2 is configured to transmit a test signal for controlling the display substrate 11 to light up the switch; the first sub-pixel signal line DR is configured to transmit a test signal for lighting up the first type of sub-pixels; the second sub-pixel signal line DG is configured to transmit a test signal for lighting up the second sub-pixel; and the third sub-pixel signal line DB is configured to transmit a test signal for lighting up the third type of sub-pixels. The first type of sub-pixels are sub-pixels with a red light-emitting color, the second type of sub-pixels are sub-pixels with a green light-emitting color, and the third type of sub-pixels are sub-pixels with a blue light-emitting color, but the present disclosure is not limited thereto.

[0081] In some embodiments, see Figure 4The display substrate 200 to be cut also includes a plurality of sub-pixels P, a plurality of gate lines 221, a plurality of data lines 251 and a plurality of power lines 252 arranged in the display area AA, and a plurality of gate control signal lines 222, at least one gate driving circuit 220, a plurality of data connection lines 253, a plurality of power connection lines 254 and a plurality of gate connection lines 223 arranged in the peripheral area BB.

[0082] Here, multiple gate lines 221, multiple data lines 251 and multiple power lines 252 are all electrically connected to multiple sub-pixels P, and the multiple binding pads of each binding part 230 include multiple data pads 231 and multiple power pads 232. The binding part corresponding to the gate connection line 223 also includes multiple gate pads 233. The power connection line 254 is electrically connected to the power line 252 and the power pad 232 to provide a power signal to the sub-pixel P to emit light. The data connection line 253 is electrically connected to the data pad 231 and the data line 251 to write data signals to the pixel circuit 210. The gate connection line 223 is electrically connected to the gate control signal line 222 and the gate pad 233 to provide a control signal for driving the gate drive circuit 220 to operate.

[0083] It should be noted that the gate control signal line 222 includes a clock signal line CLK, an initialization signal line STV, a first constant voltage signal line VGH, a second constant voltage signal line VGL, etc. The gate control signal line 222 is configured to transmit a control signal for driving the gate driving circuit 220 to work.

[0084] The data connection line 253 includes a first sub-data connection line 2531 and a second sub-data connection line 2532 . The first sub-data connection line 2531 is electrically connected to the data line 253 and the first test circuit 250 . The second sub-data connection line 2532 is electrically connected to the first test circuit 250 and the data pad 231 .

[0085] In some embodiments, Figure 4 and Figure 7 As shown, the at least one testing portion 240 includes a first testing portion 2410 and a second testing portion 2420 , and the first testing portion 2410 and the second testing portion 2420 are disposed on both sides of the at least one binding portion 230 along the first direction X.

[0086] In some embodiments, Fig. 9As shown, at least one binding part 230 includes a first binding part 2310 and a second binding part 2320; at least one testing part 240 also includes a third testing part 2430 and a fourth testing part 2440. The first testing part 2410, the first binding part 2310, the third testing part 2430, the fourth testing part 2440, the second binding part 2320, and the second testing part 2420 are arranged in sequence along the first direction X. At this time, the first testing part 2410 and the third testing part 2430 can transmit a test signal to the first binding part 2310 at the same time; the fourth testing part 2440 and the second testing part 2420 can transmit a test signal to the second binding part 2320 at the same time.

[0087] On this basis, if Fig. 9 As shown, the display substrate 200 to be cut in some embodiments of the present disclosure further includes a plurality of first connecting wires 274, which are disposed on the side of the third test section 2430 and the fourth test section 2440 close to the display area AA, and the first connecting wires 274 are electrically connected to the test pads of the third test section 2430 and the test pads of the fourth test section 2440. In this case, the test signals transmitted by the test pads of the third test section 2430 and the test pads of the fourth test section 2440 can be ensured to be synchronized, thereby enhancing stability.

[0088] In some embodiments, Fig.11 As shown, at least one binding part 230 includes a first binding part 2310, a second binding part 2320, a third binding part 2330 and a fourth binding part 2340; at least one testing part 240 includes a first testing part 2410, a second testing part 2420, a third testing part 2430, a fourth testing part 2440, a fifth testing part 2450, a sixth testing part 2460, a seventh testing part 2470 and an eighth testing part 2480; wherein the first testing part 2410, the first binding part 2310, the third testing part 2430, the fourth testing part 2440, the third binding part 2330, the fifth testing part 2450, the sixth testing part 2460, the fourth binding part 2340, the seventh testing part 2470, the eighth testing part 2480, the second binding part 2320, and the second testing part 2420 are arranged in sequence along the first direction X.

[0089] At this time, the first test part 2410 and the third test part 2430 can simultaneously transmit test signals to the first binding part 2310; the fourth test part 2440 and the fifth test part 2450 can simultaneously transmit test signals to the third binding part 2330; the sixth test part 2460 and the seventh test part 2470 can simultaneously transmit test signals to the fourth binding part 2340; the eighth test part 2480 and the second test part 2420 can simultaneously transmit test signals to the second binding part 2320.

[0090] On this basis, if Fig.11 As shown, the display substrate 200 to be cut further includes a plurality of second connecting wires 275 and a plurality of third connecting wires 276. The plurality of second connecting wires 275 are arranged on the side of the seventh test section 2470 and the eighth test section 2480 close to the display area AA, and the second connecting wires 275 are electrically connected to the test pads of the seventh test section 2470 and the test pads of the eighth test section 2480; the plurality of third connecting wires 276 are arranged on the side of the fifth test section 2450 and the sixth test section 2460 away from the display area AA, and the third connecting wires 276 are electrically connected to the test pads of the fifth test section 2450 and the test pads of the sixth test section 2460. In this case, the test signals transmitted by the test pads of the fifth test section 2450 and the sixth test section 2460 can be synchronized, and the test signals transmitted by the test pads of the seventh test section 2470 and the test pads of the eighth test section 2480 can be synchronized, thereby enhancing stability. In addition, a plurality of third connecting wires 276 are disposed on the side of the fifth test section 2450 and the sixth test section 2460 away from the display area AA, so that other circuit structures can be arranged on the side of the fifth test section 2450 and the sixth test section 2460 close to the display area AA.

[0091] In some embodiments, see Figure 7 and Fig. 9 The multiple binding pads of the first binding part 2310 and the second binding part 2320 include multiple gate pads 233, and the multiple test pads of the first test part 2410 and the second test part 2420 include a first test pad 241 and a second test pad 242. The first test pad 241 is configured to receive a control test signal transmitted by an external circuit during the test phase for driving the test circuit (the first test circuit 250 and the second test circuit 260) to work; the second test pad 242 is configured to receive a control test signal transmitted by an external circuit during the test phase for driving the gate drive circuit 220 to work.

[0092] On this basis, if Figure 7 and Fig. 9 As shown, the display substrate 200 to be cut includes two gate drive circuits 220 and a plurality of fourth test leads 277, the two gate drive circuits 220 are respectively arranged in the peripheral area BB on both sides of the display area AA along the first direction X, and each gate drive circuit 220 is electrically connected to a plurality of gate lines 221; the plurality of fourth test leads 277 are located on a side of at least one test portion 240 away from the display area AA, and the fourth test leads 277 are electrically connected to the second test pad 240 and the gate pad 233 to transmit to the gate drive circuit 220 a control test signal for driving the gate drive circuit 220 to work.

[0093] In some embodiments, Figure 4 and Figure 7As shown, the first test lead 271 includes a first routing segment 2711, a second routing segment 2712 and a third routing segment 2713. One end of the first routing segment 2711 is located in the product area MM and is electrically connected to the first test pad 241, and the other end extends to the to-be-cut area NN. One end of the second routing segment 2712 is located in the product area MM and is electrically connected to one end of the data pad 231 close to the to-be-cut area NN, and the other end extends to the to-be-cut area NN; the third routing segment 2713 is arranged in the to-be-cut area NN, and one end of the third routing segment 2713 is electrically connected to the first routing segment 2711, and the other end is electrically connected to the second routing segment 2712.

[0094] In some embodiments, Figure 4 and Figure 7 As shown, the second test lead 272 includes a fourth routing segment 2721 and a fifth routing segment 2722, one end of the fourth routing segment 2721 is located in the product area MM and is electrically connected to the first test pad 241, and the other end extends to the to-be-cut area NN. In addition, the fifth routing segment 2722 is arranged in the to-be-cut area NN, one end of the fifth routing segment 2722 is electrically connected to the fourth routing segment 2721, and the other end is electrically connected to the second test circuit 260.

[0095] In some embodiments, Fig.11 As shown, the fourth test lead 277 includes a sixth routing segment 2771, a seventh routing segment 2772 and an eighth routing segment 2773. One end of the sixth routing segment 2771 is located in the product area MM and is electrically connected to the second test pad 242, and the other end extends to the to-be-cut area NN. One end of the seventh routing segment 2772 is located in the product area MM and is electrically connected to one end of the gate pad 233 close to the to-be-cut area NN, and the other end extends to the to-be-cut area NN; the eighth routing segment 2773 is arranged in the to-be-cut area NN, and one end of the eighth routing segment 2773 is electrically connected to the sixth routing segment 2771, and the other end is electrically connected to the seventh routing segment 2772.

[0096] In some embodiments, Figure 4 and Figure 7 As shown, the gate connection line 223 includes a ninth routing segment 2231, a tenth routing segment 2232 and an eleventh routing segment 2233, the ninth routing segment 2231 is electrically connected to the gate driving circuit 220; the tenth routing segment 2232 is electrically connected to the gate pad 233; one end of the eleventh routing segment 2233 is electrically connected to the ninth routing segment 2231, and the other end is electrically connected to the tenth routing segment 2232; the orthographic projection of the eleventh routing segment 2233 on the substrate Sub1 to be cut intersects with the orthographic projection of the power connection line 254 on the substrate Sub1 to be cut.

[0097] In some embodiments, see Figure 7At least two of the first routing segment 2711, the second routing segment 2712, the fourth routing segment 2721, the sixth routing segment 2771, the seventh routing segment 2772 and the eleventh routing segment 2233 are arranged on the same layer, and at least two of the third routing segment 2713, the fifth routing segment 2722, the eighth routing segment 2773, the ninth routing segment 2231, the tenth routing segment 2232 and the power connection line 254 are arranged on the same layer.

[0098] It should be noted that the fourth test lead 273 can be set on the same layer with at least one of the first routing segment 2711, the second routing segment 2712, the fourth routing segment 2721, the sixth routing segment 2771, the seventh routing segment 2772 and the eleventh routing segment 2233, and can also be set on the same layer with at least one of the third routing segment 2713, the fifth routing segment 2722, the eighth routing segment 2773, the ninth routing segment 2231, the tenth routing segment 2232 and the power connection line 254, and the present disclosure does not limit this.

[0099] Among them, the resistance of the materials of the first routing segment 2711, the second routing segment 2712, the fourth routing segment 2721, the sixth routing segment 2771, the seventh routing segment 2772 and the eleventh routing segment 2233 is greater than the resistance of the materials of the third routing segment 2713, the fifth routing segment 2722, the eighth routing segment 2773, the ninth routing segment 2231, the tenth routing segment 2232 and the power connection line 254.

[0100] Exemplarily, the material of the first routing segment 2711, the second routing segment 2712, the fourth routing segment 2721, the sixth routing segment 2771, the seventh routing segment 2772 and the eleventh routing segment 2233 includes molybdenum. The material of the third routing segment 2713, the fifth routing segment 2722, the eighth routing segment 2773, the ninth routing segment 2231, the tenth routing segment 2232 and the power connection line 254 includes aluminum.

[0101] In some embodiments, in combination Figure 3 and Figure 7 The first routing segment 2711, the second routing segment 2712, the fourth routing segment 2721, the sixth routing segment 2771, the seventh routing segment 2772 and the eleventh routing segment 2233 can be manufactured on the same layer as the gate 1114, and the third routing segment 2713, the fifth routing segment 2722, the eighth routing segment 2773, the ninth routing segment 2231, the tenth routing segment 2232 and the power connection line 254 can be manufactured on the same layer as the source 1112 and the drain 1113, and the process is simple.

[0102] Some embodiments of the present disclosure further provide a display substrate 11 , which can be formed by cutting the display substrate 200 to be cut according to any of the above embodiments along a cutting line L, and can be applied to the display device 100 according to any of the above embodiments.

[0103] In some embodiments, Figure 5 and Figure 8 As shown, the display substrate 11 includes a base substrate Sub2 (in Figure 3 , and a plurality of sub-pixels P, at least one binding portion 230, at least one testing portion 240, a plurality of residual test leads 280, and a plurality of residual binding leads 290 arranged on the substrate Sub2.

[0104] The base substrate Sub2 includes a display area AA and a peripheral area BB at least partially surrounding the display area AA. Figure 5 The peripheral area BB is shown as surrounding the display area AA. The peripheral area BB includes a fan-out area CC located on one side of the display area AA along the second direction Y, and a binding area DD located on the side of the fan-out area CC away from the display area AA. Figure 6 ) is bound and connected to the display substrate 11 in the binding area DD.

[0105] like Figure 5 , Figure 6 and Figure 8 As shown, at least one binding portion 230 and at least one testing portion 240 are located in the binding area DD, and at least one testing portion 240 is located on at least one side of at least one binding portion 230 along the first direction X. Each binding portion 230 includes a plurality of binding pads arranged along the first direction X, and at least one binding portion 230 is configured to be connected to the circuit board 3 (see Figure 6 ) binding; each test section 240 includes a plurality of test pads arranged along the first direction X, and the test pads are configured to receive a test signal transmitted by an external circuit during the test phase.

[0106] On this basis, if Figure 8 As shown, multiple residual test leads 280 are located on a side of at least one test portion 240 away from the display area AA, and the residual test leads 280 are electrically connected to the test pads; multiple residual binding leads 290 are located on a side of at least one binding portion 230 away from the display area AA, and the residual binding leads 290 are electrically connected to at least part of the binding pads.

[0107] It should be understood that the multiple residual test leads 280 and the multiple residual binding leads 290 are some of the leads remaining after the substrate 200 to be cut is cut in the front-end process. The leads are used to electrically connect the test pads, the cut-off test circuit (the second test circuit 260) and the corresponding binding pads to ensure that the test signal transmitted by the external circuit received during the test phase can detect the circuit and signal line to determine whether there is a short circuit or open circuit problem.

[0108] Among them, a plurality of residual test leads 280 are located on a side of at least one test part 240 away from the display area AA, and a plurality of residual binding leads 290 are located on a side of at least one binding part 230 away from the display area AA. In this way, the active metal atoms on the test pad will usually corrode and diffuse along the residual test leads 280 to the side of the test pad away from the display area AA, which can reduce the corrosion and diffusion of the active metal atoms on the test pad to the inside of the display substrate 11, that is, the side of the test pad close to the display area AA, thereby reducing the defective rate of the product. In addition, there is no test lead connected to the test pad on the side of the binding part 230 close to the display area AA, which can reduce the occupied area of ​​the metal, reduce the ESD risk, and reduce the size of the display substrate 11, which is conducive to the narrow frame design of the display device 100; at the same time, it avoids the overlap of the positive projection of the test lead on the base substrate Sub2 and the positive projection of the signal line connection line on the base substrate Sub2, thereby solving the problem of serious heating of the large resistance test lead set in the transfer layer in the related art, which leads to product defects.

[0109] It should be noted that, when the display substrate 11 is obtained by cutting the display substrate 200 to be cut provided by any of the above embodiments along the cutting line L, the multiple residual test leads 280 and the multiple residual binding leads 290 can be the parts remaining on the display substrate 11 after cutting the multiple first test leads 271, the multiple second test leads 272 and the multiple third test leads 273.

[0110] In some embodiments, see Figure 5 The display substrate 11 also includes a plurality of sub-pixels P, a plurality of gate lines 221, a plurality of data lines 251 and a plurality of power lines 252 arranged in the display area AA, and a plurality of gate control signal lines 222, at least one gate driving circuit 220, a plurality of power connection lines 254, a plurality of data connection lines 253 and a plurality of gate connection lines 223 arranged in the peripheral area BB.

[0111] Here, multiple gate lines 221, multiple data lines 251 and multiple power lines 252 are all electrically connected to multiple sub-pixels P, and the multiple binding pads of each binding part 230 include multiple data pads 231 and multiple power pads 232. The binding part 230 corresponding to the gate connection line 223 also includes multiple gate pads 233. The power connection line 254 is electrically connected to the power line 252 and the power pad 232 to provide a power signal to the sub-pixel P to emit light. The data connection line 253 is electrically connected to the data pad 231 and the data line 251 to write data signals to the pixel circuit 210. The gate connection line 223 is electrically connected to the gate control signal line 222 and the gate pad 233 to provide a control signal for driving the gate drive circuit 220 to operate.

[0112] In some embodiments, see Figure 8 The power connection line 254 at least includes a first power connection line 2541 and a second power connection line 2542 , the first power connection line 2541 is configured to transmit a first voltage signal VSS, and the second power connection line 2542 is configured to transmit a second voltage signal VDD.

[0113] In some embodiments, each binding portion 230 includes two groups of power pads 232 , and the two groups of power pads 232 are respectively located at two opposite sides of the data pad 231 and the gate pad 233 along the first direction X.

[0114] In this way, during the test phase, the corresponding test signal can be input through the test pad of the test unit by using an external circuit, and the power signal can be directly input through the power pad 232 adjacent to the test pad to detect the circuit and signal line. In other words, the non-residual test lead 280 is electrically connected to the power pad 232 in the plurality of binding pads, that is, there is no need to separately set up a test line for transmitting the power signal, and no test line for transmitting the power signal will be exposed at the edge of the side of the display substrate 11, which can avoid the problem of serious heating of the large resistance line that transmits a large current.

[0115] In some embodiments, as 5 and Figure 8 As shown, the display substrate 11 further includes at least one first test circuit 250 , and the at least one first test circuit 250 is located on a side of at least one binding portion 230 close to the display area AA; each first test circuit 250 corresponds to one binding portion 230 .

[0116] The data connection line 253 includes a first sub-data connection line 2531 and a second sub-data connection line 2532 . The first sub-data connection line 2531 is electrically connected to the data line 253 and the first test circuit 250 . The second sub-data connection line 2532 is electrically connected to the first test circuit 250 and the data pad 231 .

[0117] In some embodiments, Fig.13 As shown, the first test circuit 250 includes a first switch signal line SW1, a lighting control signal line D1, and a data control signal line PCD. The first switch signal line SW1 is configured to transmit a test signal for controlling a crack detection switch of the display substrate 11; the lighting control signal line D1 is configured to transmit a test signal for lighting a sub-pixel P; the data control signal line PCD is configured to be electrically connected to at least one column of sub-pixels P. When a crack appears on the display substrate 11, a bright line, such as a green bright line, will appear in at least one column of sub-pixels P.

[0118] In some embodiments, see Figure 5 , Figure 8 and Fig.10As shown, at least one test section 240 includes a first test section 2410 and a second test section 2420, and the first test section 2410 and the second test section 2420 are arranged on both sides of at least one binding section 230 along the first direction X. Accordingly, the plurality of residual test leads 280 include a plurality of first residual test leads 281 and a plurality of second residual test leads 282, and the plurality of first residual test leads 281 are electrically connected to a plurality of test pads of the first test section 2410; and the plurality of second residual test leads 282 are electrically connected to a plurality of test pads of the second test section 2420.

[0119] In some embodiments, Fig.10 As shown, at least one binding part 230 includes a first binding part 2310 and a second binding part 2320; at least one testing part 240 also includes a third testing part 2430 and a fourth testing part 2440. The first testing part 2410, the first binding part 2310, the third testing part 2430, the fourth testing part 2440, the second binding part 2320, and the second testing part 2420 are arranged in sequence along the first direction X. At this time, the first testing part 2410 and the third testing part 2430 can transmit a test signal to the first binding part 2310 at the same time; the fourth testing part 2440 and the second testing part 2420 can transmit a test signal to the second binding part 2320 at the same time.

[0120] In addition, the multiple residual test leads 280 also include multiple third residual test leads 283 and multiple fourth residual test leads 284, the multiple third residual test leads 283 are electrically connected to the multiple test pads of the third test part 2430; the multiple fourth residual test leads 284 are electrically connected to the multiple test pads of the fourth test part 2840.

[0121] On this basis, if Fig.10 As shown, the display substrate 11 of some embodiments of the present disclosure further includes a plurality of first connecting wires 274, which are disposed on the side of the third test section 2430 and the fourth test section 2440 close to the display area AA, and the first connecting wires 274 are electrically connected to the test pads of the third test section 2430 and the test pads of the fourth test section 2440. In this case, the test signals transmitted by the test pads of the third test section 2430 and the test pads of the fourth test section 2440 can be ensured to be synchronized, thereby enhancing stability.

[0122] In some embodiments, Fig.12As shown, at least one binding part 230 includes a first binding part 2310, a second binding part 2320, a third binding part 2330 and a fourth binding part 2340; at least one testing part 240 includes a first testing part 2410, a second testing part 2420, a third testing part 2430, a fourth testing part 2440, a fifth testing part 2450, a sixth testing part 2460, a seventh testing part 2470 and an eighth testing part 2480; wherein the first testing part 2410, the first binding part 2310, the third testing part 2430, the fourth testing part 2440, the third binding part 2330, the fifth testing part 2450, the sixth testing part 2460, the fourth binding part 2340, the seventh testing part 2470, the eighth testing part 2480, the second binding part 2320, and the second testing part 2420 are arranged in sequence along the first direction X.

[0123] At this time, the first test part 2410 and the third test part 2430 can simultaneously transmit test signals to the first binding part 2310; the fourth test part 2440 and the fifth test part 2450 can simultaneously transmit test signals to the third binding part 2330; the sixth test part 2460 and the seventh test part 2470 can simultaneously transmit test signals to the fourth binding part 2340; the eighth test part 2480 and the second test part 2420 can simultaneously transmit test signals to the second binding part 2320.

[0124] On this basis, if Fig.12 As shown, the multiple residual test leads 280 also include multiple fifth residual test leads 285, multiple sixth residual test leads 286, multiple seventh residual test leads 287 and multiple eighth residual test leads 288. The multiple fifth residual test leads 285 are electrically connected to the multiple test pads of the fifth test section 2450; the multiple sixth residual test leads 286 are electrically connected to the multiple test pads of the sixth test section 2460; the multiple seventh residual test leads 287 are electrically connected to the multiple test pads of the seventh test section 2470; and the multiple eighth residual test leads 288 are electrically connected to the multiple test pads of the eighth test section 2480.

[0125] In addition, the display substrate 11 further includes a plurality of second connecting wires 275 disposed on the side of the seventh test section 2470 and the eighth test section 2480 close to the display area AA, and the second connecting wires 275 are electrically connected to the test pads of the seventh test section 2470 and the test pads of the eighth test section 2480. In this case, the test signals transmitted by the test pads of the seventh test section 2470 and the test pads of the eighth test section 2480 can be synchronized to enhance stability.

[0126] In some embodiments, Figure 8 and Fig.10As shown, the multiple binding pads of the first binding part 2310 and the second binding part 2320 include multiple gate pads 233, and the multiple test pads of the first test part 2410 and the second test part 2420 include a first test pad 241 and a second test pad 242. The first test pad 241 is configured to receive a control test signal transmitted by an external circuit during the test phase for driving the test circuit (the first test circuit 250 and the second test circuit 260) to work; the second test pad 242 is configured to receive a control test signal transmitted by an external circuit during the test phase for driving the gate drive circuit 220 to work.

[0127] On this basis, if Figure 8 and Fig.10 As shown, the display substrate 11 includes two gate driving circuits 220, which are respectively arranged in the peripheral area BB on both sides of the display area AA along the first direction X, each gate driving circuit 220 is electrically connected to a plurality of gate lines 221; a plurality of gate control signal lines 222 are electrically connected to the gate driving circuit 220, and the gate connecting line 223 is electrically connected to the gate control signal line 222 and the gate pad 233.

[0128] On this basis, the binding residual wires 290 include a plurality of first residual binding wires 291 and a plurality of second residual binding wires 292 . The plurality of first residual binding wires 291 are electrically connected to the data pads 231 , and the plurality of second residual binding wires 292 are electrically connected to the gate pads 233 .

[0129] In some embodiments, the display substrate 11 further includes floating pads 234 , which are disposed between the binding pads of the binding portion 230 and / or between the testing pads of the testing portion 240 that transmit different signals.

[0130] In some embodiments, the display substrate 11 further includes an initialization pad and an initialization connection line, and the initialization pad is configured to transmit an initialization signal VINIT.

[0131] Some embodiments of the present disclosure further provide a display device 100 , which includes a display substrate 11 and a circuit board 3 according to any of the above embodiments, wherein the circuit board 3 is bound and connected to the display substrate 11 .

[0132] Here, the circuit board 3 may be a chip on flex (COF) or a flexible printed circuit (FPC), on which a source driver chip (Source integrated circuit, Source IC) may be disposed, and the Source IC is used to provide data signals to the display substrate 11 .

[0133] The circuit board 3 is provided with pads, and the pads are connected to the binding pads (including the power pad 232, the gate pad 233, the data pad 231, etc.) of the display substrate 11 to achieve electrical connection between the circuit board 3 and the display substrate 11. The circuit board 3 can also be connected to a driving circuit board, which is configured to provide the display substrate 11 with various signals required by the display substrate 11.

[0134] Compared with the prior art, the beneficial effects of the display device 100 provided in the embodiment of the present disclosure are the same as the beneficial effects of the display substrate 11 provided in any of the above embodiments, and are not elaborated herein.

[0135] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a display area and a peripheral area at least partially surrounding the display area; A plurality of sub-pixels are located in the display area; a plurality of data lines, located in the display area and electrically connected to the plurality of sub-pixels; at least one binding portion, located in the peripheral area, the binding portion comprising a plurality of binding pads arranged along a first direction, the at least one binding portion being configured to be bound to a circuit board, the plurality of binding pads comprising a plurality of data pads; A plurality of data connection lines are located in the peripheral area, and the data connection lines are electrically connected to the data pads and the data lines; at least one testing section, located at at least one side of the at least one binding section along the first direction, the testing section comprising a plurality of testing pads arranged along the first direction, the testing pads being configured to receive a testing signal transmitted by an external circuit during a testing phase; A plurality of residual test leads are located on a side of the at least one test portion away from the display area, and the residual test leads are electrically connected to the test pad; and the residual test leads connected to the test pad do not exist on a side of the binding portion close to the display area; A plurality of residual binding leads are located at a side of the at least one binding portion away from the display area, and the residual binding leads are electrically connected to at least a portion of the binding pads.

2. The display substrate according to claim 1, characterized in that: The at least one testing portion comprises a first testing portion and a second testing portion, wherein the first testing portion and the second testing portion are arranged on both sides of the at least one binding portion along the first direction; The plurality of residual test leads include: a plurality of first residual test leads electrically connected to a plurality of test pads of the first test part; A plurality of second residual test leads are electrically connected to a plurality of test pads of the second test part.

3. The display substrate according to claim 2, characterized in that: The at least one binding portion includes a first binding portion and a second binding portion; the at least one testing portion also includes a third testing portion and a fourth testing portion; Wherein, the first testing portion, the first binding portion, the third testing portion, the fourth testing portion, the second binding portion, and the second testing portion are arranged in sequence along the first direction; The plurality of residual test leads also include: a plurality of third residual test leads electrically connected to the plurality of test pads of the third test part; A plurality of fourth residual test leads are electrically connected to a plurality of test pads of the fourth test part.

4. The display substrate according to claim 3, characterized in that: Also includes: A plurality of first connecting wires are arranged on a side of the third test section and the fourth test section close to the display area, and the first connecting wires are electrically connected to the test pads of the third test section and the test pads of the fourth test section.

5. The display substrate according to claim 4, characterized in that: The at least one binding section further includes a third binding section and a fourth binding section, and the at least one testing section further includes a fifth testing section, a sixth testing section, a seventh testing section and an eighth testing section; Wherein, the first testing portion, the first binding portion, the third testing portion, the fourth testing portion, the third binding portion, the fifth testing portion, the sixth testing portion, the fourth binding portion, the seventh testing portion, the eighth testing portion, the second binding portion, and the second testing portion are arranged in sequence along the first direction; The plurality of residual test leads also include: a plurality of fifth residual test leads electrically connected to the plurality of test pads of the fifth test part; a plurality of sixth residual test leads electrically connected to the plurality of test pads of the sixth test part; a plurality of seventh residual test leads electrically connected to the plurality of test pads of the seventh test part; A plurality of eighth residual test leads are electrically connected to a plurality of test pads of the eighth test part.

6. The display substrate according to claim 5, characterized in that: Also includes: A plurality of second connecting wires are arranged on a side of the seventh test section and the eighth test section close to the display area, and the second connecting wires are electrically connected to the test pads of the seventh test section and the test pads of the eighth test section.

7. The display substrate according to any one of claims 2 to 6, characterized in that: The plurality of binding pads of the first binding portion and the second binding portion further include a plurality of gate pads; The plurality of test pads of the first test section and the second test section include a first test pad and a second test pad, wherein the first test pad is configured to receive a control test signal transmitted by an external circuit for driving the test circuit to work during a test phase; and the second test pad is configured to receive a control test signal transmitted by an external circuit for driving the gate drive circuit to work during a test phase; The display substrate further comprises: A plurality of gate lines, located in the display area and electrically connected to the plurality of sub-pixels; Two gate driving circuits are respectively arranged in the peripheral areas on both sides of the display area along the first direction, and each of the gate driving circuits is electrically connected to the plurality of gate lines; a plurality of gate control signal lines, located in the peripheral area and electrically connected to the gate drive circuit; A plurality of gate connection lines are located in the peripheral area, and the gate connection lines are electrically connected to the gate control signal line and the gate pad.

8. The display substrate according to claim 7, characterized in that: The binding residual lead comprises: A plurality of first residual binding leads electrically connected to the data pad; A plurality of second residual bonding wires are electrically connected to the gate pad.

9. The display substrate according to claim 8, characterized in that: The plurality of binding pads of the binding portion further include a plurality of power supply pads; The display substrate further comprises: A plurality of power lines, located in the display area and electrically connected to the plurality of sub-pixels; A plurality of power connection lines are located in the peripheral area, and the power connection lines are electrically connected to the power lines and the power pads.

10. The display substrate according to claim 9, characterized in that: The binding portion further includes two groups of power pads, and the two groups of power pads are respectively located at two opposite sides of the data pad and the gate pad along the first direction.

11. The display substrate according to claim 1, characterized in that: Also includes: at least one first test circuit, located at a side of the at least one binding portion close to the display area; each first test circuit corresponds to one binding portion; The data connection line includes a first sub-data connection line and a second sub-data connection line, the first sub-data connection line is electrically connected to the data line and the first test circuit, and the second sub-data connection line is electrically connected to the first test circuit and the data pad.

12. A display substrate to be cut, characterized in that: include: A substrate to be cut, comprising a product area and an area to be cut at least partially surrounding the product area, wherein the product area comprises a display area and a peripheral area at least partially surrounding the display area; A plurality of sub-pixels are located in the display area; a plurality of data lines, located in the display area and electrically connected to the plurality of sub-pixels; at least one binding portion, located in the peripheral area, the binding portion comprising a plurality of binding pads arranged along a first direction, the at least one binding portion being configured to be bound to a circuit board, the plurality of binding pads comprising a plurality of data pads; A plurality of data connection lines are located in the peripheral area, and the data connection lines are electrically connected to the data pads and the data lines; at least one testing section, located at at least one side of the at least one binding section along the first direction, the testing section comprising a plurality of testing pads arranged along the first direction, the testing pads being configured to receive a testing signal transmitted by an external circuit during a testing phase; At least one second test circuit is located in the to-be-cut area, and each of the second test circuits corresponds to a binding portion; a plurality of first test leads, located at a side of the at least one test portion away from the display area, the first test leads being electrically connected to the test pad and the binding pad; a plurality of second test leads, located at a side of the at least one test portion away from the display area, the second test leads being electrically connected to the test pad and the second test circuit; a plurality of third test leads, located at a side of the at least one test portion away from the display area, the third test leads being electrically connected to the binding pad and the second test circuit; The first test lead, the second test lead, and the third test lead connected to the test pad do not exist on a side of the binding portion close to the display area.

13. The display substrate to be cut according to claim 12, characterized in that: The at least one binding part includes a first binding part, a second binding part, a third binding part and a fourth binding part; the at least one testing part includes a first testing part, a second testing part, a third testing part, a fourth testing part, a fifth testing part, a sixth testing part, a seventh testing part and an eighth testing part; Wherein, the first testing portion, the first binding portion, the third testing portion, the fourth testing portion, the third binding portion, the fifth testing portion, the sixth testing portion, the fourth binding portion, the seventh testing portion, the eighth testing portion, the second binding portion, and the second testing portion are arranged in sequence along the first direction; The display substrate to be cut further comprises: A plurality of first connecting wires are arranged on a side of the third test part and the fourth test part close to the display area, and the first connecting wires are electrically connected to the test pads of the third test part and the test pads of the fourth test part; A plurality of second connecting wires are arranged on a side of the seventh test section and the eighth test section close to the display area, and the second connecting wires are electrically connected to the test pads of the seventh test section and the test pads of the eighth test section; A plurality of third connecting wires are arranged on a side of the fifth test section and the sixth test section away from the display area, and the third connecting wires are electrically connected to the test pads of the fifth test section and the test pads of the sixth test section.

14. The display substrate to be cut according to claim 13, characterized in that: The plurality of binding pads of the first binding part and the second binding part further include a plurality of gate pads; the plurality of test pads of the first test part and the second test part include a first test pad and a second test pad, the first test pad being configured to receive a control test signal transmitted by an external circuit for driving the test circuit to work during a test phase; the second test pad being configured to receive a control test signal transmitted by an external circuit for driving the gate drive circuit to work during a test phase; The display substrate to be cut further comprises: A plurality of gate lines, located in the display area and electrically connected to the plurality of sub-pixels; Two gate driving circuits are respectively arranged in the peripheral areas on both sides of the display area along the first direction, and each of the gate driving circuits is electrically connected to the plurality of gate lines; a plurality of gate control signal lines, located in the peripheral area and electrically connected to the two gate drive circuits; A plurality of gate connection lines are located in the peripheral area, and the gate connection lines are electrically connected to the gate control signal line and the gate pad; A plurality of fourth test leads are located at a side of the at least one test portion away from the display area, and the fourth test leads are electrically connected to the second test pad and the gate pad.

15. The display substrate to be cut according to any one of claims 12 to 14, characterized in that: Also includes: at least one first test circuit, located at a side of the at least one binding portion close to the display area, each of the first test circuits corresponding to one of the binding portions; The data connection line includes a first sub-data connection line and a second sub-data connection line, the first sub-data connection line is electrically connected to the data line and the first test circuit, and the second sub-data connection line is electrically connected to the first test circuit and the data pad.

16. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 11; A circuit board is bound and connected to the display substrate.

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