Substrate structure and electronic device including the substrate structure

Abstract

The present disclosure provides a substrate structure and an electronic device including the substrate structure, the substrate structure including: a first printed circuit board having a first side and a second side opposite to each other; and a plurality of passive components connected to the first side of the first printed circuit board. The plurality of passive components include a first group and a second group, the first group including a plurality of first passive components arranged adjacent to each other, and the second group including a plurality of second passive components arranged adjacent to each other. The minimum distance between the first group and the second group is greater than at least one of the minimum distance between adjacent first passive components among the plurality of first passive components and the minimum distance between adjacent second passive components among the plurality of second passive components. The electronic device includes a first printed circuit board arranged on a mainboard and having a semiconductor chip and a plurality of passive components on opposite sides thereof.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2020-0030246, filed on March 11, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0002] The present disclosure relates to a substrate structure and an electronic device including the substrate structure. Background Art

[0003] With the trend towards high-performance electronic products, the number and integration density of input / output (I / O) units have increased significantly, and therefore there is a demand for high-layer and large-scale substrate technologies. For example, it is necessary to increase the size and number of layers of flip-chip ball grid array (FCBGA) substrates for high-performance semiconductors. Such demands cause problems such as increased technical difficulty and reduced yield in manufacturing and installation, which leads to increased costs. Therefore, there is a need for technologies that can reduce manufacturing costs while maintaining semiconductor performance. In addition, with the high-performance trend of electronic products, power supply integration has become an important feature. Summary of the Invention

[0004] An aspect of the present disclosure is to provide a substrate structure capable of improving power supply integration and an electronic device including the substrate structure.

[0005] An aspect of the present disclosure is to provide a substrate structure capable of satisfying demands for highly multi-layered and large-scale substrates, and an electronic device including the substrate structure.

[0006] An aspect of the present disclosure is to provide a substrate structure capable of reducing costs and an electronic device including the substrate structure.

[0007] According to an aspect of the present disclosure, a plurality of passive components are grouped on a surface of a substrate to overlap with a functional circuit of a semiconductor chip mounted on the substrate.

[0008] According to an aspect of the present disclosure, a printed circuit board is disposed on another printed circuit board to provide a substrate structure.

[0009] For example, a substrate structure includes: a first printed circuit board having a first side and a second side opposite to each other; and a plurality of passive components connected to the first side of the first printed circuit board. The plurality of passive components includes a first group and a second group, the first group including a plurality of first passive components disposed adjacent to each other, and the second group including a plurality of second passive components disposed adjacent to each other. A minimum distance between the first group and the second group is greater than at least one of a minimum distance between adjacent first passive components in the plurality of first passive components and a minimum distance between adjacent second passive components in the plurality of second passive components.

[0010] For example, an electronic device includes: a mainboard; a first printed circuit board disposed on the mainboard; a semiconductor chip disposed on one side of the first printed circuit board; and a plurality of passive components disposed on the other side of the first printed circuit board. The plurality of passive components includes a first group and a second group, the first group including a plurality of first passive components, and the second group including a plurality of second passive components. The semiconductor chip includes a first functional circuit and a second functional circuit disposed adjacent to each other on a plane. When viewed from above, at least a portion of the first group overlaps with the first functional circuit, and when viewed from above, at least a portion of the second group overlaps with the second functional circuit.

[0011] In another aspect of the present disclosure, a printed circuit board has a first surface and a second surface opposing each other in a first direction, and is configured with a semiconductor chip mounted on the second surface, the semiconductor chip having a first functional circuit and a second functional circuit arranged adjacent to each other in a plane. The printed circuit board includes: a planar insulating layer; a first passivation layer and a second passivation layer, each disposed between the planar insulating layer and a corresponding one of the first and second surfaces, and each having an opening that exposes a solder pad through the corresponding one of the first and second surfaces; and a plurality of passive components disposed on the first surface of the printed circuit board and connected to the plurality of solder pads exposed through the first surface. A first passive component of the plurality of passive components is disposed in a region overlapping with the first functional circuit of the semiconductor chip in the first direction, and a second passive component of the plurality of passive components is spaced apart from the first passive component and disposed in a region overlapping with the second functional circuit of the semiconductor chip in the first direction.

[0012] In another aspect of the present disclosure, a printed circuit board (PCB) includes a first surface and a second surface opposing each other in a first direction, and is configured with a semiconductor chip mounted on the second surface, the semiconductor chip having input / output interface functional circuitry. The PCB includes: a planar insulating layer; a first passivation layer and a second passivation layer, each disposed between the planar insulating layer and a respective one of the first and second surfaces, and each having an opening that exposes a solder pad through the respective one of the first and second surfaces; and a plurality of passive components disposed on the first surface of the PCB and connected to the plurality of solder pads exposed through the first surface. A first passive component of the plurality of passive components is disposed in a region that overlaps with the input / output interface functional circuitry of the semiconductor chip in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0015] Figure 2 is a schematic perspective view illustrating an example of an electronic device.

[0016] Figure 3 is a schematic cross-sectional view illustrating an example of a substrate structure.

[0017] Figure 4 It shows Figure 3 Schematic plan view of the underside of a printed circuit board of the substrate structure shown in FIG.

[0018] Figure 5 It shows Figure 3 Schematic cross-sectional view of a modified example of the substrate structure shown in .

[0019] Figure 6 It is shown that Figure 3 Schematic cross-sectional view of an example of an electronic device having a substrate structure shown in FIG.

[0020] Figure 7 It shows Figure 6 Schematic plan view of the underside of a printed circuit board of an electronic device shown in .

[0021] Figure 8 It shows Figure 6 Schematic plan view of the arrangement of functional circuits inside the substrate structure of the electronic device shown in .

[0022] Figure 9 It is a depiction Figure 7 The passive components on the underside of the first printed circuit board are shown in Figure 8 Schematic plan view showing overlapping functional circuits inside a semiconductor chip shown in FIG.

[0023] Figure 10 It shows Figure 6 A schematic cross-sectional view of a modified example of the electronic device shown in .

[0024] Figure 11 is a schematic cross-sectional view showing another example of the substrate structure.

[0025] Figure 12 It shows Figure 11 Schematic plan view of the underside of the first printed circuit board of the substrate structure shown in FIG.

[0026] Figure 13 It shows Figure 11 Schematic cross-sectional view of a modified example of the substrate structure shown in .

[0027] Figure 14 It shows Figure 11 Schematic cross-sectional view of a modified example of the substrate structure shown in .

[0028] Figure 15 It is shown that Figure 11 Schematic cross-sectional view of another example of an electronic device having a substrate structure shown in .

[0029] Figure 16 It shows Figure 15 Schematic plan view of the underside of the first printed circuit board of the substrate structure of the electronic device shown in FIG.

[0030] Figure 17 It shows Figure 15 Schematic plan view of the arrangement of functional circuits inside a semiconductor chip of an electronic device shown in .

[0031] Figure 18 It is a depiction Figure 16 The passive components on the underside of the first printed circuit board are shown in Figure 17 Schematic plan view showing overlapping functional circuits inside a semiconductor chip shown in FIG.

[0032] Figure 19 It shows Figure 15 A schematic cross-sectional view of a modified example of the electronic device shown in .

[0033] Figure 20 It shows Figure 15 A schematic cross-sectional view of a modified example of the electronic device shown in . DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0035] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0036] Reference Figure 1 , the electronic device 1000 may house a motherboard 1010 therein. The motherboard 1010 may include chip-related components 1020, network-related components 1030, and other components 1040, etc., which are physically or electrically connected to the motherboard 1010. These components may be connected to other components described below via various signal lines 1090.

[0037] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; logic chips, such as analog-to-digital converters, and application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0038] The network-related components 1030 may include components compatible with and implementing various protocols such as Wi-Fi (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto and may also include components compatible with and implementing various other wireless standards or protocols or wired standards or protocols. In addition, the network-related components 1030 may be combined with the chip-related components 1020 described above.

[0039] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto, but may also include passive components for various other purposes, etc. In addition, other components 1040 may be combined with the chip-related components 1020 and / or network-related components 1030 described above.

[0040] Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically or electrically connected to the mainboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, and the like. However, these other components are not limited thereto and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disc (CD) drive, a digital versatile disc (DVD) drive, and the like. These other components may also include other components for various purposes depending on the type of electronic device 1000, etc.

[0041] The electronic device 1000 may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.

[0042] Figure 2 is a schematic perspective view illustrating an example of an electronic device.

[0043] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components that may or may not be physically or electrically connected to the mainboard 1110 (such as a camera module 1130 and / or a speaker 1140) may be housed in the electronic device. A portion of the electronic components 1120 may be chip-related components, for example, a semiconductor package 1121, but is not limited thereto. The semiconductor package 1121 may have a form in which a semiconductor chip or a passive component is surface-mounted on a package substrate in the form of a multi-layer printed circuit board or a substrate structure including a package substrate. The electronic device is not necessarily limited to the smart phone 1100 and may be other electronic devices as described above.

[0044] Figure 3 is a schematic cross-sectional view illustrating an example of a substrate structure.

[0045] Figure 4 It shows Figure 3 Schematic plan view of the underside of a printed circuit board in the substrate structure.

[0046] Reference Figure 3 and Figure 4According to the example, the substrate structure 500A includes a printed circuit board 100 and a plurality of passive components 300, and the printed circuit board 100 has a first side 100a and a second side 100b opposite to each other. The substrate structure 500A according to the example can be used as a package substrate. The passive component 300 can be, for example, a land side capacitor (LSC) connected to one side 100a of the printed circuit board 100, so that the power supply integration can be improved. When such an LSC is used, the size of the printed circuit board 100 can be further reduced compared to a die side capacitor (DSC). In addition, since the LSC is closer to the semiconductor chip (for example, Figure 6 The distance 400) can be relatively short, so the LSC can have a better power integration effect.

[0047] The plurality of passive components 300 includes a first group PG1, a second group PG2, a third group PG3, and a fourth group PG4. The first group PG1 includes a plurality of first passive components 300a disposed adjacent to each other, the second group PG2 includes a plurality of second passive components 300b disposed adjacent to each other, the third group PG3 includes a plurality of third passive components 300c disposed adjacent to each other, and the fourth group PG4 includes a plurality of fourth passive components 300d disposed adjacent to each other. The number of groups in the first group PG1 to the fourth group PG4 can be adjusted. For example, the plurality of passive components 300 can include fewer groups than shown in the drawings, or can include more groups than shown in the drawings.

[0048] When the plurality of passive components 300 includes a plurality of passive components 300a, 300b, 300c, and 300d that may be grouped into a plurality of groups PG1, PG2, PG3, and PG4, the plurality of passive components 300a, 300b, 300c, and 300d may be selectively disposed on a plane (e.g., the same plane) to be aligned with semiconductor chips (e.g., Figure 6 In the embodiment of the present invention, the passive components 300a, 300b, 300c, and 300d are grouped into groups PG1, PG2, PG3, and PG4, and each of the groups PG1, PG2, PG3, and PG4 can be arranged directly below the main core unit or specific input / output unit of the semiconductor chip. For example, the passive components 300a, 300b, 300c, and 300d grouped into the same group PG1, PG2, PG3, or PG4 can be arranged directly below the same corresponding functional circuit of the semiconductor chip, while the passive components 300a, 300b, 300c, and 300d grouped into different groups PG1, PG2, PG3, and PG4 can be arranged directly below different corresponding functional circuits of the semiconductor chip. Therefore, a better improvement in power supply integration can be achieved.

[0049] Groups PG1, PG2, PG3, and PG4 may be determined based on the distances between adjacent passive components in each group and the distances between adjacent groups. In this regard, distances ga1 and ga2 may be defined as the distances between adjacent first passive components 300a of the first group PG1 (e.g., distances in the first and second directions, respectively), and distances gb1 and gb2 may be defined as the distances between adjacent second passive components 300b of the second group PG2 (e.g., distances in the first and second directions, respectively). Of the distances GA between the first and second groups PG1 and PG2, the minimum distance may be greater than at least one of the minimum distance between ga1 and ga2 and the minimum distance between gb1 and gb2. Of the distances GB between the first and third groups PG1 and PG3, the minimum distance may be greater than at least one of the minimum distance between ga1 and ga2 and the minimum distance between adjacent third passive components 300c of the third group PG3. Among the distances GC between the second group PG2 and the third group PG3, the minimum distance may be greater than at least one of the minimum distances gb1 and gb2 and the minimum distance gc between adjacent third passive components 300c of the third group PG3. Among the distances GD between the first group PG1 and the fourth group PG4, the minimum distance may be greater than at least one of the minimum distances ga1 and ga2 and the minimum distance gd between adjacent fourth passive components 300d of the fourth group PG4.

[0050] As described above, each passive component is grouped with its nearest passive component such that each passive component is positioned closer to another component from the same group than to any passive component from any other group.

[0051] To better group the components into groups PG1, PG2, PG3, and PG4, the plurality of first passive components 300a of the first group PG1 are arranged at equal intervals ga1 based on a first direction on a plane, and may also be arranged at equal intervals ga2 based on a second direction on the plane. Furthermore, the plurality of second passive components 300b of the second group PG2 may be arranged at equal intervals gb1 based on the first direction on the plane, and may also be arranged at equal intervals gb2 based on the second direction on the plane. The plurality of third passive components 300c of the third group PG3 may be arranged at equal intervals gc based on the second direction on the plane. The plurality of fourth passive components 300d of the fourth group PG4 may be arranged at equal intervals gd based on the first direction on the plane. "Equal intervals" include substantially equal intervals.

[0052] To better group the components into groups PG1, PG2, PG3, and PG4, at least two of the plurality of first passive components 300a, the plurality of second passive components 300b, the plurality of third passive components 300c, and the plurality of fourth passive components 300d included in the first group PG1, the second group PG2, the third group PG3, and the fourth group PG4 may be different from each other. For example, the number (or count) of the plurality of first passive components 300a of the first group PG1 may be greater than the number of the plurality of second passive components 300b of the second group PG2, the number of the plurality of third passive components 300c of the third group PG3, and the number of the plurality of fourth passive components 300d of the fourth group PG4. In addition, the number of the plurality of second passive components 300b of the second group PG2 may be greater than the number of the third passive components 300c of the third group PG3 and the number of the fourth passive components 300d of the fourth group PG4.

[0053] Each of the plurality of passive components 300 may be a chip passive component, such as a chip capacitor or a chip inductor. Examples of chip passive components introduced as each of the plurality of passive components 300 may be a multilayer ceramic capacitor (MLCC), a low inductance chip capacitor (LICC), or the like. Each of the plurality of passive components 300 may have two terminals. However, the number of terminals is not limited thereto, and each of the plurality of passive components 300 may have eight terminals.

[0054] The substrate structure 500A according to the example may further include a plurality of first connection metals 180 disposed on the first side 100a of the printed circuit board 100 to connect to the first side 100a. When viewed from above, the plurality of first connection metals 180 may surround the first group PG1, the second group PG2, the third group PG3, and the fourth group PG4. Each of the first connection metals 180 may be an alloy including a low-melting-point metal having a melting point lower than that of copper (Cu), such as tin (Sn) or a tin-containing alloy. For example, each of the first connection metals 180 may be formed using solder, but the present disclosure is not limited thereto. The first connection metals 180 may be ground pads, balls, pins, etc., and may have a multi-layer structure or a single-layer structure. When the first connection metals 180 have a multi-layer structure, the first connection metals 180 may include copper pillars and solder. When the first connection metals 180 have a single-layer structure, the first connection metals 180 may include tin-silver solder. However, this is merely an example, and the present disclosure is not limited thereto.

[0055] Figure 5 It shows Figure 3 Schematic cross-sectional view of a modified example of the substrate structure in .

[0056] Reference Figure 5The substrate structure 500A′ according to the modified example can be a coreless printed circuit board (coreless PCB). When the printed circuit board 100 is a coreless PCB, the first connection metal 180 does not need to have a fine pitch. Therefore, ordinary LSCs can be used for the plurality of passive components 300 instead of low-profile LSCs to reduce costs.

[0057] Most of the other contents are substantially the same as described above, and therefore, repeated explanations are omitted.

[0058] The printed circuit board 100 may include a buildup layer 110 and a plurality of wiring layers 112 embedded in the buildup layer 110. Vertically adjacent layers disposed above and below each of the plurality of wiring layers 112 may be connected to each other via a plurality of vias penetrating the buildup layer 110. A first passivation layer 140 may be disposed on the lower side of the buildup layer 110. A second passivation layer 150 may be disposed on the upper side of the buildup layer 110. The first passivation layer 140 may have a plurality of first openings that respectively expose a plurality of first pads 112P1. A first connection metal 180 may be disposed on each of the plurality of first openings to connect to a corresponding first pad 112P1. The second passivation layer 150 may have a plurality of second openings that respectively expose a plurality of second pads 112P2. A second connection metal 190 may be disposed on each of the second openings to connect to a corresponding second pad 112P2. A plurality of passive components 300 may be disposed on openings of the plurality of first openings (e.g., on openings without the first connection metal 180). Each of the plurality of passive components 300 may be connected to the corresponding first pad 112P1 through the conductive adhesive 350. The printed circuit board 100 does not need to be a coreless type printed circuit board and may be a core type printed circuit board.

[0059] The buildup layer 110 may provide an insulating region for forming a multilayer wiring. The buildup layer 110 may include multiple insulating layers, and the boundaries between the multiple insulating layers may be distinct or indistinct. The material of the insulating layer may be an insulating material. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including a thermosetting resin and a thermoplastic resin, glass fiber and / or a reinforcing material (such as an inorganic filler), for example, polypropylene glycol (PPG), ABF, etc. Alternatively, the material of the insulating layer may be PID. On the other hand, the insulating layers may include the same material, or may include materials different from each other.

[0060] Wiring layer 112 may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Wiring layer 112 may be formed using processes such as additive plating (AP), semi-AP (SAP), modified SAP (MSAP), and hole sealing (TT). As a result, wiring layer 112 may include a seed layer serving as an electroless plating layer, and an electroplated layer formed based on the seed layer. Wiring layer 112 may perform various functions depending on its design. For example, wiring layer 112 may include a ground pattern, a power pattern, a signal pattern, and the like. Signal patterns may include various signal patterns in addition to ground patterns and power patterns, such as data signal patterns. Each pattern may include a line pattern, a plane pattern, and / or a pad pattern. Vias, including connection vias connected to wiring layer 112, may also include a metal material. Vias may also be formed using plating processes such as AP, SAP, MSAP, and TT processes. Vias may also perform various functions depending on their design. For example, the vias may include wiring vias for signal connections, wiring vias for ground connections, wiring vias for power connections, etc. The vias may be completely filled with a metal material, or the metal material may be formed along the walls of the vias. In addition, various shapes (such as a tapered shape, etc.) may be applied to the vias.

[0061] Passivation layers 140 and 150 are additional components that protect the internal structure of printed circuit board 100 from external physical and chemical damage. Each of passivation layers 140 and 150 may include a thermosetting resin. For example, each of passivation layers 140 and 150 may be ABF. However, the present disclosure is not limited thereto, and each of passivation layers 140 and 150 may be an SR layer. Alternatively, each of passivation layers 140 and 150 may include a PID. Each of passivation layers 140 and 150 may have multiple openings. A surface finish layer may be formed on the surfaces of pads 112P1 and 112P2 exposed by the multiple openings. The surface finish layer may be formed by, for example, electroplating gold, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / displacement gold plating, DIG plating, HASL plating, etc. Optionally, each of the openings may have multiple vias. Optionally, an under-bump metallurgy (UBM) may be provided on each of the openings to improve reliability.

[0062] The connection metals 180 and 190 are additional elements that can physically connect and / or electrically connect the printed circuit board 100 to an external entity. For example, the printed circuit board 100 can be mounted on another printed circuit board via the first connection metal 180. In addition, a semiconductor chip or the like can be surface-mounted on the printed circuit board 100 via the second connection metal 190. Each of the connection metals 180 and 190 can be provided on each of the plurality of openings of the passivation layers 140 and 150, except for the opening having the passive component 300 thereon. Each of the connection metals 180 and 190 can include a low-melting-point metal having a melting point lower than copper (Cu), such as tin (Sn) or a tin-containing alloy. For example, each of the connection metals 180 and 190 can be formed using solder. However, this is merely an example, and the materials of the connection metals 180 and 190 are not limited thereto.

[0063] Each of the connection metals 180 and 190 can be a ground pad, a ball, a pin, etc. Each of the connection metals 180 and 190 can have a multi-layer structure or a single-layer structure. When having a multi-layer structure, each of the connection metals 180 and 190 can include a copper pillar and solder. When having a single-layer structure, each of the connection metals 180 and 190 can include tin-silver solder. However, this is merely an example, and the present disclosure is not limited thereto. The number, spacing, arrangement, etc. of the connection metals 180 and 190 are not necessarily limited and can be fully modified according to design details.

[0064] The passive components 300 can be connected to the printed circuit board 100. Each of the multiple passive components 300 can be a chip passive component, for example, a chip capacitor or a chip inductor. Examples of chip passive components introduced as each of the multiple passive components 300 can be multilayer ceramic capacitors (MLCCs), low inductance chip capacitors (LICCs), etc. Each of the multiple passive components 300 can have two terminals. However, the number of terminals is not limited to this, and each of the multiple passive components 300 can have eight terminals, etc. The conductive adhesive 350 for surface mounting of the passive components 300 may include a low melting point metal having a lower melting point than copper (Cu), for example, tin (Sn) or a tin-containing alloy, in more detail, solder. However, the present disclosure is not limited to this.

[0065] Figure 6 It is shown that Figure 3 Schematic cross-sectional view of an example of an electronic device having a substrate structure shown in FIG.

[0066] Reference Figure 6According to an example, an electronic device 800A includes a main board 600, a printed circuit board 100 disposed on the main board 600, a semiconductor chip 400 disposed on the upper side of the printed circuit board 100, and a plurality of passive components 300 disposed on the lower side of the printed circuit board 100. The printed circuit board 100 may be connected to the main board 600 via a plurality of first connection metals 180. The semiconductor chip 400 may be connected to the printed circuit board 100 via a plurality of second connection metals 190. An underfill resin 170 may be disposed between the printed circuit board 100 and the semiconductor chip 400 to cover at least a portion of the plurality of second connection metals 190. In the following description, most of the same content as above will be omitted to avoid repeated description.

[0067] The motherboard 600 provides physical and / or electrical connection paths and positions various electronic components in the electronic device 800A. The motherboard 600 can be any of various types of printed circuit boards. The motherboard 600 can be a multi-layer printed circuit board (multi-layer PCB). The motherboard 600 can be a rigid PCB or a rigid-flexible PCB. Various types of electronic components can be embedded in the motherboard 600. In addition to the above-mentioned substrate structure, various electronic components can be arranged on the motherboard 600.

[0068] The semiconductor chip 400 may be an integrated circuit (IC) that provides hundreds to millions of components or more integrated into a single chip. The integrated circuit constituting the semiconductor chip 400 may be, for example, an application processor chip, but is not limited thereto. The semiconductor chip 400 may be an integrated circuit in a bare state in which no additional bumps or wiring layers are formed. However, the semiconductor chip 400 is not limited thereto and, where appropriate, may be a packaged integrated circuit. The integrated circuit may be formed based on an active wafer. In this case, the base material of the main body of the semiconductor chip 400 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various circuits may be formed on the main body. The semiconductor chip 400 may be connected to other components via connection pads, the material of which may be any metal material such as copper (Cu), aluminum (Al), etc. A passivation layer (not shown) may be formed on the main body to expose the connection pads and may be an oxide layer, a nitride layer, etc., or a double layer of an oxide layer and a nitride layer. An insulating layer, etc. may be further provided at other locations. In the semiconductor chip 400, the surface on which the connection pads are provided may be an active surface, and the rear surface opposite to the active surface may be an inactive surface. However, depending on circumstances, connection pads may also be provided on the rear surface so that both surfaces can be effective surfaces.

[0069] Figure 7 It shows Figure 6 Schematic plan view of the underside of a printed circuit board 100 of an electronic device shown in FIG.

[0070] Reference Figure 7 The plurality of passive components 300 includes a first group PG1, a second group PG2, a third group PG3, and a fourth group PG4. The first group PG1 includes a plurality of first passive components 300a adjacent to each other, the second group PG2 includes a plurality of second passive components 300b adjacent to each other, the third group PG3 includes a plurality of third passive components 300c adjacent to each other, and the fourth group PG4 includes a plurality of fourth passive components 300d adjacent to each other. The number of groups in the first group PG1 to the fourth group PG4 can be adjusted. For example, the plurality of passive components 300 may include fewer groups than shown in the drawings, or may include more groups than shown in the drawings. Most of the details are the same as described above, and a detailed description thereof will be omitted.

[0071] Figure 8 It shows Figure 6 Schematic plan view of the arrangement of functional circuits (e.g., functional circuit units) within the substrate structure of an electronic device.

[0072] Reference Figure 8 , the semiconductor chip 400 includes a plurality of functional circuits (e.g., functional circuit units) C1, C2, C3, I1, I2, I3, I4, and I5. For example, the semiconductor chip 400 may include one or more core functional circuit units C1, C2, and C3 and one or more input / output functional circuit units (interface units) I1, I2, I3, I4, and I5. However, the present disclosure is not limited thereto, and the semiconductor chip 400 may further include an interface unit, a memory unit, and the like. The core functional circuits C1, C2, and C3 may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor unit (DSPU), an image signal processing unit (ISPU), and a neural network processing unit (NPU). The semiconductor chip 400 including such internal units may be, for example, an application processor chip, but is not limited thereto. Most of the other contents are substantially the same as described above, and therefore, repeated descriptions are omitted.

[0073] Figure 9 is provided so that Figure 7 The underside of the first printed circuit board shown in FIG. Figure 8 is a schematic plan view showing functional circuits inside a semiconductor chip arranged to overlap with each other.

[0074] Reference Figure 9When viewed from above, at least a portion of the plurality of passive components 300a, 300b, 300c, and 300d, grouped into groups PG1, PG2, PG3, and PG4, of the plurality of passive components 300 may be disposed so as to overlap at least one of the plurality of functional circuit units C1, C2, C3, I1, I2, I3, I4, and I5 of the semiconductor chip 400. For example, the first group PG1 may be disposed directly below the first core functional circuit unit C1 (e.g., all passive components of the first group PG1 may be disposed directly below the first core functional circuit unit C1, and / or components of any group other than the first group PG1 may not be disposed directly below the first core functional circuit unit C1). The second group PG2 may be disposed directly below the second core functional circuit unit C2 (e.g., all passive components of the second group PG2 may be disposed directly below the second core functional circuit unit C2, and / or components of any group other than the second group PG2 may not be disposed directly below the second core functional circuit unit C2). The third group PG3 may be disposed directly below the third core functional circuit unit C3 (e.g., all passive components of the third group PG3 may be disposed directly below the third core functional circuit unit C3, and / or components of any group other than the third group PG3 may not be disposed directly below the third core functional circuit unit C3). As described above, when the plurality of passive components 300a, 300b, and 300c grouped into groups PG1, PG2, and PG3 are disposed directly below the core functional circuit units C1, C2, and C3, respectively, a better power supply integration improvement effect may be achieved. In addition, the fourth group PG4 may be disposed directly below the input / output functional circuit unit I2 having a relatively larger planar area than each of the other input / output functional circuit units I1, I3, I4, and I5 (e.g., all passive components of the fourth group PG4 may be disposed directly below the input / output functional circuit unit I2, and / or components of any group other than the fourth group PG4 may not be disposed directly below the input / output functional circuit unit I2). Most of the other contents are substantially the same as described above, and therefore, repeated descriptions are omitted.

[0075] In one example, a first group PG1 may be disposed directly below a first core functional circuit unit C1, and the passive components of the first group PG1 may be electrically connected to the circuitry of the first core functional circuit C1 (e.g., via one or more pads disposed directly below the first core functional circuit C1). A second group PG2 may be disposed directly below a second core functional circuit C2, and the passive components of the second group PG2 may be electrically connected to the circuitry of the second core functional circuit C2 (e.g., via one or more pads disposed directly below the second core functional circuit C2). A third group PG3 may be disposed directly below a third core functional circuit C3, and the passive components of the third group PG3 may be electrically connected to the circuitry of the third core functional circuit C3 (e.g., via one or more pads disposed directly below the third core functional circuit C3). As described above, when the plurality of passive components 300a, 300b, and 300c grouped into groups PG1, PG2, and PG3 are disposed directly below the core functional circuits C1, C2, and C3 to which they are electrically connected, a better improvement in power supply integration may be achieved. In addition, the fourth group PG4 may be disposed directly below an input / output functional circuit I2 having a relatively larger area than each of the other input / output functional circuits I1, I3, I4, and I5, and the passive components of the fourth group PG4 may be electrically connected to the circuit of the input / output functional circuit I2 (for example, via one or more pads disposed directly below the input / output functional circuit I2).

[0076] Figure 10 It shows Figure 6 A schematic cross-sectional view of a modified example of the electronic device shown in .

[0077] Reference Figure 10 The electronic device 800A' according to the modified example includes the substrate structure 500A' according to the modified example. For example, the printed circuit board 100 may be a core-type printed circuit board including multiple core layers. Most of the other contents are substantially the same as described above, and therefore, repeated descriptions are omitted.

[0078] Figure 11 is a schematic cross-sectional view showing another example of the substrate structure.

[0079] Figure 12 It shows Figure 11 Schematic plan view of the underside of the first printed circuit board of the substrate structure.

[0080] Reference Figure 11 and Figure 12According to another example, a substrate structure 500B includes a second printed circuit board 200 having a third side 200a and a fourth side 200b opposite to each other, a first printed circuit board 100 disposed on the fourth side 200b of the second printed circuit board 200 and having a first side 100a and a second side 100b opposite to each other, and a plurality of passive components 300 disposed between the fourth side 200b of the second printed circuit board 200 and the first side 100a of the first printed circuit board 100 and connected to the first side 100a of the first printed circuit board 100. The substrate structure 500B according to another example may have a substrate-on-substrate structure and may be used as a package substrate. Hereinafter, descriptions of structures similar to those described above will be omitted to reduce repetition.

[0081] As described above, another example substrate structure 500B has a structure in which a first printed circuit board 100 and a second printed circuit board 200 are stacked, meeting the demand for high-layer and large-scale substrates. Therefore, compared to manufacturing high-layer and large-scale substrates using only a single printed circuit board, the technical difficulty can be reduced and the yield rate can be improved. As a result, costs can be reduced. Furthermore, the wiring designs of the first printed circuit board 100 and the second printed circuit board 200 are different from each other, thereby achieving an optimized wiring design. As a result, better performance can be achieved.

[0082] In addition, a substrate structure 500B according to another example includes a plurality of passive components 300 disposed between a first printed circuit board 100 and a second printed circuit board 200. These passive components 300 may be, for example, LSCs connected to one side 100a of the first printed circuit board 100, thereby improving integration. Using such LSCs can further reduce the size of the first printed circuit board 100 compared to DSCs. Furthermore, since the distance between the LSCs and the semiconductor chips disposed on the first printed circuit board 100 is shorter than that between the DSCs and the semiconductor chips disposed on the first printed circuit board 100, a greater improvement in power supply integration can be achieved.

[0083] The plurality of passive components 300 includes a first group PG1, a second group PG2, a third group PG3, and a fourth group PG4. The first group PG1 includes a plurality of first passive components 300a disposed adjacent to each other, the second group PG2 includes a plurality of second passive components 300b disposed adjacent to each other, the third group PG3 includes a plurality of third passive components 300c disposed adjacent to each other, and the fourth group PG4 includes a plurality of fourth passive components 300d disposed adjacent to each other. The number of groups in the first group PG1 to the fourth group PG4 can be adjusted as appropriate. For example, the plurality of passive components 300 can include fewer groups than shown in the drawings, or can include more groups than shown in the drawings.

[0084] As will be described below, when the plurality of passive components 300 includes a plurality of passive components 300a, 300b, 300c, and 300d that can be grouped into a plurality of groups PG1, PG2, PG3, and PG4, the plurality of passive components 300a, 300b, 300c, and 300d can be selectively arranged on a plane to overlap with a plurality of functional circuit units within the semiconductor chip 400 disposed on the printed circuit board 100 (e.g., overlap with corresponding units among the plurality of units). For example, each of the passive components 300a, 300b, 300c, and 300d grouped into the groups PG1, PG2, PG3, and PG4 can be arranged directly below a main core unit or a specific input / output unit of the semiconductor chip. Thus, a better power supply integration improvement effect can be achieved.

[0085] The second printed circuit board 200 may be larger in size than the first printed circuit board 100. For example, the second printed circuit board 200 may be thicker than the first printed circuit board 100. In addition, the second printed circuit board 200 may have a larger planar area than the first printed circuit board 100. In a non-limiting example, the second printed circuit board 200 may be a high-density interconnect (HDI) interposer substrate, and the first printed circuit board 100 may be a flip-chip ball grid array (FCBGA) substrate. The wiring layers in the first printed circuit board 100 may be primarily used to transmit signals, and the wiring layers in the second printed circuit board 200 may primarily provide power and ground.

[0086] According to another example, the substrate structure 500B may further include a plurality of first connection metals 180 disposed between the fourth side 200b of the second printed circuit board 200 and the first side 100a of the first printed circuit board 100 to connect the fourth side 200b of the second printed circuit board 200 to the first side 100a of the first printed circuit board 100. The plurality of first connection metals 180 may surround the first group PG1, the second group PG2, the third group PG3, and the fourth group PG4. In addition, the substrate structure 500B may further include second connection metals (e.g., 190) disposed on the second side 100b of the first printed circuit board 100 to connect thereto. As will be described later, a semiconductor chip or the like may be disposed on the second side 100b of the first printed circuit board 100 in a surface-mounted manner via the plurality of second connection metals 190. When viewed from above, at least a portion of the plurality of second connection metals 190 may be disposed so as to overlap at least a portion of the plurality of passive components 300.

[0087] According to another example, the substrate structure 500B may further include a plurality of third connection metals 290 disposed on the third side of the second printed circuit board 200 (see, for example, FIG. Figure 13). As described later, the substrate structure 500B can be set on a mainboard, etc. to be connected to the mainboard, etc. Each of the third connection metals 290 may also include a low melting point metal having a melting point lower than copper (Cu), for example, tin (Sn) or a tin-containing alloy. For example, each of the third connection metals 290 can be formed using solder, but the present disclosure is not limited thereto. Each of the third connection metals 290 can also be a ground pad, a ball, a pin, etc., and may have a multi-layer structure or a single-layer structure. When having a multi-layer structure, each of the third connection metals 290 may include a copper column and a solder. When having a single-layer structure, each of the third connection metals 290 may include a tin-silver solder, but this is merely an example, and the present disclosure is not limited thereto.

[0088] Alternatively, the substrate structure 500B according to another example may further include an underfill resin 160 disposed between the first side 100a of the first printed circuit board 100 and the fourth side 200b of the second printed circuit board 200 and covering at least a portion of the plurality of first connection metals 180 (see, for example, FIG. Figure 15 ). The material of the underfill resin 160 may be an insulating adhesive such as epoxy resin, but is not limited thereto. Other materials that are used as underfill may be used as the material of the underfill resin 160.

[0089] Figure 13 It shows Figure 11 Schematic cross-sectional view of a modified example of the substrate structure in .

[0090] Reference Figure 13 In the substrate structure 500B' according to the variant example, the first printed circuit board 100 can be a coreless printed circuit board. In addition, the second printed circuit board 200 can also be a core-type printed circuit board. When the first printed circuit board 100 is a coreless printed circuit board, the first connection metal 280 does not need to have a fine pitch. Therefore, since a general LSC rather than an LSC with a low profile can be used as each of the multiple passive components 300, costs can be reduced. When the second printed circuit board 200 is a core-type printed circuit board, it can be more advantageous in controlling the warpage of the substrate structure 500B'. In addition, providing multiple passive components 300 can be more advantageous. In addition, it can be more advantageous in achieving high-density interconnection (HDI). In the following, most of the other contents are roughly the same as the above description, and therefore, repeated descriptions are omitted.

[0091] The printed circuit board 200 may include a core layer 210, a first buildup layer 220 disposed on the lower side of the core layer 210, a second buildup layer 230 disposed on the upper side of the core layer 210, a plurality of first wiring layers 222 embedded in the first buildup layer 220, a plurality of second wiring layers 232 embedded in the second buildup layer 230, and a plurality of through-vias 215 penetrating the core layer 210 and electrically connecting the plurality of first wiring layers 222 and the plurality of second wiring layers 232. A plurality of passive components 300 may be disposed on the lower surface of the first printed circuit board 100, between the first printed circuit board 100 and the second printed circuit board 200. The plurality of passive components 300 may be electrically connected to the plurality of second wiring layers 232 via connection vias penetrating a portion of the core layer of the first printed circuit board 100, a first connection metal 280 connecting the first printed circuit board 100 and the second printed circuit board 200, and connection pads 232P. Vertically adjacent layers disposed above and below each of the plurality of first wiring layers 222 and the plurality of second wiring layers 232 may be connected to each other via a plurality of vias penetrating the first buildup layer 220 and the second buildup layer 230. A third passivation layer 240 may be disposed on the first buildup layer 220. A fourth passivation layer 250 may be disposed on the second buildup layer 230. The third passivation layer 240 may have a plurality of third openings that respectively expose the plurality of third pads 222P. A third connection metal 290 may be disposed on each of the third openings to connect to the corresponding first pad 222P. The fourth passivation layer 250 may have a plurality of fourth openings that respectively expose the plurality of fourth pads 232P. A first connection metal 280 may be disposed on each of the fourth openings to connect to the corresponding fourth pad 232P. Where appropriate, the second printed circuit board 200 need not be a core-type printed circuit board and may be a coreless printed circuit board.

[0092] The core layer 210 may be a core substrate serving as the center of the second printed circuit board 200. The material of the core layer 210 may be an insulating material. The insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material including a thermosetting resin and a thermoplastic resin, glass fiber (or glass cloth or glass fabric) and / or a reinforcing material (such as an inorganic filler), for example, a copper clad laminate (CCL), an unclad CCL, etc. However, the materials of the first insulating layer 111a and the second insulating layer 111b are not limited thereto and may be a metal plate or a glass plate, or may be a ceramic plate. Alternatively, the material of the core layer 210 may be a liquid crystal polymer (LCP). For purposes such as warpage control, the core layer 210 may have a greater thickness than each of the insulating layers that respectively constitute the buildup layers 220 and 230. In addition, for purposes such as warpage control, the core layer 210 may have greater rigidity than each of the insulating layers that respectively constitute the buildup layers 220 and 230. For example, the core layer 210 may have a greater elastic modulus than each of the insulating layers.

[0093] The buildup layers 220 and 230 may provide an insulating region for forming multilayer wiring on opposite sides adjacent to the core layer 210. Each of the buildup layers 220 and 230 may include multiple insulating layers, and the boundaries between the multiple insulating layers may be distinct or indistinct. The material of the insulating layer may be an insulating material. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including a thermosetting resin and a thermoplastic resin, glass fiber and / or a reinforcing material (such as an inorganic filler), for example, a prepreg, Ajinomoto Build-up Film (ABF), etc. Alternatively, the material of the insulating layer may be a photosensitive dielectric (PID). On the other hand, the buildup layers 220 and 230 may include the same material, or may include materials different from each other.

[0094] Wiring layers 222 and 232 may include metal materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of wiring layers 222 and 232 may be formed using processes such as additive process (AP), semi-AP (SAP), modified SAP (MSAP), and hole sealing (TT) processes. As a result, each of wiring layers 222 and 232 may include a seed layer serving as an electroless plating layer and an electroplated layer formed based on the seed layer. Wiring layers 222 and 232 may perform various functions depending on their design. For example, each of wiring layers 222 and 232 may include a ground pattern, a power pattern, a signal pattern, and the like. The signal pattern may include various signal patterns in addition to the ground pattern, power pattern, and the like, such as a data signal pattern. Each pattern may include a line pattern, a plane pattern, and / or a pad pattern. The vias, including the connection vias connected to wiring layers 222 and 232, may also include metal materials. Vias can also be formed using plating processes such as AP, SAP, MSAP, and TT processes. Vias can also perform various functions depending on their design. For example, vias can include routing vias for signal connections, routing vias for ground connections, routing vias for power connections, and the like. Vias can be completely filled with metal material, or metal material can be formed along the walls of the via hole. In addition, various shapes (such as tapered shapes) can be applied to vias.

[0095] The through hole 215 can penetrate the core layer 210 and can connect the wiring layers 222 and 232 respectively arranged on the lower side and the upper side of the core layer 210 to each other. The through hole 215 may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The through hole 215 can also be formed by AP, SAP, MSAP, TT process, etc. As a result, the through hole 215 may include a seed layer used as an electroless plating layer and an electroplating layer formed based on the seed layer. The through hole 215 may include a via for signal connection, a via for ground connection, a via for power connection, etc. The through hole 215 may have various shapes such as a cylindrical shape, an hourglass shape, etc. Optionally, the through hole 215 can be filled with an insulating material.

[0096] Passivation layers 240 and 250 are additional components that protect the internal structure of printed circuit board 200 from external physical and chemical damage. Each of passivation layers 240 and 250 may include a thermosetting resin. For example, each of passivation layers 240 and 250 may be ABF. However, the present disclosure is not limited thereto, and each of passivation layers 240 and 250 may be a solder resist (SR) layer. Alternatively, each of passivation layers 240 and 250 may include a PID. Each of passivation layers 240 and 250 may have multiple openings. A surface treatment layer may be formed on the surfaces of pads 222P and 232P exposed by the multiple openings. The surface treatment layer may be formed by, for example, electroplating gold, electroless gold plating, organic solderability preservative (OSP), or electroless tin plating, electroless silver plating, electroless nickel plating / displacement gold plating, direct immersion gold (DIG) plating, hot air leveling (HASL), etc. Alternatively, the openings may be multiple vias. Optionally, under bump metallurgy (UBM) may be provided on each of the openings to improve reliability.

[0097] The third connection metal 290 is an additional element that can physically and / or electrically connect the printed circuit board 200 to an external entity. For example, the printed circuit board 200 can be mounted on another main board, etc. via the third connection metal 290. Each of the third connection metals 290 can be respectively disposed on a corresponding opening among the plurality of openings in the passivation layers 240 and 250. The third connection metal 290 may include a low-melting-point metal having a lower melting point than copper (Cu), such as tin (Sn) or a tin-containing alloy. For example, the third connection metal 290 can be formed using solder. However, this is merely an example and the material of the third connection metal 290 is not limited thereto.

[0098] The third connection metal 290 can be a ground pad, a ball, a pin, etc. The third connection metal 290 can have a multi-layer structure or a single-layer structure. When having a multi-layer structure, the third connection metal 290 can include a copper column and solder. When having a single-layer structure, the third connection metal 290 can include tin-silver solder. However, this is merely an example, and the present disclosure is not limited thereto. The number, spacing, arrangement, etc. of the connection metals 280 and 290 are not necessarily limited and can be fully modified according to design details.

[0099] Figure 14 It shows Figure 11 Schematic cross-sectional view of a modified example of the substrate structure in .

[0100] Reference Figure 14 The substrate structure 500B″ according to the modified example includes a passive component 300, which is also connected to the second printed circuit board 200 in the above-mentioned substrate structure 500B′. For example, the passive component 300 can be connected to the first pad 112P1 on the lower side of the first printed circuit board 100 via the first conductive adhesive 350a, and can also be connected to the fourth pad 232P on the upper side of the second printed circuit board 200 via the second conductive adhesive 350b. Therefore, the power transmission path can be further reduced, and the power supply integration can be more effectively improved. Most of the other contents are substantially the same as the above description, and therefore, repeated description is omitted.

[0101] Figure 15 It is shown that Figure 11 Schematic cross-sectional view of another example of an electronic device having a substrate structure in FIG.

[0102] Reference Figure 15According to another example, an electronic device 800B includes a mainboard 600, a first printed circuit board 100 disposed on the mainboard 600, a second printed circuit board 200 disposed between the mainboard 600 and the first printed circuit board 100, a plurality of passive components 300 disposed between the first printed circuit board 100 and the second printed circuit board 200, and a semiconductor chip 400 disposed on the first printed circuit board 100. The first printed circuit board 100 and the second printed circuit board 200 may be connected via a plurality of first connection metals 180. The semiconductor chip 400 may be surface-mounted on the first printed circuit board 100 via a plurality of second connection metals 190. The first printed circuit board 100 may be connected to the second printed circuit board 200 via the plurality of first connection metals 180. The second printed circuit board 200 may be connected to the mainboard 600 via a plurality of third connection metals 290. A first underfill resin 160 may be disposed between the first printed circuit board 100 and the second printed circuit board 200 to cover at least a portion of each of the plurality of first connection metals 180 and the plurality of passive components 300. An underfill resin 170 may be provided between the first printed circuit board 100 and the semiconductor chip 400 to cover at least a portion of the plurality of second connection metals 190. Most of the other contents are substantially the same as described above, and thus, repeated descriptions are omitted.

[0103] Figure 16 It shows Figure 15 Schematic plan view of the underside of the first printed circuit board of the substrate structure of the electronic device shown in FIG.

[0104] Reference Figure 16 The plurality of passive components 300 includes a first group PG1, a second group PG2, a third group PG3, and a fourth group PG4. The first group PG1 includes a plurality of first passive components 300a disposed adjacent to each other, the second group PG2 includes a plurality of second passive components 300b disposed adjacent to each other, the third group PG3 includes a plurality of third passive components 300c disposed adjacent to each other, and the fourth group PG4 includes a plurality of fourth passive components 300d disposed adjacent to each other. The number of groups in the first group PG1 to the fourth group PG4 can be adjusted appropriately. For example, the plurality of passive components 300 may include fewer groups than shown in the drawings, or may include more groups than shown in the drawings. Most of the details are the same as described above, and a detailed description thereof will be omitted.

[0105] Figure 17 It shows Figure 15 Schematic plan view of the arrangement of functional circuits inside a semiconductor chip of an electronic device shown in .

[0106] Reference Figure 17, the semiconductor chip 400 includes a plurality of functional circuits C1, C2, C3, I1, I2, I3, I4 and I5. For example, the semiconductor chip 400 may include one or more core functional circuit units C1, C2 and C3 and one or more input / output functional circuit units (interface units) I1, I2, I3, I4 and I5. However, the present disclosure is not limited to this, and the semiconductor chip 400 may also include an interface unit, a memory unit, etc. The core functional circuit units C1, C2 and C3 may include at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor unit (DSPU), an image signal processing unit (ISPU) and a neural network processing unit (NPU). The semiconductor chip 400 including such internal functional circuit units may be, for example, an application processor chip, but is not limited thereto. Most of the other contents are substantially the same as described above, and therefore, repeated descriptions are omitted.

[0107] Figure 18 is provided so that Figure 16 The underside of the first printed circuit board shown in FIG. Figure 17 is a schematic plan view showing functional circuits inside a semiconductor chip arranged to overlap with each other.

[0108] Reference Figure 18When viewed from above, at least a portion of the plurality of passive components 300a, 300b, 300c, and 300d, grouped into groups PG1, PG2, PG3, and PG4, of the plurality of passive components 300 may be disposed so as to overlap at least one of the plurality of functional circuit units C1, C2, C3, I1, I2, I3, I4, and I5 of the semiconductor chip 400. For example, the first group PG1 may be disposed directly below the first core functional circuit unit C1 (e.g., such that all first passive components 300a of the first group PG1 are disposed directly below the first core functional circuit unit C1). The second group PG2 may be disposed directly below the second core functional circuit unit C2 (e.g., such that all second passive components 300b of the second group PG2 are disposed directly below the second core functional circuit unit C2). The third group PG3 may be disposed directly below the third core functional circuit unit C3 (e.g., such that all third passive components 300c of the third group PG3 are disposed directly below the third core functional circuit unit C3). As described above, when the plurality of passive components 300a, 300b, and 300c grouped into groups PG1, PG2, and PG3 are arranged directly below the core functional circuit units C1, C2, and C3, a better power supply integration improvement effect can be achieved. Alternatively, the fourth group PG4 can be arranged directly below the input / output unit I2 having a relatively larger planar area than each of the other input / output units I1, I3, I4, and I5 (for example, such that all fourth passive components 300d of the fourth group PG4 are arranged directly below the input / output functional circuit I2). Most of the other contents are substantially the same as described above, and therefore, repeated descriptions are omitted.

[0109] Figure 19 It shows Figure 15 Schematic cross-sectional view of a modified example of the electronic device in .

[0110] Reference Figure 19 An electronic device 800B' according to a modified example includes the substrate structure 500B' described above according to the modified example. For example, the first printed circuit board 100 may be a coreless printed circuit board. Furthermore, the second printed circuit board 200 may be a core-type printed circuit board. The remainder of the description is largely the same as described above, and therefore, repeated descriptions are omitted.

[0111] Figure 20 It shows Figure 15 Schematic cross-sectional view of a modified example of the electronic device in .

[0112] Reference Figure 20, an electronic device 800B according to a modified example includes the above-described substrate structure 500B according to the above-described modified example. For example, the passive component 300 may be connected to the first pad 111P1 on the lower side of the first printed circuit board 100 via a first conductive adhesive 350a, and may also be connected to the fourth pad 232P on the upper side of the second printed circuit board 200 via a second conductive adhesive 350b. Most of the other contents are substantially the same as the above description, and therefore, repeated descriptions are omitted.

[0113] As described above, it is possible to provide a substrate structure that can compete with high-layer and large-scale substrates, and an electronic device including the substrate structure.

[0114] In addition, a substrate structure capable of reducing costs and an electronic device including the substrate structure can be provided.

[0115] In addition, a substrate structure capable of improving power supply integration and an electronic device including the substrate structure can be provided.

[0116] In the present disclosure, terms such as “lower side,” “lower portion,” and “lower surface” are used to indicate a direction toward a mounting surface of an electronic component package relative to a cross section of a drawing, and terms such as “upper side,” “upper portion,” and “upper surface” are used to indicate a direction opposite to the direction indicated by the terms such as “lower side,” “lower portion,” and “lower surface.” However, as described above, these directions are defined merely for convenience of explanation, and the claims are not particularly limited by the defined directions.

[0117] In the specification, the meaning of "connection" of a component to another component includes indirect connection through an adhesive layer and direct connection between two components. In addition, "electrical connection" includes physical connection or physical disconnection. It is understood that when an element is referred to as "first" and "second", the element is not limited thereto. These terms may only be used to distinguish an element from other elements and may not limit the order or importance of the elements. In some cases, without departing from the scope of the claims set forth herein, a first element may be referred to as a second element. Similarly, a second element may also be referred to as a first element.

[0118] The term "exemplary embodiment" as used herein does not always refer to the same exemplary embodiment and is provided to emphasize a specific feature or characteristic that is different from a specific feature or characteristic of another exemplary embodiment. However, the features of the exemplary embodiments provided herein can generally be implemented in combination with each other in whole or in part within the same embodiment. For example, unless a contrary or contradictory description is provided therein, an element described in a particular exemplary embodiment (even if it is not described in another exemplary embodiment) can be understood as a description related to another exemplary embodiment.

[0119] The terms used herein are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, unless otherwise explained based on a specific context, a singular form includes a plural form.

[0120] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A substrate structure comprising: a first printed circuit board having a first side and a second side opposite to each other in a first direction; a semiconductor chip disposed on the second side of the first printed circuit board; as well as a plurality of passive components connected to the first side of the first printed circuit board, wherein the plurality of passive components include a first group, a second group, and a third group, the first group includes a plurality of first passive components disposed adjacent to each other, the second group includes a plurality of second passive components disposed adjacent to each other, and the third group includes a plurality of third passive components disposed adjacent to each other, a minimum distance between the first group and the second group is greater than any one of a minimum distance between adjacent first passive components in the plurality of first passive components and a minimum distance between adjacent second passive components in the plurality of second passive components, and a minimum distance between adjacent first passive components in the plurality of first passive components is less than a minimum distance between the first group and the third group, The semiconductor chip includes a first functional circuit, a second functional circuit and a third functional circuit. At least a portion of the first group, at least a portion of the second group, and at least a portion of the third group overlap with the first functional circuit, the second functional circuit, and the third functional circuit, respectively, in the first direction. Each of the first functional circuit and the second functional circuit includes at least one of a central processing unit, a graphics processing unit, a digital signal processor unit, an image signal processing unit, and a neural network processing unit, and the third functional circuit includes an input / output unit.

2. The substrate structure according to claim 1, wherein: When viewed from above, the plurality of first passive components are arranged at equal intervals from one another based on a second direction perpendicular to the first direction, and when viewed from above, the plurality of second passive components are arranged at equal intervals from one another based on the second direction.

3. The substrate structure according to claim 1, wherein: The number of the first passive components included in the first group is different from the number of the second passive components included in the second group.

4. The substrate structure according to claim 1, wherein: The plurality of passive components includes a pad-side capacitor.

5. The substrate structure according to claim 1, further comprising: a second printed circuit board having a third side and a fourth side opposite to each other, wherein the first printed circuit board is disposed on the second printed circuit board such that the first side of the first printed circuit board faces the fourth side of the second printed circuit board, and The plurality of passive components are disposed between the first side of the first printed circuit board and the fourth side of the second printed circuit board. The substrate structure according to claim 5 , wherein: The plurality of passive components are connected to the first side of the first printed circuit board via a first physical connection and to the fourth side of the second printed circuit board via a second physical connection separate from the first physical connection.

7. The substrate structure according to claim 6, wherein: The plurality of passive components are connected to the first side of the first printed circuit board via a first conductive adhesive and to the fourth side of the second printed circuit board via a second conductive adhesive.

8. The substrate structure according to claim 5, further comprising: A plurality of first connection metals are provided between the first side of the first printed circuit board and the fourth side of the second printed circuit board, and connect the first side of the first printed circuit board and the fourth side of the second printed circuit board.

9. The substrate structure according to claim 8, wherein: When viewed from above, the plurality of first connection metals surround the first group and the second group.

10. The substrate structure according to claim 5, wherein: The first printed circuit board is a coreless printed circuit board, and The second printed circuit board is a core type printed circuit board.

11. The substrate structure according to claim 10, wherein: The thickness of the second printed circuit board is greater than the thickness of the first printed circuit board.

12. The substrate structure according to claim 10, wherein: The second printed circuit board has a larger plane area than the first printed circuit board.

13. An electronic device comprising: Motherboard; a first printed circuit board, disposed on the main board; a semiconductor chip disposed on one side of the first printed circuit board; as well as A plurality of passive components are arranged on the other side of the first printed circuit board, the other side of the first printed circuit board facing the main board, The plurality of passive components include a first group and a second group, the first group includes a plurality of first passive components, and the second group includes a plurality of second passive components. The semiconductor chip includes a first functional circuit and a second functional circuit disposed adjacent to each other on a plane, and When viewed from above, at least a portion of the first group overlaps with the first functional circuit, and when viewed from above, at least a portion of the second group overlaps with the second functional circuit, wherein the plurality of passive components further include a third group and a fourth group, the third group includes a plurality of third passive components, and the fourth group includes a plurality of fourth passive components and is separated from the third group, The semiconductor chip further includes a third functional circuit and a fourth functional circuit, When viewed from above, at least a portion of the third group overlaps with the third functional circuit, and at least a portion of the fourth group overlaps with the fourth functional circuit, Each of the third functional circuit and the fourth functional circuit includes an input / output unit, and The planar area of ​​the third functional circuit is greater than the planar area of ​​the fourth functional circuit.

14. The electronic device according to claim 13, wherein: Each of the first functional circuit and the second functional circuit includes at least one of a central processing unit, a graphics processing unit, a digital signal processor unit, an image signal processing unit, and a neural network processing unit.

15. The electronic device according to claim 13, wherein: The fourth group and the third group are spaced apart from each other by the first group.

16. The electronic device according to claim 13, further comprising: a second printed circuit board, disposed between the main board and the first printed circuit board; wherein the first printed circuit board is arranged on the second printed circuit board, and The plurality of passive components are disposed between the first printed circuit board and the second printed circuit board.

17. A printed circuit board having a first surface and a second surface opposing each other in a first direction, and provided with a semiconductor chip mounted on the second surface, the semiconductor chip having a first functional circuit and a second functional circuit arranged adjacent to each other on a plane, and further having a third functional circuit and a fourth functional circuit, the printed circuit board comprising: Planar insulation layer; a first passivation layer and a second passivation layer, each disposed between the planar insulating layer and a corresponding one of the first surface and the second surface, and each having an opening exposing a pad through the corresponding one of the first surface and the second surface; as well as a plurality of passive components disposed on the first surface of the printed circuit board and connected to a plurality of pads exposed through the first surface, the plurality of passive components comprising a first group, a second group, a third group, and a fourth group, the first group comprising a plurality of first passive components disposed adjacent to each other, the second group comprising a plurality of second passive components disposed adjacent to each other, the third group comprising a plurality of third passive components disposed adjacent to each other, and the fourth group comprising a plurality of fourth passive components disposed adjacent to each other, The first plurality of passive components, the second plurality of passive components, the third plurality of passive components, and the fourth plurality of passive components among the plurality of passive components are respectively arranged in regions overlapping with the first functional circuit, the second functional circuit, the third functional circuit, and the fourth functional circuit of the semiconductor chip in the first direction, respectively. Each of the third functional circuit and the fourth functional circuit includes an input / output unit, and the third group and the fourth group are spaced apart from each other by the first group.

18. The printed circuit board according to claim 17, wherein A plurality of pads exposed through the second surface overlap the plurality of passive components in the first direction.

19. The printed circuit board according to claim 17, further comprising: a buildup layer disposed between the planar insulating layer and one of the first surface and the second surface of the printed circuit board and having a wiring layer disposed therein and connected to the exposed pads, At least one of the first passivation layer and the second passivation layer is disposed between the accumulation layer and one of the first surface and the second surface.

20. The printed circuit board according to claim 17, further comprising: connecting metals, each having a melting point lower than that of copper, disposed on the pads in the openings of the first passivation layer and the second passivation layer on the first surface and the second surface of the printed circuit board, The distance that the connection metal on the first surface extends from the first surface in the first direction is greater than the distance that the passive components of the plurality of passive components extend from the first surface in the first direction.

21. The printed circuit board according to claim 17, wherein The plurality of first passive components are disposed adjacent to each other at equal intervals and the plurality of second passive components are disposed adjacent to each other at equal intervals.

22. The printed circuit board according to claim 17, wherein The first passive components are closer to each other than to any second passive component, and the second passive components are closer to each other than to any first passive component.

23. An electronic device comprising: A printed circuit board according to any one of claims 17 to 22; The semiconductor chip is mounted on the second surface of the printed circuit board; as well as An interposer is mounted to the first surface of the printed circuit board and includes a plurality of wiring layers connected to the pads exposed through the first surface of the printed circuit board.

24. A printed circuit board having a first surface and a second surface facing each other in a first direction, and provided with a semiconductor chip mounted on the second surface, the semiconductor chip having an input / output interface functional circuit, the printed circuit board comprising: Planar insulation layer; a first passivation layer and a second passivation layer, each disposed between the planar insulating layer and a corresponding one of the first surface and the second surface, and each having an opening exposing a pad through the corresponding one of the first surface and the second surface; as well as a plurality of passive components disposed on the first surface of the printed circuit board and connected to a plurality of pads exposed through the first surface, wherein the plurality of first passive components classified into the first group and the plurality of second passive components classified into the second group of the plurality of passive components respectively overlap with the first input / output interface function circuit and the second input / output interface function circuit of the semiconductor chip in the first direction; The first group is separated from the second group, and a planar area of ​​the first input / output interface functional circuit overlapping with the plurality of first passive components is larger than a planar area of ​​the second input / output interface functional circuit overlapping with the plurality of second passive components.

25. The printed circuit board according to claim 24, wherein The first passive component is electrically connected to the first input / output interface functional circuit of the semiconductor chip.

26. The printed circuit board according to claim 24, wherein The first passive component among the plurality of passive components connected to the pads exposed through the first surface is disposed in a region overlapping with at least one of the plurality of pads exposed through the second surface in the first direction.

27. The printed circuit board according to claim 24, wherein Each first passive component is disposed closer to another first passive component than any passive component disposed outside a region overlapping with the first input / output interface functional circuit of the semiconductor chip in the first direction.

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