SiC power device with terminal active region and same design and preparation method thereof

Abstract

The present invention provides a terminal active region same design SiC power device and a preparation method thereof, and relates to the field of SiC power devices. In the terminal active region same design SiC power device, the channel injection region forming the cellular structure channel and the junction terminal injection region of the terminal region for forming the junction terminal are simultaneously formed by the same masking layer etching and ion implantation process. By adopting the same ion implantation structure in the terminal region and the active region, the problem of uncontrollable channel size during ion implantation of the corresponding channel caused by different etching side wall angles due to different pattern area densities is solved.

Description

Technical Field

[0001] The present invention relates to the field of SiC power devices, and in particular to a SiC power device with a terminal active region and a preparation method thereof. Background Art

[0002] Modern power devices are made by connecting several cellular structures in parallel on a silicon wafer. The surface voltages of the cellular structures in the active area are roughly the same, but the voltages between the terminal (outermost end) and the substrate are very different, so measures need to be taken to reduce the surface electric field and increase the breakdown voltage. This technology is called junction termination technology. Junction termination technology sets an extension structure at the edge of the active area to widen the main junction depletion area outward to increase the withstand voltage level of the device, so that the gate of the power device is prevented from being broken down, thereby achieving the purpose of protecting the chip device.

[0003] At the same time, the third-generation wide bandgap semiconductor material silicon carbide (SiC) has many characteristics different from traditional silicon semiconductor materials. Its energy band gap is 2.8 times that of silicon, reaching 3.09 electron volts. The insulation breakdown field strength of silicon carbide is 5.3 times that of silicon, up to 3.2MV / cm, which allows silicon carbide devices to use thinner epitaxial layers than traditional silicon materials to achieve the same withstand voltage level as traditional silicon devices, while having lower on-resistance. Silicon carbide devices have good reverse recovery characteristics, small reverse recovery time period and current, small switching loss, and can reduce the power consumption of the entire system. Therefore, more and more companies are developing power devices made of silicon carbide materials to replace power devices made of silicon materials.

[0004] However, in the preparation process of silicon carbide power devices, if the existing preparation process of silicon power devices is used, especially in the ion implantation process, the problem of deviation in the ion implantation area often occurs; in the process of forming a channel by ion implantation, the channel size will be uncontrollable, thereby affecting the yield. Summary of the invention

[0005] In order to overcome the shortcomings of the prior art, the present invention provides a SiC power device with a terminal active area of ​​the same design and a preparation method thereof, which can achieve consistency in channel size and doping uniformity between the active area and the terminal area without adjusting the ion implantation process, thereby greatly reducing the process complexity and the difficulty of etching control.

[0006] To achieve the above-mentioned object, an embodiment of the present invention provides a SiC power device with a terminal active region of the same design, comprising: a second conductive type silicon carbide semiconductor substrate, the second conductive type silicon carbide semiconductor substrate comprising an active region and a terminal region surrounding the active region, the active region having a plurality of cellular structures;

[0007] The channel injection region for forming the channel of the cell structure and the junction terminal injection region for forming the junction terminal of the terminal region are formed simultaneously by adopting the same masking layer etching and ion implantation process.

[0008] Optionally, the cell structure of the active region is a silicon carbide MOSFET or a silicon carbide IGBT.

[0009] Optionally, when the SiC power device cell structure is a silicon carbide MOSFET, the specific structure of the silicon carbide MOSFET includes: a gate structure located on the first surface of the active area of ​​the second conductive type silicon carbide semiconductor substrate and a gate-source dielectric covering the gate structure; a drain electrode located on the other surface of the second conductive type silicon carbide semiconductor substrate; a first conductive type injection base region and a second conductive type injection source region located in the active area of ​​the second conductive type silicon carbide semiconductor substrate and on both sides of the gate structure, the first conductive type injection base region surrounds the second conductive type injection source region, the first conductive type injection base region and the second conductive type injection source region serve as channel injection regions for forming the silicon carbide MOSFET channel, the first conductive type injection base region is located between the second conductive type injection source region and the second conductive type silicon carbide semiconductor substrate and close to the gate structure as the channel of the silicon carbide MOSFET, the junction terminal injection region of the channel injection region and the terminal region is formed simultaneously using the same masking layer etching and ion implantation process; a source electrode located on the surface of the second conductive type injection source region.

[0010] Optionally, the terminal region is a field limiting ring or a JTE structure.

[0011] Optionally, when the terminal region is a field limiting ring, the structure of the terminal region includes: a plurality of annular first conductivity type terminal injection regions and second conductivity type terminal injection regions located in the terminal region of the second conductivity type silicon carbide semiconductor substrate; the annular first conductivity type terminal injection region surrounds the second conductivity type terminal injection region, the first conductivity type terminal injection region and the second conductivity type terminal injection region serve as junction terminal injection regions, and the junction terminal injection region and the channel injection region for forming a channel are formed simultaneously by using the same masking layer etching and ion implantation process.

[0012] Optionally, when the SiC power device cell structure is a silicon carbide MOSFET, the terminal region is a field limiting ring, and the specific structure of the silicon carbide MOSFET includes: a gate structure located on the first surface of the active region of the second conductive type silicon carbide semiconductor substrate and a gate-source dielectric covering the gate structure; a drain electrode located on the other surface of the second conductive type silicon carbide semiconductor substrate; a first conductive type injection base region, a second conductive type injection source region, and a first conductive type re-injection body region located in the active region of the second conductive type silicon carbide semiconductor substrate and on both sides of the gate structure, the first conductive type injection base region surrounds the second conductive type injection source region, the first conductive type injection base region and the second conductive type injection source region serve as channel injection regions for forming the silicon carbide MOSFET channel, and the first conductive type re-injection body region is located at the bottom of the channel injection region ; The first conductive type injection base region is located between the second conductive type injection source region and the second conductive type silicon carbide semiconductor substrate and close to the gate structure as a channel of the silicon carbide MOSFET; the structure of the terminal region includes: a plurality of annular first conductive type terminal injection regions, second conductive type terminal injection regions and first conductive type terminal re-injection regions located in the terminal region of the second conductive type silicon carbide semiconductor substrate; the annular first conductive type terminal injection region surrounds the second conductive type terminal injection region, the first conductive type terminal injection region and the second conductive type terminal injection region serve as junction terminal injection regions, and the first conductive type terminal re-injection region is located at the bottom of the junction terminal injection region; the junction terminal injection region and the channel injection region are formed simultaneously using the same masking layer etching and ion implantation process; the first conductive type re-injection body region and the first conductive type terminal re-injection region are formed simultaneously.

[0013] The embodiment of the present invention further provides a method for preparing a SiC power device with a terminal active region having the same design, comprising:

[0014] Providing a second conductive type silicon carbide semiconductor substrate, wherein the second conductive type silicon carbide semiconductor substrate comprises an active region and a terminal region surrounding the active region, wherein the active region has a plurality of cellular structures;

[0015] A channel injection region is formed in the active region and a junction termination injection region is formed in the terminal region simultaneously by using the same mask layer etching and ion implantation process. The channel injection region is used to form a channel, and the junction termination injection region is used to form a junction termination.

[0016] Optionally, the same masking layer etching and ion implantation process specifically includes: depositing a masking material layer on the surface of the second conductive type silicon carbide semiconductor substrate, and etching the masking material layer to form a masking layer for ion implantation, wherein the opening formed by etching the masking layer simultaneously exposes the surfaces of the active area and the terminal area where ion implantation is required; performing a first ion implantation on the exposed areas of the active area and the terminal area using the same ion implantation process; repeating the above-mentioned masking layer etching and ion implantation process steps, and performing a second ion implantation on the exposed areas of the active area and the terminal area using the same ion implantation process, so that a first conductive type injection base area and a second conductive type injection source area are formed in the active area, and a first conductive type terminal injection area and a second conductive type terminal injection area are formed in the terminal area, and the first conductive type injection base area and the first conductive type terminal injection area are simultaneously formed using the same masking layer etching and ion implantation process. The second conductive type injection source region and the second conductive type terminal injection region are formed simultaneously by another identical masking layer etching and ion implantation process, wherein a first conductive type injection base region and a second conductive type injection source region are formed in the active region of the second conductive type silicon carbide semiconductor substrate and on both sides of the gate structure, the first conductive type injection base region surrounds the second conductive type injection source region, and the first conductive type injection base region and the second conductive type injection source region serve as channel implantation regions for forming the silicon carbide MOSFET channel; a plurality of annular first conductive type terminal injection regions and second conductive type terminal injection regions are formed in the terminal region of the second conductive type silicon carbide semiconductor substrate; the annular first conductive type terminal injection region surrounds the second conductive type terminal injection region, and the first conductive type terminal injection region and the second conductive type terminal injection region serve as junction terminal injection regions.

[0017] The embodiment of the present invention further provides a method for preparing a SiC power device with a terminal active region having the same design, comprising:

[0018] Providing a second conductive type silicon carbide semiconductor substrate, wherein the second conductive type silicon carbide semiconductor substrate comprises an active region and a terminal region surrounding the active region, and the second conductive type silicon carbide semiconductor substrate comprises a silicon carbide substrate and a silicon carbide epitaxial layer located on a surface of the silicon carbide substrate;

[0019] A channel injection region is formed in the active region and a junction terminal injection region is formed in the terminal region by using the same masking layer etching and ion implantation process, wherein the channel injection region is used to form a channel, and the junction terminal injection region is used to form a junction terminal, wherein the channel injection region includes a first conductive type injection base region and a second conductive type injection source region, and the junction terminal injection region includes a plurality of annular first conductive type terminal injection regions and second conductive type terminal injection regions located in the second conductive type silicon carbide semiconductor substrate terminal region, wherein the first conductive type injection base region and the first conductive type terminal injection region are formed simultaneously by using the same masking layer etching and ion implantation process, and the second conductive type injection source region and the second conductive type terminal injection region are formed simultaneously by using the same masking layer etching and ion implantation process;

[0020] forming a gate structure corresponding to the channel injection region on the surface of the active region;

[0021] Forming a source electrode on the surface of the second conductive type injection source region, and forming a drain electrode on the surface of the second conductive type silicon carbide semiconductor substrate;

[0022] forming a gate-source dielectric covering a surface of the gate structure;

[0023] A passivation layer structure is formed on the surface of the terminal region.

[0024] Optionally, it also includes: forming a first conductive type re-injection body region at the bottom of the junction terminal injection region, forming a first conductive type terminal re-injection region at the bottom of the junction terminal injection region, and the first conductive type re-injection body region and the first conductive type terminal re-injection region are formed simultaneously using the same masking layer etching and ion implantation process.

[0025] Optionally, if the first conductivity type is N-type, the second conductivity type is P-type; conversely, if the first conductivity type is P-type, the second conductivity type is N-type.

[0026] In summary, the beneficial effects of the present invention are:

[0027] The embodiment of the present invention provides a terminal active area with the same design SiC power device and a preparation method thereof. The number of cell structures required for silicon carbide devices corresponding to different current sizes is different, resulting in different proportions of chip area occupied by the active area and different densities of the graphic areas. Etching and ion implantation are performed simultaneously in the terminal area and the active area. Due to the different densities of the graphic areas corresponding to different current sizes, the etching side wall angles of the active area are different, which in turn affects the edge accuracy of the area implanted by the mask, making the ion implantation patterns formed in different silicon carbide devices using the same ion implantation process inconsistent, causing the channel size to be uncontrollable for the channel area, thereby affecting the yield. However, since the present invention performs ion implantation simultaneously in the terminal area and the active area, the influence of different densities of the graphic areas corresponding to different current sizes is minimized, the side wall morphology of the etching performed using the same etching parameters is consistent, the etching process control is easier to control, and the ion implantation process control is also easier to control, thereby solving the problem of different etching side wall angles caused by different graphic area densities and thus causing the corresponding channel size to be uncontrollable.

[0028] Since the same process is adopted for etching and ion implantation in the terminal area and the active area of ​​the silicon carbide substrate, and the implantation damage after ion implantation is repaired by annealing process, an ion implantation area with the same junction depth is formed in the active area and the terminal area, and the junction terminal implantation area of ​​the terminal area and the channel implantation area of ​​the active area are formed at the same time with the same junction depth. In addition, there is good consistency in junction width and spacing, so there is a smaller curved surface at the connection interface between the active area and the terminal area, thereby reducing the curvature effect and increasing the breakdown voltage of the device.

[0029] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram showing that when the first etching is used in the prior art, the angle of the sidewall of the masking layer changes, thereby causing the junction terminal or the active area to be over-etched;

[0031] Figure 2 It is a schematic diagram showing that when the second etching is used in the prior art, the angle of the sidewall of the masking layer changes, thereby causing the junction terminal or the active area to be under-etched;

[0032] Figure 3 The figure shows one of the structural schematic diagrams of a SiC power device with a terminal active region of the embodiment of the present invention;

[0033] Figure 4 The figure shows the second structural schematic diagram of the SiC power device with the same design of the terminal active region according to the embodiment of the present invention;

[0034] Figures 5 to 8 It is a schematic diagram of the process structure of the method for preparing a SiC power device with a terminal active region design according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Why is it that in the preparation process of silicon carbide power devices, especially in the ion implantation process, the problem of deviation in the ion implantation area often occurs; in the process of forming a channel by ion implantation, the channel size will be uncontrollable and a tail will be formed, affecting the channel implantation concentration and thus affecting the yield. Why does this problem almost never occur in the preparation process of existing silicon power devices? After research, the inventors found that in the preparation process of silicon carbide power devices, ion implantation will not diffuse due to the annealing process, and the ion implantation area is the final doping area. Therefore, silicon carbide power devices have higher control requirements for the ion implantation area, while silicon devices will diffuse with the annealing process after the ion implantation process, and the ion implantation area after the annealing step will expand, so the control requirements for the ion implantation area are relatively low.

[0036] The ion implantation of silicon carbide power devices requires a mask layer to provide a mask, that is, the ion implantation area is determined by the opening and sidewall morphology formed after etching the mask layer. However, after further research, the inventors found that even if the same etching process (same etching machine and etching parameters) is used, the corresponding sidewall morphology is different in the preparation process of different silicon carbide power devices.

[0037] Further research has found that in existing power devices, for devices of the same voltage level, the width design of the junction terminal BB' area surrounding the active area AA' is the same, but for devices of different current sizes, the number of cell structures required is different, that is, the area of ​​the active area AA' is different. Therefore, the larger the current, the larger the active area area required, the larger the proportion of the active area in the entire device area, and the larger the proportion of the active area in the entire wafer area; the smaller the current, the smaller the active area area required, the smaller the proportion of the active area in the entire device area, and the smaller the proportion of the active area in the entire wafer area. In the existing preparation process of active area AA' and junction terminal BB', due to the different requirements of doping concentration, doping depth, etc., generally speaking, the ion implantation of active area AA' and junction terminal BB' is carried out separately. However, when ion implantation is carried out in active area AA', since the active areas corresponding to devices with different current sizes account for different proportions in the entire device (wafer), that is, the density of the graphic area is different, even if the same etching process (the same etching machine and etching parameters) is used, the local etching parameters (such as etching gas concentration) at the corresponding position of the active area are still biased, which will cause the etching side wall morphology of the mask layer to be different. Please refer to Figure 1 and Figure 2Using the underetched or overetched masking layer as a mask for ion implantation will naturally cause uncontrollable ion implantation areas.

[0038] If you want to solve this problem, one way is to adjust the etching process. Each power device of different size and current needs to have a corresponding etching menu to achieve the best etching angle. Not only is the experimental period long, but there are also control problems in the production process. Therefore, after research, the inventor proposed a SiC power device with the same design of the terminal active area, which solves the problem of different etching side wall angles caused by different density of the graphic area, which in turn causes the corresponding channel size to be uncontrollable.

[0039] In order to facilitate understanding by those skilled in the art, the present invention will be further described in detail below in conjunction with specific embodiments.

[0040] The embodiment of the present invention provides a SiC power device with a terminal active region and a same design. Figure 3 As shown, it includes a second conductive type silicon carbide semiconductor substrate, the second conductive type silicon carbide semiconductor substrate includes a silicon carbide substrate 201 and a silicon carbide epitaxial layer 202 located on the surface of the substrate; the second conductive type silicon carbide semiconductor substrate includes an active area AA' and a terminal area BB' surrounding the active area AA', the active area AA' has a plurality of cellular structures, Figure 3 In the figure, for the convenience of illustration, only one cell structure is used as an example.

[0041] a drain electrode 207 located on the other surface of the second conductivity type silicon carbide semiconductor substrate;

[0042] The channel injection region 1 and the junction terminal injection region 2 located in the silicon carbide epitaxial layer 202 are formed simultaneously by the same masking layer etching and ion implantation process. The channel injection region 1 for forming the cellular structure channel in the active region and the junction terminal injection region 2 for forming the junction terminal in the terminal region are formed simultaneously by the same masking layer etching and ion implantation process.

[0043] A gate structure 3 located on the surface of the epitaxial layer of the active area AA' and a gate-source dielectric 210 covering the gate structure, wherein the gate structure 3 includes a gate dielectric layer 208 located on the surface of the epitaxial layer of the active area AA' and polysilicon 209 located on the gate dielectric layer; in an embodiment of the present invention, polysilicon is used as the gate, and compared with a metal gate, the doping conditions in the polysilicon are changed to change its work function so as to reduce the critical voltage of the device. In other embodiments, other materials such as metal are used as the gate.

[0044] A source electrode 211 is located on the surface of the channel injection region; and a passivation layer structure 212 is located on the surface of the epitaxial layer in the terminal region BB' and covers the surface of the junction terminal injection region.

[0045] Specifically, the SiC power device with the same design in the terminal active region of this embodiment is a SiC power MOSFET device. In other embodiments, the SiC power device may also be a SiC IGBT device.

[0046] Please refer to Figure 3 In this embodiment, the channel injection region 1 includes a first conductivity type injection base region 203 and a second conductivity type injection source region 204 located above the surface of the first conductivity type injection base region 203; the junction terminal injection region 2 includes a first conductivity type terminal injection region 205 and a second conductivity type terminal injection region 206 located above the surface of the first conductivity type terminal injection region 205; in this embodiment, the junction terminal injection region 2 is in a plurality of concentric ring structures, and each ring-shaped junction terminal injection region 2 is not connected to each other and has the same junction width, and the junction terminal injection regions 2 have different spacings. In other embodiments, the junction terminal injection regions 2 may have different junction widths and the same spacings.

[0047] The first conductive type injection base region 203 and the first conductive type terminal injection region 205 are formed by simultaneously performing ion implantation on the etching windows located in the active area AA' and the terminal area BB' using the first ion doping concentration and the first energy, and the first conductive type injection base region 203 and the first conductive type terminal injection region 205 have a first junction depth; the second conductive type injection source region 204 and the second conductive type terminal injection region 206 are formed by simultaneously performing ion implantation on the etching windows located in the active area AA' and the terminal area BB' using the second ion doping concentration and the second energy, and the second conductive type injection source region 204 and the second conductive type terminal injection region 206 have a second junction depth. The first conductive type injection base region surrounds the second conductive type injection source region, and the annular first conductive type terminal injection region surrounds the second conductive type terminal injection region.

[0048] Please refer to Figure 4 In other embodiments, the channel injection region 1 further includes a first conductive type re-injection body region 313, and the junction terminal injection region 2 further includes a first conductive type terminal re-injection region 314; the first conductive type re-injection body region 313 is located below the first conductive type injection base region 303 and is connected to the first conductive type injection base region 303; the first conductive type terminal re-injection region 314 is located below the first conductive type injection region 305 and is connected to the first conductive type injection region 305; the first conductive type re-injection body region 313 and the first conductive type terminal re-injection region 314 are formed simultaneously using the same masking layer etching and ion implantation process, and the junction depth is equal.

[0049] In this embodiment, the first conductivity type is P-type doping, and the second conductivity type is N-type doping, that is, the first conductivity type injection base region is a P-type injection base region, and the first conductivity type injection region is a P-type injection region; the second conductivity type injection source region is an N-type injection source region, and the second conductivity type injection region is an N-type injection region; in addition, the first conductivity type heavy injection body region is a P-type heavy injection body region, and the first conductivity type heavy injection region is a P-type heavy injection region.

[0050] In other embodiments, the first conductivity type may also be N-type doping, and the second conductivity type may be P-type doping.

[0051] The present invention adopts the same structure for the terminal area and the active area, that is, the channel injection area of ​​the terminal area and the junction terminal injection area of ​​the active area are formed at the same time and the junction depth is equal, which solves the problem that the different etching side wall angles caused by the different densities of the two graphic areas of the terminal area and the active area lead to inconsistent corresponding channel dimensions.

[0052] The embodiment of the present invention further provides a method for preparing a SiC power device with a terminal active region having the same design, comprising:

[0053] Please refer to Figure 5 , providing a second conductive type silicon carbide semiconductor substrate, wherein the second conductive type silicon carbide semiconductor substrate includes a silicon carbide substrate 201 and a silicon carbide epitaxial layer 202 located on a surface of the silicon carbide substrate 201 .

[0054] A channel injection region is formed in the active region and a junction terminal injection region is formed in the terminal region by using the same masking layer etching and ion implantation process, wherein the channel injection region is used to form a channel, and the junction terminal injection region is used to form a junction terminal, wherein the channel injection region includes a first conductive type injection base region and a second conductive type injection source region, and the junction terminal injection region includes a plurality of annular first conductive type terminal injection regions and second conductive type terminal injection regions located in the terminal region of the second conductive type silicon carbide semiconductor substrate, wherein the first conductive type injection base region and the first conductive type terminal injection region are formed simultaneously by using the same ion implantation process, and the second conductive type injection source region and the second conductive type terminal injection region are formed simultaneously by using the same ion implantation process.

[0055] Before forming the channel injection region 1 and the junction terminal injection region 2, mask layer deposition, etching and other steps are required, as follows:

[0056] A masking material layer is deposited on the surface of the second conductive type silicon carbide semiconductor substrate, wherein the masking material is silicon oxide, silicon nitride or polysilicon, and the masking material layer is etched to form a masking layer for ion implantation. Since when etching the masking material layer, not only the channel implantation area of ​​the active area is etched, but also the junction terminal implantation area of ​​the terminal area is etched, even if the circuit size is different and the proportion of the active area in the entire wafer is different, the local etching parameters will not change much when etching is finally performed, resulting in not much change in the etched side wall morphology, resulting in not much error in the final ion implantation area of ​​different devices, thereby solving the problem of uncontrollable corresponding channel size caused by different etching side wall angles due to different graphic area densities.

[0057] Since the morphology of the sidewall structure of the masking layer is controllable, the problem of over-injection or under-injection will not occur in the subsequent ion implantation process, so that the channel implantation region 1 and the junction terminal implantation region 2 have better consistency.

[0058] Please refer to Figure 6 In the present embodiment, ion implantation is performed on the surface etching windows of the epitaxial layer located in the active area AA' and the terminal area BB' at the same time using the first ion doping concentration and the first energy to form a first conductive type implantation base area 203 located in the active area AA' and a first conductive type terminal implantation area 205 located in the terminal area BB', wherein the first conductive type implantation base area 203 and the first conductive type terminal implantation area 205 have a first junction depth.

[0059] Please refer to Figure 7 In the present embodiment, ion implantation is then performed simultaneously on the surfaces of the first conductive type injection base region 203 and the first conductive type terminal injection region 205 through a second masking layer using a second ion doping concentration and a second energy to form a second conductive type injection source region 204 located in the first conductive type injection base region 203 and a second conductive type terminal injection region 206 located in the first conductive type terminal injection region 205, wherein the second conductive type injection source region 204 and the second conductive type terminal injection region 206 have a second junction depth; the masking layer growth, photolithography and other steps required between the first ion implantation and the second ion implantation can be referred to as described above and will not be elaborated herein.

[0060] In addition, in other embodiments, please refer to Figure 4Before or after forming the first conductive type injection base region 303 and the first conductive type injection region 305, it also includes: simultaneously forming a first conductive type heavy injection body region 313 located below the first conductive type injection base region 303 and a first conductive type heavy injection region 314 located below the first conductive type injection region 305, the first conductive type heavy injection body region 313 and the first conductive type heavy injection region 314 having a third junction depth, the first conductive type heavy injection body region 313 being connected to the first conductive type injection base region 303; the first conductive type heavy injection region 314 being connected to the first conductive type injection region 305.

[0061] Since the same process is used for etching and ion implantation in the silicon carbide substrate, the etching process control is easier to control, and the implantation damage after ion implantation is repaired through the annealing process to form an ion implantation area with the same junction depth in the active area and the terminal area. The channel implantation area in the terminal area and the junction terminal implantation area in the active area are formed at the same time and have the same junction depth. In addition, they have good consistency in junction width and spacing, so there is a smaller curved surface at the connection interface between the active area and the terminal area, thereby reducing the curvature effect and increasing the breakdown voltage of the device.

[0062] Please refer to Figure 8 In this embodiment, after forming the corresponding channel injection region 1 and the junction terminal injection region 2 on the surface of the epitaxial layer 202, a gate structure 3 is then formed between the surface of the epitaxial layer in the active area AA' and the channel injection region 1; a passivation layer structure 212 is formed on the surface of the epitaxial layer in the terminal area BB'; a source electrode 211 is formed on the surface of the channel injection region 1, and a drain electrode 207 is formed on the surface of the second conductive type silicon carbide semiconductor substrate; and a gate-source dielectric 210 is formed covering the surface of the gate structure.

[0063] In this embodiment, since the first conductivity type is P-type doping and the second conductivity type is N-type doping, a P-type re-injection body region and a P-type re-injection region are simultaneously generated by P-type ion re-injection using the first mask layer; a P-type injection base region and a P-type injection region are simultaneously formed by P-type ion injection using the second mask layer; in addition, an N-type injection source region and an N-type injection region are formed by N-type ion injection using the third mask layer, and then a gate structure and a passivation layer structure are formed on the surface of the silicon carbide epitaxial layer.

[0064] In other embodiments, the first conductivity type may be N-type doped and the second conductivity type may be P-type doped to prepare corresponding devices.

[0065] Finally, it is to be noted that any modification or equivalent replacement of part or all of the technical features based on the device structure of the present invention and the technical solution of the described embodiment, which does not deviate from the essence of the corresponding technical solution of the present invention, belongs to the patent scope of the device structure of the present invention and the described implementation scheme.

Claims

1. A SiC power device with a terminal active region design, characterized in that: include: A second conductive type silicon carbide semiconductor substrate, wherein the second conductive type silicon carbide semiconductor substrate comprises an active region and a terminal region surrounding the active region, wherein the active region has a plurality of cellular structures; The channel injection region for forming the channel of the cell structure and the junction terminal injection region for forming the junction terminal of the terminal region are formed simultaneously by the same masking layer etching and ion implantation process; when the cell structure of the SiC power device is a silicon carbide MOSFET, the terminal region is a field limiting ring, and the specific structure of the silicon carbide MOSFET includes: a gate structure located on the first surface of the active region of the second conductive type silicon carbide semiconductor substrate and a gate-source dielectric covering the gate structure; a drain electrode located on the other surface of the second conductive type silicon carbide semiconductor substrate; a first conductive type injection base region, a second conductive type injection source region and a first conductive type re-injection body region located in the active region of the second conductive type silicon carbide semiconductor substrate and on both sides of the gate structure, the first conductive type injection base region surrounds the second conductive type injection source region, the first conductive type injection base region and the second conductive type injection source region serve as the channel injection region for forming the channel of the silicon carbide MOSFET, and the first conductive type re-injection body region is located at the bottom of the channel injection region; the first conductive type injection base region is located between the second conductive type injection source region and the second conductive type carbon The position between the silicon carbide semiconductor substrate and close to the gate structure is used as the channel of the silicon carbide MOSFET; the structure of the terminal area includes: a plurality of annular first conductivity type terminal injection areas, second conductivity type terminal injection areas and first conductivity type terminal re-injection areas located in the terminal area of ​​the second conductivity type silicon carbide semiconductor substrate; the annular first conductivity type terminal injection area surrounds the second conductivity type terminal injection area, the first conductivity type terminal injection area and the second conductivity type terminal injection area serve as junction terminal injection areas, and the first conductivity type terminal re-injection area is located at the bottom of the junction terminal injection area; the junction terminal injection area and the channel injection area are formed simultaneously by the same masking layer etching and ion implantation process; the first conductivity type re-injection body area and the first conductivity type terminal re-injection area are formed simultaneously; when the SiC power device cell structure is a silicon carbide MOSFET, the specific structure of the silicon carbide MOSFET includes: a gate structure located on the first surface of the active area of ​​the second conductivity type silicon carbide semiconductor substrate and a gate-source dielectric covering the gate structure; a drain electrode located on the other surface of the second conductivity type silicon carbide semiconductor substrate;A first conductive type implantation base region and a second conductive type implantation source region located in the active region of the second conductive type silicon carbide semiconductor substrate and located on both sides of the gate structure, the first conductive type implantation base region surrounds the second conductive type implantation source region, the first conductive type implantation base region and the second conductive type implantation source region serve as channel implantation regions for forming the channel of the silicon carbide MOSFET, the first conductive type implantation base region is located between the second conductive type implantation source region and the second conductive type silicon carbide semiconductor substrate and close to the gate structure as the channel of the silicon carbide MOSFET, the junction terminal implantation region of the channel implantation region and the terminal region are formed simultaneously by the same masking layer etching and ion implantation process; a source electrode located on the surface of the second conductive type implantation source region. ; 2. The SiC power device with terminal active region design as claimed in claim 1, characterized in that: The cell structure of the active region is a silicon carbide MOSFET or a silicon carbide IGBT.

3. The SiC power device with terminal active region design as claimed in claim 1, characterized in that: The terminal area is a field limiting ring or a JTE structure.

4. The SiC power device with terminal active region design as claimed in claim 3, characterized in that: When the terminal region is a field limiting ring, the structure of the terminal region includes: a plurality of annular first conductivity type terminal injection regions and second conductivity type terminal injection regions located in the terminal region of the second conductivity type silicon carbide semiconductor substrate; the annular first conductivity type terminal injection region surrounds the second conductivity type terminal injection region, the first conductivity type terminal injection region and the second conductivity type terminal injection region serve as junction terminal injection regions, and the junction terminal injection region and the channel injection region used to form a channel are formed simultaneously using the same mask layer etching and ion implantation process.

5. A method for preparing a SiC power device with a terminal active region having the same design, characterized in that: include: Providing a second conductive type silicon carbide semiconductor substrate, wherein the second conductive type silicon carbide semiconductor substrate comprises an active region and a terminal region surrounding the active region, wherein the active region has a plurality of cellular structures; A channel injection region is formed in the active region and a junction terminal injection region is formed in the terminal region simultaneously by using the same masking layer etching and ion implantation process, wherein the channel injection region is used to form a channel, and the junction terminal injection region is used to form a junction terminal; a first conductive type re-injection body region is formed at the bottom of the junction terminal injection region, and a first conductive type terminal re-injection region is formed at the bottom of the junction terminal injection region, and the first conductive type re-injection body region and the first conductive type terminal re-injection region are formed simultaneously by using the same masking layer etching and ion implantation process.

6. The method for preparing a SiC power device with a terminal active region design as claimed in claim 5, characterized in that: The same masking layer etching and ion implantation process specifically includes: depositing a masking material layer on the surface of the second conductive type silicon carbide semiconductor substrate, and etching the masking material layer to form a masking layer for ion implantation, wherein the opening formed by etching the masking layer simultaneously exposes the surfaces of the active area and the terminal area where ion implantation is required; performing a first ion implantation on the exposed areas of the active area and the terminal area using the same ion implantation process; repeating the above masking layer etching and ion implantation process steps, and performing a second ion implantation on the exposed areas of the active area and the terminal area using the same ion implantation process, so that a first conductive type implantation base area and a second conductive type implantation source area are formed in the active area, and a first conductive type terminal implantation area and a second conductive type terminal implantation area are formed in the terminal area, and the first conductive type implantation base area and the first conductive type terminal implantation area are simultaneously formed using the same masking layer etching and ion implantation process. The second conductive type injection source region and the second conductive type terminal injection region are formed simultaneously by another identical masking layer etching and ion implantation process, wherein a first conductive type injection base region and a second conductive type injection source region are formed in the active region of the second conductive type silicon carbide semiconductor substrate and on both sides of the gate structure, the first conductive type injection base region surrounds the second conductive type injection source region, and the first conductive type injection base region and the second conductive type injection source region serve as channel implantation regions for forming the silicon carbide MOSFET channel; a plurality of annular first conductive type terminal injection regions and second conductive type terminal injection regions are formed in the terminal region of the second conductive type silicon carbide semiconductor substrate; the annular first conductive type terminal injection region surrounds the second conductive type terminal injection region, and the first conductive type terminal injection region and the second conductive type terminal injection region serve as junction terminal injection regions.

7. A method for preparing a SiC power device with a terminal active region having the same design, characterized in that: include: A second conductive type silicon carbide semiconductor substrate is provided, wherein the second conductive type silicon carbide semiconductor substrate comprises an active area and a terminal area surrounding the active area, and the second conductive type silicon carbide semiconductor substrate comprises a silicon carbide substrate and a silicon carbide epitaxial layer located on the surface of the silicon carbide substrate; a channel injection region is formed in the active area and a junction terminal injection region is formed in the terminal area by using the same masking layer etching and ion implantation process, wherein the channel injection region is used to form a channel, and the junction terminal injection region is used to form a junction terminal, wherein the channel injection region comprises a first conductive type injection base region and a second conductive type injection source region, and the junction terminal injection region comprises a plurality of annular first conductive type terminal injection regions and second conductive type terminal injection regions located in the terminal area of ​​the second conductive type silicon carbide semiconductor substrate, wherein the first conductive type injection base region and the first conductive type terminal injection region are formed simultaneously by using the same masking layer etching and ion implantation process, and the second conductive type injection source region and the second conductive type terminal injection region are formed simultaneously by using the same masking layer etching and ion implantation process; and a gate structure corresponding to the channel injection region is formed on the surface of the active area; A source electrode is formed on the surface of the second conductive type injection source region, and a drain electrode is formed on the surface of the second conductive type silicon carbide semiconductor substrate; a gate-source dielectric covering the surface of the gate structure is formed; and a passivation layer structure is formed on the surface of the terminal region.

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