A battery voltage detection circuit

Abstract

The present invention relates to the technical field of voltage detection, and discloses a battery voltage detection circuit, comprising a reference voltage, a first capacitor voltage divider circuit, a second capacitor voltage divider circuit, a voltage clamping circuit and a comparator. The reference voltage is input to the comparator via the first capacitor voltage divider circuit, and the voltage clamping circuit clamps the voltage at the input end of the second capacitor voltage divider circuit to the voltage of a single battery. The voltage of the single battery is input to the comparator via the second capacitor voltage divider circuit. In actual use, the capacitor voltage divider circuit can be used to compare the voltage of the single battery with the reference voltage, thereby improving the detection accuracy. In addition, since there is no need to set a detection resistor and a related fuse structure, the cost of the chip using the present invention is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage detection, and in particular to a battery voltage detection circuit. Background Art

[0002] Batteries are an independent power source that can store electrical energy first and then supply power to the load independently without relying on the power grid. They are widely used in people's daily lives. For example, two-wheeled electric vehicles, new energy vehicles and other means of transportation are driven by the electrical energy released by batteries.

[0003] During the use of the battery, battery monitoring and protection is crucial to the safe use of the battery. Knowing the battery voltage in time can prevent the battery from being overcharged during charging and over-discharged during discharging, and can disconnect the battery from the load in time when the battery voltage is abnormal. Most existing battery voltage detection is performed by resistor voltage division, and using resistor voltage division to detect the voltage of each battery in multiple series batteries requires more resistors for detection, and when improving the product's high-precision voltage detection, it is also necessary to add multiple fuse structures, which increases the cost of the chip using the voltage division resistor voltage detection circuit. Summary of the invention

[0004] In view of the shortcomings of the background technology, the present invention provides a battery voltage detection circuit, and the technical problem to be solved is the high cost of the chip of the voltage detection circuit of the voltage divider resistor type.

[0005] To solve the above technical problems, the present invention provides the following technical solutions: a battery voltage detection circuit, comprising a reference voltage, a first capacitor voltage divider circuit, a second capacitor voltage divider circuit, a voltage clamping circuit and a comparator, wherein the reference voltage is input to the first input terminal of the comparator via the first capacitor voltage divider circuit; one electrode of a single battery in a plurality of series-connected batteries is electrically connected to the first capacitor voltage divider circuit, and another electrode of the single battery in the plurality of series-connected batteries is electrically connected to the second capacitor voltage divider circuit, and the voltage clamping circuit clamps the voltage at the input terminal of the second capacitor voltage divider circuit to the voltage of the single battery, and the voltage of the single battery is input to the second input terminal of the comparator via the second capacitor voltage divider circuit.

[0006] In a certain embodiment, it also includes a first switching switch circuit and a second switching switch circuit, the first switching switch circuit includes multiple switching channels, and the second switching switch circuit includes multiple switching channels; one electrode of a single battery in the multiple series-connected batteries is electrically connected to the first capacitor voltage divider circuit via a single switching channel in the first switching switch circuit, and the other electrode of the single battery in the multiple series-connected batteries is electrically connected to the second capacitor voltage divider circuit via a single switching channel in the second switching switch circuit.

[0007] In some implementations, when one switching channel in the first switching switch circuit is turned on, the other switching channels are turned off, and when one switching channel in the second switching switch circuit is turned on, the other switching channels are turned off.

[0008] In a certain embodiment, the voltage clamping circuit includes a capacitor V_CAP, a switch S3, a switch S10, a switch S11 and a switch S12, the two ends of the capacitor V_CAP are electrically connected to the input end of the first capacitor voltage divider circuit and the input end of the second capacitor voltage divider circuit, respectively, the two ends of the switch S3 are electrically connected to the input end of the first capacitor voltage divider circuit and the input end of the second capacitor voltage divider circuit, respectively, the first input end of the comparator is grounded through the switch S10, the second input end of the comparator is grounded through the switch S11, one end of the switch S12 is electrically connected to the end of the voltage divider capacitor at the end of the first capacitor voltage divider circuit and the end of the voltage divider capacitor at the end of the second capacitor voltage divider circuit, respectively, and the switch 10, switch S11 and switch S12 are closed or opened at the same time.

[0009] In a certain embodiment, the first capacitor voltage-dividing circuit includes a capacitor C11, a capacitor C12, and a switch S40 connected in series in sequence, the connection point between the capacitor C12 and the capacitor C11 is electrically connected to the first input terminal of the comparator, and the connection point between the capacitor C12 and the switch S40 is electrically connected to one end of the switch S12; the reference voltage is input to the input terminal of the switch S40; the second capacitor voltage-dividing circuit includes a capacitor C21, a capacitor C22, and a switch S41 connected in series in sequence, the end of the switch S41 that is not electrically connected to the capacitor C22 is grounded, the end of the capacitor C21 and the capacitor C22 that is electrically connected is electrically connected to the second input terminal of the comparator, the connection point between the capacitor C22 and the switch S41 is electrically connected to one end of the switch S12, and the switch S40 and the switch S41 are closed or opened at the same time.

[0010] In a certain embodiment, one electrode of each battery of the multiple batteries connected in series is connected to a switching channel of a first switching switch circuit, and another electrode of each battery of the multiple batteries connected in series is connected to a switching channel of a second switching switch circuit, one switching channel in the first switching switch circuit is electrically connected to only an electrode of one battery, and one switching channel in the second switching switch circuit is electrically connected to only an electrode of one battery.

[0011] In a certain embodiment, a first switching timing signal is input to the first switching switch circuit, and a second switching timing signal is input to the second switching switch circuit, so that the battery voltage detection circuit first detects the voltage of the single battery with the lowest positive electrode voltage during voltage detection, and then detects the voltage across each battery in the order of increasing positive electrode voltage.

[0012] In a certain embodiment, when the voltage of the first detected battery is detected, the fifth timing signal of the first state is first input to the switch S10 and the switch S11 to close the switch S10 and the switch S11, and then the first switching timing signal is input to the first switching switch circuit to connect the positive electrode of the first detected battery to the first capacitor voltage divider circuit, and the second switching timing signal is input to the second switching switch circuit to connect the negative electrode of the first detected battery to the second capacitor voltage divider circuit, so as to realize the charging of the capacitor V_CAP and the capacitor C11. After charging, the second switching timing signal is input to the second switching switch circuit to disconnect the negative electrode of the first detected battery from the second capacitor voltage divider circuit, and the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and then the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41, and the third timing signal of the first state is input to the switch S3 to close the switch S3;

[0013] When the voltage of the second detected battery is detected, the fourth timing signal of the second state is input to the switch S40 and the switch S41 to disconnect the switch S40 and the switch S41, and the fifth timing signal of the first state is input to the switch S10 and the switch S11 to close the switch S10 and the switch S11, so that the capacitor C11 and the capacitor C21 are charged. After charging, the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and the third timing signal of the second state is input to the switch S3 to disconnect the switch S3, and then the second switching timing signal is input to the second switching switch circuit to connect the positive electrode of the second detected battery to the second capacitor voltage divider circuit, and then the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41;

[0014] When the voltage of the third detected battery is detected, the first switching timing signal is input to the first switching switch circuit to connect the positive electrode of the third detected battery to the first capacitor voltage divider circuit, and then the fourth timing signal of the second state is input to the switch S40 and the switch S41 to disconnect the switch S40 and the switch S41, and the fifth timing signal of the first state is input to the switch S10 and the switch S11 to close the switch S10 and the switch S11, so that the capacitor C11 is charged. After charging, the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and then the second switching timing signal is input to the second switching switch circuit to disconnect the negative electrode of the third detected battery from the second capacitor voltage divider circuit, the third timing signal of the first state is input to the switch S3 to close the switch S3, and the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41;

[0015] When the Nth detected battery is detected, N is an even number greater than 2, a fourth timing signal of the second state is input to switch S40 and switch S41 to disconnect switch S40 and switch S41, and a fifth timing signal of the first state is input to switch S10 and switch S11 to close switch S10 and switch S11, so that capacitor C11 and capacitor C21 are charged. After charging, a fifth timing signal of the second state is input to switch S10 and switch S11 to disconnect switch S10 and switch S11, and a third timing signal of the second state is input to switch S3 to disconnect switch S3, and then a second switching timing signal is input to the second switching switch circuit to connect the positive electrode of the Nth detected battery to the second capacitor voltage divider circuit, and then a fourth timing signal of the first state is input to switch S40 and switch S41 to close switch S40 and switch S41;

[0016] When the battery detected in the Mth section is detected, M is an odd number greater than 3, and the first switching timing signal is input to the first switching switch circuit to connect the positive electrode of the battery detected in the Mth section to the first capacitor voltage divider circuit, and then the fourth timing signal of the second state is input to the switch S40 and the switch S41 to disconnect the switch S40 and the switch S41, and the fifth timing signal of the first state is input to the switch S10 and the switch S11 to close the switch S10 and the switch S11 to charge the capacitor C11. After charging, the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and then the second switching timing signal is input to the second switching switch circuit to disconnect the negative electrode of the battery detected in the Mth section from the second capacitor voltage divider circuit, the third timing signal of the first state is input to the switch S3 to close the switch S3, and the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41. In some embodiments, a digital timing logic module is further included, wherein the digital timing logic module is configured to generate a first switching timing signal, a second switching timing signal, a third timing signal, a fourth timing signal and a fifth timing signal, wherein the first state is a high level state and the second state is a low level state.

[0017] In a certain embodiment, the reference voltage includes an over-discharge reference voltage and an over-charge reference voltage. The reference voltage module generates the over-discharge reference voltage and the over-charge reference voltage. The over-discharge reference voltage and the over-charge reference voltage are input into the first capacitor voltage divider circuit through the dual-channel switch S6. In the period T when the reference voltage is input into the comparator, the time when the over-discharge reference voltage is input into the comparator is A*T / C, and the time when the over-charge reference voltage is input into the comparator is B*T / C. A, B and C are all positive numbers, and A+B=C.

[0018] In a certain embodiment, the present invention also includes a detection module, the output end of the comparator inputs a first detection signal to the detection module, the output end of the comparator inputs a second detection signal to the detection module through an inverter, and when the first detection signal is in a first state, the detection module outputs an overcharge protection signal, and when the second detection signal is in the first state, the detection module outputs an over-discharge protection signal.

[0019] In some implementations, the capacitor in the first capacitor voltage divider circuit and the capacitor in the second capacitor voltage divider circuit are MOM capacitor structures.

[0020] Compared with the prior art, the present invention has the following beneficial effects: the voltage of a single battery cell can be compared with a reference voltage through a capacitive voltage divider circuit, thereby improving detection accuracy; and since there is no need to set a detection resistor and a related fuse structure, the cost of the chip using the present invention is reduced; in addition, the voltage at both ends of each battery is dynamically detected through timing control, rather than always energizing the resistor for detection, thereby reducing the loss of the present invention in actual use. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a structural diagram of an implementation of a battery voltage detection circuit in an embodiment;

[0022] Figure 2 is another structural diagram of a battery voltage detection circuit in the embodiment;

[0023] Figure 3 is a connection circuit diagram of a first capacitor voltage divider circuit, a second capacitor voltage divider circuit, a voltage clamp circuit, a first switching switch circuit, a second switching switch circuit and a comparator in an embodiment;

[0024] Figure 4 A schematic diagram of a reference voltage generation module generating a reference voltage in an embodiment;

[0025] Figure 5 is a schematic diagram of the connection between the comparator and the detection module in the embodiment;

[0026] Figure 6 A charging structure diagram of five batteries connected in series as tested in the embodiment;

[0027] Figure 7 for Figure 3 Schematic diagram of signal flow when the circuit in the figure detects the first battery;

[0028] Figure 8 for Figure 3 Schematic diagram of signal flow when the circuit in is detecting the second battery;

[0029] Fig. 9 for Figure 3 Schematic diagram of signal flow when the circuit in the figure detects the third battery;

[0030] Fig.10 for Figure 3 Schematic diagram of signal flow when the circuit in is testing the fourth battery;

[0031] Fig.11 for Figure 3 Schematic diagram of signal flow when the circuit in is testing the fifth battery;

[0032] Fig.12This is a timing diagram of all timing signals generated by the digital timing module. DETAILED DESCRIPTION

[0033] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0034] like Figure 1 As shown, a battery voltage detection circuit includes a reference voltage VREF, a first capacitor voltage divider circuit 1, a second capacitor voltage divider circuit 2, a voltage clamping circuit 3 and a comparator CMP, the reference voltage VREF is input to the first input terminal V- of the comparator CMP through the first capacitor voltage divider circuit 1; one electrode of a single battery in a plurality of series-connected batteries is electrically connected to the first capacitor voltage divider circuit 1, and another electrode of the single battery in the plurality of series-connected batteries is electrically connected to the second capacitor voltage divider circuit 2, the voltage clamping circuit 3 clamps the voltage of the input terminal IN2 of the second capacitor voltage divider circuit 2 to the voltage of the single battery, and the voltage of the single battery is input to the second input terminal V+ of the comparator CMP through the second capacitor voltage divider circuit 2.

[0035] In actual use, the voltage at the input terminal IN2 of the second capacitor voltage divider circuit 2 is clamped to the voltage of a single battery cell through the voltage clamping circuit 3, and then the voltage of the single battery cell is input to the comparator CMP through the second capacitor voltage divider circuit 2. The comparator CMP compares the voltage of the single battery cell after the voltage is divided by the second capacitor voltage divider circuit 2 with the voltage of the reference voltage VREF after the voltage is divided by the first capacitor voltage divider circuit 1, and determines whether the voltage of the single battery cell is too high or too low.

[0036] like Figure 2 As shown, in Figure 1 On the basis of the implementation mode, in this implementation mode, the present invention also includes a first switching switch circuit 4 and a second switching switch circuit 5, the first switching switch circuit 4 includes multiple switching channels, and the second switching switch circuit 5 includes multiple switching channels; one electrode of a single battery in the multiple series-connected batteries is electrically connected to the first capacitor voltage divider circuit 1 via a single switching channel in the first switching switch circuit 4, and the other electrode of the single battery in the multiple series-connected batteries is electrically connected to the second capacitor voltage divider circuit 2 via a single switching channel in the second switching switch circuit 5.

[0037] In actual use, the two ends of a single battery can be connected to the first capacitor voltage divider circuit 1 and the second capacitor voltage divider circuit respectively through the first switching switch circuit 4 and the second switching switch circuit 5, and then the voltage of the single battery is detected and judged through the voltage clamp circuit 3, the first capacitor voltage divider circuit 1, the second capacitor voltage divider circuit 2 and the comparator CMP. In addition, in order to ensure that no other battery is connected to the first switching switch circuit 4 and the second switching switch circuit 6 when the current single battery is detected, when one switching channel in the first switching switch circuit 4 is turned on, the other switching channels are turned off, and when one switching channel in the second switching switch circuit 5 is turned on, the other switching channels are turned off.

[0038] like Figure 3 As shown, the voltage clamping circuit includes a capacitor V_CAP, a switch S3, a switch S10, a switch S11 and a switch S12, the two ends of the capacitor V_CAP are electrically connected to the input end of the first capacitor voltage divider circuit 1 and the input end of the second capacitor voltage divider circuit 2 respectively, the two ends of the switch S3 are electrically connected to the input end of the first capacitor voltage divider circuit 1 and the input end of the second capacitor voltage divider circuit 2 respectively, the first input end V- of the comparator CMP is grounded through the switch S10, the second input end V+ of the comparator CMP is grounded through the switch S11, one end of the switch S12 is electrically connected to the end of the voltage divider capacitor at the end of the first capacitor voltage divider circuit 1 and the end of the voltage divider capacitor at the end of the second capacitor voltage divider circuit 2 respectively, and the switch 10, the switch S11 and the switch S12 are closed or opened at the same time.

[0039] The first capacitor voltage divider circuit 1 includes a capacitor C11, a capacitor C12 and a switch S40 connected in series in sequence, the connection point between the capacitor C12 and the capacitor C11 is electrically connected to the first input terminal V- of the comparator CMP, and the connection point between the capacitor C12 and the switch S40 is electrically connected to one end of the switch S12; the reference voltage VREF is input to the input end of the switch S40; the second capacitor voltage divider circuit 2 includes a capacitor C21, a capacitor C22 and a switch S41 connected in series in sequence, the end of the switch S41 that is not electrically connected to the capacitor C22 is grounded, the end of the capacitor C21 and the capacitor C22 that is electrically connected is electrically connected to the second input terminal V+ of the comparator CMP, the connection point between the capacitor C22 and the switch S41 is electrically connected to one end of the switch S12, and the switch S40 and the switch S41 are closed or opened at the same time.

[0040] exist Figure 3 In the embodiment, the first switching circuit 4 includes three switching channels, and the second switching circuit 5 includes three switching channels. Figure 3The circuit in can detect the voltage of at most five batteries connected in series. In actual use, the number of switching channels of the first switching switch circuit 4 and the second switching switch circuit 5 can be determined according to the actual detection requirements, and there is no restriction here. When the voltage of seven batteries connected in series is detected, the first switching switch circuit 4 and the second switching switch circuit 5 each include four switching channels, and when the voltage of nine batteries connected in series is detected, the first switching switch circuit 4 and the second switching switch circuit 5 each include five switching channels. For the channels in the first switching switch circuit 4 and the second switching switch circuit 5, each channel can be a control switch composed of a single MOS tube.

[0041] like Figure 4 As shown, in actual use, the reference voltage includes an over-discharge reference voltage and an over-charge reference voltage. The reference voltage module can be used to generate the over-discharge reference voltage and the over-charge reference voltage. The over-discharge reference voltage and the over-charge reference voltage are input into the first capacitor voltage divider circuit 1 through the dual-channel switch S6. In the period T of the reference voltage input into the comparator CMP, the time for the over-discharge reference voltage to be input into the comparator CMP is A*T / C, and the time for the over-charge reference voltage to be input into the comparator CMP is B*T / C. A, B and C are all positive numbers, and A+B=C. Preferably, A and B are the same, that is, the over-discharge reference voltage and the over-charge reference voltage are input into the comparator CMP for half of the time in the period T of the reference voltage VREF input into the comparator CMP. The comparator CMP compares the voltages at both ends of the battery with the over-discharge reference voltage and the over-charge reference voltage in turn during voltage detection.

[0042] In actual use, since the comparator CMP outputs a high-level detection signal only when the voltage at the second input terminal V+ is greater than the voltage at the first input terminal V-, the high-level detection signal can only detect one state, and cannot realize overcharge detection or over-discharge detection of the battery voltage. Figure 5 In the embodiment, the output end of the comparator CMP is also connected to an inverter. When over-discharge detection is performed, if the voltage of the second output end V+ of the comparator CMP is less than the voltage of the first input end V-, the comparator CMP outputs a low-level detection signal, and the low-level detection signal outputs a high-level signal after passing through the inverter. Over-discharge detection can be achieved based on the high-level signal; when over-charge detection is performed, if the voltage of the second output end V+ of the comparator CMP is greater than the voltage of the first input end V-, the comparator CMP outputs a high-level detection signal, and the inverter outputs a low-level detection signal. Battery over-charge detection can be achieved based on the high-level detection signal.

[0043] In addition Figure 5In the embodiment, the output end of the comparator CMP directly inputs the first detection signal to the detection module, and the output end of the comparator CMP inputs the second detection signal to the detection module via the inverter. The detection module outputs an overcharge protection signal to drive the peripheral overcharge protection circuit to operate when the first detection signal is in the first state, i.e., a high level, and outputs an over-discharge protection signal to drive the peripheral over-discharge protection circuit to operate when the second detection signal is in the first state, i.e., a high level.

[0044] During actual voltage detection, one electrode of each battery of the multiple batteries connected in series is connected to a switching channel of the first switching switch circuit 4, and the other electrode of each battery of the multiple batteries connected in series is connected to a switching channel of the second switching switch circuit 5. One switching channel in the first switching switch circuit 4 is electrically connected to only one electrode of the battery, and one switching channel in the second switching switch circuit 5 is electrically connected to only one electrode of the battery.

[0045] During actual voltage detection, a first switching timing signal can be input into the first switching switch circuit 4, and a second switching timing signal can be input into the second switching switch circuit 5, so as to select which switching channel in the first switching switch circuit 4 is turned on and which switching channel in the second switching switch circuit 5 is turned on, so that the battery voltage detection circuit first detects the voltage of the single battery with the lowest positive pole voltage when performing voltage detection, and then detects the voltage at both ends of each battery in the order of increasing positive pole voltage of the battery.

[0046] Specifically, the working process of the first voltage divider circuit 1, the second capacitor voltage divider circuit and the voltage clamp circuit when performing voltage detection is as follows:

[0047] When the voltage of the first detected battery is detected, the fifth timing signal of the first state is first input to the switch S10 and the switch S11 to close the switch S10 and the switch S11, and then the first switching timing signal is input to the first switching switch circuit 4 to connect the positive electrode of the first detected battery to the first capacitor voltage divider circuit 1, and the second switching timing signal is input to the second switch switching circuit 5 to connect the negative electrode of the first detected battery to the second capacitor voltage divider circuit 2, so as to realize the charging of the capacitor V_CAP and the capacitor C11. After charging, the second switching timing signal is input to the second switch switching circuit 5 to disconnect the negative electrode of the first detected battery from the second capacitor voltage divider circuit 2, and the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and then the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41, and the third timing signal of the first state is input to the switch S3 to close the switch S3;

[0048] When the voltage of the second detected battery is detected, the fourth timing signal of the second state is input to the switch S40 and the switch S41 to disconnect the switch S40 and the switch S41, and the fifth timing signal of the first state is input to the switch S10 and the switch S11 to close the switch S10 and the switch S11, so that the capacitor C11 and the capacitor C21 are charged. After charging, the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and the third timing signal of the second state is input to the switch S3 to disconnect the switch S3, and then the second switching timing signal is input to the second switching switch circuit 5 to connect the positive electrode of the second detected battery to the second capacitor voltage divider circuit 2, and then the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41;

[0049] When the voltage of the third detected battery is detected, the first switching timing signal is input to the first switching switch circuit 4 so that the positive electrode of the third detected battery is connected to the first capacitor voltage divider circuit, and then the fourth timing signal of the second state is input to the switch S40 and the switch S41 to disconnect the switch S40 and the switch S41, and the fifth timing signal of the first state is input to the switch S10 and the switch S11 to close the switch S10 and the switch S11, so that the capacitor C11 is charged. After charging, the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and then the second switching timing signal is input to the second switching switch circuit to disconnect the negative electrode of the third detected battery from the second capacitor voltage divider circuit 2, the third timing signal of the first state is input to the switch S3 to close the switch S3, and the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41;

[0050] When the Nth detected battery is detected, N is an even number greater than 2, a fourth timing signal of the second state is input to switch S40 and switch S41 to disconnect switch S40 and switch S41, and a fifth timing signal of the first state is input to switch S10 and switch S11 to close switch S10 and switch S11, so that capacitor C11 and capacitor C21 are charged. After charging, a fifth timing signal of the second state is input to switch S10 and switch S11 to disconnect switch S10 and switch S11, and a third timing signal of the second state is input to switch S3 to disconnect switch S3, and then a second switching timing signal is input to the second switching switch circuit 5 to connect the positive electrode of the Nth detected battery to the second capacitor voltage divider circuit, and then a fourth timing signal of the first state is input to switch S40 and switch S41 to close switch S40 and switch S41;

[0051] When the battery detected in the Mth section is detected, M is an odd number greater than 3, and the first switching timing signal is input to the first switching switch circuit 4 to connect the positive electrode of the battery detected in the Mth section to the first capacitor voltage divider circuit 1, and then the fourth timing signal of the second state is input to the switch S40 and the switch S41 to disconnect the switch S40 and the switch S41, and the fifth timing signal of the first state is input to the switch S10 and the switch S11 to close the switch S10 and the switch S11 to charge the capacitor C11. After charging, the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and then the second switching timing signal is input to the second switching switch circuit 5 to disconnect the negative electrode of the battery detected in the Mth section from the second capacitor voltage divider circuit 2, the third timing signal of the first state is input to the switch S3 to close the switch S3, and the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41.

[0052] To Figure 6 Take the voltage detection of five rechargeable and dischargeable batteries in the example as an example. Figure 6 The five batteries in series are also electrically connected to the charger, load, discharge path and charging path. The five charging and discharging batteries have six common test points, so use Figure 3 The circuit in can just realize the voltage detection of all battery cells. Figure 3 and Figure 6 In the figure, the points with the same number are directly connected points in the actual circuit. The node with the lowest battery voltage is V1. In the order of increasing battery voltage, the voltage between V1 and the ground point, the voltage between V2 and V1, the voltage between V3 and V2, the voltage between V4 and V3, and the voltage between V5 and V4 are tested in turn. The specific testing process is as follows:

[0053] The first thing you need to understand is the capacitance reactance formula: Capacitive reactance is inversely proportional to capacitance. The larger the capacitance, the smaller the capacitive reactance.

[0054] The design defines known quantities: C11=C21, C12=C22, n*C11=C12, that is, Xc11=Xc21Xc12=Xc22, Xc11=Xc21=n*Xc12=n*Xc22, GND is the reference point, equal to 0V.

[0055] The workflow for detecting the voltage between point V1 and GND is as follows:

[0056] a: First, close the switches S10 and S11, and the voltages of the first input terminal V- and the second input terminal V+ of the comparator CMP are 0V;

[0057] b: Connect switch S1 to V1 and switch S2 to GND, so that V11 = V1 and V22 = GND. At this time, capacitors V_CAP and C11 are fully charged by V1.

[0058] c: Open the switch S2 and leave it suspended, open the switches S10 and S11, close the switches S3, S40 and S41, and generate two capacitor charging paths. The two capacitor charging paths can be referenced Figure 7 ;

[0059] Path 1: From V1→S1→V11→S3→V22→C21→C22→GND, we can know the voltage on V+, which is obtained by dividing the series capacitors (refer to the above capacitor reactance formula):

[0060]

[0061] Path 2: VREF→C12→C11→V11→S1→V1. As above, we can see that the voltage on V- is obtained by dividing the series capacitors:

[0062]

[0063] According to the op amp, V+-V- is:

[0064]

[0065] Since GND is 0V, VREF minus GND is directly obtained by taking VREF and substituting it into the known quantities defined in the design to obtain:

[0066]

[0067] When n = 2, In this way, the voltage between V1 and GND can be obtained:

[0068] In actual use, by changing the value of the reference voltage VREF, voltage detection for different purposes can be achieved. Figure 4 When the reference voltage module in the switch S40 is generated, in the closed cycle of the switch S40, the reference voltage VREF can be connected to the overcharge reference voltage in half of the cycle, and the reference voltage can be connected to the overdischarge reference voltage in the other half of the cycle, thereby realizing overcharge detection and overdischarge detection of the battery.

[0069] When S6 is connected to the overcharge reference voltage (assuming it is equal to 2.1V), VREF = overcharge reference voltage = 2.1V,

[0070] According to the above formula It is found that when the voltage of V1 is greater than 4.2V, the comparator CMP generates a first detection signal of the first state, that is, a first detection signal of a high level. Figure 5 The detection module in the circuit outputs an overcharge protection signal to close the charging path NM2 tube, stop charging, and implement overcharge detection protection.

[0071] When S6 is connected to the over-discharge reference voltage (assuming 1.3V), VREF = over-discharge reference voltage = 1.3V. According to the above formula It is found that when the voltage of V1 is less than 2.6V, the comparator CMP and the inverter generate the second detection signal of the first state, that is, the second detection signal of high level.

[0072] The discharge protection signal closes the discharge path NM1 tube and stops the discharge. Figure 5 The detection module in the circuit outputs an over-discharge protection signal to close the discharge path NM1 tube, stop discharging, and implement over-discharge detection protection.

[0073] Through the voltage detection function, it can generate protection signals for battery charging overvoltage or discharging overvoltage, thus increasing the battery life;

[0074] After the voltage detection between V1 and GND is completed, the process of detecting the voltage between V2 and V1 is as follows:

[0075] a: Switch S1 remains connected to V1, switch S3 remains closed, V1 = V11 = V22;

[0076] b: Switch S40 is open, switch S10 is closed, V+=V-=GND, capacitors C11 and C21 are fully charged by V1;

[0077] c: After capacitor C11 and capacitor C21 are fully charged, switch S10 and switch S3 are disconnected;

[0078] d: Switch S2 to connect to V2, and switch S40 is closed. At this time, two capacitor charging paths are generated. Figure 8 ;

[0079] Path 1: V2→S2→V22→C21→C22→GND. At this time, since the initial potential of V22 is equal to V1, the dynamic voltage is the difference between V2 and V1, which is divided by the series capacitors to obtain the V+ voltage:

[0080]

[0081] Path 2: From VREF→C12→C11→V11→S1→V1, we get the V- voltage:

[0082]

[0083] The same known quantities as above, rearranged to get,

[0084]

[0085] Referring to the example of detecting the voltage between point V1 and point GND, take n=2, so that the voltage value between V2-V1 can be detected. Through the voltage detection function, a protection signal can be generated for the battery's charging overvoltage or discharging overvoltage, thereby increasing the battery's service life;

[0086] After the voltage detection between points V2 and V1 is completed, the process of detecting the voltage between points V3 and V2 is as follows:

[0087] a: Switch S1 is switched to V3, switch S40 and switch S3 are disconnected, switch S10 is closed, V11 = V3, and capacitor C11 is fully charged by V3;

[0088] b: Switch S2 to maintain connection with V2, V22 = V2, and capacitor C21 is fully charged by V2;

[0089] c: After capacitor C21 is fully charged, switch S10 is disconnected;

[0090] d: Switch S2 is disconnected and suspended, and switches S3 and S40 are closed. At this time, two capacitor charging paths are generated. The two capacitor charging paths refer to Fig. 9 ;

[0091] Path 1: V3→S1→V11→S3→V22→C21→C22→GND. At this time, since the initial potential of V22 = V2, the dynamic voltage is the difference between V3 and V2, which is divided by the series capacitors to obtain the V+ voltage:

[0092]

[0093] Path 2: VREF→C12→C11→V11→S1→V3. As above, we can see that the voltage on V- is obtained by dividing the series capacitors:

[0094]

[0095] The same known quantities as above, rearranged to get,

[0096]

[0097] Referring to the example of detecting the voltage between point V1 and point GND, take n=2, so that the voltage value between V3-V2 can be detected. Through the voltage detection function, a protection signal can be generated for the battery's charging overvoltage or discharging overvoltage, thereby increasing the battery's service life;

[0098] The steps for detecting the voltage between points V4 and V3 refer to the steps for detecting the voltage between points V2 and V1. The two battery charging paths generated are as follows: Fig.10 As shown, the difference is that in step d, the switch S2 is connected to V4.

[0099] The steps for detecting the voltage between points V5 and V4 refer to the steps for detecting the voltage between points V3 and V2. The two battery charging paths generated are as follows: Fig.11 As shown, the difference is that in step a, the switch S1 is connected to V5, and in step b, the switch S2 is connected to V4 for a period of time and then disconnected and suspended.

[0100] right Figure 6 When each battery in the Figure 3 The control signals of the switching switches S1, S2, S3, S40, S10 and S6 in the embodiment can be generated by the digital timing logic module to generate different control timing signals to control the on and off of all the above switches. The specific timing diagram and Figure 3 The voltage reference of the relevant nodes in the circuit Fig.12 shown.

[0101] In actual use, the capacitors in the first capacitor voltage-dividing circuit 1 and the second voltage-dividing capacitor circuit and other capacitors in the detection circuit can adopt a MOM capacitor structure. The MOM capacitor utilizes the capacitance formed between the edges of the same layer of Metal (metal), saves area, can be stacked with multiple layers of metal, and the upper and lower plates of the capacitor are interchangeable. For MIM or PIP capacitors, the number of photolithography times is large, which increases the design cost. For capacitors formed by MOS tubes, the upper and lower plates are not interchangeable. When the MOM capacitor is used as a proportional capacitor, it has high matching and precision, and can achieve the purpose of high-precision voltage detection. Therefore, the use of the present invention can reduce losses, save costs, and improve the competitiveness of products.

[0102] In summary, the present invention can compare the voltage of a single battery with a reference voltage through a capacitive voltage divider circuit, thereby improving detection accuracy. Moreover, since there is no need to set a detection resistor and a related fuse structure, the cost of using the chip of the present invention is reduced. In addition, the voltage at both ends of each battery is dynamically detected through timing control, rather than always powering on the resistor for detection, which reduces the loss of the present invention in actual use.

[0103] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A battery voltage detection circuit, characterized in that: It includes a reference voltage, a first capacitor voltage divider circuit, a second capacitor voltage divider circuit, a voltage clamping circuit and a comparator, wherein the reference voltage is input to a first input terminal of the comparator via the first capacitor voltage divider circuit; an electrode of a single battery in a plurality of series-connected batteries is electrically connected to the first capacitor voltage divider circuit, and another electrode of a single battery in a plurality of series-connected batteries is electrically connected to the second capacitor voltage divider circuit; the voltage clamping circuit clamps the voltage at the input terminal of the second capacitor voltage divider circuit to the voltage of the single battery, and the voltage of the single battery is input to the second input terminal of the comparator via the second capacitor voltage divider circuit; It also includes a first switching switch circuit and a second switching switch circuit, wherein the first switching switch circuit includes a plurality of switching channels, and the second switching switch circuit includes a plurality of switching channels; one electrode of a single battery in the plurality of series-connected batteries is electrically connected to the first capacitor voltage divider circuit via a single switching channel in the first switching switch circuit, and another electrode of a single battery in the plurality of series-connected batteries is electrically connected to the second capacitor voltage divider circuit via a single switching channel in the second switching switch circuit; when one switching channel in the first switching switch circuit is turned on, the other switching channels are turned off, and when one switching channel in the second switching switch circuit is turned on, the other switching channels are turned off; The voltage clamping circuit includes a capacitor V_CAP, a switch S3, a switch S10, a switch S11 and a switch S12, the two ends of the capacitor V_CAP are electrically connected to the input end of the first capacitor voltage divider circuit and the input end of the second capacitor voltage divider circuit respectively, the two ends of the switch S3 are electrically connected to the input end of the first capacitor voltage divider circuit and the input end of the second capacitor voltage divider circuit respectively, the first input end of the comparator is grounded through the switch S10, the second input end of the comparator is grounded through the switch S11, one end of the switch S12 is electrically connected to the end of the voltage divider capacitor at the end of the first capacitor voltage divider circuit and the end of the voltage divider capacitor at the end of the second capacitor voltage divider circuit respectively, the other end of the switch S12 is grounded, and the switch 10, the switch S11 and the switch S12 are closed or disconnected at the same time. The first capacitor voltage-dividing circuit comprises a capacitor C11, a capacitor C12 and a switch S40 connected in series in sequence, the connection point between the capacitor C12 and the capacitor C11 is electrically connected to the first input terminal of the comparator, and the connection point between the capacitor C12 and the switch S40 is electrically connected to one end of the switch S12; the reference voltage is input to the input terminal of the switch S40; the second capacitor voltage-dividing circuit comprises a capacitor C21, a capacitor C22 and a switch S41 connected in series in sequence, the end of the switch S41 not electrically connected to the capacitor C22 is grounded, the end of the capacitor C21 and the capacitor C22 is electrically connected to the second input terminal of the comparator, the connection point between the capacitor C22 and the switch S41 is electrically connected to one end of the switch S12, and the switch S40 and the switch S41 are closed or opened at the same time.

2. A battery voltage detection circuit according to claim 1, characterized in that: One electrode of each battery of the multiple batteries connected in series is connected to a switching channel of the first switching switch circuit, and another electrode of each battery of the multiple batteries connected in series is connected to a switching channel of the second switching switch circuit. One switching channel in the first switching switch circuit is electrically connected to only one electrode of the battery, and one switching channel in the second switching switch circuit is electrically connected to only one electrode of the battery.

3. A battery voltage detection circuit according to claim 2, characterized in that: A first switching timing signal is input to the first switching switch circuit, and a second switching timing signal is input to the second switching switch circuit, so that the battery voltage detection circuit first detects the voltage of the single battery with the lowest positive electrode voltage when performing voltage detection, and then detects the voltage at both ends of each battery in the order of increasing positive electrode voltage of the battery.

4. A battery voltage detection circuit according to claim 3, characterized in that: When the voltage of the first detected battery is detected, the fifth timing signal of the first state is first input to the switch S10 and the switch S11 to close the switch S10 and the switch S11, and then the first switching timing signal is input to the first switching switch circuit to connect the positive electrode of the first detected battery to the first capacitor voltage divider circuit, and the second switching timing signal is input to the second switching switch circuit to connect the negative electrode of the first detected battery to the second capacitor voltage divider circuit, so as to realize the charging of the capacitor V_CAP and the capacitor C11. After charging, the second switching timing signal is input to the second switching switch circuit to disconnect the negative electrode of the first detected battery from the second capacitor voltage divider circuit, and the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and then the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41, and the third timing signal of the first state is input to the switch S3 to close the switch S3; When the voltage of the second detected battery is detected, the fourth timing signal of the second state is input to the switch S40 and the switch S41 to disconnect the switch S40 and the switch S41, and the fifth timing signal of the first state is input to the switch S10 and the switch S11 to close the switch S10 and the switch S11, so that the capacitor C11 and the capacitor C21 are charged. After charging, the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and the third timing signal of the second state is input to the switch S3 to disconnect the switch S3, and then the second switching timing signal is input to the second switching switch circuit to connect the positive electrode of the second detected battery to the second capacitor voltage divider circuit, and then the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41; When the voltage of the third detected battery is detected, the first switching timing signal is input to the first switching switch circuit to connect the positive electrode of the third detected battery to the first capacitor voltage divider circuit, and then the fourth timing signal of the second state is input to the switch S40 and the switch S41 to disconnect the switch S40 and the switch S41, and the fifth timing signal of the first state is input to the switch S10 and the switch S11 to close the switch S10 and the switch S11, so that the capacitor C11 is charged. After charging, the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and then the second switching timing signal is input to the second switching switch circuit to disconnect the negative electrode of the third detected battery from the second capacitor voltage divider circuit, the third timing signal of the first state is input to the switch S3 to close the switch S3, and the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41; When the Nth detected battery is detected, N is an even number greater than 2, a fourth timing signal of the second state is input to switch S40 and switch S41 to disconnect switch S40 and switch S41, and a fifth timing signal of the first state is input to switch S10 and switch S11 to close switch S10 and switch S11, so that capacitor C11 and capacitor C21 are charged. After charging, a fifth timing signal of the second state is input to switch S10 and switch S11 to disconnect switch S10 and switch S11, and a third timing signal of the second state is input to switch S3 to disconnect switch S3, and then a second switching timing signal is input to the second switching switch circuit to connect the positive electrode of the Nth detected battery to the second capacitor voltage divider circuit, and then a fourth timing signal of the first state is input to switch S40 and switch S41 to close switch S40 and switch S41; When the battery detected in the Mth section is detected, M is an odd number greater than 3, and the first switching timing signal is input to the first switching switch circuit to connect the positive electrode of the battery detected in the Mth section to the first capacitor voltage divider circuit, and then the fourth timing signal of the second state is input to the switch S40 and the switch S41 to disconnect the switch S40 and the switch S41, and the fifth timing signal of the first state is input to the switch S10 and the switch S11 to close the switch S10 and the switch S11 to charge the capacitor C11. After charging, the fifth timing signal of the second state is input to the switch S10 and the switch S11 to disconnect the switch S10 and the switch S11, and then the second switching timing signal is input to the second switching switch circuit to disconnect the negative electrode of the battery detected in the Mth section from the second capacitor voltage divider circuit, the third timing signal of the first state is input to the switch S3 to close the switch S3, and the fourth timing signal of the first state is input to the switch S40 and the switch S41 to close the switch S40 and the switch S41.

5. A battery voltage detection circuit according to claim 4, characterized in that: It also includes a digital timing logic module, which is configured to generate a first switching timing signal, a second switching timing signal, a third timing signal, a fourth timing signal and a fifth timing signal, wherein the first state is a high level state and the second state is a low level state.

6. A battery voltage detection circuit according to claim 1, characterized in that: The reference voltage includes an over-discharge reference voltage and an over-charge reference voltage. The reference voltage module generates the over-discharge reference voltage and the over-charge reference voltage. The over-discharge reference voltage and the over-charge reference voltage are input into the first capacitor voltage divider circuit through the dual-channel switch S6. In the period T when the reference voltage is input into the comparator, the time when the over-discharge reference voltage is input into the comparator is A*T / C, and the time when the over-charge reference voltage is input into the comparator is B*T / C. A, B and C are all positive numbers, and A+B=C.

7. A battery voltage detection circuit according to claim 6, characterized in that: It also includes a detection module, the output end of the comparator inputs a first detection signal to the detection module, the output end of the comparator inputs a second detection signal to the detection module through an inverter, when the first detection signal is in a first state, the detection module outputs an overcharge protection signal, and when the second detection signal is in the first state, the detection module outputs an over-discharge protection signal.

8. A battery voltage detection circuit according to claim 1, characterized in that: The capacitor in the first capacitor voltage divider circuit and the capacitor in the second capacitor voltage divider circuit are MOM capacitor structures.

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