Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a layer to be etched; forming a core film pattern on the surface of the layer to be etched, wherein the core film pattern exposes a portion of the surface of the layer to be etched; forming a sidewall material layer on the surface of the layer to be etched and the surface of the core film pattern; removing a portion of the sidewall material layer by several modification etching processes until the top surface of the core film pattern and the surface of the layer to be etched are exposed, so as to form a sidewall on the sidewall surface of the core film pattern, wherein the modification etching process includes: modifying the sidewall material layer so that the surface of the sidewall material layer on the surface of the layer to be etched and the top surface of the core film pattern is transformed into a layer to be removed; and removing the layer to be removed by an etching process. Thus, the performance of the semiconductor structure can be improved by the formation method.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the advancement of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and compatible with more functions, many different methods are used in the prior art to reduce the feature size (CD) of semiconductor devices to achieve the purpose of increasing the integration density of semiconductor chips. Among them, the self-aligned multiple patterning technology (SAMP) is widely used in various semiconductor manufacturing technologies. SAMP first forms a mandrel pattern (Mandrel or Core) by photolithography, and then forms a spacer structure on both sides of each mandrel pattern once or multiple times. Finally, the mandrel pattern is removed by a selective etching process. The density of the remaining spacer structure can be several times higher than that of the original mandrel pattern.

[0003] When 193nm deep ultraviolet immersion lithography and the self-aligned multiple patterning technology are used in combination, the spatial half-period of the circuit can be reduced several times. The self-aligned triple patterning technology (SATP) in the self-aligned multiple patterning technology can reduce the circuit half-period to about 13 nanometers, the self-aligned quadruple patterning technology (SAQP) can reduce the circuit half-period to about 10 nanometers, and the self-aligned sextuple patterning technology (SASP) can reduce the circuit half-period to about 7 nanometers.

[0004] Self-aligned multiple patterning technology has achieved a doubling of spatial pattern density. However, due to manufacturing process limitations, the performance of semiconductor structures still needs to be further optimized and improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a layer to be etched; forming a core film pattern on the surface of the layer to be etched, the core film pattern exposing a portion of the surface of the layer to be etched; forming a sidewall material layer on the surface of the layer to be etched and the surface of the core film pattern; using several modification etching treatments to remove a portion of the sidewall material layer until the top surface of the core film pattern and the surface of the layer to be etched are exposed to form a sidewall on the sidewall surface of the core film pattern, the modification etching treatment including: performing modification treatment on the sidewall material layer to transform the surface of the sidewall material layer on the surface of the layer to be etched and the top surface of the core film pattern into a layer to be removed; and using an etching process to remove the layer to be removed.

[0007] Optionally, the etching process for removing the layer to be removed has a first etching speed for the layer to be removed, the etching process for removing the layer to be removed has a second etching speed for the side wall material layer, and the etching process for removing the layer to be removed has a third etching speed for the layer to be etched, the first etching speed is greater than the second etching speed, and the second etching speed is greater than the third etching speed.

[0008] Optionally, the modification process includes an anisotropic plasma treatment process.

[0009] Optionally, the gas used in the anisotropic plasma treatment process includes hydrogen.

[0010] Optionally, the process parameters of the plasma treatment process also include: a pressure range of 2 mTorr to 50 mTorr; a radio frequency power range of 100 W to 1000 W; a bias range of 10 V to 500 V; a hydrogen gas flow range of 100 standard ml / min to 1000 standard ml / min; and a temperature range of 25°C to 200°C.

[0011] Optionally, the etching process for removing the layer to be removed is an atomic layer etching process.

[0012] Optionally, the atomic layer etching process includes a plasma dry etching process, and the reaction gases used in the plasma dry etching process include nitrogen trifluoride gas and hydrogen gas.

[0013] Optionally, the process parameters of the plasma dry etching process also include: a gas flow ratio of the nitrogen trifluoride gas to the hydrogen gas is 2:1; and a gas flow range of the nitrogen trifluoride gas is 10 standard milliliters per minute to 200 standard milliliters per minute.

[0014] Optionally, the process parameters of the plasma dry etching process also include: the carrier gas includes argon and helium, and the gas flow range of argon and helium is 100 standard ml / min to 1000 standard ml / min; the RF power range is 100 watts to 1000 watts; the pressure range is 100 mTorr to 500 mTorr; and the bias voltage is 0 to 10V.

[0015] Optionally, the material of the spacer material layer includes silicon nitride.

[0016] Optionally, the material of the layer to be etched includes silicon oxide.

[0017] Optionally, the material of the core film pattern includes amorphous silicon or amorphous carbon.

[0018] Optionally, the method further includes: before performing the modification etching treatment on the sidewall material layer, forming a protective layer on the sidewall surface of the sidewall material layer.

[0019] Optionally, the method for forming the protective layer includes: forming an initial protective layer on the surface of the layer to be etched and the surface of the core film pattern before performing the modified etching treatment; removing the initial protective layer on the surface of the layer to be etched and the top surface of the core film pattern to form a protective layer.

[0020] Optionally, the material of the protective layer includes silicon oxynitride.

[0021] Optionally, the process of forming the protective layer includes an oxidation process.

[0022] Optionally, the oxidation process includes a plasma treatment process.

[0023] Optionally, the process parameters of the plasma treatment process include: the gas includes oxygen; the gas flow range of oxygen is 50 standard ml / min to 500 standard ml / min; the pressure range is 2 mTorr to 100 mTorr; the RF power range is 100 W to 1500 W; the bias range is 50 V to 500 V; the treatment time range is 5 seconds to 200 seconds; and the temperature range is 25°C to 200°C.

[0024] Optionally, it also includes: after exposing the top surface of the core film pattern and the surface of the layer to be etched to form a side wall on the surface of the side wall of the core film pattern, removing the core film pattern; after removing the core film pattern, etching the layer to be etched using the side wall as a mask.

[0025] Optionally, the layer to be etched includes: a substrate, and a mask material layer located on the substrate; the method for etching the layer to be etched includes: after removing the core film pattern, etching the mask material layer using the side wall as a mask until the surface of the substrate is exposed to form a mask layer; using the mask layer as a mask, etching the substrate to form a base and a plurality of fin structures located on the base.

[0026] Optionally, the layer to be etched includes a first region and a second region, in the first region, adjacent sidewalls have a first spacing therebetween, in the second region, adjacent sidewalls have a second spacing therebetween, and the first spacing is smaller than the second spacing.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] In the method for forming a semiconductor structure provided by the technical solution of the present invention, on the one hand, since the thickness of the layer to be removed is less than the thickness of the sidewall material layer in the direction perpendicular to the surface of the layer to be etched, the process of removing the sidewall material layer on the top surface of the core film pattern and the surface of the layer to be etched can be more accurately controlled by performing several modified etching processes, that is, by forming the layer to be removed with a smaller thickness several times and removing the layer to be removed by using an etching process, so that in the process of removing the sidewall material layer on the top surface of the core film pattern and the surface of the layer to be etched to form the sidewall, the time required for removing the sidewall material layer on the layer to be etched can be reduced. damage, so that after the core film pattern is subsequently removed, the surface flatness of the layer to be etched is better, so that when the layer to be etched is subsequently etched using the side wall as a mask, the accuracy of the pattern transferred to the layer to be etched can be improved, so as to improve the performance of the semiconductor structure; on the other hand, since the side wall material layer is modified to form the layer to be removed, and an etching process is used for the layer to be removed to form the side wall, therefore, when the side wall material layer on the top surface of the core film pattern and the surface of the layer to be etched is removed, the influence of the removal process on the side wall material layer on the side wall surface of the core film pattern can be reduced, thereby improving the pattern accuracy of the side wall, so as to improve the performance of the semiconductor structure.

[0029] Furthermore, since a protective layer is formed on the side wall surface of the side wall material layer before the side wall material layer is modified, the side wall surface of the side wall material layer can be protected by the protective layer, thereby better reducing the impact of the modification treatment on the side wall surface of the side wall material layer, thereby improving the graphic accuracy of the subsequently formed side wall and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 5 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure;

[0031] Figures 6 to 13 It is a schematic cross-sectional structure diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, the performance of the semiconductor structure is relatively poor. Now, an analysis and description will be given in conjunction with a specific embodiment.

[0033] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0034] Figures 1 to 5 The invention is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure.

[0035] Please refer to Figure 1 , providing a substrate 10; forming a mask material layer 20 on the surface of the substrate 10, wherein the mask material layer 20 is a single-layer or multi-layer stacked structure; forming a core film pattern 30 on the surface of the mask material layer 20, wherein the core film pattern 30 exposes a portion of the surface of the mask material layer 20; forming a sidewall material layer 40 on the surface of the mask material layer 20 and the surface of the core film pattern 30.

[0036] The process of forming the spacer material layer 40 includes a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal treatment process, and the like.

[0037] Please refer to Figure 2 , the sidewall material layer 40 is etched to form a sidewall 41 .

[0038] The method for forming the sidewall 41 includes: using an anisotropic etching process to etch the sidewall material layer 40 on the surface of the mask material layer 20 and the top surface of the core film pattern 30 until the top surface of the core film pattern 30 and the surface of the mask material layer 20 are exposed.

[0039] Please refer to Figure 3 After forming the sidewall 41 , the core film pattern 30 is removed.

[0040] Please refer to Figure 4 After removing the core film pattern 30 , the sidewall 41 and the exposed portion of the mask material layer 20 are etched until the surface of the substrate 10 is exposed to form a mask layer 21 , which is a hard mask.

[0041] Please refer to Figure 5 After forming the mask layer 21 , the exposed surface of the substrate 10 is etched to a preset depth using the mask layer 21 as a mask, so as to transfer the pattern of the sidewall 41 to the substrate 10 .

[0042] In the above method, by controlling the deposition process parameters, the thickness of the formed sidewall material layer 40 can be controlled to form a thinner sidewall material layer 40, thereby forming a sidewall 41 with a smaller critical dimension. Therefore, after the pattern of the sidewall 41 is subsequently transferred to the substrate 10, a pattern with a smaller critical dimension can be formed to meet the requirements of smaller and smaller semiconductor structure sizes.

[0043] However, in the process of etching the sidewall material layer 40, on the one hand, the etching selectivity between the sidewall material layer 40 and the mask material layer 20 is relatively small; on the other hand, due to the uneven plasma distribution caused by the dense pattern area and the sparse pattern area, in the process of forming the sidewall 41, after the sidewall material layer 40 on the surface of the mask material layer 20 is etched, the exposed mask material layer 20 (especially the sparse pattern area) is easily etched further, resulting in over-etching and damage of part of the mask material layer 20. Therefore, on the one hand, the surface of the mask material layer 20 at the bottom of the core film pattern 30 and the surface of the mask material layer 20 at the bottom of the non-core film pattern 30 have different height differences and uneven morphology; on the other hand, the pattern transferred to the substrate 10 has different sizes, poor uniformity, and poor morphology of the sidewall surface. In summary, the performance of the formed semiconductor structure is poor, resulting in poor performance of the semiconductor device. .

[0044] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure. When forming a side wall, the side wall material layer on the top surface of the core film pattern and the surface of the layer to be etched is more accurately removed by adopting several modified etching treatments, thereby improving the performance of the semiconductor structure.

[0045] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Figures 6 to 13 It is a schematic cross-sectional structure diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0047] Please refer to Figure 6 , providing a layer to be etched.

[0048] In this embodiment, the layer to be etched includes: a substrate 100 and a mask material layer 110 located on the substrate 100 .

[0049] The substrate 100 is made of semiconductor material.

[0050] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0051] In this embodiment, the mask material layer 110 is a composite mask material layer, and the mask material layer 110 includes a first mask material layer 111 located on the substrate 100 , and a second mask material layer 112 located on the surface of the first mask material layer 111 .

[0052] The first mask material layer 111 provides material for subsequently forming a first mask layer.

[0053] In this embodiment, the material of the first mask material layer 111 includes silicon nitride.

[0054] In this embodiment, the material of the second mask material layer 112 includes silicon oxide.

[0055] On the one hand, the second mask material layer 112 is used to protect the first mask material layer 111, reduce the impact of the first mask material layer 111 in the subsequent etching and modification process of forming the sidewall, thereby improving the morphology of the second mask layer and the small-size pattern formed subsequently, so as to improve the transfer pattern accuracy of the semiconductor structure. On the other hand, the second mask material layer 112 is used as an etching stop layer in the subsequent etching process of forming the sidewall to achieve the formation of the sidewall. In addition, since the second mask material layer 112 has good fluidity and filling properties, it can also repair the surface of the first mask material layer 111, improve the interface state of the first mask material layer 111, and the flatness of the entire mask material layer 110, thereby improving the morphology of the subsequently formed structure, and then improving the performance of the semiconductor device.

[0056] In another embodiment, the mask material layer is a single material layer, and the material of the mask material layer includes silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride.

[0057] In this embodiment, the layer to be etched further includes a dielectric layer (not shown) located between the substrate 100 and the mask material layer 110 .

[0058] On the one hand, the dielectric layer is used to protect the substrate 100 and reduce the influence of the etching process of forming the mask layer on the substrate 110 when the mask layer is subsequently formed. On the other hand, the dielectric layer is used to repair the surface of the substrate 100, thereby improving the interface state of the substrate 100 and the flatness of the entire substrate 100.

[0059] In this embodiment, the layer to be etched further includes a first region I and a second region II.

[0060] Please refer to Figure 7 A core film pattern 200 is formed on the surface of the layer to be etched, and the core film pattern 200 exposes a portion of the surface of the layer to be etched.

[0061] Specifically, in this embodiment, forming the core film pattern 200 on the surface of the layer to be etched means forming the core film pattern 200 on the surface of the second mask material layer 112 , and the core film pattern 200 exposes a portion of the surface of the second mask material layer 112 .

[0062] In this embodiment, the method for forming the core film pattern 200 includes: forming a core film pattern material layer (not shown) on the surface of the second mask material layer 112; forming a first patterned layer on the surface of the core film pattern material layer, the first patterned layer exposing a portion of the surface of the second mask material layer 112; using the first patterned layer as a mask, etching the core film pattern material layer until the surface of the second mask material layer 112 is exposed to form the core film pattern 200.

[0063] The process of forming the core film pattern material layer includes a deposition process.

[0064] In this embodiment, the process of forming the core film pattern material layer includes a chemical vapor deposition process.

[0065] The process of etching the core film pattern material layer includes a dry etching process.

[0066] In this embodiment, the process of etching the core film pattern material layer includes a plasma gas etching process.

[0067] In this embodiment, after forming the core film pattern 200, the first patterned layer is removed. The process of removing the first patterned layer includes an ashing process.

[0068] In this embodiment, the spacing between the sidewall surfaces of the core film pattern 200 in the first region I is smaller than the spacing between the sidewall surfaces of the core film pattern 200 in the second region II.

[0069] In another embodiment, a spacing between sidewall surfaces of the core film pattern in the first region is equal to a spacing between sidewall surfaces of the core film pattern in the second region.

[0070] In this embodiment, the material of the core film pattern includes amorphous silicon or amorphous carbon.

[0071] Please refer to Figure 8 A spacer material layer 300 is formed on the surface of the layer to be etched and the surface of the core film pattern 200 .

[0072] The spacer material layer 300 is used to provide material for the subsequent formation of spacers.

[0073] In this embodiment, the material of the spacer material layer 300 includes silicon nitride.

[0074] The process of forming the spacer material layer 300 includes a deposition process.

[0075] In this embodiment, the process of forming the spacer material layer 300 includes an atomic layer deposition process.

[0076] In another embodiment, the process of forming the spacer material layer 300 includes a chemical vapor deposition process.

[0077] In this embodiment, before the spacer material layer 300 is subsequently subjected to a modification etching process, a protection layer 400 is formed on the sidewall surface of the spacer material layer 300 .

[0078] Since a protective layer 400 is formed on the side wall surface of the side wall material layer 300 before the side wall material layer 300 is modified, the side wall surface of the side wall material layer 300 can be protected by the protective layer 400, and the influence of the modification treatment on the side wall surface of the side wall material layer 300 can be better reduced, thereby improving the graphic accuracy of the subsequently formed side wall and improving the performance of the semiconductor structure.

[0079] In another embodiment, the protective layer is not formed.

[0080] The method for forming the protective layer 400 includes: before performing the modified etching treatment, forming an initial protective layer (not shown) on the surface of the layer to be etched and the surface of the core film pattern 200; removing the initial protective layer from the surface of the layer to be etched, the top surface of the core film pattern 200, and the surface of the second mask material layer 112 not covered by the core film pattern 200 to form a protective layer 400.

[0081] In this embodiment, the process for forming the initial protective layer includes an oxidation process, the oxidation process includes a plasma treatment process, and the process parameters of the plasma treatment process include: the gas includes oxygen; the gas flow range of oxygen is 50 standard ml / min to 500 standard ml / min; the pressure range is 2 mTorr to 100 mTorr; the RF power range is 100 W to 1500 W; the bias range is 50 V to 500 V; the processing time range is 5 seconds to 200 seconds; and the temperature range is 25°C to 200°C.

[0082] By controlling the process parameters of the plasma treatment process, that is, making the process parameters of the plasma treatment process within the above-mentioned appropriate range, a thinner initial protective layer can be formed, which is conducive to the subsequent formation of a thinner protective layer 400. Since the initial protective layer is thin, it is conducive to reducing the subsequent process time of removing the initial protective layer on the surface of the layer to be etched and the top surface of the core film pattern 200.

[0083] In other embodiments, the process of forming the initial protection layer includes a deposition process, which includes an atomic layer deposition process or a chemical vapor deposition process.

[0084] In this embodiment, the method for removing the initial protective layer on the surface of the layer to be etched and the top surface of the core film pattern 200 includes: before performing a modification etching treatment on the side wall material layer 300, using the modification etching process to etch the initial protective layer on the surface of the layer to be etched and the top surface of the core film pattern 200 until the surface of the layer to be etched and the top surface of the core film pattern 200 are exposed.

[0085] In other embodiments, the method for removing the initial protective layer on the surface of the layer to be etched and the top surface of the core film pattern includes: using an anisotropic dry etching process to etch back the initial protective layer until the surface of the layer to be etched and the top surface of the core film pattern. Wherein, the anisotropic dry etching process includes: a dry etching process in which a bias voltage perpendicular to the substrate direction is applied in the etching chamber.

[0086] In this embodiment, the material of the protection layer 400 includes silicon oxynitride.

[0087] Subsequently, a portion of the sidewall material layer 300 is removed by several modification etching processes until the top surface of the core film pattern 200 and the surface of the layer to be etched are exposed, so as to form a sidewall on the sidewall surface of the core film pattern 200. For the specific process of performing the modification etching process, please refer to Fig. 9 and Fig.10 .

[0088] Please refer to Fig. 9, the sidewall material layer 300 is modified so that the surface of the sidewall material layer 300 on the surface of the layer to be etched and the top surface of the core film pattern 200 is transformed into a layer to be removed 310 .

[0089] The modification process includes an anisotropic plasma treatment process.

[0090] The gas used in the anisotropic plasma treatment includes hydrogen.

[0091] Specifically, in this embodiment, the process parameters of the anisotropic plasma treatment process include: a pressure range of 2 mTorr to 50 mTorr; a RF power range of 100 W to 1000 W; a bias range of 10 V to 500 V; a hydrogen gas flow range of 100 standard ml / min to 1000 standard ml / min; and a temperature range of 25°C to 200°C.

[0092] Through the modification treatment, the surface portion of the sidewall material layer 300 on the top surface of the core film pattern 200 and the surface of the layer to be etched can react with the gas used in the plasma treatment, thereby converting the surface portion of the sidewall material layer 300 that reacts with the used gas into the layer to be removed 310.

[0093] On the one hand, since the modification process is an anisotropic plasma treatment process, through the plasma treatment process, it is possible to convert the surface portion of the sidewall material layer 300 on the top surface of the core film pattern 200 and the surface of the layer to be etched into the layer to be removed 310 while reducing the impact on the sidewall material layer 300 on the side wall surface of the core film pattern 200, thereby subsequently being able to form a sidewall with better morphology and higher graphic accuracy.

[0094] On the other hand, if the thickness of the layer to be removed 310 is too thin, the process time for forming the sidewall will be too long; if the thickness of the layer to be removed 310 is too thick, it will be difficult to control the etching speed in the modification etching process, thereby reducing the etching accuracy in the modification etching process and reducing the damage to the layer to be etched by the etching process in the modification etching process. Therefore, by controlling the process of the modification treatment, that is, making the process parameters of the plasma treatment process within the above-mentioned appropriate range, a layer to be removed 310 with a moderate thickness can be formed, so that the process time for forming the sidewall is appropriate, and the control of the etching speed in the modification etching process is enhanced, thereby improving the etching accuracy in the modification etching process and reducing the damage to the layer to be etched by the etching process in the modification etching process.

[0095] Please refer to Fig.10 , an etching process is used to remove the layer to be removed 310.

[0096] In this embodiment, the etching process for removing the layer to be removed 310 has a first etching speed for the layer to be removed 310, the etching process for removing the layer to be removed 310 has a second etching speed for the side wall material layer 300, and the etching process for removing the layer to be removed 310 has a third etching speed for the layer to be etched, the first etching speed is greater than the second etching speed, and the second etching speed is greater than the third etching speed.

[0097] Thus, through the etching process, the etching accuracy can be improved while removing the layer to be removed 310, reducing the damage caused by the etching process to the sidewall material layer 300 and the damage caused by the etching process to the layer to be etched, thereby reducing over-etching when removing the sidewall material layer 300 on the top surface of the core film pattern 200 and the surface of the layer to be etched, thereby improving the accuracy of the graphics subsequently transferred to the layer to be etched.

[0098] Moreover, since the spacing between the side wall surfaces of the core film pattern 200 in the first zone I is smaller than the spacing between the side wall surfaces of the core film pattern 200 in the second zone II, that is, the depth-to-width ratio between the side wall surfaces of the side wall material layer 300 on the first zone I is larger, and the depth-to-width ratio between the side wall surfaces of the side wall material layer 300 on the second zone II is smaller, the side wall material layer 300 on the surface of the layer to be etched in the first zone I is more difficult to etch, while the side wall material layer 300 on the surface of the layer to be etched in the second zone II is easily etched. Therefore, in order to form a side wall on the first zone I, while etching the side wall material layer 300 in the first zone I, it is easy to cause over-etching of the layer to be etched in the second zone II. Since the etching accuracy of the sidewall material layer 300 can be improved through the modified etching treatment, when the sidewall is formed in the first area I, the over-etching of the layer to be etched in the second area II caused by the etching process can be reduced. Therefore, when the sidewall with a small spacing between the sidewall surfaces is formed in the first area I and the sidewall with a large spacing between the sidewall surfaces is formed in the second area II, it is beneficial to form a sidewall with a good morphology and improve the accuracy of the pattern transferred to the layer to be etched.

[0099] Specifically, in this embodiment, the etching process for removing the layer to be removed 310 has a third etching rate for the layer to be etched, which means that the etching process for removing the layer to be removed 310 has a third etching rate for the second mask material layer 112 .

[0100] In this embodiment, the etching process for removing the layer to be removed 310 is an atomic layer etching process.

[0101] The to-be-removed layer 310 can be etched at the atomic level through the atomic layer etching process, that is, the to-be-removed layer 310 can be accurately removed through the atomic layer etching process.

[0102] Specifically, in this embodiment, the atomic layer etching process includes a plasma dry etching process, and the reaction gases used in the plasma dry etching process include nitrogen trifluoride gas and hydrogen gas.

[0103] The nitrogen trifluoride gas and hydrogen can react quickly with the modified layer 310 to be removed to remove the layer 310. At the same time, the nitrogen trifluoride gas and hydrogen react slowly with the side wall material layer 300 that has not been modified, which can reduce the damage caused by the atomic layer etching process to the side wall material layer 300, so as to better control the etching accuracy of the etching process for removing the layer 310 to be removed.

[0104] In this embodiment, the process parameters of the plasma dry etching process also include: the gas flow ratio of the nitrogen trifluoride gas and the hydrogen gas is 2:1; the gas flow range of the nitrogen trifluoride gas is 10 standard ml / min to 200 standard ml / min.

[0105] In this embodiment, the process parameters of the plasma dry etching process also include: the carrier gas includes argon and helium, and the gas flow range of argon and helium is 100 standard ml / min to 1000 standard ml / min; the RF power range is 100 watts to 1000 watts; the pressure range is 100 mTorr to 500 mTorr; and the bias voltage is 0 to 10V.

[0106] The significance of selecting the RF power range is that: if the RF power is less than 100 watts, the etching reaction rate is too low, which is not conducive to improving the production rate; if the RF power is greater than 1000 watts, it is not conducive to controlling the etching reaction rate, and the ion penetration depth is large, which easily causes excessive loss of the side wall material layer 300 that has not undergone the modified treatment, resulting in subsequent increased damage to the surface to be etched, and ultimately reducing the accuracy of the characteristic size of the pattern transferred to the layer to be etched.

[0107] In summary, on the one hand, since the thickness of the layer to be removed 310 is less than the thickness of the sidewall material layer 300 in the direction perpendicular to the surface of the layer to be etched, the process of removing the top surface of the core film pattern 200 and the sidewall material layer 300 on the surface of the layer to be etched can be more accurately controlled through several times of modified etching treatment, that is, by forming the layer to be removed 310 with a smaller thickness several times and removing the layer to be removed 310 by etching process, so that in the process of removing the sidewall material layer 300 on the top surface of the core film pattern 200 and the surface of the layer to be etched to form the sidewall, the damage to the layer to be etched caused by the process of removing the sidewall material layer 300 can be reduced, thereby After the core film pattern is subsequently removed, the surface flatness of the layer to be etched is better, so that when the layer to be etched is subsequently etched using the side wall as a mask, the accuracy of the pattern transferred to the layer to be etched can be improved, thereby improving the performance of the semiconductor structure; on the other hand, since the side wall material layer 300 is modified to form the layer to be removed 310, and an etching process is used for the layer to be removed to form the side wall, therefore, when the side wall material layer 300 on the top surface of the core film pattern 200 and the surface of the layer to be etched is removed, the effect of the removal process on the side wall material layer 300 on the side wall surface of the core film pattern 200 can be reduced, thereby improving the pattern accuracy of the side wall, thereby improving the performance of the semiconductor structure.

[0108] Please refer to Fig.11 , using several times of the modified etching treatment (such as Fig. 9 and Fig.10 As shown in the figure, a portion of the spacer material layer 300 is removed until the top surface of the core film pattern 200 and the surface of the layer to be etched are exposed, so as to form a spacer 320 on the side wall surface of the core film pattern 200.

[0109] In this embodiment, in the first region I, adjacent sidewalls 320 have a first spacing A, and in the second region II, adjacent sidewalls 320 have a second spacing B. Since the spacing between the sidewall surfaces of the core film pattern 200 in the first region I is smaller than the spacing between the sidewall surfaces of the core film pattern 200 in the second region II, the first spacing A is smaller than the second spacing B.

[0110] In another embodiment, since the spacing between the sidewall surfaces of the core film pattern in the first region is equal to the spacing between the sidewall surfaces of the core film pattern in the second region, the first spacing is equal to the second spacing.

[0111] In this embodiment, after the sidewall spacer 320 is formed, the core film pattern 200 is removed.

[0112] After removing the core film pattern 200, the layer to be etched is etched using the sidewall 320 as a mask. For details on the process of etching the layer to be etched, please refer to Figure 12 to Figure 13.

[0113] Please refer to Fig.12 After removing the core film pattern 200 , the mask material layer 110 is etched using the sidewall 320 as a mask until the surface of the substrate 100 is exposed to form a mask layer 120 .

[0114] In this embodiment, before etching the mask material layer 110 using the sidewall spacer 320 as a mask, the protection layer 400 is not removed.

[0115] Specifically, in this embodiment, the mask material layer 110 is etched using the side wall 320 as a mask to form the mask layer 120, including: using a first etching process to etch the second mask material layer 112 until the first mask material layer 111 is exposed to form a second mask layer 122; after forming the second mask layer 122, using a second etching process to etch the first mask material layer 111 until the surface of the substrate 100 is exposed to form the first mask layer 121.

[0116] In this embodiment, the first mask layer 121 and the second mask layer 122 constitute the mask layer 120. The mask layer 120 can increase the stability of pattern transfer during the process of transferring the pattern to the substrate 100.

[0117] In this embodiment, the first etching process includes a dry etching process.

[0118] In this embodiment, the second etching process includes a dry etching process.

[0119] Please refer to Fig.13 , using the mask layer 120 as a mask, etching the substrate 100 to form a base 101 and a plurality of fin structures 102 located on the base 101 .

[0120] In this embodiment, the process of etching the substrate 100 includes a dry etching process.

[0121] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a layer to be etched; forming a core film pattern on the surface of the layer to be etched, wherein the core film pattern exposes a portion of the surface of the layer to be etched; forming a spacer material layer on the surface of the layer to be etched and the surface of the core film pattern; A portion of the sidewall material layer is removed by performing several modification etching processes until the top surface of the core film pattern and the surface of the layer to be etched are exposed, so as to form a sidewall on the sidewall surface of the core film pattern. The modification etching process includes: Performing modification treatment on the sidewall material layer so that the surface of the sidewall material layer on the surface of the layer to be etched and the top surface of the core film pattern is transformed into a layer to be removed; Removing the layer to be removed by an etching process; Before performing the modification etching process on the sidewall material layer, forming a protective layer on the sidewall surface of the sidewall material layer; After exposing the top surface of the core film pattern and the surface of the layer to be etched to form a side wall on the surface of the side wall of the core film pattern, the core film pattern is removed; after removing the core film pattern, the layer to be etched is etched using the side wall and the protective layer as a mask.

2. The method for forming a semiconductor structure according to claim 1, wherein: The etching process for removing the layer to be removed has a first etching speed for the layer to be removed, the etching process for removing the layer to be removed has a second etching speed for the sidewall material layer, and the etching process for removing the layer to be removed has a third etching speed for the layer to be etched, the first etching speed is greater than the second etching speed, and the second etching speed is greater than the third etching speed.

3. The method for forming a semiconductor structure according to claim 1, wherein: The modification process includes an anisotropic plasma treatment process.

4. The method for forming a semiconductor structure according to claim 3, wherein: The gas used in the anisotropic plasma treatment process includes hydrogen.

5. The method for forming a semiconductor structure according to claim 4, wherein: The process parameters of the plasma treatment process also include: a pressure range of 2 mTorr to 50 mTorr; a radio frequency power range of 100 W to 1000 W; a bias range of 10 V to 500 V; a hydrogen gas flow range of 100 standard ml / min to 1000 standard ml / min; and a temperature range of 25°C to 200°C.

6. The method for forming a semiconductor structure according to claim 4, wherein: The etching process for removing the layer to be removed is an atomic layer etching process.

7. The method for forming a semiconductor structure according to claim 6, wherein: The atomic layer etching process includes a plasma dry etching process, and the reaction gases used in the plasma dry etching process include nitrogen trifluoride gas and hydrogen gas.

8. The method for forming a semiconductor structure according to claim 7, wherein: The process parameters of the plasma dry etching process also include: the gas flow ratio of the nitrogen trifluoride gas to the hydrogen gas is 2:1; the gas flow range of the nitrogen trifluoride gas is 10 standard milliliters per minute to 200 standard milliliters per minute.

9. The method for forming a semiconductor structure according to claim 8, wherein: The process parameters of the plasma dry etching process also include: the carrier gas includes argon and helium, and the gas flow range of argon and helium is 100 standard ml / min to 1000 standard ml / min; the RF power range is 100 watts to 1000 watts; the pressure range is 100 mTorr to 500 mTorr; and the bias voltage is 0 to 10V.

10. The method for forming a semiconductor structure according to claim 9, wherein: The material of the spacer material layer includes silicon nitride.

11. The method for forming a semiconductor structure according to claim 9, wherein: The material of the layer to be etched includes silicon oxide.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the core film pattern includes amorphous silicon or amorphous carbon.

13. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the protective layer includes: forming an initial protective layer on the surface of the layer to be etched and the surface of the core film pattern before performing the modified etching treatment; removing the initial protective layer on the surface of the layer to be etched and the top surface of the core film pattern to form a protective layer.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the protection layer includes silicon oxynitride.

15. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the protection layer includes an oxidation process.

16. The method for forming a semiconductor structure according to claim 15, wherein: The oxidation process includes a plasma treatment process.

17. The method for forming a semiconductor structure according to claim 16, wherein: The process parameters of the plasma treatment process include: the gas includes oxygen; the gas flow range of oxygen is 50 standard ml / min to 500 standard ml / min; the pressure range is 2 mTorr to 100 mTorr; the RF power range is 100 W to 1500 W; the bias range is 50 V to 500 V; the treatment time range is 5 seconds to 200 seconds; and the temperature range is 25°C to 200°C.

18. The method for forming a semiconductor structure according to claim 1, wherein: The layer to be etched includes: a substrate, and a mask material layer located on the substrate; the method for etching the layer to be etched includes: after removing the core film pattern, etching the mask material layer using the side wall as a mask until the surface of the substrate is exposed to form a mask layer; using the mask layer as a mask, etching the substrate to form a base and a plurality of fin structures located on the base.

19. The method for forming a semiconductor structure according to claim 1, wherein: The layer to be etched includes a first area and a second area. In the first area, adjacent sidewalls have a first spacing, and in the second area, adjacent sidewalls have a second spacing. Furthermore, the first spacing is smaller than the second spacing.

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