Method for forming a semiconductor structure

Abstract

The present invention discloses a method for forming a semiconductor structure, comprising: injecting doping ions into a second initial top mask layer to form a doping region in the second initial top mask layer; etching and removing the second initial top mask layer except the doping region, and forming the second top mask layer in the doping region; etching the second initial bottom mask layer with the second top mask layer as a mask to form the second initial bottom mask layer; after reducing the width of the second bottom mask layer and the second top mask layer, etching the first initial mask structure with the second bottom mask layer and the second top mask layer as masks to form the first initial mask structure into a first mask structure. By adopting the above scheme, the line width size of the pattern of the first mask structure is reduced. The first mask structure is used as a mask for etching the substrate, so that the size of the pattern formed in the substrate is reduced to meet the process requirements. As a result, the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In order to comply with the development of Morgan's Law, semiconductor devices have developed to a 7-nanometer process node. Among the semiconductor devices with smaller device sizes, taking Fin Field-Effect Transistor (FinFET) as an example, 57-nanometer contacted poly pitch (CPP) and 0.027 square micron high-density static random-access memory (SRAM) have become the most popular and widely used.

[0003] The formation of the mask structure is the most difficult part in the semiconductor manufacturing process. Although the prior art uses immersion multi-patterning lithography technology, the size of some mask patterns still cannot meet the standard, especially the mask pattern with a width of 30 nanometers of the graphical structure of the mask structure.

[0004] If lithography technology does not develop further, the minimum width of the patterned structure of the mask structure formed by the current immersion multi-patterning lithography technology is 40 nanometers. Even after subsequent etching, the final width can only be as small as 38 nanometers, which is still far from our target size. If the width of the patterned structure of the mask structure exceeds 30 nanometers, the semiconductor device cannot be reduced as targeted, and the size of the semiconductor device is large, which will affect the performance and market share of the semiconductor device. Summary of the invention

[0005] The purpose of the present invention is to solve the problem of poor performance of semiconductor devices caused by the wide width of the patterned structure of the mask structure in the prior art. The present invention provides a method for forming a mask pattern, which can reduce the line width of the pattern of the mask structure, thereby reducing the size of the pattern formed in the substrate, thereby improving the performance of the semiconductor device.

[0006] In order to solve the above technical problems, an embodiment of the present invention discloses a method for forming a semiconductor structure, comprising:

[0007] providing a substrate;

[0008] forming a first initial mask structure and a second initial mask structure located on the first initial mask structure on the substrate, wherein the second initial mask structure comprises a second initial bottom mask layer and a second initial top mask layer located on the second initial bottom mask layer;

[0009] Implanting doping ions into a partial region of the second initial top mask layer to form a doping region in the second initial top mask layer;

[0010] Etching away the second initial top mask layer except the doped region, and making the doped region form a second top mask layer;

[0011] Using the second top mask layer as a mask, etching the second initial bottom mask layer, so that the second initial bottom mask layer forms a second bottom mask layer;

[0012] reducing the width of the second bottom mask layer and the second top mask layer;

[0013] After reducing the widths of the second bottom mask layer and the second top mask layer, the first initial mask structure is etched using the second bottom mask layer and the second top mask layer as masks, so that the first initial mask structure forms a first mask structure.

[0014] Optionally, the material of the second initial bottom mask layer includes silicon oxide, and the material of the second initial top mask layer includes an amorphous silicon layer.

[0015] Optionally, the first initial mask structure includes a first initial bottom mask layer and a first initial top mask layer located on the first initial bottom mask layer; a material of the first initial top mask layer is different from a material of the second initial bottom mask layer.

[0016] Optionally, the first initial bottom mask layer and the second initial bottom mask layer are made of the same material; and the second initial top mask layer and the first initial top mask layer are made of the same material.

[0017] Optionally, the method of etching the first initial mask structure using the second bottom mask layer and the second top mask layer as masks includes: etching the first initial top mask layer using the second bottom mask layer and the second top mask layer as masks so that the first initial top mask layer forms the first top mask layer; etching and removing the first initial bottom mask layer on the side of the first top mask layer so that the first initial bottom mask layer forms the first bottom mask layer.

[0018] Optionally, the process of reducing the width of the second bottom mask layer and the second top mask layer is a lateral etching process.

[0019] Optionally, the lateral etching process includes an isotropic wet etching process or an isotropic dry etching process.

[0020] Optionally, the method of injecting the doping ions into the second initial top mask layer includes: forming a patterned structure on the second initial top mask layer; injecting the doping ions into the second initial top mask layer using the patterned structure as a mask; and after injecting the doping ions into the second initial top mask layer, removing the patterned structure.

[0021] Optionally, the doping region includes a first doping region to an Nth doping region, and the first doping region to the Nth doping region are separated from each other;

[0022] The second initial top mask layer is implanted with the doping ions by using multiple ion implantation processes to form the doping region.

[0023] Optionally, the substrate includes: a substrate; a plurality of gate structures located on the substrate; source and drain regions located on both sides of the gate structures; a dielectric layer located on the substrate and covering the gate structures and the source and drain regions; the first mask structure covers a portion of the dielectric layer on the source and drain regions;

[0024] The method for forming the semiconductor structure further includes: after forming the first mask structure, forming a plug trench in the dielectric layer between the gate structures, the plug trench exposing a portion of the source and drain regions, and the plug trench being divided by the first mask structure in an extension direction of the gate structure.

[0025] By adopting the above technical solution, the pattern of the second top mask layer formed by the doped region is transferred to the second bottom mask layer, and then the width of the second bottom mask layer and the second top mask layer is reduced, so that when the pattern is further transferred to the first mask structure, the line width of the pattern of the first mask structure is reduced. The first mask structure is used as a mask for etching the substrate, so that the size of the pattern formed in the substrate is reduced to meet the process requirements. As a result, the performance of the semiconductor structure is also improved accordingly. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 to Figure 2 It is a schematic diagram of a process of forming a semiconductor structure in the prior art;

[0027] Figure 3 to Figure 4 This is a scanning electron microscope image of an existing semiconductor structure;

[0028] Figure 5 is a schematic flow chart of a method for forming a semiconductor structure provided by an embodiment of the present invention;

[0029] Figures 6 to 11 is a schematic diagram of a structure formed by each step of a method for forming a semiconductor structure provided by an embodiment of the present invention;

[0030] Fig.12is a scanning electron microscope image of a semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following specific embodiments illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Although the description of the present invention will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to this implementation. On the contrary, the purpose of introducing the invention in conjunction with the implementation is to cover other options or modifications that may extend based on the claims of the present invention. In order to provide a deep understanding of the present invention, the following description will include many specific details. The present invention can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present invention, some specific details will be omitted in the description. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0032] It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0033] In the description of this embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0034] The terms “first”, “second”, etc. are only used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0035] In the description of this embodiment, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this embodiment can be understood according to specific circumstances.

[0036] As described in the background art, in the prior art, the width of the patterned structure of the mask structure is relatively wide, which will cause the semiconductor device to be larger in size and have poor performance. Figure 1 to Figure 2 shown.

[0037] First, refer to Figure 1 , providing a substrate 01, forming an initial mask layer 02 on the substrate 01, and forming a patterned structure 03 on the initial mask layer 02.

[0038] Continue to refer Figure 1 , doping ions are implanted into the initial mask layer 02 using the patterned structure 03 as a mask to form a doping region 04 in the initial mask layer 02 .

[0039] refer to Figure 2 , remove the patterned structure 03, etch and remove the initial mask layer 02 outside the doped region 04, and form the mask structure 05 in the doped region 04.

[0040] The scanning electron microscope image of the semiconductor structure formed by the above process in the cross-sectional direction is as follows: Figure 3 The SEM image in the top view is shown in Figure 4 As shown, it can be seen that the pattern line width size of the mask structure formed in the prior art is relatively large, which will make the size of the pattern formed in the substrate also relatively large, further affecting the performance of the semiconductor device.

[0041] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure. Figure 5 The schematic diagram of the process of forming a semiconductor structure shown in FIG. 1 is a schematic diagram of the process of forming a semiconductor structure. The method of forming a semiconductor structure provided in this embodiment includes the following steps:

[0042] Step S1: providing a substrate;

[0043] Step S2: forming a first initial mask structure and a second initial mask structure located on the first initial mask structure on the substrate, wherein the second initial mask structure comprises a second initial bottom mask layer and a second initial top mask layer located on the second initial bottom mask layer;

[0044] Step S3: injecting doping ions into a partial area of ​​the second initial top mask layer to form a doping region in the second initial top mask layer;

[0045] Step S4: etching and removing the second initial top mask layer outside the doped region, and forming the second top mask layer in the doped region;

[0046] Step S5: etching the second initial bottom mask layer using the second top mask layer as a mask, so that the second initial bottom mask layer forms a second bottom mask layer;

[0047] Step S6: reducing the width of the second bottom mask layer and the second top mask layer;

[0048] Step S7: after reducing the widths of the second bottom mask layer and the second top mask layer, etching the first initial mask structure using the second bottom mask layer and the second top mask layer as masks to form the first initial mask structure into a first mask structure.

[0049] In the semiconductor structure formed by the above scheme, the line width of the pattern of the first mask structure is reduced. The first mask structure is used as a mask for etching the substrate, so that the size of the pattern formed in the substrate is reduced to meet the process requirements. As a result, the performance of the semiconductor structure is also improved accordingly.

[0050] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0051] First, if Figure 6 As shown, a substrate 1 is provided.

[0052] Continue to refer Figure 6 A first initial mask structure 2 and a second initial mask structure 3 located on the first initial mask structure 2 are formed on the substrate 1 , and the second initial mask structure 3 includes a second initial bottom mask layer 31 and a second initial top mask layer 32 located on the second initial bottom mask layer 31 .

[0053] Preferably, in this embodiment, the second initial bottom mask layer 31 and the second initial top mask layer 32 are made of different materials, wherein the material of the second initial bottom mask layer 31 includes silicon oxide, and the material of the second initial top mask layer 32 includes an amorphous silicon layer.

[0054] It should be noted that, in this embodiment, the first initial mask structure 2 includes a first initial bottom mask layer 21 and a first initial top mask layer 22 located on the first initial bottom mask layer 21; the material of the first initial top mask layer 22 is different from that of the second initial bottom mask layer 31.

[0055] It should also be noted that, in this embodiment, the first initial bottom mask layer 21 and the second initial bottom mask layer 31 are made of the same material; the second initial top mask layer 32 and the first initial top mask layer 22 are made of the same material.

[0056] In this embodiment, the material of the first initial top mask layer 22 is an amorphous silicon layer; the material of the first initial bottom mask layer 21 is silicon oxide.

[0057] Continue to refer Figure 6 , doping ions are implanted into a partial region of the second initial top mask layer 32 to form a doping region 4 in the second initial top mask layer 32 .

[0058] Specifically, in this embodiment, the method of injecting doping ions into the second initial top mask layer 32 includes: forming a patterned structure 6 on the second initial top mask layer 32; injecting doping ions into the second initial top mask layer 32 using the patterned structure 6 as a mask; after injecting doping ions into the second initial top mask layer 32, removing the patterned structure 6.

[0059] It should be noted that the patterned structure 6 in this embodiment includes a bottom layer pattern located on the top of the second initial top mask layer 32 and a top layer pattern located on the top of the bottom layer pattern.

[0060] Preferably, the material of the bottom pattern in this embodiment is a spin-on carbon layer (SOC), and the material of the top pattern is an anti-reflective silicon coating (SiARC). Of course, other embodiments of the present application may also choose to set only one layer of patterned structure 6, or may choose to set multiple layers of patterned structure 6, which is not specifically limited in this embodiment.

[0061] In this embodiment, the method for removing the patterned structure 6 includes but is not limited to etching, which is not specifically limited in this embodiment.

[0062] It should be noted that the doping region 4 in this embodiment includes a first doping region to an N-th doping region, and the first doping region to the N-th doping region are separated from each other.

[0063] That is to say, the number of doping regions 4 in this embodiment can be one, two or even more. When the number of patterned structures 6 formed on the second initial top mask layer 32 is two, a doping region 4 is formed between the two patterned structures 6; when the number of patterned structures 6 is three, a doping region 4 is formed between two adjacent patterned structures 6, and so on.

[0064] Any two adjacent doping regions 4 are separated from each other, and the interval between them is approximately the width of a patterned structure 6 .

[0065] Preferably, in this embodiment, multiple ion implantation processes are successively used to implant doping ions into the second initial top mask layer 32 to form the doping region 4 .

[0066] refer to Figure 7 , the second initial top mask layer 32 outside the doped region 4 is removed by etching, and the doped region 4 forms a second top mask layer 41 .

[0067] refer to Figure 8 , the second initial bottom mask layer 31 is etched using the second top mask layer 41 as a mask, so that the second initial bottom mask layer 31 forms a second bottom mask layer 5 .

[0068] refer to Fig. 9, reducing the width of the second bottom mask layer 5 and the second top mask layer 41.

[0069] Preferably, in this embodiment, the process of reducing the width of the second bottom mask layer 5 and the second top mask layer 41 is a lateral etching process.

[0070] Specifically, the lateral etching process includes an isotropic wet etching process or an isotropic dry etching process.

[0071] Furthermore, it should be noted that, while reducing the width of the second bottom mask layer 5 and the second top mask layer 41, the present embodiment also reduces the thickness of the second bottom mask layer 5 in a direction perpendicular to the substrate 1, and reduces the thickness of the first initial top mask layer 22 in a direction perpendicular to the substrate 1.

[0072] Further, after reducing the width of the second bottom mask layer 5 and the second top mask layer 41, the first initial mask structure 2 is etched using the second bottom mask layer 5 and the second top mask layer 41 as masks, so that the first initial mask structure 2 forms a first mask structure, including:

[0073] like Fig.10 As shown, the first initial top mask layer 22 is etched using the second bottom mask layer 5 and the second top mask layer 41 as masks, so that the first initial top mask layer 22 forms a first top mask layer 8 .

[0074] Further, while etching to form the first top mask layer 8, the second top mask layer 41 and part of the second bottom mask layer 5 can also be etched to be completely removed. Alternatively, while etching to form the first top mask layer 8, the second top mask layer 41 can also be etched to partially remove the second top mask layer 41 or completely remove the second top mask layer 41.

[0075] Then as Fig.11 As shown, the first initial bottom mask layer 21 on the side of the first top mask layer 8 is removed by etching, so that the first initial bottom mask layer 21 forms the first bottom mask layer 7 .

[0076] Furthermore, while etching to form the first bottom mask layer 7, a portion of the second bottom mask layer 5 may also be etched away.

[0077] Furthermore, the substrate 1 provided in this embodiment includes: a substrate; multiple gate structures located on the substrate; source and drain regions located on both sides of the gate structures; a dielectric layer located on the substrate covering the gate structures and the source and drain regions; and a first mask structure 23 covering the dielectric layer on part of the source and drain regions.

[0078] The material of the substrate in this embodiment includes, but is not limited to, silicon, silicon oxide, germanium, and other commonly used semiconductor substrate materials, which are not listed here one by one.

[0079] The gate structure can be a dummy gate or a metal gate structure.

[0080] The material of the dielectric layer includes but is not limited to silicon dioxide, or other dielectric layer materials.

[0081] It should be noted that the specific structure of the substrate 1 is not shown in the drawings of this embodiment. In fact, the substrate 1 may also include other structures, such as an isolation structure, and may not completely include the above structures. This embodiment does not make specific limitations on this.

[0082] It should be noted that, in this embodiment, after forming the first mask structure 23 , plug trenches are formed in the dielectric layer between the gate structures, the plug trenches expose part of the source and drain regions, and the plug trenches are divided by the first mask structure 23 in the extension direction of the gate structures.

[0083] The semiconductor structure formed by the above technical solution is as follows: Fig.12 From the scanning electron microscope image of the semiconductor structure provided by the embodiment of the present invention, it can be seen that the pattern line width of the first mask structure is relatively small. In the present application, the pattern of the second top mask layer formed by the doped region is transferred to the second bottom mask layer, and then the width of the second bottom mask layer and the second top mask layer is reduced, so that when the pattern is further transferred to the first mask structure, the pattern line width of the first mask structure is reduced. The first mask structure is used as a mask for etching the substrate, so that the size of the pattern formed in the substrate is reduced to meet the process requirements. As a result, the performance of the semiconductor structure is also improved accordingly.

[0084] Although the present invention has been illustrated and described with reference to certain preferred embodiments of the present invention, it should be understood by those skilled in the art that the above is a further detailed description of the present invention in conjunction with specific embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. Those skilled in the art may make various changes in form and details, including making several simple deductions or substitutions, without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A first initial mask structure and a second initial mask structure located on the first initial mask structure are formed on the substrate, wherein the first initial mask structure comprises a first initial bottom mask layer and a first initial top mask layer located on the first initial bottom mask layer; the second initial mask structure comprises a second initial bottom mask layer and a second initial top mask layer located on the second initial bottom mask layer; the material of the first initial top mask layer is an amorphous silicon layer; the material of the second initial bottom mask layer comprises silicon oxide, and the material of the second initial top mask layer comprises an amorphous silicon layer; Implanting doping ions into a partial region of the second initial top mask layer to form a doping region in the second initial top mask layer; Etching and removing the second initial top mask layer except the doped region, and forming the second top mask layer in the doped region; Using the second top mask layer as a mask, etching the second initial bottom mask layer, so that the second initial bottom mask layer forms a second bottom mask layer; reducing the width of the second bottom mask layer and the second top mask layer; After reducing the widths of the second bottom mask layer and the second top mask layer, the first initial mask structure is etched using the second bottom mask layer and the second top mask layer as masks, so that the first initial mask structure forms a first mask structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first preliminary bottom mask layer and the second preliminary bottom mask layer are made of the same material.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method for etching the first initial mask structure using the second bottom mask layer and the second top mask layer as masks includes: etching the first initial top mask layer using the second bottom mask layer and the second top mask layer as masks to form the first initial top mask layer; etching and removing the first initial bottom mask layer on the side of the first top mask layer to form the first initial bottom mask layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The process of reducing the width of the second bottom mask layer and the second top mask layer is a lateral etching process.

5. The method for forming a semiconductor structure according to claim 4, wherein: The lateral etching process includes an isotropic wet etching process or an isotropic dry etching process.

6. The method for forming a semiconductor structure according to claim 1, wherein: The method for injecting the doping ions into the second initial top mask layer includes: forming a patterned structure on the second initial top mask layer; injecting the doping ions into the second initial top mask layer using the patterned structure as a mask; and after injecting the doping ions into the second initial top mask layer, removing the patterned structure.

7. The method for forming a semiconductor structure according to claim 1, wherein: The doping region includes a first doping region to an N-th doping region, and the first doping region to the N-th doping region are separated from each other; The second initial top mask layer is implanted with the doping ions by using multiple ion implantation processes to form the doping region.

8. The method for forming a semiconductor structure according to claim 1 or 7, wherein: The substrate includes: a substrate; a plurality of gate structures on the substrate; source and drain regions on both sides of the gate structures; a dielectric layer on the substrate covering the gate structures and the source and drain regions; and the first mask structure covering a portion of the dielectric layer on the source and drain regions; The method for forming the semiconductor structure further includes: after forming the first mask structure, forming a plug trench in the dielectric layer between the gate structures, the plug trench exposing a portion of the source and drain regions, and the plug trench being divided by the first mask structure in an extension direction of the gate structure.

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