Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a layer to be etched, the layer to be etched includes a plurality of effective areas and ineffective areas, the effective areas are located between the ineffective areas; forming a sacrificial layer on the layer to be etched; modifying part of the sacrificial layer on the effective areas into a first modified layer, and modifying the sacrificial layer on the ineffective areas between adjacent effective areas into a second modified layer; modifying the sacrificial layer on the ineffective areas into a third modified layer, the third modified layer being adjacent to the sacrificial layer on the effective areas and the first modified layer; removing the sacrificial layer on the effective areas, and forming a first groove between the first modified layer, the second modified layer and the third modified layer; etching the layer to be etched using the first modified layer, the second modified layer and the third modified layer as masks, and forming a second groove in the layer to be etched. The performance of the semiconductor structure formed by the method is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the semiconductor field, in order to obtain a semiconductor structure with multiple functions, it is necessary to design a more complex mask pattern for pattern transfer. In the front, middle and back stages of the semiconductor process, a combination of one or more of the self-aligned multiple patterning (SAMP), reverse litho-etch-litho-etch (RLELE) and etching processes are often used to form a variety of semiconductor structures that meet the needs.

[0003] However, as the size of semiconductor structures continues to shrink, the accuracy of existing photolithography technology cannot meet the dimensional accuracy requirements of semiconductor structures. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can improve the dimensional accuracy of the semiconductor structure.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a layer to be etched, the layer to be etched includes a plurality of effective areas and ineffective areas, and the effective areas are located between the ineffective areas; forming a sacrificial layer on the layer to be etched; modifying part of the sacrificial layer on the effective areas into a first modified layer, and modifying the sacrificial layer on the ineffective areas between adjacent effective areas into a second modified layer; modifying the sacrificial layer on the ineffective areas into a third modified layer, and the third modified layer is adjacent to the sacrificial layer on the effective areas and the first modified layer; removing the sacrificial layer on the effective areas, and forming a first groove between the first modified layer, the second modified layer and the third modified layer; etching the layer to be etched using the first modified layer, the second modified layer and the third modified layer as masks, and forming a second groove in the layer to be etched.

[0006] Optionally, the modification treatment process includes an ion implantation process.

[0007] Optionally, the material of the sacrificial layer includes an amorphous material; and the amorphous material includes amorphous silicon.

[0008] Optionally, the implanted ions include carbon ions, boron ions or fluorine ions.

[0009] Optionally, the layer to be etched includes: a substrate; a device layer located on the substrate, the device layer including an isolation structure and a device structure located within the isolation structure; and a hard mask layer located on the device layer.

[0010] Optionally, the process of removing the sacrificial layer includes a wet etching process.

[0011] Optionally, the wet etching process has an etching rate ratio between the sacrificial layer and the first modified layer that is greater than 1; the wet etching process has an etching rate ratio between the sacrificial layer and the second modified layer that is greater than 1; the wet etching process has an etching rate ratio between the sacrificial layer and the third modified layer that is greater than 1.

[0012] Optionally, after forming the first groove and before etching the layer to be etched, the method further includes: forming a first sidewall spacer on the sidewall of the first groove.

[0013] Optionally, the material of the first sidewall spacer includes an inorganic material, and the inorganic material includes one or a combination of multiple of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon oxide, silicon carbide, titanium oxide, aluminum nitride, tantalum nitride or titanium nitride.

[0014] Optionally, the method for forming the first side wall includes: forming a side wall material layer on the inner wall surface of the first groove, the surface of the first modified layer, the surface of the second modified layer and the surface of the third modified layer; back etching the side wall material layer until the surface of the layer to be etched is exposed, thereby forming the first side wall on the side wall of the first groove.

[0015] Optionally, the process of forming the spacer material layer includes an atomic layer deposition process.

[0016] Optionally, after forming the second groove, the method further includes: removing the first modified layer, the second modified layer and the third modified layer; and after removing the first modified layer, the second modified layer and the third modified layer, forming a conductive layer in the second groove.

[0017] Optionally, the process of removing the first modified layer, the second modified layer and the third modified layer includes a dry etching process.

[0018] Optionally, the method for forming the conductive layer includes: forming a conductive material layer in the second groove and on the surface of the layer to be etched; planarizing the conductive material layer until the surface of the layer to be etched is exposed, and forming the conductive layer in the second groove.

[0019] Optionally, the material of the conductive layer includes metal, and the metal includes a combination of one or more of copper, tungsten and titanium nitride.

[0020] Optionally, after removing the first modified layer, the second modified layer and the third modified layer and before forming the conductive layer, the method further includes: forming a second sidewall spacer on the sidewall of the second groove.

[0021] Optionally, the material of the second sidewall spacer includes an inorganic material, and the inorganic material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon oxide, silicon carbide, titanium oxide, aluminum nitride, tantalum nitride and titanium nitride.

[0022] Optionally, the method for modifying a portion of the sacrificial layer on the effective area and the sacrificial layer on the invalid area between adjacent effective areas includes: forming a first mask layer on the sacrificial layer, the first mask layer exposing a portion of the surface of the sacrificial layer on the effective area and the surface of the sacrificial layer on the invalid area between adjacent effective areas; using the first mask layer as a mask to modify the exposed sacrificial layer to form the first modified layer and the second modified layer.

[0023] Optionally, after forming the first modified layer and the second modified layer, the first mask layer is removed.

[0024] Optionally, after forming the first modified layer and the second modified layer, the method for modifying the sacrificial layer on the invalid area includes: forming a second mask layer on the first modified layer, the second modified layer and the sacrificial layer, the second mask layer exposing the surface of the sacrificial layer on the invalid area; using the second mask layer as a mask to modify the exposed sacrificial layer to form the third modified layer.

[0025] Optionally, after forming the third modified layer, the second mask layer is removed.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0027] The semiconductor structure of the technical solution of the present invention forms a first modified layer in the sacrificial layer of the effective area and a second modified layer between the sacrificial layers of the adjacent effective areas by modifying part of the sacrificial layer on the effective area and the sacrificial layer on the invalid area between adjacent effective areas; and then the sacrificial layer on the invalid area is modified to form a third modified layer, wherein the third modified layer is adjacent to the sacrificial layer and the first modified layer on the effective area, and the first modified layer, the second modified layer and the third modified layer have a large etching selectivity with the sacrificial layer, so that when the sacrificial layer on the effective area is removed, the first modified layer, the second modified layer and the third modified layer can be less damaged, so that when the first modified layer, the second modified layer and the third modified layer are used as the pattern of the semiconductor structure for transfer, an effective device can be formed on the effective area, avoiding the formation of an invalid device in the process, so that the formed semiconductor structure is affected, thereby improving the performance of the semiconductor structure; at the same time, avoiding the need to add a photolithography process to remove the invalid device after it is formed, thereby reducing the use of masks, thereby simplifying the process flow and saving production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 18 Schematic diagram of a semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] As described in the background art, the accuracy of existing photolithography technology cannot meet the dimensional accuracy requirements of semiconductor structures.

[0030] Specifically, in the back-end process, when a mask pattern is formed by using a multi-pattern self-alignment technique, the mask pattern is transferred layer by layer, and finally a conductive layer is formed, and some non-functional conductive layers will also be formed. The presence of a non-functional conductive layer in a semiconductor structure will increase the resistance and capacitance of the semiconductor structure, thereby affecting the electrical performance of the semiconductor structure. Therefore, it is necessary to add a mask to remove the non-functional conductive layer. However, as the size of semiconductor structures becomes smaller and smaller, the exposure accuracy of existing photolithography technology cannot accurately form a mask pattern for removing non-functional conductive layers, and the position of the formed mask pattern will have a certain offset, which makes the non-functional conductive layer not removed cleanly, or the process of removing the non-functional conductive layer causes damage to other positions of the semiconductor structure, thereby affecting the performance of the semiconductor structure.

[0031] In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, by performing one or more modification treatments on the sacrificial layer on the etched layer to form a modified layer, the modified layer and the sacrificial layer have a large etching selectivity ratio, so that after the sacrificial layer is subsequently removed, the mask pattern formed by the modified layer has better accuracy, and the semiconductor device formed with the mask pattern has a higher degree of effectiveness, avoiding the formation of invalid devices in the process, which affects the formed semiconductor structure, thereby improving the performance of the semiconductor structure.

[0032] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] Figures 1 to 18 Schematic diagram of a semiconductor structure forming process in an embodiment of the present invention.

[0034] Please refer to Figure 1 and Figure 2 , Figure 1 for Figure 2 Schematic diagram of the structure along the section line AA'. Figure 2 for Figure 1 A top view of a layer to be etched is provided, wherein the layer to be etched includes a plurality of effective regions I and ineffective regions II, and the effective regions I are located between the ineffective regions II.

[0035] The layer to be etched includes: a substrate 100, a device layer 101 located on the substrate 100, and a hard mask layer 102 located on the device layer 101, the device layer 101 includes an isolation structure (not shown) and a device structure (not shown) located within the isolation structure; the device structure includes a transistor, a diode, a triode or a metal wire, etc.

[0036] The material of the substrate 100 includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide or silicon on insulator, etc. The material of the hard mask layer 102 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride and silicon oxycarbon nitride.

[0037] In this embodiment, the material of the substrate 200 includes silicon; the material of the hard mask layer 102 includes silicon nitride.

[0038] The hard mask layer 102 is used to stably transfer the pattern to the device layer 101 .

[0039] Please refer to Figure 3 and Figure 4 , Figure 3 for Figure 4 Schematic diagram of the structure along the section line BB'. Figure 4 for Figure 3 A sacrificial layer 104 is formed on the layer to be etched.

[0040] The material of the sacrificial layer 104 includes an amorphous material.

[0041] In this embodiment, the material of the sacrificial layer 104 includes amorphous silicon (a-Si).

[0042] The material of the sacrificial layer 104 includes amorphous silicon (a-Si, Amorphous Silicon), and the sacrificial layer is subsequently modified to form a first modified layer, a second modified layer and a third modified layer. The sacrificial layer 104 has a larger etching selectivity ratio with the first modified layer, the sacrificial layer 104 has a larger etching selectivity ratio with the second modified layer, and the sacrificial layer 104 has a larger etching selectivity ratio with the third modified layer, so that the first modified layer, the second modified layer and the third modified layer can be less damaged while removing the sacrificial layer 104, so that when the first modified layer, the second modified layer and the third modified layer are subsequently transferred as the pattern of the semiconductor structure, an effective device can be formed on the effective area I, avoiding the formation of an invalid device in the process, so that the formed semiconductor structure is affected, thereby improving the performance of the semiconductor structure.

[0043] Please refer to Figure 5 , Figure 5 for Figure 4Based on the schematic diagram, a first mask layer 105 is formed on the sacrificial layer 104, and the first mask layer 105 exposes a portion of the surface of the sacrificial layer 104 on the effective area I and the surface of the sacrificial layer 104 on the ineffective area II between adjacent effective areas I.

[0044] In this embodiment, the material of the first mask layer 105 includes photoresist.

[0045] Please refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 Schematic diagram of the structure along the section line CC'. Figure 7 for Figure 6 The sacrificial layer 104 exposed by the first mask layer 105 is modified, part of the sacrificial layer 104 on the effective area I is modified into a first modified layer 106, and the sacrificial layer 104 on the ineffective area II between adjacent effective areas I is modified into a second modified layer 107.

[0046] The modification process includes an ion implantation process.

[0047] The implanted ions include carbon ions, boron ions or fluorine ions.

[0048] Ion implantation is performed on the sacrificial layer 104, and the first modified layer 106 and the sacrificial layer 104 formed after the ion implantation have a large etching selectivity ratio, and the second modified layer 107 and the sacrificial layer 104 have a large etching selectivity ratio, so that when the sacrificial layer 104 on the effective area I is subsequently removed, the first modified layer 106 and the second modified layer 107 can be less damaged, so that the first modified layer 106 and the second modified layer 107 can form a pattern with good morphology and precise size, and then after the pattern is transferred to the layer to be etched, a semiconductor structure with good morphology and precise size can be formed.

[0049] In other embodiments, the process of modifying the sacrificial layer includes a doping process.

[0050] After forming the first modified layer 106 and the second modified layer 107 , the first mask layer is removed.

[0051] In this embodiment, the process of removing the first mask layer includes an ashing process.

[0052] Please refer to Figure 8 , Figure 8 for Figure 7 Based on the schematic diagram, a second mask layer 108 is formed on the first modified layer 106, the second modified layer 107 and the sacrificial layer 104, and the second mask layer 108 exposes the surface of the sacrificial layer 104 on the ineffective area II.

[0053] In this embodiment, the material of the second mask layer 108 includes photoresist.

[0054] Please refer to Fig. 9 and Fig.10 , Fig. 9 for Fig.10 Schematic diagram of the structure along the section line DD'. Fig.10 for Fig. 9 , using the second mask layer 108 as a mask, the sacrificial layer 104 on the invalid area is modified into a third modified layer 109, and the third modified layer 109 is adjacent to the sacrificial layer 104 and the first modified layer 106 on the effective area I.

[0055] The modification process includes an ion implantation process.

[0056] The implanted ions include carbon ions, boron ions or fluorine ions.

[0057] Ion implantation is performed on the sacrificial layer 104, and the third modified layer 109 and the sacrificial layer 104 formed after the ion implantation have a large etching selectivity ratio, so that when the sacrificial layer 104 on the effective area I is subsequently removed, the third modified layer 109 can be less damaged, so that the third modified layer 109 can form a pattern with good morphology and precise size with the first modified layer 106 and the second modified layer 107, and then after the pattern is transferred to the layer to be etched, a semiconductor structure with good morphology and precise size can be formed.

[0058] In other embodiments, the process of modifying the sacrificial layer includes a doping process.

[0059] After the third modified layer 109 is formed, the second mask layer 108 is removed.

[0060] In this embodiment, the process of removing the second mask layer 108 includes an ashing process.

[0061] Please refer to Fig.11 and Fig.12 , Fig.11 for Fig.12 Schematic diagram of the structure along the section line EE'. Fig.12 for Fig.11 After forming the third modified layer 109, the sacrificial layer 104 on the effective area I is removed, and a first groove 110 is formed between the first modified layer 106, the second modified layer 107 and the third modified layer 109.

[0062] The process of removing the sacrificial layer 104 includes a combination of one or more of a wet etching process and a dry etching process. In this embodiment, the process of removing the sacrificial layer 104 includes a wet etching process.

[0063] The wet etching process has an etching rate ratio between the sacrificial layer 104 and the first modified layer 106 that is greater than 1; the wet etching process has an etching rate ratio between the sacrificial layer 104 and the second modified layer 107 that is greater than 1; and the wet etching process has an etching rate ratio between the sacrificial layer 104 and the third modified layer 109 that is greater than 1.

[0064] The first modified layer 106, the second modified layer 107 and the third modified layer 109 have a large etching selectivity with the sacrificial layer 104, so that when the sacrificial layer 104 on the effective area I is removed, the first modified layer 106, the second modified layer 107 and the third modified layer 109 can be less damaged. Therefore, when the first modified layer 106, the second modified layer 107 and the third modified layer 109 are used as the pattern of the semiconductor structure for transfer, an effective device can be formed on the effective area I, avoiding the formation of invalid devices in the process, which affects the formed semiconductor structure, thereby improving the performance of the semiconductor structure.

[0065] Please refer to Fig.13 and Fig.14 , Fig.13 for Fig.14 Schematic diagram of the structure along the section line FF'. Fig.14 for Fig.13 In the top view, a first side wall 111 is formed on the side wall of the first groove 110.

[0066] The method for forming the first side wall 111 includes: forming a side wall material layer (not shown) on the inner wall surface of the first groove 110, the surface of the first modified layer 106, the surface of the second modified layer 107 and the surface of the third modified layer 109; etching back the side wall material layer until the surface of the layer to be etched is exposed, thereby forming the first side wall 111 on the side wall of the first groove 110.

[0067] The material of the first spacer 111 includes an inorganic material, and the inorganic material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon nitride, silicon carbide, titanium oxide, aluminum nitride, tantalum nitride and titanium nitride. The process of forming the spacer material layer includes a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0068] In this embodiment, the material of the first spacer 111 includes titanium oxide; and the process of forming the spacer material layer includes an atomic layer deposition (ALD) process.

[0069] The first sidewall spacer 111 is used to serve as the pattern of the semiconductor structure together with the first modified layer 106 , the second modified layer 107 , and the third modified layer 109 , so that the pattern can be transferred more accurately.

[0070] Next, the layer to be etched is etched using the first modified layer 106 , the second modified layer 107 , the third modified layer 109 and the first sidewall 111 as masks to form a second groove 112 in the layer to be etched.

[0071] Please refer to Fig.15 , Fig.15 for Fig.13 Based on the schematic diagram, the first modified layer 106 , the second modified layer 107 , the third modified layer 109 and the first sidewall 111 are used as masks to etch the hard mask layer 102 until the surface of the device layer 101 is exposed, and an initial second groove 112 is formed in the hard mask layer 102 .

[0072] The process of etching the hard mask layer 102 includes a dry etching process or a wet etching process or a combination of one or more of the above.

[0073] In this embodiment, the process of etching the hard mask layer 102 includes a dry etching process, which can form an initial second groove 112 with relatively straight side walls and good morphology, so that the pattern transfer effect formed by the first modified layer 106, the second modified layer 107, the third modified layer 109 and the first side wall 111 is better.

[0074] Please continue to refer to Fig.15 After the initial second groove 112 is formed, the first modified layer 106 , the second modified layer 107 , the third modified layer 109 and the first sidewall 111 are removed.

[0075] The process of removing the first modified layer 106 , the second modified layer 107 , the third modified layer 109 and the first spacer 111 includes a combination of one or more of a dry etching process and a wet etching process.

[0076] In this embodiment, the process of removing the first modified layer 106 , the second modified layer 107 , the third modified layer 109 and the first spacer 111 includes a dry etching process.

[0077] Please refer to Fig.16 , using the hard mask layer 102 as a mask, etching the device layer 101 until the top surface of the device structure is exposed, and forming a second groove 113 in the layer to be etched.

[0078] The process of etching the device layer 101 includes a dry etching process or a wet etching process or a combination of one or more of them.

[0079] In this embodiment, the process of etching the device layer 101 includes a dry etching process, which can form a second groove 113 with relatively straight side walls and good morphology, so that the pattern transfer effect formed by the first modified layer 106, the second modified layer 107, the third modified layer 109 and the first side wall 111 is better.

[0080] Please continue to refer to Fig.16 A second sidewall 114 is formed on the sidewall of the second groove 113 .

[0081] The method for forming the second sidewall 114 includes: forming a sidewall material layer (not shown) on the inner wall surface of the second groove 113 and the surface of the mask layer 102; etching back the sidewall material layer until the bottom surface of the second groove 113 is exposed, and forming the second sidewall 114 on the sidewall of the second groove 113.

[0082] The material of the second spacer 114 includes an inorganic material, and the inorganic material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon nitride, silicon carbide, titanium oxide, aluminum nitride, tantalum nitride and titanium nitride. The process of forming the spacer material layer includes a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0083] In this embodiment, the material of the second spacer 114 includes titanium oxide; and the process of forming the spacer material layer includes an atomic layer deposition (ALD) process.

[0084] The second sidewall 114 is used to isolate adjacent conductive layers when a conductive layer is subsequently formed in the second groove 113 , thereby preventing adjacent conductive layers from being short-circuited.

[0085] Please refer to Fig.17 and Fig.18 , Fig.17 for Fig.18 Schematic diagram of the structure along the section line GG'. Fig.18 for Fig.17 After forming the second sidewall 114, a conductive layer 115 is formed in the second groove 113, and the conductive layer 115 is electrically connected to the device structure in the device layer 101.

[0086] The method for forming the conductive layer 115 includes: forming a conductive material layer in the second groove 113 and on the surface of the hard mask layer 102 ; planarizing the conductive material layer until the surface of the hard mask layer 102 is exposed, and forming the conductive layer 115 in the second groove 113 .

[0087] The material of the conductive layer 115 includes metal, and the metal includes one or more combinations of copper, tungsten and titanium nitride.

[0088] So far, the method forms a conductive layer 115 on the active area I, thereby avoiding the generation of invalid devices.

[0089] In the method for forming the semiconductor structure, a first modified layer 106 is formed in the sacrificial layer 104 of the effective area I and a second modified layer 107 is formed between the sacrificial layers 104 of the adjacent effective areas I by modifying a portion of the sacrificial layer 104 on the effective area I and the sacrificial layer 104 on the ineffective area II between adjacent effective areas I; and the sacrificial layer 104 on the ineffective area II is modified to form a third modified layer 109, wherein the third modified layer 109 is adjacent to the sacrificial layer 104 and the first modified layer 106 on the effective area I, and the first modified layer 106, the second modified layer 107 and the third modified layer 109 have a large etching distance from the sacrificial layer 104. The etching selectivity ratio is improved, so that when the sacrificial layer 104 on the effective area I is removed, the first modified layer 106, the second modified layer 107 and the third modified layer 109 can be less damaged, so that when the first modified layer 106, the second modified layer 107 and the third modified layer 109 are used as the pattern of the semiconductor structure for transfer, an effective device can be formed on the effective area I, avoiding the formation of invalid devices in the process, so that the formed semiconductor structure is affected, thereby improving the performance of the semiconductor structure; at the same time, it avoids the need to increase the photolithography process for removal after the invalid device is formed, thereby reducing the use of masks, thereby simplifying the process flow and saving production costs.

[0090] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a layer to be etched, wherein the layer to be etched includes a plurality of effective areas and ineffective areas, wherein the effective areas are located between the ineffective areas; forming a sacrificial layer on the layer to be etched; Modifying a portion of the sacrificial layer on the effective area into a first modified layer, and modifying a portion of the sacrificial layer on the ineffective area between adjacent effective areas into a second modified layer; Modifying the sacrificial layer on the ineffective area not between adjacent effective areas into a third modified layer, wherein the third modified layer is adjacent to the sacrificial layer and the first modified layer on the effective area; removing the sacrificial layer on the effective area, and forming a first groove between the first modified layer, the second modified layer and the third modified layer; The layer to be etched is etched using the first modified layer, the second modified layer and the third modified layer as masks to form a second groove in the layer to be etched.

2. The method for forming a semiconductor structure according to claim 1, wherein: The modification process includes an ion implantation process.

3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the sacrificial layer includes an amorphous material; and the amorphous material includes amorphous silicon.

4. The method for forming a semiconductor structure according to claim 3, wherein: The implanted ions in the ion implantation process include carbon ions, boron ions or fluorine ions.

5. The method for forming a semiconductor structure according to claim 1, wherein: The layer to be etched includes: a substrate; a device layer located on the substrate, wherein the device layer includes an isolation structure and a device structure located in the isolation structure; and a hard mask layer located on the device layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the sacrificial layer includes a wet etching process.

7. The method for forming a semiconductor structure according to claim 6, wherein: The wet etching process has an etching rate ratio between the sacrificial layer and the first modified layer that is greater than 1; the wet etching process has an etching rate ratio between the sacrificial layer and the second modified layer that is greater than 1; the wet etching process has an etching rate ratio between the sacrificial layer and the third modified layer that is greater than 1.

8. The method for forming a semiconductor structure according to claim 1, wherein: After forming the first groove and before etching the layer to be etched, the method further includes: forming a first sidewall spacer on the sidewall of the first groove.

9. The method for forming a semiconductor structure according to claim 8, wherein: The material of the first spacer includes an inorganic material, and the inorganic material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon oxide, silicon carbide, titanium oxide, aluminum nitride, tantalum nitride and titanium nitride.

10. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first side wall includes: forming a side wall material layer on the inner wall surface of the first groove, the surface of the first modified layer, the surface of the second modified layer and the surface of the third modified layer; etching back the side wall material layer until the surface of the layer to be etched is exposed, thereby forming the first side wall on the side wall of the first groove.

11. The method for forming a semiconductor structure according to claim 10, wherein: The process of forming the spacer material layer includes an atomic layer deposition process.

12. The method for forming a semiconductor structure according to claim 1, wherein: After forming the second groove, the method further includes: removing the first modified layer, the second modified layer and the third modified layer; and after removing the first modified layer, the second modified layer and the third modified layer, forming a conductive layer in the second groove.

13. The method for forming a semiconductor structure according to claim 12, wherein: The process of removing the first modified layer, the second modified layer and the third modified layer includes a dry etching process.

14. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the conductive layer includes: forming a conductive material layer in the second groove and on the surface of the layer to be etched; planarizing the conductive material layer until the surface of the layer to be etched is exposed, and forming the conductive layer in the second groove.

15. The method for forming a semiconductor structure according to claim 12, wherein: The material of the conductive layer includes metal, and the metal includes a combination of one or more of copper, tungsten and titanium nitride.

16. The method for forming a semiconductor structure according to claim 12, wherein: After removing the first modified layer, the second modified layer and the third modified layer and before forming the conductive layer, the method further includes: forming a second sidewall spacer on the sidewall of the second groove.

17. The method for forming a semiconductor structure according to claim 16, wherein: The material of the second spacer includes an inorganic material, and the inorganic material includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon oxide, silicon carbide, titanium oxide, aluminum nitride, tantalum nitride and titanium nitride.

18. The method for forming a semiconductor structure according to claim 1, wherein: The method for modifying a portion of a sacrificial layer on an effective area and a sacrificial layer on an ineffective area between adjacent effective areas comprises: forming a first mask layer on the sacrificial layer, the first mask layer exposing a portion of the sacrificial layer surface on the effective area and the sacrificial layer surface on the ineffective area between adjacent effective areas; modifying the exposed sacrificial layer using the first mask layer as a mask to form the first modified layer and the second modified layer.

19. The method for forming a semiconductor structure according to claim 18, wherein: After forming the first modified layer and the second modified layer, the first mask layer is removed.

20. The method for forming a semiconductor structure according to claim 1, wherein: After forming the first modified layer and the second modified layer, the method for modifying the sacrificial layer on the invalid area includes: forming a second mask layer on the first modified layer, the second modified layer and the sacrificial layer, the second mask layer exposing the surface of the sacrificial layer on the invalid area; using the second mask layer as a mask to modify the exposed sacrificial layer to form the third modified layer.

21. The method for forming a semiconductor structure according to claim 20, wherein: After forming the third modified layer, the second mask layer is removed.

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