Spin memristor synaptic device based on skyrmions
By introducing Sgmingson in spintronics devices and using STT and SOT currents for control, the problems of single conductivity and high energy consumption of traditional devices are solved, and the spin-memory resistance with polymorphic synaptic weight and low energy consumption are achieved Synaptic devices.
Patent Information
- Application Number
- CN202010262550.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-04-03
- Publication Date
- 2025-02-21
- Estimated Expiration
- 2040-04-03
AI Technical Summary
Traditional spintronics devices can only achieve two conductivity states, which is difficult to meet the needs of polymorphic synaptic weights, and write and read energy consumption is high.
A spin-memory synaptic device based on Segmentone is designed to generate Segmentone through STT current and use SOT current to migrate between the tunnel junction area and the storage area to achieve diversity of conductivity states and variability of synaptic weights.
It realizes synaptic weight update and reading with low energy consumption, greatly increases the number of conductivity, and improves stability and nonvolatileness, which is suitable for the application of large-scale integration neural networks.
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Figure CN113497180B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of magnetic elements, and in particular relates to a skyrmion-based spin memristor synaptic device utilizing topological protection. Background Art
[0002] Memristors are the fourth basic circuit element after resistors, capacitors and inductors. In recent years, their non-volatility, excellent read-write energy efficiency and write speed have attracted a lot of research. At the same time, the low energy efficiency and memory separation system of traditional von Neumann architecture computers has been increasingly unable to meet people's demand for high-performance computing. Brain-like neuromorphic computing is regarded as the most potential competitor of traditional von Neumann architecture and has developed rapidly.
[0003] Brain-like neuromorphic computing achieves high-performance computing such as recognition through the construction of artificial neural networks. Artificial neural networks include two types of devices: artificial neurons and artificial synapses. Neurons have the characteristics of nonlinear response, while synapses have the function of storing weights, and are the most critical devices for realizing high-efficiency computing with integrated storage and computing. Memristors are the most advantageous way to implement synaptic devices. The non-volatile variable conductance of memristors can be used as variable synaptic weights, and the low write and read power consumption makes them very conducive to the construction of highly integrated networks. Therefore, memristors as neural network synapses have attracted a large number of studies in recent years.
[0004] Spintronic devices have intrinsically variable resistance, and their different conductance states have unique advantages in terms of stability, write and read power consumption. However, traditional spintronic devices, such as magnetic tunnel junctions, often have only two conductance states and are not suitable as multi-state synapses. Summary of the invention
[0005] In view of the shortcomings of the prior art, in order to achieve stable multi-state conductance, i.e., multi-state synaptic weights, in spin electronics devices, the present invention aims to provide a skyrmion-based spin memristor synaptic device with low read and write energy consumption, high stability, and a relatively large number of conductance states.
[0006] To achieve the above object, the present invention adopts the following technical solutions:
[0007] A skyrmion-based spin memristor synaptic device, comprising:
[0008] There are heavy metal layers with spin Hall angles at both ports;
[0009] A magnetic free layer located on the heavy metal layer; the magnetic free layer is divided into a tunnel junction region and a skyrmion storage region, and a barrier that hinders the free movement of skyrmions is provided between the tunnel junction region and the skyrmion storage region;
[0010] An insulating barrier layer, a magnetic pinning layer and a metal top electrode are sequentially arranged on the tunnel junction region;
[0011] The metal top electrode is configured to connect an initialization current to generate skyrmions in the tunnel junction region, the heavy metal layer is configured to connect a write current to drive skyrmions to move between the tunnel junction region and the skyrmion storage region, and the metal top electrode is also configured to connect a readout current to read the conductivity of the tunnel junction region.
[0012] Preferably, the barrier is a high perpendicular magnetic anisotropy barrier layer located on the magnetic free layer, and the length of the high perpendicular magnetic anisotropy barrier layer in the width direction of the magnetic free layer does not completely cover the magnetic free layer.
[0013] Specifically, the material of the high perpendicular magnetic anisotropy barrier layer is CoFeB / MgO, Fe / MgO, [Co / Pt], FeB / MgO or Co.
[0014] More specifically, the thickness of the high perpendicular magnetic anisotropy barrier layer is 1 nm to 100 nm.
[0015] Preferably, the barrier is a nanowire disposed in the magnetic free layer, one end of the nanowire is connected to the tunnel junction region, and the other end of the nanowire is connected to the skyrmion storage region.
[0016] Specifically, the line width of the nanowire is set to allow only a single skyrmion to pass through under the effect of its boundary.
[0017] More specifically, the nanowire has a line width of 20 nm to 10 μm.
[0018] Among them, the material of the heavy metal layer is Pt or Ta; the material of the magnetic free layer is CoFeB, Fe, [Co / Pt], FeB or Co; the material of the insulating barrier layer is MgO, TiO2, Al2O3 or MgAlO; the magnetic pinning layer includes a first magnetic layer, an antiferromagnetic coupling spacer layer and a second magnetic layer arranged in sequence from bottom to top, and the materials of the first magnetic layer and the second magnetic layer are respectively selected from Co, Fe, [Co / Pt], CoFeB, CoFe, FeB or NiFe, and the material of the antiferromagnetic coupling spacer layer is Ru or W; the material of the metal top electrode is Pt, Ta, Cr, Au or Ti.
[0019] The thickness of the heavy metal layer is 2nm-10nm, the thickness of the magnetic free layer is 0.5nm-3nm, the thickness of the insulating barrier layer is 0.5nm-3nm, the thickness of the magnetic pinned layer is 2nm-10nm, and the thickness of the metal top electrode is 10nm-100nm.
[0020] The heavy metal layer has the same width as the magnetic free layer, and the heavy metal layer extends from both ends of the magnetic free layer in the length direction.
[0021] The skyrmion-based spin memristor synaptic device provided in an embodiment of the present invention generates skyrmions in a tunnel junction region using an STT (Spin Transfer Torque) current (i.e., initialization current), and migrates skyrmions between a tunnel junction region and a storage region using an SOT (Spin Orbit Torque) current (i.e., write current), thereby changing the conductance of the tunnel junction region to complete the update of the synaptic weights, and obtaining a synaptic device with a relatively large number of conductance states. Among them, the generation of skyrmions and the reading of the conductance state are the same path, the SOT current drives the movement of skyrmions, which has a lower current requirement than the driving domain wall movement by several orders of magnitude, and the initialization current only needs to be used once, which can greatly reduce the energy consumption of updating and reading the weights of the synaptic device, and its conductance state is also greatly increased. In addition, due to the stability and non-volatile characteristics of skyrmions, the stability of the synaptic device provided by the present invention is excellent. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 is a schematic structural diagram of a spin memristor synaptic device provided in Example 1 of the present invention;
[0023] Figure 2 Yes Figure 1 Top view of the spin memristor synaptic device;
[0024] Figure 3 Yes Figure 2 A schematic cross-sectional view of the device along line AA;
[0025] Figure 4 It is a schematic diagram of the structure of the spin memristor synapse device provided in Example 2 of the present invention. DETAILED DESCRIPTION
[0026] In order to make the purpose, technical scheme and advantages of the present invention clearer, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the present invention shown in the accompanying drawings and described according to the accompanying drawings are merely exemplary, and the present invention is not limited to these embodiments.
[0027] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.
[0028] Example 1
[0029] This embodiment provides a spin memristor synaptic device based on skyrmions, see Figures 1 to 3 The spin memristor synaptic device includes: a heavy metal layer 10 with spin Hall angles at two ports; a magnetic free layer 20 located on the heavy metal layer 10, and the magnetic free layer 20 is divided into a tunnel junction area 20a and a skyrmion storage area 20b; an insulating barrier layer 30, a magnetic pinning layer 40 and a metal top electrode 50 are sequentially arranged on the tunnel junction area 20a.
[0030] Wherein, a barrier 60 is provided between the tunnel junction region 20a and the skyrmion storage region 20b to prevent the skyrmions from moving freely. Figures 1 to 3 As shown in FIG. 1 , the barrier 60 is a high perpendicular magnetic anisotropy barrier layer located on the magnetic free layer 20. The high perpendicular magnetic anisotropy barrier layer is in the width direction of the magnetic free layer 20 (eg Figure 2 The length in the Y direction (in the Y direction) does not completely cover the magnetic free layer 20.
[0031] The magnetic pinned layer 40 is vertically pinned, and the high perpendicular magnetic anisotropy barrier layer and the magnetic free layer are both perpendicular to the easy axis. The magnetic free layer 20 requires an energy environment that can stabilize skyrmions, and the perpendicular anisotropy energy of the high perpendicular magnetic anisotropy barrier layer 60 must be significantly higher than that of the magnetic free layer 20 to achieve the function of hindering the movement of skyrmions.
[0032] The heavy metal layer 10 has the same width as the magnetic free layer 20, and the heavy metal layer 10 has a length direction (such as Figure 2 The two ends of the magnetic free layer 20 are extended in the X direction in the middle to form electrodes so as to more conveniently access the current.
[0033] The material of the heavy metal layer 10 can be Pt or Ta; the material of the magnetic free layer 20 can be CoFeB, Fe, [Co / Pt], FeB or Co; the material of the insulating barrier layer 30 can be MgO, TiO2, Al2O3 or MgAlO; the magnetic pinning layer 40 includes a first magnetic layer, an antiferromagnetic coupling spacer layer and a second magnetic layer arranged in sequence from bottom to top, and the materials of the first magnetic layer and the second magnetic layer can be Co, Fe, [Co / Pt], CoFeB, CoFe, FeB or NiFe respectively, and the material of the antiferromagnetic coupling spacer layer can be Ru, W, etc.; the material of the metal top electrode 50 can be Pt, Ta, Cr, Au or Ti. The material of the high perpendicular magnetic anisotropy barrier layer 60 can be CoFeB / MgO, Fe / MgO, [Co / Pt], FeB / MgO or Co.
[0034] The thickness of the heavy metal layer 10 can be set to 2nm-10nm, the thickness of the magnetic free layer 20 can be set to 0.5nm-3nm, the thickness of the insulating barrier layer 30 can be set to 0.5nm-3nm, the thickness of the magnetic pinned layer 40 can be set to 2nm-10nm, the thickness of the metal top electrode 50 can be set to 10nm-100nm. The thickness of the high perpendicular magnetic anisotropy barrier layer 60 can be set to 1nm-100nm.
[0035] The metal top electrode 50 is configured to connect the initialization current I int In order to generate skyrmions 70 in the tunnel junction region 20a, the heavy metal layer 10 is configured to connect the write current I write To drive the skyrmion 70 to move between the tunnel junction region 20a and the skyrmion storage region 20b, the metal top electrode 50 is also configured to connect a readout current I read The conductance of the tunnel junction region 20a is read. The generation of skyrmions and the reading of the conductance state are performed in the same way.
[0036] Combination Figures 1 to 3 , initialization current I int The spin current generated by the STT effect will generate skyrmions in the magnetic free layer junction region 20a of a specific magnetic moment. The saturation number of skyrmions is related to the size of skyrmions, the repulsion between skyrmions, and the initialization current I int The magnetic energy environment of the magnetic free layer 20 plays a decisive role. The larger the area of the free layer, the more saturation numbers there are. int No longer accessible.
[0037] At the initialization current I int After a sufficient number of skyrmions are generated in the tunnel junction region 20a, a write current pulse I write The write current pulse I write The amplitude and pulse time of I will affect the number of skyrmions crossing the barrier region, leaving different numbers of skyrmions in the tunnel junction region 20a. write This can drive skyrmions to migrate from the skyrmion storage region 20b to the tunnel junction region 20a.
[0038] I writeThe direction of the skyrmion and the direction of skyrmion movement are determined by the micromagnetic structure of the skyrmion and the spin Hall angle of the heavy metal layer 10. For example, for skyrmions with the same magnetic structure, when the same current is passed through the Pt and Ta heavy metal layers, the skyrmions move in opposite directions in the two cases.
[0039] The number of skyrmions remaining in the tunnel junction region 20a determines the conductance of the junction region. Different numbers of skyrmions will have different conductances, which can be expressed by I read read out, thereby achieving the synaptic write current I write Controlled variable synaptic weights.
[0040] The embodiments of the present invention will be further described below in combination with the motion law of skyrmions and the principle of tunnel junction conductance.
[0041] For a single skyrmion, the motion of its magnetic structure under the action of the spin current generated by SOT can be obtained by the LLG equation:
[0042]
[0043] Where m is the reduced magnetic moment, γ is the gyromagnetic ratio, and H eff is the total effective field, α is the damping coefficient of the magnetic free layer 20, M s is the saturation magnetic moment, μ B is the Bohr magneton, θ SH and t f are the spin Hall angle of the heavy metal layer 10 and the thickness of the magnetic free layer 20, respectively. e is the SOT current. Through calculations of the material system, it is found that the SOT effect will cause skyrmions to move along or against the direction of the SOT current, and the threshold current density that drives the skyrmion movement is 10 6 A / m 2 orders of magnitude, 10 times greater than that of the driving domain wall 10 A / m 2 The magnitude is much lower. The movement speed of skyrmions will be between 10 and 100 m / s, and the spin Hall angle will determine its direction. Therefore, the energy consumption of using skyrmions as the basis of the conductance state is much lower than that of using domain walls. Therefore, the energy consumed by the conductance change (i.e., the update of synaptic weights) of the skyrmion memristor-based device is much lower than that of the traditional memristor.
[0044] Assuming that the magnetic free layer 20 and the magnetic pinned layer 40 are completely antiparallel before initialization, their conductivity is G1, the internal magnetic moment of the skyrmion is parallel to the magnetic pinned layer 40, the area of the skyrmion is S, the number of skyrmions in the junction region is n, the area of the junction region is S0, and the conductivity when the magnetic free layer 20 and the magnetic pinned layer 40 are completely parallel is G2 (G2>G1). In addition, when the area of the skyrmion wall is small, the total conductance of the tunnel junction region 20a is regarded as the parallel magnetic moment region with an area of nS and the antiparallel magnetic moment region with an area of S0-nS in parallel. Then, the total conductance of the tunnel junction region 20a is calculated according to the following formula:
[0045]
[0046] From the above formula, it can be seen that the total conductance of the tunnel junction region 20a can be controlled by the number of skyrmions. Therefore, by selecting a suitable I write The amplitude and width control the number of skyrmions, and thus control the conductance, that is, update the synaptic weight of the spin memristor synaptic device, thereby obtaining a synaptic device with a relatively larger number of conductance states.
[0047] Example 2
[0048] This embodiment provides another skyrmion-based spin memristor synaptic device. Compared with Example 1, the barrier 60 located between the tunnel junction region 20a and the skyrmion storage region 20b in this embodiment is different from that in Example 1, and the remaining components are the same, so the same parts are not repeated in this embodiment.
[0049] See also Figure 4 In this embodiment, the barrier 60 between the tunnel junction region 20a and the skyrmion storage region 20b is a nanowire 60 disposed in the magnetic free layer 20, one end of the nanowire 60 is connected to the tunnel junction region 20a, and the other end is connected to the skyrmion storage region 20b. After the magnetic free layer 20 is prepared, the nanowire 60 is prepared in the magnetic free layer 20, for example, by a patterned etching process.
[0050] The line width of the nanowire 60 needs to be determined according to the size of the skyrmions 70 generated. The boundary effect can only allow a single skyrmion to pass through, and the skyrmions will be arranged and move in the nanowire 70. At the same time, due to the repulsive force between skyrmions, the skyrmions are blocked from entering the nanowire. In a preferred solution, the line width of the nanowire can be set to 20nm to 10μm.
[0051] As in Example 1, the write current pulse I writeThe skyrmions are driven to migrate between the tunnel junction region 20a and the skyrmion storage region 20b through the nanowire 70, thereby leaving different numbers of skyrmions in the tunnel junction region 20a. The number of skyrmions left in the tunnel junction region 20a determines the conductance of the junction region. Different numbers of skyrmions have different conductances, which can be expressed by I read read out, thereby achieving the synaptic write current I write Controlled variable synaptic weights.
[0052] The two skyrmion-based spin memristor synaptic devices provided in the above embodiments of the present invention both distinguish between the tunnel junction region and the skyrmion storage region, use STT current to complete the generation of skyrmions, and use SOT current to complete the migration of skyrmions, that is, the update of synaptic weights, to obtain a synaptic device with a relatively large number of conductance states. Among them, the generation of skyrmions and the reading of conductance states are the same path, the SOT current drives the movement of skyrmions, which has a lower current requirement than the driving domain wall movement, and the initialization current only needs to be once, which can greatly reduce the energy consumption of updating and reading the weight of the synaptic device, and its conductance state is also greatly increased. The spin memristor synaptic device of the embodiment of the present invention has non-volatility and high stability, and also has the characteristics of extremely low write and read energy consumption, a large number of conductance states, and easy control, which has great advantages as a neural network synaptic device.
[0053] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.
Claims
1. A skyrmion-based spin memristor synaptic device, characterized in that: include: There are heavy metal layers with spin Hall angles at both ports; A magnetic free layer located on the heavy metal layer; the magnetic free layer is divided into a tunnel junction region and a skyrmion storage region, and a barrier that hinders the free movement of skyrmions is provided between the tunnel junction region and the skyrmion storage region; An insulating barrier layer, a magnetic pinning layer and a metal top electrode are sequentially arranged on the tunnel junction region; The metal top electrode is configured to connect an initialization current to generate skyrmions in the tunnel junction region, the heavy metal layer is configured to connect a write current to drive skyrmions to move between the tunnel junction region and the skyrmion storage region, and the metal top electrode is further configured to connect a readout current to read the conductance of the tunnel junction region; The barrier is a nanowire disposed in the magnetic free layer, one end of the nanowire is connected to the tunnel junction region, and the other end is connected to the skyrmion storage region; the line width of the nanowire is set to allow only a single skyrmion to pass through under the action of its boundary.
2. The spin memristor synapse device according to claim 1, characterized in that: The line width of the nanowire is 20nm-10μm.
3. The spin memristor synapse device according to claim 1 or 2, characterized in that: The material of the heavy metal layer is Pt or Ta; the material of the magnetic free layer is CoFeB, Fe, [Co / Pt], FeB or Co; the material of the insulating barrier layer is MgO, TiO2, Al2O3 or MgAlO; the magnetic pinning layer includes a first magnetic layer, an antiferromagnetic coupling spacer layer and a second magnetic layer arranged in sequence from bottom to top, and the materials of the first magnetic layer and the second magnetic layer are respectively selected from Co, Fe, [Co / Pt], CoFeB, CoFe, FeB or NiFe, and the material of the antiferromagnetic coupling spacer layer is Ru or W; the material of the metal top electrode is Pt, Ta, Cr, Au or Ti.
4. The spin memristor synapse device according to claim 3, characterized in that: The thickness of the heavy metal layer is 2nm-10nm, the thickness of the magnetic free layer is 0.5nm-3nm, the thickness of the insulating barrier layer is 0.5nm-3nm, the thickness of the magnetic pinning layer is 2nm-10nm, and the thickness of the metal top electrode is 10nm-100nm.
5. The spin memristor synapse device according to claim 1 or 2, characterized in that: The heavy metal layer has the same width as the magnetic free layer, and the heavy metal layer extends from both ends of the magnetic free layer in the length direction.