Display panel and display device including the same

Abstract

A display panel and a display device including the display panel are provided. The display device includes a base substrate, a signal pad, an insulating layer and a first opening, the base substrate includes a display area including pixels and a pad area defining an end face of the base substrate that is farthest from the display area and exposed outside the display panel, the signal pad is located in the pad area on the base substrate and is electrically connected to the pixel and the dummy pad, the insulating layer is located in the display area and the pad area on the base substrate, the insulating layer covers the signal pad and the dummy pad in the pad area and defines an end face of the insulating layer that is farthest from the display area and exposed outside the display panel in the pad area, and the first opening is located in the insulating layer, and the first opening exposes the signal pad outside the insulating layer and outside the display panel. In the pad area, the end faces of the base substrate and the insulating layer together define the inclined edge of the display panel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2020-0040717, filed on Apr. 3, 2020, the entire contents of which are hereby incorporated by reference. Technical Field

[0003] The present disclosure relates to a display panel and a display device including the display panel, and in particular, to a display panel that reduces or effectively prevents pixel failure and a display device including the display panel. Background Art

[0004] Various display devices are being developed for multimedia devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles.

[0005] The display device includes a display panel that displays an image. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the plurality of gate lines and the plurality of data lines. The display panel is connected to electronic components outside the display panel and provides electrical signals for displaying images to the gate lines or the data lines. The electronic components are mounted on the display panel using an anisotropic conductive film or an ultrasonic inspection method. Summary of the invention

[0006] Embodiments provide a display panel and a display device including the display panel, which improve the reliability of electrical connection with an electronic component (eg, a circuit board) that supplies an electrical signal to the display panel from outside the display panel.

[0007] According to an embodiment, a display panel includes a base substrate, a signal pad, an insulating layer and a first opening, wherein the base substrate includes a display area including pixels and a pad area defining an end face of the base substrate that is farthest from the display area and exposed outside the display panel, the signal pad is located in the pad area on the base substrate and is electrically connected to the pixel and the dummy pad, the insulating layer is located in the display area and the pad area on the base substrate, the insulating layer covers the signal pad and the dummy pad in the pad area and defines an end face of the insulating layer that is farthest from the display area and exposed outside the display panel in the pad area, and the first opening is located in the insulating layer, and the first opening exposes the signal pad outside the insulating layer and outside the display panel. In the pad area, the end faces of the base substrate and the insulating layer together define an inclined edge of the display panel.

[0008] In an embodiment, in the thickness direction of the base substrate, the insulating layer includes a lower insulating layer, an intermediate insulating layer and an upper insulating layer, wherein the lower insulating layer is located between the base substrate and the dummy pad, the intermediate insulating layer is located between the lower insulating layer and the signal pad, and the upper insulating layer faces the intermediate insulating layer with the signal pad interposed therebetween, and the lower insulating layer, the intermediate insulating layer and the upper insulating layer respectively define respective end faces, and the respective end faces together define the end faces of the insulating layer.

[0009] In an embodiment, the signal pad may include a first signal pad and a second signal pad arranged in the first direction. The dummy pad may include a first dummy pad corresponding to the first signal pad and a second dummy pad corresponding to the second signal pad.

[0010] In an implementation, the intermediate insulating layer may include a first insulating layer and a second insulating layer on the first insulating layer, and the signal pad may be on the second insulating layer.

[0011] In an implementation, the first and second dummy pads may be located on the lower insulating layer and may be electrically connected to the first and second signal pads, respectively.

[0012] In an embodiment, the display panel may further include a first connection pad and a second connection pad on the first insulating layer. The first connection pad may connect the first signal pad to the first dummy pad, and the second connection pad may connect the second signal pad to the second dummy pad.

[0013] In an implementation, the upper insulating layer may be defined with a second opening therein, and the second opening may be located between the first dummy pad and the second dummy pad in the first direction. The display panel may further include a dummy insulating pattern located in the second opening.

[0014] In an implementation, the dummy insulation pattern may protrude from the upper insulation layer.

[0015] In an implementation, the upper insulating layer may be located between the first signal pad and the second signal pad in the first direction.

[0016] In an embodiment, the first dummy pad, the second dummy pad, and the dummy insulating pattern may extend in an oblique direction crossing the first direction. The length of each of the first and second dummy pads in the oblique direction may be greater than the length of the dummy insulating pattern.

[0017] In an embodiment, the dummy pad may define a surface of the dummy pad exposed outside the display panel, and in the pad region, the surfaces of the base substrate, the insulation layer, and the dummy pad together define an inclined edge of the display panel.

[0018] In an implementation, a height difference between a top surface of the dummy insulation pattern and a top surface of the upper insulation layer in a thickness direction of the base substrate may be in a range of about 0.1 micrometers (μm) to about 0.5 μm.

[0019] In an implementation, the pad region may include a first region where the signal pad is arranged and a second region adjacent to the first region in a first direction. The first opening may be defined in the first region, and the second opening may be defined in the second region.

[0020] In an implementation, a width of a top surface of the signal pad exposed by the first opening and measured in the first direction may be greater than a width of a top surface of the dummy insulation pattern measured in the first direction.

[0021] In an implementation, the signal pad may extend in an oblique direction crossing the first direction. A portion of the upper insulating layer in the pad region may overlap the dummy pad.

[0022] According to an embodiment, a display device may include a display panel, an electronic component and a conductive adhesive film, wherein the display panel includes a display area including pixels and a pad area adjacent to the display area and defining an inclined edge of the display panel that is farthest from the display area and exposed outside the display panel, the electronic component is connected to the display panel at the pad area of ​​the display panel, and the conductive adhesive film electrically connects the electronic component to the display panel at the pad area of ​​the display panel. The display panel includes a base substrate, a signal pad, a dummy pad, an insulating layer and a first opening, wherein the base substrate defines an end face of the base substrate that is farthest from the display area and exposed outside the display panel, the signal pad is located in the pad area on the base substrate and is electrically connected to the pixel, the dummy pad is located in the pad area on the base substrate and is electrically connected to the signal pad, the insulating layer is located in the display area and the pad area on the base substrate, the insulating layer covers the signal pad and the dummy pad in the pad area and defines an end face of the insulating layer that is farthest from the display area and exposed outside the display panel in the pad area, and the first opening is located in the insulating layer, and the first opening exposes the signal pad outside the insulating layer and outside the display panel. In the pad area, the end face of the base substrate and the end face of the insulating layer together define the inclined edge of the display panel.

[0023] In an embodiment, the pad area may include a first area where a signal pad is arranged and a second area adjacent to the first area in a first direction. The electronic component includes a plurality of protrusions directly contacting the pad area of ​​the display panel and a plurality of gaps respectively located between the plurality of protrusions. The plurality of protrusions may overlap with the first area, and the plurality of gaps may overlap with the second area.

[0024] In an implementation, the plurality of protrusions may contact the signal pad.

[0025] In an embodiment, the signal pad may include a first signal pad and a second signal pad arranged in the first direction. The dummy pad may include a first dummy pad corresponding to the first signal pad and a second dummy pad corresponding to the second signal pad.

[0026] In an implementation, the upper insulating layer may have a second opening defined therein, and the second opening may be located between the first dummy pad and the second dummy pad in the first direction. The display device may further include a dummy insulating pattern located in the second opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings represent non-limiting embodiments as described herein.

[0028] Figure 1 is a plan view showing an embodiment of a display device.

[0029] Figure 2A is a cross-sectional view showing an embodiment of a display device.

[0030] Figure 2B is along Figure 2A An enlarged cross-sectional view taken along line V-V'.

[0031] Figure 2C is an enlarged cross-sectional view showing an embodiment of a display panel.

[0032] Figure 3 It is shown Figure 1 An enlarged top view of portion AA'.

[0033] Figure 4 is an enlarged top view showing an embodiment of a pad area of ​​a display panel.

[0034] FIG. 5A to FIG. 5C is an enlarged cross-sectional view showing an embodiment of a pad area of ​​a display panel.

[0035] Figure 6 is an enlarged cross-sectional view showing an embodiment of a pad area.

[0036] Figure 7 is an enlarged cross-sectional view showing an embodiment of a pad area.

[0037] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures and / or materials used in the embodiments, and are intended to supplement the written description provided below. However, these drawings are not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment, and should not be interpreted as limiting or restricting the range of values ​​or properties covered by the embodiments. For example, for clarity, the relative thickness and position of molecules, layers, regions and / or structural elements may be reduced or exaggerated. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0038] The embodiments will now be described more fully with reference to the accompanying drawings showing the embodiments. However, the embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that the disclosure will be thorough and complete and the embodiments will be fully communicated to those of ordinary skill in the art. In the accompanying drawings, the thickness of layers and regions is exaggerated for clarity. Similar reference numerals in the drawings represent similar elements, and therefore their description will be omitted.

[0039] It will be understood that when an element is referred to as being associated with another element, such as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being associated with another element, such as being "directly connected to" or "directly coupled to" another element, there are no intervening elements. Other words used to describe the relationship between elements or layers should be interpreted in the same manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," "on" versus "directly on").

[0040] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part without departing from the teachings of the embodiments.

[0041] Spatially relative terms such as "beneath", "below", "lower", "above", and "upper" may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. It will be understood that in addition to the orientations shown in the figures, spatially relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, the elements described as being "below" or "beneath" other elements or features will subsequently be oriented as being "above" other elements or features. Therefore, the exemplary term "below" can cover both the orientations of above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0042] The terms used herein are for the purpose of describing the embodiments only, and are not intended to limit the embodiments. Unless otherwise clearly indicated in the context, the singular forms "a", "an" and "the" as used herein are also intended to include plural forms. For example, unless otherwise clearly indicated in the context, "element" has the same meaning as "at least one element". "At least one" is not interpreted as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that if the terms "comprise", "comprising", "include" and / or "including" are used in this article, the existence of the stated features, integers, steps, operations, elements and / or parts is indicated, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or their clusters is not excluded.

[0043] Embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be anticipated. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

[0044] As used herein, "about" or "approximately" includes the stated value and the mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the embodiments belong. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense.

[0046] Figure 1 is a plan view showing an embodiment of the display device 100 . Figure 2A is a cross-sectional view showing an embodiment of the display device 100 . Figure 2A is along Figure 1 A cross-sectional view taken along line II'.

[0047] Reference Figure 1 and Figure 2A , the display device 100 may include a display panel 110, an electronic component 120, and a conductive adhesive film 140 (e.g., a conductive adhesive layer or a conductive adhesive pattern). The display device 100 may include a main circuit board 130 electrically connected to the electronic component 120 through the conductive adhesive film 140. In an embodiment, the electronic component 120 may include one or more of a flexible circuit board 122 (e.g., a circuit board) and a data driving circuit 125 (e.g., a driving chip).

[0048] The display panel 110 may include a display area DA provided with pixels PX and a non-display area NDA adjacent to the display area DA. The pixels PX may be provided in plurality in the display area DA to include a plurality of pixels PX. A pad area PA may be defined in the non-display area NDA, and a pad electrode to be described below may be arranged in the pad area PA. In an embodiment, the display panel 110 may include a mounting area MA in which an electronic component 120 is arranged. The electronic component 120 may be coupled to the display panel 110 at the mounting area MA of the display panel 110 through a conductive adhesive film 140.

[0049] In an embodiment, the non-display area NDA and the mounting area MA may not be distinguished from each other. The mounting area MA may be a part of the non-display area NDA. The pad area PA may be defined as a part of the mounting area MA. That is, the non-display area NDA may include both the mounting area MA and the pad area PA. The pad area PA will be described in more detail below. One or more of the various components of the display device 100 may include a display area DA, a non-display area NDA, a mounting area MA and / or a pad area PA corresponding to those described above.

[0050] Reference Figure 1 , the display panel 110 may generate and / or display an image by applying a driving signal (e.g., an electrical signal) to a plurality of pixels PX. The pixels PX may be arranged along a first direction A1 and a second direction A2 intersecting the first direction A1. The pixels PX may be arranged in a matrix shape within the display area DA, but are not limited thereto. The first direction A1 and the second direction A2 may be perpendicular to each other, but are not limited thereto. In an embodiment, the plurality of pixels PX may include a first pixel R, a second pixel G, and a third pixel B that display red, green, and blue, respectively. In an embodiment, the plurality of pixels PX may also include a pixel PX that displays at least one of white, cyan, and magenta.

[0051] Each of the plurality of pixels PX may include a display element or a light emitting element such as an organic light emitting diode and a driving circuit GDC connected thereto. The driving circuit GDC and the signal line SGL may include Figure 2A The circuit device layer DP-CL shown in FIG.

[0052] The drive circuit GDC may include a scan drive circuit. The scan drive circuit may generate a plurality of scan signals as electrical signals, and may sequentially output the scan signals to the scan lines GL provided as a plurality to include a plurality of scan lines GL described below. In addition, the scan drive circuit may output other electrical signals as control signals to the pixel drive circuit of the pixel PX.

[0053] The scan drive circuit may include a plurality of thin film transistors, wherein a portion or layer of the plurality of thin film transistors is provided or formed by the same method as a portion or layer of a pixel drive circuit of the pixel PX. In an embodiment, a plurality of thin film transistors and / or a portion or layer of a pixel drive circuit may be provided by a low-temperature polycrystalline silicon (LTPS) or low-temperature polycrystalline silicon oxide (LTPO) process.

[0054] The signal line SGL may include a scan line GL provided in plurality to include a plurality of scan lines GL, a data line DL provided in plurality to include a plurality of data lines DL, a power line PL, and a control signal line CSL. Each of the plurality of scan lines GL may be connected to a corresponding one of the plurality of pixels PX, and each of the plurality of data lines DL may be connected to a corresponding one of the plurality of pixels PX. The power line PL may be connected to a pixel PX (such as each of the plurality of pixels PX), but is not limited thereto. The control signal line CSL may provide a control signal to the scan driving circuit.

[0055] The plurality of signal lines SGL may overlap or correspond to both the display area DA and the non-display area NDA. Each of the plurality of signal lines SGL may include a pad portion and a line portion. The line portion may overlap the display area DA and the non-display area NDA. In one of the plurality of signal lines SGL, the pad portion may be connected to an end of the line portion. The pad portion of the signal line SGL may be arranged in the non-display area NDA and may overlap with a corresponding one of the plurality of signal pads SD. The area of ​​the non-display area NDA where the signal pad SD is arranged may be defined as a pad area PA. This will be described in more detail below.

[0056] Based on the structure of the pixel PX, the display panel 110 may be classified as a liquid crystal display panel, an organic field emission display panel, an electrowetting display panel, etc. In an embodiment, the display panel 110 may be an organic field emission display panel.

[0057] like Figure 2A As shown in , the display panel 110 may include a base substrate BL and a circuit device layer DP-CL, a display device layer DP-OLED, and an encapsulation layer TFL arranged on the base substrate BL. The circuit device layer DP-CL, the display device layer DP-OLED, and the encapsulation layer TFL may be arranged sequentially from the base substrate BL, but are not limited thereto. As used herein, the expression "a region / portion corresponds to another region / portion" means that the regions / portions (for example, along the third direction A3) overlap with each other, but are not limited to having the same plane area and / or the same plane shape as each other.

[0058] The base substrate BL may include a synthetic resin material such as a synthetic resin film.The base substrate BL may include a glass substrate, a metal substrate, or a substrate including or made of an organic / inorganic composite material.

[0059] The circuit device layer DP-CL may include at least one insulating layer and a circuit device. The insulating layer may include at least one inorganic material layer and at least one organic material layer. The circuit device may include a signal line SGL and a pixel driving circuit, etc.

[0060] The display device layer DP-OLED may include an emission device such as an organic light emitting diode used as the emission device. The display device layer DP-OLED may further include an organic material layer such as a pixel defining layer.

[0061] The encapsulation layer TFL may include a plurality of thin films, some of which may be provided to improve optical efficiency, and others of which may be provided to protect the organic light emitting diode.

[0062] like Figure 1 As shown in the figure, a black matrix (not shown) that blocks light may be arranged in the non-display area NDA. A driving circuit GDC that provides a gate signal as an electrical signal to the pixel PX may be provided in the non-display area NDA. In an embodiment, a data driving circuit 125 may also be provided in the non-display area NDA. A pad area PA for receiving an electrical signal from the electronic component 120 may be defined in the mounting area MA.

[0063] like Figure 1 and Figure 2A As shown in FIG. 1 , the electronic component 120 may include a flexible circuit board 122 and a data driving circuit 125. The data driving circuit 125 may include a driving chip. The data driving circuit 125 may be electrically connected to interconnection lines (eg, wires) of the flexible circuit board 122.

[0064] In the case where the electronic component 120 includes the data driving circuit 125, the pad portion of the display panel 110 may include a data pad electrically connected to the data line DL and a control signal pad electrically connected to the control signal line CSL. The data line DL may be connected to the pixel PX, and the control signal line CSL may be connected to the driving circuit GDC. In an embodiment, the electronic component 120 is shown as having a chip-on-film structure, but is not limited to this example.

[0065] The main circuit board 130 may provide image data, control signals, power supply voltage, etc. to the display panel 110 and / or the data driving circuit 125. The main circuit board 130 may be an interconnect substrate having a larger plane area than the flexible circuit board 122, and may include at least one of an active device and a passive device. The main circuit board 130 may be a flexible interconnect substrate or a rigid interconnect substrate, and may include a pad portion (not shown) at which the main circuit board 130 is connected to the flexible circuit board 122.

[0066] Figure 2B is along Figure 2A An enlarged cross-sectional view taken along line V-V'.

[0067] Reference Figure 2A and Figure 2B, the electronic component 120 may include a protrusion LD provided in plurality to include a plurality of protrusions LD and a gap portion SP provided in plurality to include a plurality of gap portions SP between the protrusions LD adjacent to each other. In an embodiment, the protrusion LD and the gap portion SP may extend from the flexible circuit board 122. A portion of the flexible circuit board 122 may be exposed outside the protrusion LD to define an exposed portion of the flexible circuit board 122.

[0068] The flexible circuit board 122 may correspond to the electronic component 120 disposed on the display panel 110 and connected to the display panel 110. Figure 2A and Figure 2B , the protrusion LD may be in direct contact with the display panel 110 at the pad area PA of the display panel 110. Due to the direct contact, the elements may form an interface with each other, but are not limited thereto. In detail, the protrusion LD may be attached to the circuit device layer DP-CL of the display panel 110. The protrusion LD may be in contact with the pad electrode of the circuit device layer DP-CL. The protrusion LD may electrically connect the electronic component 120 to the display panel 110. That is, the display panel 110 may be electrically connected to the electronic component 120 at the protrusion LD of the electronic component 120. In an embodiment, the protrusion LD may be conductive to electrically connect the electronic component 120 to the display panel 110.

[0069] The conductive adhesive film 140 may be arranged between the electronic component 120 and the display panel 110. In the pad area PA, the conductive adhesive film 140 may be arranged between the electronic component 120 and the circuit device layer DP-CL. The conductive adhesive film 140 may include a plurality of conductive members, such as a plurality of conductive balls 142, that electrically connect the electronic component 120 to the display panel 110. When the display panel 110 is electrically connected to the electronic component 120, the plurality of conductive balls 142 may be aligned with each other in the first direction A1. The conductive adhesive film 140 may include a base layer (in Figure 2B ” indicated in “140”) and conductive balls 142 arranged in the base layer.

[0070] Figure 2C is a cross-sectional view showing an embodiment of the display panel 110 . Figure 2C is along Figure 1 A cross-sectional view taken along line O-O'.

[0071] Figure 2C FIG. 1 is a cross-sectional view of a display area DA of the display panel 110. Referring to FIG. Figure 2C, the display panel 110 may include a buffer layer BFL, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer ILD, an upper insulating layer VIA1, a semiconductor layer including a semiconductor pattern ACP provided in plurality to include a plurality of semiconductor patterns ACP, a first conductive layer GMP1, a second conductive layer GMP2, and a third conductive layer DMP1. Here, the first conductive layer GMP1 may include a plurality of first gate metal patterns, the second conductive layer GMP2 may include a plurality of second gate metal patterns, and the third conductive layer DMP1 may include a plurality of first data metal patterns.

[0072] In an embodiment, each of the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD may include an organic material layer and / or an inorganic material layer. In an embodiment, each of the first gate insulating layer GI1, the second gate insulating layer GI2, and the first insulating layer ILD1 may include a plurality of inorganic material layers. The inorganic material layer may include a silicon nitride layer and a silicon oxide layer. In an embodiment, each of the first conductive layer GMP1 and the second conductive layer GMP2 may be formed of or include molybdenum (Mo), but is not limited thereto.

[0073] In an embodiment, the third conductive layer DMP1 may be formed of or include at least one of aluminum (Al) and titanium (Ti), but is not limited thereto. In an embodiment, the third conductive layer DMP1 may have a structure in which titanium, aluminum, and titanium layers are sequentially stacked.

[0074] The buffer layer BFL may be disposed on the base substrate BL. The buffer layer BFL may include a first buffer layer and a second buffer layer. The second buffer layer may face the base substrate BL with the first buffer layer interposed therebetween. The buffer layer BFL may reduce or effectively prevent contamination materials from entering the pixel PX from the base substrate BL. In particular, the buffer layer BFL may reduce or effectively prevent contamination materials from diffusing into the semiconductor pattern ACP of the first transistor T1 and the second transistor T2 within the pixel PX.

[0075] The contamination material may be supplied from outside the display panel 110 or may be generated when the base substrate BL is heat-treated in a process of providing the display device 100. The contamination material may be a gaseous material or sodium exhausted from the base substrate BL. In addition, the buffer layer BFL may reduce or effectively prevent external moisture from entering the pixel PX.

[0076] The semiconductor pattern ACP may be disposed on the buffer layer BFL. In an implementation, the semiconductor pattern ACP may face the base substrate BL with the buffer layer BFL interposed therebetween.

[0077] The semiconductor layer including the semiconductor pattern ACP may provide corresponding portions of the first transistor T1 and the second transistor T2. The semiconductor pattern ACP may be formed of or include at least one of polycrystalline silicon, amorphous silicon, and a metal oxide semiconductor material. In an embodiment, for example, Figure 2C As shown in FIG. 1 , the semiconductor pattern ACP may provide a first source region S1 , a first active region C1 , and a first drain region D1 of the first transistor T1 , and a second source region S2 , a second active region C2 , and a second drain region D2 of the second transistor T2 .

[0078] The first gate insulating layer GI1 may be disposed on the buffer layer BFL to cover the semiconductor pattern ACP. The first conductive layer GMP1 may be disposed on the first gate insulating layer GI1. The first gate G1 of the first transistor T1 and the second gate G2 of the second transistor T2 are shown as corresponding portions of the first conductive layer GMP1. In an embodiment, although not shown, the corresponding portion of the first conductive layer GMP1 may include or provide one of the two electrodes constituting the capacitor of the pixel PX.

[0079] The second gate insulating layer GI2 may be disposed on the first gate insulating layer GI1 to cover the first conductive layer GMP1. The second conductive layer GMP2 may be disposed on the second gate insulating layer GI2. In an embodiment, a corresponding portion of the second conductive layer GMP2 may include or provide the other of the two electrodes constituting the capacitor of the pixel PX. The upper electrode UE is shown as a corresponding portion of the second conductive layer GMP2.

[0080] The interlayer insulating layer ILD may be disposed on the second gate insulating layer GI2 to cover the second conductive layer GMP2. The first connection electrode CNE-D1 may be provided in plurality on the interlayer insulating layer ILD to include a plurality of first connection electrodes CNE-D1. The first connection electrode CNE-D1 of the third conductive layer DMP1 may be connected to the second source region S2 of the second transistor T2. The upper insulating layer VIA1 may be disposed on the interlayer insulating layer ILD to cover the third conductive layer DMP1.

[0081] Reference Figure 2C In the display area DA, the emission device layer ELL may include an emission device ED (e.g., a light emitting device) and a planarization layer PDL. The emission device ED may include an anode AE, an emission layer EML, and a cathode CE. In the emission device ED, a first electrode may face a second electrode with the emission device layer ELL interposed therebetween. The planarization layer PDL may correspond to a pixel defining layer.

[0082] The emission device layer ELL may be disposed on the upper insulating layer VIA1. The anode AE ​​may be electrically connected to the third conductive layer DMP1 through a contact hole defined in the planarization layer PDL. The planarization layer PDL may be disposed on the upper insulating layer VIA1 to expose at least a portion of the anode AE ​​outside the planarization layer PDL. The emission layer EML may be disposed on the anode AE. The cathode CE may face the anode AE ​​with the emission layer EML interposed therebetween.

[0083] In the case where the emission device ED is an organic light emitting diode (OLED), the emission layer EML may be formed of or include an organic material. In the case where the emission device ED is a micro light emitting diode (LED), the emission layer EML may be formed of or include an inorganic material. The encapsulation layer TFL may hermetically seal the emission device layer ELL and may protect the emission device layer ELL from external oxygen or moisture. The encapsulation layer TFL may include at least one of an organic material layer and an inorganic material layer.

[0084] Figure 3 It is shown Figure 1 An enlarged top view of an embodiment of portion AA'.

[0085] Reference Figure 3 , the display panel 110 may include a pad area PA. The pad area PA may be defined in a portion of the mounting area MA. The display panel 110 may include a signal pad SD and a dummy pad GE1. The signal pad SD and the dummy pad GE1 may be arranged in the pad area PA. An electrical signal from outside the display panel 110 may be provided to the display panel 110 through the signal pad SD and / or the dummy pad GE1.

[0086] Reference Figures 1 to 3 , the flexible circuit board 122 of the electronic component 120 can be electrically connected to the display panel 110 at the pad area PA of the display panel 110 through the conductive adhesive film 140. In addition, the pad portion (not shown) of the main circuit board 130 may include a pad corresponding to the protrusion LD of the flexible circuit board 122. The input pad portion (not shown) of the flexible circuit board 122 and the pad portion (not shown) of the main circuit board 130 can also be connected to each other through the conductive adhesive film 140. The conductive adhesive film 140 may be an anisotropic conductive film (ACF). In an embodiment, the conductive adhesive film 140 may be replaced by a solder bump.

[0087] The protrusion LD of the flexible circuit board 122 may be electrically connected to the display panel 110 at the pad area PA of the display panel 110 through the conductive adhesive film 140. The conductive adhesive film 140 may include conductive balls 142. When the conductive adhesive film 140 between the flexible circuit board 122 and the display panel 110 is compressed, the conductive balls 142 aligned in the first direction A1 may electrically connect the protrusion LD of the flexible circuit board 122 to the display panel 110.

[0088] The pad area PA of the display panel 110 has a flat structure. The pad area PA may be arranged parallel to a plane defined by a first direction A1 and a second direction A2 intersecting each other. Therefore, the conductive balls 142 may be uniformly aligned and compressed along the first direction A1 and / or the second direction A2 without being gathered together.

[0089] Refer again Figure 2B , the pad area PA may include a first area LA and a second area SA. The protrusion LD may overlap with the plane area of ​​the first area LA, and the gap portion SP may overlap with the plane area of ​​the second area SA. The signal pad SD may be arranged in the pad area PA of the display panel 110. In an embodiment, a plurality of signal pads SD may be provided. The first area LA may be a plane area for electrically connecting the display panel 110 and the electronic component 120 to each other.

[0090] Reference Figure 3 , the display panel 110 may include a signal pad SD and a dummy pad GE1 provided in the pad area PA. The signal pad SD may be electrically connected to the electronic component 120 through the conductive adhesive film 140. The dummy pad GE1 may be connected to the signal pad SD through a contact hole and may extend to the edge EZ of the display panel 110 (for example, see Figure 5A ).

[0091] The edge EZ of the display panel 110 may correspond to the outermost area of ​​the mounting area MA of the display panel 110 along the second direction A2. The edge EZ may extend along the first direction A1. The outermost area may be farthest from the display area DA along the second direction A2. Ends or end surfaces of various layers within the display panel 110 may define corresponding parts of the edge EZ. The edge EZ may be a collection of ends or end surfaces. Ends or end surfaces of various layers may be exposed outside the display panel 110 at the edge EZ of the display panel 110. In an embodiment, a monitoring device for monitoring the operating state of the signal pad SD may be connected to the dummy pad GE1.

[0092] In an embodiment, the conductive adhesive film 140 may completely overlap the pad area PA. In the pad area PA, the plurality of conductive balls 142 may be pressed not only against the signal pad SD but also against the area corresponding to the dummy pad GE1. According to an embodiment, the display panel 110 may be provided with a cross-section that minimizes or effectively prevents agglomeration or aggregation of the conductive balls 142 caused by the conductive balls 142 being pressed against the area corresponding to the dummy pad GE1.

[0093] Figure 4 is an enlarged top view showing an embodiment of the pad area PA of the display panel 110 . Figure 4 It is shown Figure 3 An enlarged top view of portion BB'. Figure 4 The planar structure of the signal pads SD arranged in a portion of the pad area PA is schematically shown. FIG. 5A to FIG. 5C The stacking structure in the cross-sectional view is described in more detail.

[0094] Reference Figure 4 , the first area LA may include a plane area defined by a size along the first direction A1 and the second direction A2. The signal pad SD and the dummy pad GE1 electrically connected to each other may be arranged in the pad area PA of the display panel 110. The signal pad SD and the dummy pad GE1 may be arranged in the first area LA. The dummy pad GE1 may be connected to the signal pad SD through a contact hole, and may be arranged in the first area LA along the second direction A2 to be farther away from the display area DA than the signal pad SD. The dummy pad GE1 may be connected to the signal pad SD through a connecting pad GE2. The connecting pad GE2 may be arranged between the signal pad SD and the dummy pad GE1 along the thickness direction of the signal pad SD (for example, along the third direction A3). In more detail, the dummy pad GE1 may be electrically connected to the connecting pad GE2 through the first contact hole CH1. The connecting pad GE2 may be electrically connected to the signal pad SD through the second contact hole CH2.

[0095] The plurality of signal pads SD may include first signal pads SD1 and second signal pads SD2 arranged spaced apart from each other along a first direction A1 (i.e., along a length direction of the edge EZ). The lengths of the first signal pads SD1 and the second signal pads SD2 may extend in an oblique direction (e.g., an inclined direction) intersecting the first direction A1. The angle between the oblique direction and the second direction A2 may be smaller than the angle between the oblique direction and the first direction A1.

[0096] The plurality of dummy pads GE1 may include a first dummy pad GE1-1 corresponding to the first signal pad SD1 and a second dummy pad GE1-2 corresponding to the second signal pad SD2. The second dummy pad GE1-2 is spaced apart from the first dummy pad GE1-1 in the first direction A1. The first dummy pad GE1-1 may be connected to an end of the first signal pad SD1 that is closest to the edge EZ along the second direction A2, and the second dummy pad GE1-2 may be connected to an end of the second signal pad SD2 that is closest to the edge EZ along the second direction A2. The plurality of connecting pads GE2 may include a first connecting pad GE2-1 and a second connecting pad GE2-2. The first connecting pad GE2-1 may electrically connect the first signal pad SD1 to the first dummy pad GE1-1, and the second connecting pad GE2-2 may electrically connect the second signal pad SD2 to the second dummy pad GE1-2. Reference Figure 5A and Figure 5B , for example, along the thickness direction of the base substrate BL, the first connection pad GE2-1 and the second connection pad GE2-2 are each located between the first insulating layer and the second insulating layer of the intermediate insulating layer 2IL.

[0097] Reference Figure 4 , the display panel 110 may include an upper insulating layer VIA1 and a dummy insulating pattern VIA2 provided in the pad area PA. A portion of the upper insulating layer VIA1 in the second area SA may be arranged between the first signal pad SD1 and the second signal pad SD2, and a portion of the upper insulating layer VIA1 in the first area LA may overlap with the first dummy pad GE1-1 and the second dummy pad GE1-2 and may be arranged between the dummy insulating pattern VIA2. The dummy insulating pattern VIA2 may overlap with the second area SA. The dummy insulating pattern VIA2 may be arranged between the first dummy pad GE1-1 and the second dummy pad GE1-2.

[0098] In an embodiment, the first dummy pad GE1-1, the second dummy pad GE1-2 and / or the dummy insulation pattern VIA2 may extend longitudinally in an oblique direction intersecting the first direction A1. The oblique direction may be a direction between the first direction A1 and the second direction A2. In an embodiment, the length of the first dummy pad GE1-1 and the second dummy pad GE1-2 along the oblique direction may be greater than the length of the dummy insulation pattern VIA2 taken along the oblique direction.

[0099] Will refer to Figure 2C describe Figure 4The dummy pad GE1 may be referred to as a first gate electrode GE1. The first gate electrode GE1 in the pad area PA of the display panel 110 and the first conductive layer GMP1 in the display area DA may be corresponding parts of the same material layer on the base substrate BL. The first gate electrode GE1, the first gate G1 of the first transistor T1, and the second gate G2 of the second transistor T2 may be corresponding parts of the same material layer on the base substrate BL.

[0100] The connection pad GE2 may be referred to as a second gate electrode GE2. The second gate electrode GE2 in the pad area PA and the second conductive layer GMP2 in the display area DA may be corresponding parts of the same material layer on the base substrate BL. The second gate electrode GE2 in the pad area PA and the upper electrode UE in the display area DA may be corresponding parts of the same material layer on the base substrate BL.

[0101] The signal pad SD in the pad area PA and the first connection electrode CNE-D1 in the display area DA may be corresponding parts of the same material layer on the base substrate BL. FIG. 5A to FIG. 5C The stack structure in the pad area PA is described.

[0102] FIG. 5A to FIG. 5C is an enlarged cross-sectional view showing an embodiment of the pad area PA of the display panel 110 .

[0103] Figure 5A is along Figure 4 An enlarged cross-sectional view taken along line II-II'. Figure 5A is a diagram illustrating a zone (eg, an end portion or an edge portion of the display panel 110 ) where an edge EZ of the pad area PA is provided.

[0104] Reference Figure 5A , in the pad area PA, the display panel 110 may include a base substrate BL, a buffer layer BFL, a first gate insulating layer GI1, a second gate insulating layer GI2, and a portion of an upper insulating layer VIA1. In an embodiment, the display panel 110 may include an interlayer insulating layer ILD. The upper insulating layer VIA1 may include an organic material layer. In an embodiment, for example, the upper insulating layer VIA1 may be formed of or include polyimide (PI).

[0105] Hereinafter, a structure including a buffer layer BFL and a first gate insulating layer GI1 may be referred to as a lower insulating layer 1IL. A structure including a second gate insulating layer GI2 and an interlayer insulating layer ILD may be referred to as an intermediate insulating layer 2IL. In detail, the intermediate insulating layer 2IL may include a first insulating layer and a second insulating layer arranged on the first insulating layer, and the first insulating layer and the second insulating layer may correspond to the second gate insulating layer GI2 and the interlayer insulating layer ILD, respectively. Along the thickness direction of the base substrate BL, the intermediate insulating layer 2IL includes a first insulating layer and a second insulating layer in order from the lower insulating layer 1IL to the signal pad SD.

[0106] More than one of the lower insulating layer 1IL, the intermediate insulating layer 2IL, and the upper insulating layer VIA1 may be collectively referred to as an insulating layer. In the pad area PA, the insulating layer covers each of the signal pad SD and the dummy pad GE1. In an embodiment, one or more of the base substrate BL, the insulating layer, and the dummy pad GE1 define an end face that is farthest from the display area DA and exposed to the outside of the display panel 110. The end faces together define an edge EZ (e.g., a slanted edge) of the display panel 110.

[0107] The dummy pad GE1 may be arranged on the lower insulating layer 1IL. The dummy pad GE1 may face the base substrate BL with the lower insulating layer 1IL interposed therebetween. The dummy pad GE1 may extend to the edge EZ in the pad area PA, and may have a side surface positioned at the edge EZ and exposed outside the display panel 110 to define an exposed side surface of the dummy pad GE1. The edge EZ of the display panel 110 may have an inclined shape from the upper insulating layer VIA1 to the base substrate BL relative to a plane defined by the first direction A1 and the second direction A2 intersecting each other. In an embodiment, the display panel 110 may have a continuous inclined surface as an edge EZ located in the pad area PA and extending from the end surface of the upper insulating layer VIA1 to the end surface of the base substrate BL in the second direction A2. The exposed side surface of the dummy pad GE1 may constitute a part of the inclined surface. Here, the expression "continuous" may be used to indicate that there is no stepped structure between adjacent layers in the area from the upper insulating layer VIA1 to the base substrate BL. In other words, the continuous inclined surface may correspond to a linear inclined surface that makes the corresponding side surfaces of the layers coplanar with each other. Although a linear inclined surface is shown, the inclined surface may be provided to have a bent shape. The display panel 110 may include an edge EZ defined by the inclined surface, and the upper insulating layer VIA1 may extend to the edge EZ.

[0108] The connection pad GE2 may be disposed in the intermediate insulating layer 2IL. In detail, the connection pad GE2 may be disposed on the second gate insulating layer GI2. The first contact hole CH1 may be defined in the second gate insulating layer GI2.

[0109] The signal pad SD may be disposed on the intermediate insulating layer 2IL and may be partially covered by the upper insulating layer VIA1. In detail, the signal pad SD may be disposed on the interlayer insulating layer ILD. The second contact hole CH2 may be defined in the interlayer insulating layer ILD.

[0110] Figure 5B is along Figure 4 An enlarged cross-sectional view taken along line III-III'. Figure 5B is an enlarged cross-sectional view showing a non-display area NDA of the signal pad SD.

[0111] Reference Figure 5B , the pad area PA may be defined in the display panel 110 and may include a first area LA and a second area SA.

[0112] The display panel 110 may include a signal pad SD arranged on the interlayer insulating layer ILD. A portion of the signal pad SD may be exposed outside the upper insulating layer VIA1 and thus may be electrically connected to the electronic component 120 through the conductive adhesive film 140. The signal pad SD may overlap the first area LA. In an embodiment, the signal pad SD may be provided in plurality. A portion of the upper insulating layer VIA1 may be arranged between the signal pads SD along the first direction A1. In an embodiment, a portion of the upper insulating layer VIA1 may be arranged between the first signal pad SD1 and the second signal pad SD2.

[0113] The upper insulating layer VIA1 may be arranged on the intermediate insulating layer 2IL and may overlap both the display area DA and the pad area PA. A first opening OP1 may be defined in the upper insulating layer VIA1 to expose the signal pad SD outside the display panel 110. The first opening OP1 may overlap the first area LA. In an embodiment, the first opening OP1 may be provided in plurality so as to include a plurality of first openings OP1 corresponding to the plurality of signal pads SD, respectively. The upper insulating layer VIA1 may be divided into a plurality of upper insulating layer patterns by the plurality of first openings OP1. A portion of the upper insulating layer VIA1 may overlap the second area SA. The portion of the upper insulating layer VIA1 overlapping the second area SA may have a first width W1 in the range of about 12 micrometers (μm) to about 16 μm. The first width W1 may be the maximum size of the portion of the upper insulating layer VIA1 between the signal pads SD adjacent to each other.

[0114] The second thickness TH2 of the upper insulating layer VIA1 at the first area LA (eg, see Figure 5C ) may be in the range of about 0.6 μm to about 1.0 μm. In an embodiment, the second thickness TH2 may be about 0.8 μm. As used herein, the thickness of an element may be the maximum dimension of the element along a direction parallel to the third direction A3, and may correspond to the thickness of the element measured in the thickness direction of the base substrate BL.

[0115] Refer again Figure 5B , the upper insulating layer VIA1 may overlap the second area SA. The upper insulating layer VIA1 may cover a gap area between the signal pads SD adjacent to each other. Figure 5A , the upper insulating layer VIA1 may cover the end of the signal pad SD. In an embodiment, a third distance W3 (e.g., a third width) between adjacent signal pads SD may be in a range of about 4 μm to about 5 μm. The third distance W3 may be a minimum distance between adjacent signal pads SD. The width portion of the signal pad SD exposed by the first opening OP1 may have a second width W2 in a range of about 9 μm to about 12 μm.

[0116] like Figure 5B As shown in , the connection pad GE2 may overlap the first area LA and may be arranged on the second gate insulating layer GI2. The maximum width of the connection pad GE2 taken along the base substrate BL and along the first direction A1 may be greater than the second width W2 of the exposed portion of the signal pad SD. The maximum width of the connection pad GE2 may be in the range of about 13 μm to about 15 μm.

[0117] Figure 5C is along Figure 4 An enlarged cross-sectional view taken along line IV-IV'. Figure 5C is a cross-sectional view of the pad area PA provided with the dummy pad GE1.

[0118] Reference Figure 5C , the display panel 110 may include a plurality of dummy pads GE1. The plurality of dummy pads GE1 may include a first dummy pad GE1-1 and a second dummy pad GE1-2. The dummy pad GE1 may overlap the upper insulating layer VIA1 and may be arranged in the first area LA. The second opening OP2 may be defined at a position between the first dummy pad GE1-1 and the second dummy pad GE1-2. The second opening OP2 may overlap the second area SA. The second opening OP2 may be defined in the upper insulating layer VIA1 and extend through the lower insulating layer 1IL and the intermediate insulating layer 2IL. That is, the second opening OP2 at least exposes the intermediate insulating layer 2IL outside the upper insulating layer VIA1. The fourth width W4 of the second opening OP2 defined in the upper insulating layer VIA1 may be in the range of about 6 μm to about 10 μm. In an embodiment, the fourth width W4 of the second opening OP2 may be about 8 μm. The fourth width W4 may be the minimum size of the second opening OP2 at the upper insulating layer VIA1.

[0119] Refer again Figure 5C, the upper insulating layer VIA1 may be arranged between the dummy insulating patterns VIA2 adjacent to each other and may overlap with the first area LA. Along the first direction A1, the fifth width W5 of the upper insulating layer VIA1 arranged between the dummy insulating patterns VIA2 may be greater than the width of the dummy insulating pattern VIA2 at its top surface farthest from the base substrate BL. The fifth width W5 may be the maximum dimension along the first direction A1. In an embodiment, for example, along the first direction A1, the fifth width W5 of the upper insulating layer VIA1 in the first area LA between the dummy insulating patterns VIA2 adjacent to each other may be in the range of about 16 μm to about 18 μm. The width of the dummy insulating pattern VIA2 along the first direction A1 may be about 8 μm.

[0120] In an embodiment, along the first direction A1, the width of the dummy insulation pattern VIA2 at the top surface thereof may be smaller than the second width W2 (eg, see FIG. 2 ) of the exposed top surface of the signal pad SD. Figure 5B In an embodiment, for example, the top surface of the signal pad SD (see, for example, Figure 5B ) The second width W2 along the first direction A1 may be in the range of about 9 μm to about 12 μm, and the width of the dummy insulation pattern VIA2 at the top surface thereof along the first direction A1 may be about 8 μm.

[0121] The second opening OP2 may expose the base substrate BL. A sixth width W6 of the exposed portion of the base substrate BL may be in the range of about 3 μm to about 6 μm. The sixth width W6 may also represent a minimum size of the second opening OP2 taken along the first direction A1.

[0122] The various widths described above are shown relative to the first direction A1. In an embodiment, their corresponding widths and sizes may be further defined relative to the second direction A2, but are not limited thereto.

[0123] The dummy insulation pattern VIA2 may be arranged in the second opening OP2. In other words, the dummy insulation pattern VIA2 may cover the second opening OP2. The dummy insulation pattern VIA2 may extend from the outside of the upper insulating layer VIA1 and into the second opening OP2 to meet the base substrate BL, but is not limited thereto. The dummy insulation pattern VIA2 may be arranged between portions of the pattern of the upper insulating layer VIA1. The dummy insulation pattern VIA2 may be defined by a corresponding portion or pattern of an organic material layer including polyimide (PI). A portion of the dummy insulation pattern VIA2 may protrude from the top surface of the upper insulating layer VIA1 farthest from the base substrate BL along a third direction A3. The protrusion of the dummy insulation pattern VIA2 may define its top surface. The dummy insulation pattern VIA2 in the second opening OP2 at a position between the first dummy pad GE1-1 and the second dummy pad GE1-2 protrudes to the outside of the upper insulating layer VIA1.

[0124] In the thickness direction of the base substrate BL (e.g., in the third direction A3), the first thickness TH1 of the protruding portion of the dummy insulation pattern VIA2 is defined by the distance between the top surface of the dummy insulation pattern VIA2 and the top surface of the upper insulation layer VIA1. The first thickness TH1 may be in the range of about 0.1 μm to about 0.5 μm. In an embodiment, the first thickness TH1 may be about 0.3 μm. That is, the first thickness TH1 protrudes outside the upper insulation layer VIA1.

[0125] In an embodiment, the maximum thickness of the dummy insulation pattern VIA2 along the third direction A3 may be in a range of about 1.2 μm to about 2.0 μm, and may be about 1.6 μm. In an embodiment, for example, the maximum thickness of the dummy insulation pattern VIA2 may be about twice the maximum thickness of the upper insulation layer VIA1. The maximum thickness of the dummy insulation pattern VIA2 may correspond to a vertical length from the top surface of the dummy insulation pattern VIA2 to the base substrate BL.

[0126] In an embodiment, each of the upper insulating layer VIA1 and the dummy insulating pattern VIA2 may include a top surface farthest from the base substrate BL, at least a portion of which is flat. In an embodiment, both the upper insulating layer VIA1 and the dummy insulating pattern VIA2 may be provided to have a flat top surface. The top surfaces of the upper insulating layer VIA1 and the dummy insulating pattern VIA2 may be parallel to each other, that is, arranged on corresponding planes parallel to each other. The top surface of the dummy insulating pattern VIA2 is shown as being farther away from the base substrate BL than the top surface of the upper insulating layer VIA1 along the third direction A3, but is not limited thereto. In an embodiment, the top surface of the dummy insulating pattern VIA2 may be closer to the base substrate BL than the top surface of the upper insulating layer VIA1.

[0127] Figure 6 is an enlarged cross-sectional view showing an embodiment of the pad area PA. Figure 6 Shown along Figure 4 1 is an embodiment of the pad area PA of the display panel 110 taken along line IV-IV'.

[0128] Reference Figure 6, the dummy insulation pattern VIA2 may be arranged in the second area SA. The dummy insulation pattern VIA2 may protrude from the top surface of the upper insulation layer VIA1 in a direction away from the base substrate BL and along the third direction A3. In an embodiment, the length TH3 (e.g., the third thickness) of the portion of the dummy insulation pattern VIA2 protruding from the top surface of the upper insulation layer VIA1 may be substantially equal to the second thickness TH2 of the upper insulation layer VIA1. In an embodiment, for example, both the second thickness TH2 and the length TH3 may be approximately 0.8 μm. The dummy insulation pattern VIA2 may cover the opening OP2 defined in the upper insulation layer VIA1. In an embodiment, the maximum thickness of the dummy insulation pattern VIA2 covering the opening OP2 may be approximately twice the maximum thickness of the upper insulation layer VIA1.

[0129] The dummy insulation pattern VIA2 may extend only through the upper insulation layer VIA1. Figure 6 , the dummy insulation pattern VIA2 may face the base substrate BL with each of the intermediate insulation layer 2IL and the lower insulation layer 1IL interposed therebetween.

[0130] Figure 7 is an enlarged cross-sectional view showing an embodiment of the pad area PA.

[0131] In an embodiment, the display panel 110 may exclude the dummy insulating pattern VIA2 in the pad area PA at the second area SA thereof. The upper insulating layer VIA1 may have an opening OP2 overlapping the second area SA. The opening OP2 may expose the interlayer insulating layer ILD and / or the intermediate insulating layer 2IL outside the upper insulating layer VIA1.

[0132] According to one or more embodiments, a stepped structure at an edge portion of a signal pad SD connected to a pixel PX through a signal line SGL is omitted, thereby reducing or effectively preventing a pixel malfunction problem.

[0133] According to one or more embodiments, the upper insulating layer VIA1 on the signal pad SD may extend to the edge portion of the display panel 110 where the dummy pad GE1 is arranged, and the dummy insulating pattern VIA2 may be arranged between the patterns of the extended portion of the upper insulating layer VIA1. Accordingly, the height difference between the layers and the technical problems that come with it (for example, the agglomeration problem of the conductive ball 142 that contacts the dummy pad GE1 and the short circuit problem caused thereby) may be reduced or effectively prevented. That is, the upper insulating layer VIA1 and the dummy insulating pattern VIA2 may effectively flatten the stepped structure defined by the lower layer to minimize the height difference.

[0134] While embodiments have been shown and described, workers skilled in the art will recognize that changes may be made in form and details without departing from the spirit and scope of the following claims.

Claims

1. A display panel, comprising: A base substrate, the base substrate comprising: a display area, the display area including pixels, and a pad area, the pad area being adjacent to the display area and defining an end surface of the base substrate that is farthest from the display area and exposed outside the display panel; a signal pad located in the pad region on the base substrate and electrically connected to the pixel; a dummy pad located in the pad region on the base substrate and electrically connected to the signal pad; an insulating layer, the insulating layer being located in the display area and the pad area on the base substrate, the insulating layer covering the signal pad and the dummy pad in the pad area, and the insulating layer defining an end surface of the insulating layer farthest from the display area and exposed outside the display panel in the pad area; and a first opening, the first opening being located in the insulating layer, the first opening exposing the signal pad to the outside of the insulating layer and to the outside of the display panel, Wherein, in the pad area, the end surface of the base substrate and the end surface of the insulating layer together define an inclined edge of the display panel.

2. The display panel according to claim 1, wherein: In the thickness direction of the base substrate, the insulating layer comprises: a lower insulating layer, the lower insulating layer being located between the base substrate and the dummy pad, an intermediate insulating layer, the intermediate insulating layer being located between the lower insulating layer and the signal pad, and an upper insulating layer, the upper insulating layer facing the middle insulating layer, the signal pad being between the upper insulating layer and the middle insulating layer, and The lower insulating layer, the middle insulating layer and the upper insulating layer respectively define respective end surfaces, and the respective end surfaces together define the end surface of the insulating layer.

3. The display panel according to claim 2, wherein: The inclined edge of the display panel extends along a first direction, The signal pad is provided in plurality and includes a first signal pad and a second signal pad arranged to be spaced apart from each other in the first direction, and The dummy pad is provided in plural and includes a first dummy pad corresponding to the first signal pad and a second dummy pad corresponding to the second signal pad and spaced apart from the first dummy pad in the first direction.

4. The display panel according to claim 3, wherein: The intermediate insulating layer includes a first insulating layer and a second insulating layer in order from the lower insulating layer to the signal pad along the thickness direction of the base substrate.

5. The display panel according to claim 3, wherein: Along the thickness direction of the base substrate, the first dummy pad and the second dummy pad are each located between the lower insulating layer and the upper insulating layer, and The first dummy pad and the second dummy pad are electrically connected to the first signal pad and the second signal pad, respectively.

6. The display panel according to claim 4, further comprising: a first connecting pad connecting the first signal pad to the first dummy pad, and a second connecting pad, the second connecting pad connecting the second signal pad to the second dummy pad, Wherein, along the thickness direction of the base substrate, the first connection pad and the second connection pad are respectively located between the first insulating layer and the second insulating layer of the intermediate insulating layer.

7. The display panel according to claim 3, further comprising: a second opening defined in the upper insulating layer at a position between the first dummy pad and the second dummy pad, wherein the second opening exposes the intermediate insulating layer to the outside of the upper insulating layer, and A dummy insulating pattern is located in the second opening.

8. The display panel according to claim 7, wherein: The dummy insulation pattern located in the second opening at the position between the first dummy pad and the second dummy pad protrudes outside the upper insulation layer.

9. The display panel according to claim 3, wherein: The first opening is defined in the upper insulating layer, and The upper insulating layer extends between the first signal pad and the second signal pad in the first direction.

10. The display panel according to claim 7, wherein: The oblique line direction intersects the first direction, Each of the first dummy pad, the second dummy pad, and the dummy insulating pattern has a length along the oblique line direction, and The length of the first dummy pad and the length of the second dummy pad are each greater than the length of the dummy insulation pattern.

11. The display panel according to claim 1, wherein: The dummy pad defines an end surface of the dummy pad exposed outside the display panel, and In the pad region, the end surface of the base substrate, the end surface of the insulating layer, and the end surface of the dummy pad together define the inclined edge of the display panel.

12. The display panel according to claim 8, wherein: A thickness of a portion of the dummy insulation pattern outside the upper insulation layer is in a range of 0.1 micrometers to 0.5 micrometers in the thickness direction of the base substrate.

13. The display panel according to claim 7, wherein: The pad area includes: a first region corresponding to the first signal pad and the second signal pad, and a second region located between the first signal pad and the second signal pad and adjacent to the first region in the first direction, The first opening exposing the signal pad is defined in the first region, and The second opening exposing the intermediate insulating layer to the outside of the upper insulating layer is defined in the second region.

14. The display panel according to claim 7, wherein: The signal pad has a width exposed by the first opening and measured in the first direction, The dummy insulating pattern has a width measured in the first direction, and The width of the signal pad is greater than the width of the dummy insulating pattern.

15. The display panel according to claim 1, wherein: In the pad area, The inclined edge of the display panel extends along a first direction, The signal pad extends in an oblique direction intersecting the first direction, and The insulating layer extends from the signal pad to overlap the dummy pad connected to the signal pad.

16. A display device, comprising: A display panel, the display panel comprising: a display area, the display area including pixels, and a pad area, the pad area being adjacent to the display area and defining an inclined edge of the display panel that is farthest from the display area and exposed outside the display panel; an electronic component connected to the display panel at the pad region of the display panel; and a conductive adhesive film that electrically connects the electronic component to the display panel at the pad region of the display panel, Wherein, the display panel comprises: a base substrate, the base substrate defining an end surface of the base substrate that is farthest from the display area and exposed outside the display panel; a signal pad located in the pad region on the base substrate and electrically connected to the pixel; a dummy pad located in the pad region on the base substrate and electrically connected to the signal pad; an insulating layer, the insulating layer being located in the display area and the pad area on the base substrate, the insulating layer covering the signal pad and the dummy pad in the pad area, and defining an end surface of the insulating layer farthest from the display area and exposed outside the display panel in the pad area, and a first opening, the first opening being located in the insulating layer, the first opening exposing the signal pad to the outside of the insulating layer and to the outside of the display panel, Wherein, in the pad area, the end surface of the base substrate and the end surface of the insulating layer together define the inclined edge of the display panel.

17. The display device according to claim 16, wherein: The inclined edge of the display panel extends along a first direction, The pad area includes: a first area corresponding to the signal pad, and a second region adjacent to the signal pad in the first direction, The electronic components include: a plurality of protrusions, the plurality of protrusions directly contacting the pad area of ​​the display panel, and a plurality of gap portions, wherein the plurality of gap portions are respectively located between the plurality of protrusions, The plurality of protrusions correspond to the first region, and The plurality of gap portions correspond to the second region.

18. The display device according to claim 16, wherein: The electronic components include: a plurality of protrusions, the plurality of protrusions directly contacting the pad area of ​​the display panel, and a plurality of gap portions, the plurality of gap portions being respectively located between the plurality of protrusions, and The plurality of protrusions are in contact with the signal pad.

19. The display device according to claim 16, wherein: The inclined edge of the display panel extends along a first direction, The signal pad is provided in plurality and includes a first signal pad and a second signal pad arranged in the first direction, and The dummy pad is provided in plural and includes a first dummy pad corresponding to the first signal pad and a second dummy pad corresponding to the second signal pad and spaced apart from the first dummy pad in the first direction.

20. The display device according to claim 19, further comprising: a second opening located in the insulating layer at a position between the first dummy pad and the second dummy pad; as well as A dummy insulating pattern is located in the second opening.

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