A large capacitor pre-charging circuit, system and control method thereof

Abstract

The present invention relates to the field of automobile technology, and the present invention provides a large capacitor pre-charging circuit, system and control method thereof. The large capacitor pre-charging circuit includes at least one primary pre-charging circuit; the primary pre-charging circuit includes a first transistor, a second transistor and a first current limiting resistor; the base of the first transistor is connected to the first control port of the control unit, the first end of the first transistor is connected to the base of the second transistor, and the second end of the first transistor is grounded; the first end of the second transistor is connected to the first end of the first current limiting circuit, and the second end of the second transistor is connected to a power supply; the second end of the first current limiting resistor is connected to a capacitor set, so that the power supply pre-charges the capacitor set through the primary pre-charging circuit. Thus, the pre-charging circuit provided by the present application can effectively reduce the current impact and improve the life of the device when charging the capacitor set.

Description

Technical Field

[0001] The present invention relates to the field of automobile technology, and in particular to a large-capacitor precharging circuit, system and control method thereof. Background Art

[0002] Intelligent electric chassis is a key component of automobiles and is also a key development direction for future automobiles. It includes three key independent executive components: braking, steering, and suspension. Taking the braking system as an example, the intelligent braking control system includes mechanical hydraulic components, algorithm control, and electronic control unit. It integrates functional modules such as motor drive, vehicle stability control, and dual-control electronic parking brake, which can meet the braking requirements of vehicles above L3 level. Among them, the electronic control unit is the link between algorithm control and mechanical hydraulic components. It has key module circuits such as power management, motor drive, valve drive, and signal processing. For the power supply filtering processing of the motor drive, large capacitors need to be connected in parallel on the power supply line, such as Figure 1 As shown, power supply stability and circuit reliability are improved.

[0003] Under the initial conditions, the power input is 0 and the capacitor charge capacity is 0. When the power is connected, due to the charging characteristics of the capacitor itself, the capacitor is equivalent to an instantaneous short circuit at the moment the power is connected, and the current impact is large, which reduces the life of the power device before the capacitor or damages the power device. Summary of the invention

[0004] The present invention aims to solve the technical problem of large current impact during the pre-charging process of a capacitor in the prior art.

[0005] To solve the above technical problems, the present application discloses, on one hand, a large-capacitor pre-charging circuit, which includes at least one primary pre-charging circuit;

[0006] The primary pre-charging circuit includes a first transistor, a second transistor and a first current limiting resistor;

[0007] The base of the first transistor is connected to the first control port of the control unit, the first end of the first transistor is connected to the base of the second transistor, and the second end of the first transistor is grounded;

[0008] The first end of the second transistor is connected to the first end of the first current limiting circuit, and the second end of the second transistor is connected to the power supply;

[0009] The second end of the first current limiting resistor is connected to the capacitor set, so that the power supply pre-charges the capacitor set through the first-level pre-charging circuit.

[0010] Optionally, the first-level pre-charging circuit further includes a first resistor, a second resistor, a third resistor and a fourth resistor;

[0011] The first end of the first resistor is connected to the first control port, and the second end of the first resistor is connected to the base of the first transistor;

[0012] The first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is connected to the second end of the first transistor;

[0013] A first end of the third resistor is connected to the first end of the first transistor, and a second end of the third resistor is connected to the base of the second transistor;

[0014] The first end of the fourth resistor is connected to the second end of the third resistor, and the second end of the fourth resistor is connected to the second end of the second transistor.

[0015] Optionally, comprising a first level pre-charging circuit and a second level pre-charging circuit connected in parallel;

[0016] The circuit structure of the first primary pre-charging circuit is the same as the circuit structure of the second primary pre-charging circuit;

[0017] The base of the first transistor of the first level pre-charging circuit is connected to the first control port;

[0018] The base of the first transistor of the second primary pre-charging circuit is connected to the second control port of the control unit;

[0019] The resistance value of the first current limiting resistor of the first level pre-charging circuit is greater than the resistance value of the first current limiting resistor of the second level pre-charging circuit, so that when the current in the large-capacitor pre-charging circuit is greater than a preset current, the first level pre-charging circuit is controlled to operate through the first control port; otherwise, the second level pre-charging circuit is controlled to operate through the second control port.

[0020] Optionally, a secondary pre-charging circuit is also included;

[0021] A first detection point is provided on the circuit close to the second end of the second transistor; a second detection point is provided on the capacitor set;

[0022] The secondary pre-charging circuit includes a first voltage-stabilizing tube, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a second current-limiting resistor;

[0023] The cathode of the first voltage regulator tube is connected to the first end of the second transistor, and the anode of the first voltage regulator tube is connected to the first end of the third transistor;

[0024] The second end of the third transistor is connected to the base of the fourth transistor, and the base of the third transistor is connected to the capacitor set;

[0025] A first terminal of the fourth transistor is connected to the base of the fifth transistor, and a second terminal of the fourth transistor is grounded;

[0026] The first end of the fifth transistor is connected to the first end of the second transistor, and the second end of the fifth transistor is connected to the capacitor set through the second current limiting resistor;

[0027] The base of the sixth transistor is connected to the third control port of the control unit, the first end of the sixth transistor is connected to the base of the fourth transistor, and the second end of the sixth transistor is grounded;

[0028] The resistance of the second current limiting resistor is smaller than the resistance of the first current limiting resistor, so that when the difference between the voltage at the first detection point and the voltage at the second detection point is smaller than the first preset threshold value, the first control port is used to control the operation of the first-level pre-charging circuit, and the third control port is used to control the operation of the second-level pre-charging circuit.

[0029] Optionally, it includes a first MOS tube, a second MOS tube and an inductor connected in series in sequence;

[0030] The first MOS tube is connected to the power supply;

[0031] The inductor is connected to the capacitor set;

[0032] The first end of the fourth transistor is connected to the gate of the first MOS tube, so that when the secondary pre-charging circuit is working, the fourth transistor can provide a voltage to cut off the first MOS tube.

[0033] Optionally, the secondary pre-charging circuit includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor;

[0034] A first end of the fifth resistor is connected to the anode of the first voltage regulator tube, and a second end of the fifth resistor is connected to the base of the third transistor;

[0035] A first end of the sixth resistor is connected to the base of the third transistor, and a second end of the sixth resistor is connected to the capacitor set;

[0036] The first end of the seventh resistor is connected to the second end of the third transistor, and the second end of the seventh resistor is connected to the base of the fourth transistor;

[0037] A first end of the eighth resistor is connected to the base of the fourth transistor, and a second end of the eighth resistor is grounded;

[0038] A first end of the ninth resistor is connected to the first end of the second transistor, and a second end of the ninth resistor is connected to the base of the fifth transistor;

[0039] A first end of the tenth resistor is connected to the base of the fifth transistor, and a second end of the tenth resistor is connected to the first end of the fourth transistor;

[0040] The third control port is connected to the sixth transistor through the eleventh resistor;

[0041] A first end of the twelfth resistor is connected to the base of the sixth transistor, and a second end of the twelfth resistor is grounded.

[0042] Optionally, a three-stage pre-charge circuit is included;

[0043] The three-stage pre-charging circuit includes a seventh transistor, an eighth transistor, a second voltage-stabilizing tube and a third current-limiting resistor;

[0044] The base of the seventh transistor is connected to the first end of the eighth transistor, the first end of the seventh transistor is connected to the first end of the second transistor, and the second end of the seventh transistor is connected to the capacitor set through the third current limiting resistor;

[0045] The base of the eighth transistor is connected to the anode of the second voltage regulator tube, and the second end of the eighth transistor is grounded;

[0046] The cathode of the voltage regulator tube is connected to the capacitor set;

[0047] The resistance of the third current limiting resistor is smaller than the resistance of the second current limiting resistor, so that when the difference between the voltage at the first detection point and the voltage at the second detection point is smaller than the second preset threshold value, and when the voltage at the second detection point is greater than the first voltage drop, which is the difference between the voltage drop of the second voltage regulator tube and the voltage drop of the eighth transistor, the large capacitor pre-charging circuit pre-charges the capacitor set through the first-stage pre-charging circuit and the third-stage pre-charging circuit.

[0048] Optionally, the three-stage pre-charging circuit further includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor and a sixteenth resistor;

[0049] A first end of the thirteenth resistor is connected to the base of the eighth transistor, and a second end of the thirteenth resistor is grounded;

[0050] A first end of the fourteenth resistor is connected to the first end of the eighth transistor, and a second end of the fourteenth resistor is connected to the base of the seventh transistor;

[0051] A first end of the fifteenth resistor is connected to the first end of the second transistor, and a second end of the fifteenth resistor is connected to the base of the seventh transistor;

[0052] The second voltage regulator is connected to the capacitor set via a sixteenth resistor.

[0053] On the other hand, the present application also discloses a large-capacitor pre-charging circuit system, which includes a power supply, a control unit and the large-capacitor pre-charging circuit mentioned above.

[0054] The present application further discloses a control method for a large capacitor pre-charging circuit, which is applied to the large capacitor pre-charging circuit, wherein the large capacitor pre-charging circuit includes at least one primary pre-charging circuit, and the primary pre-charging circuit includes a first transistor, a second transistor and a first current limiting resistor; the base of the first transistor is connected to the first control port of the control unit, the first end of the first transistor is connected to the base of the second transistor, and the second end of the first transistor is grounded; the first end of the second transistor is connected to the first end of the first current limiting circuit, and the second end of the second transistor is connected to a power supply; the second end of the first current limiting resistor is connected to a capacitor set; and the following steps are included:

[0055] receiving a driving voltage of the first port and a voltage of the power supply;

[0056] The first transistor and the second transistor are controlled to be turned on based on the driving voltage of the first port and the voltage of the power supply, so that the power supply pre-charges the capacitor set through the first-level pre-charging circuit.

[0057] By adopting the above technical solution, the large capacitor pre-charging circuit provided by the present application has the following beneficial effects:

[0058] The large capacitor pre-charging circuit includes at least one primary pre-charging circuit; the primary pre-charging circuit includes a first transistor, a second transistor and a first current limiting resistor; the base of the first transistor is connected to the first control port of the control unit, the first end of the first transistor is connected to the base of the second transistor, and the second end of the first transistor is grounded; the first end of the second transistor is connected to the first end of the first current limiting circuit, and the second end of the second transistor is connected to the power supply; the second end of the first current limiting resistor is connected to the capacitor set, so that the power supply pre-charges the capacitor set through the primary pre-charging circuit. Compared with the technical solution of directly charging the capacitor set in the prior art, since the transistor and the current limiting resistor are set in the pre-charging circuit of the present application, the conduction and closing of the circuit can be stably controlled, and under the action of the current limiting resistor, the impact of large current on the capacitor set can be effectively buffered, thereby improving the life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0060] Figure 1 It is a structural schematic diagram of a pre-charging circuit in the prior art;

[0061] Figure 2This is a structural schematic diagram of a large capacitor pre-charging circuit in an optional implementation manner of the present application;

[0062] Figure 3 It is a structural schematic diagram of a pre-charging circuit in the prior art;

[0063] Figure 4 This is a structural schematic diagram of a large capacitor pre-charging circuit in another optional implementation manner of the present application;

[0064] Figure 5 This is a structural schematic diagram of a large capacitor pre-charging circuit in another optional implementation manner of the present application;

[0065] Figure 6 This is a structural schematic diagram of a large capacitor pre-charging circuit in another optional implementation manner of the present application;

[0066] Figure 7 This is a structural schematic diagram of a large capacitor pre-charging circuit in another optional implementation manner of the present application;

[0067] Figure 8 This is a schematic structural diagram of a large capacitor pre-charging circuit in another optional implementation manner of the present application.

[0068] The following is a supplementary description of the attached drawings:

[0069] 1-level pre-charging circuit; 101-first level pre-charging circuit; 102-second level pre-charging circuit; 5-level pre-charging circuit; 6-second control port; 7-first fuse; 8-second fuse; 9-level pre-charging circuit; 2-first control port; 3-power supply; 4-capacitor set. DETAILED DESCRIPTION

[0070] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0071] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may include one or more of the features explicitly or implicitly. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here.

[0072] like Figure 2 As shown, Figure 2 The present application discloses a large capacitor pre-charging circuit in an optional embodiment of the present application. The present application discloses a large capacitor pre-charging circuit on the one hand, which includes at least one primary pre-charging circuit 1; the primary pre-charging circuit 1 includes a first transistor Q1, a second transistor Q2 and a first current limiting resistor Ra; the base of the first transistor Q1 is connected to the first control port 2 of the control unit, the first end of the first transistor Q1 is connected to the base of the second transistor Q2, and the second end of the first transistor Q1 is grounded; the first end of the second transistor Q2 is connected to the first end of the first current limiting circuit, and the second end of the second transistor Q2 is connected to the power supply 3; the second end of the first current limiting resistor Ra is connected to the capacitor set 4, so that the power supply 3 pre-charges the capacitor set 4 through the primary pre-charging circuit 1. Optionally, the first transistor Q1 is an NPN transistor, and the second transistor Q2 is a PNP transistor. They can also be set to other types as needed. Since multiple transistors and current limiting resistors are set in the pre-charging circuit of the present application, the conduction and closing of the circuit can be stably controlled, and under the action of the current limiting resistor, the impact of large current on the capacitor set 4 can be effectively buffered, thereby improving the life of the device.

[0073] Although the prior art also adopts Figure 3The circuit shown pre-charges a large capacitor, but it is controlled by a relay, that is, when pre-charging is required, it is achieved through a relay, a resistor R, a MOS tube (FET1 and FET2), and an inductor L1. However, since it uses a relay for control, it has the disadvantages of high cost, large space, and high mass. The relay will occupy the layout space of the electronic control unit, and may sacrifice performance to meet the space requirements.

[0074] Optionally, the various transistors and the various poles of the MOS tube in the present application can be connected in the manner shown in the accompanying drawings, or in other ways as needed, as long as the effect of the pre-charging circuit of the present application can be achieved, and no limitation is made here.

[0075] Optionally, the capacitor set 4 includes 6 capacitors connected in parallel. Of course, according to needs, the number can also be 4, 5, 7, etc., which is not limited here.

[0076] In an optional embodiment, see Figure 4 , Figure 4 It is a structural schematic diagram of a large capacitor pre-charging circuit in another optional implementation mode of the present application. The first-level pre-charging circuit 1 also includes a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4; the first end of the first resistor R1 is connected to the first control port 2, and the second end of the first resistor R1 is connected to the base of the first transistor Q1; the first end of the second resistor R2 is connected to the second end of the first resistor R1, and the second end of the second resistor R2 is connected to the second end of the first transistor Q1; the first end of the third resistor R3 is connected to the first end of the first transistor Q1, and the second end of the third resistor R3 is connected to the base of the second transistor Q2; the first end of the fourth resistor R4 is connected to the second end of the third resistor R3, and the second end of the fourth resistor R4 is connected to the second end of the second transistor Q2.

[0077] Optionally, the circuit may also include only the first resistor R1 and the third resistor R3 mentioned above for current limiting; the second resistor R2 and the fourth resistor R4 are used to provide bias voltages to the corresponding transistors connected in parallel, such as the second resistor R2 provides a bias voltage to the first transistor Q1, and the fourth resistor R4 provides a bias voltage to the second transistor Q2.

[0078] Optionally, a first detection point AD1 is provided on a line close to the second end of the second transistor Q2 ; and a second detection point AD2 is provided on the capacitor set 4 .

[0079] It should be noted that the first current limiting resistor Ra can be Figure 4The resistor shown can also be composed of two parallel resistors, as long as the resistor power can meet the preset requirements. The second current limiting resistor Rb and the third current limiting resistor Rc mentioned below are also the same. They are not limited here. The current limiting resistor can also effectively improve the heat dissipation effect, thereby improving the system reliability. During initial charging, the voltage at the second detection point AD2 is 0, the detection voltage at the first detection point AD1 is V1, and the maximum current of the first-level pre-charging circuit 1 during charging is I max =V1 / Ra, wherein V1 is the voltage of the power supply 3, and Ra is the resistance of the first current limiting resistor Ra; optionally, as the charging process continues, the voltage of AD2 gradually increases, so that the difference between the voltage of AD2 and the voltage of AD1 gradually decreases, and the voltage difference between the two can be used as a judgment condition to determine whether to open other pre-charging circuits. The specific scheme is described below.

[0080] In an optional embodiment, participating Figure 5 , Figure 5 This is a schematic diagram of the structure of a large capacitor pre-charging circuit in another optional implementation of the present application. The circuit includes a first level pre-charging circuit 101 and a second level pre-charging circuit 102 connected in parallel; the circuit structure of the first level pre-charging circuit 101 is the same as the circuit structure of the second level pre-charging circuit 102; the base of the first transistor Q1 of the first level pre-charging circuit 101 is connected to the first control port 2; the base of the first transistor Q1 of the second level pre-charging circuit 102 is connected to the second control port 6 of the control unit; the resistance value of the first current limiting resistor Ra of the first level pre-charging circuit 101 is greater than the resistance value of the first current limiting resistor Ra of the second level pre-charging circuit 102, so that when the current in the large capacitor pre-charging circuit is greater than the preset current, the first level pre-charging circuit 101 is controlled to work through the first control port 2; otherwise, the second level pre-charging circuit 102 is controlled to work through the second control port 6. Based on the present application Figure 5 The circuit shown can flexibly use current limiting resistors with different resistance values ​​to limit the charging current according to different charging currents, thereby effectively improving the charging flexibility and avoiding the impact of large current on the capacitor set 4.

[0081] Optionally, the pre-charging circuit can also first determine whether to charge based on the first level pre-charging circuit 101 or the second level pre-charging circuit 102 based on the voltage of the power supply 3. When the voltage of the power supply 3 is greater than the preset voltage, charging can be based on the first level pre-charging circuit 101.

[0082] If a fixed current limiting resistor is used for charging control, as the amount of charge increases, the charging speed will gradually decrease during the charging process, and the fast charging requirement cannot be met. In order to avoid the above situation, the above circuit of the present application can also realize segmented control of the current, that is, the charging current can be adjusted as needed, that is, when charging just starts, the capacitor set 4 can be pre-charged based on the first level pre-charging circuit 101, when the voltage of the second detection point AD2 reaches the preset threshold or the current in the circuit is less than the preset threshold or the difference between the voltage of the first detection point AD1 and the voltage of the second detection point AD2 is less than the third preset threshold, the first level pre-charging circuit 101 can be closed, and the second level pre-charging circuit 102 can be opened, so that the charging rate can be increased.

[0083] Of course, the first-level pre-charging circuit 1 can not only be set to two, but can also include a third first-level pre-charging circuit 1, a fourth first-level pre-charging circuit 1 and other N first-level pre-charging circuits 1, where N is an integer greater than or equal to 5, and the resistance values ​​of the first current limiting resistors Ra in the N first-level pre-charging circuits 1 are different to meet the requirements of different charging rates and charging currents.

[0084] In an optional embodiment, as Figure 6 As shown, Figure 6 This is a structural diagram of a large capacitor pre-charging circuit in another optional implementation of the present application. The circuit also includes a secondary pre-charging circuit 5; the secondary pre-charging circuit 5 includes a first voltage regulator tube Z1, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, and a second current limiting resistor Rb; the cathode of the first voltage regulator tube Z1 is connected to the first end of the second transistor Q2, and the anode of the first voltage regulator tube Z1 is connected to the first end of the third transistor Q3; the second end of the third transistor Q3 is connected to the base of the fourth transistor Q4, and the base of the third transistor Q3 is connected to the capacitor set 4; the first end of the fourth transistor Q4 is connected to the base of the fifth transistor Q5, and the second end of the fourth transistor Q4 is grounded; the first end of the fifth transistor Q5 is connected to the base of the fifth transistor Q5, and the second end of the fourth transistor Q4 is grounded; The first end of the fifth transistor Q5 is connected to the first end of the second transistor Q2, and the second end of the fifth transistor Q5 is connected to the capacitor set 4 through the second current limiting resistor Rb; the base of the sixth transistor Q6 is connected to the third control port of the control unit, the first end of the sixth transistor Q6 is connected to the base of the fourth transistor Q4, and the second end of the sixth transistor Q6 is grounded; the resistance of the second current limiting resistor Rb is less than the resistance of the first current limiting resistor Ra, so that when the difference between the voltage at the first detection point AD1 and the voltage at the second detection point AD2 is less than the first preset threshold, the first control port 2 is used to control the primary pre-charging circuit 1 to work, and the third control port is used to control the secondary pre-charging circuit 5 to work. Optionally, as Figure 6The circuit shown can be controlled as needed. Optionally, when the current is large, in order to reduce the impact of the large current, the first control port 2 and the second control port 6 can be driven to turn on the corresponding transistors at the same time, that is, the first-level pre-charging circuit 1 and the second-level pre-charging circuit 5 work at the same time; Optionally, the voltage output by the second control port 6 can be set to the default level for turning on the sixth transistor Q6 to simplify the control process; Optionally, as needed, only when the current in the pre-charging circuit is less than a preset threshold, the second control port 6 outputs a low level to control the sixth transistor Q6 to turn on, thereby making the second-level pre-charging circuit 5 work.

[0085] Optionally, the third transistor Q3 is a PNP transistor, the fourth transistor Q4 is an NPN transistor, the fifth transistor Q5 is a PNP transistor, and the sixth transistor Q6 is an NPN transistor. Other types may also be used as required. Figure 6 When the primary pre-charging circuit 1 and the secondary pre-charging circuit 5 work at the same time, the maximum current in the charging process of the circuit is I max =(V1-VAD2) / Ra+(V1-VAD2) / Rb, wherein V1 is the voltage of the power supply 3, VAD2 is the voltage of the second detection point, and Rb is the resistance of the second current limiting resistor Rb.

[0086] In an optional embodiment, as Figure 7 As shown, Figure 7 This is a structural schematic diagram of a large capacitor pre-charging circuit in another optional implementation of the present application. The large capacitor pre-charging circuit includes a first MOS tube FET1, a second MOS tube FET2 and an inductor L1 connected in series in sequence; the first MOS tube FET1 is connected to the power supply 3; the inductor L1 is connected to the capacitor set 4; the first end of the fourth transistor Q4 is connected to the base of the first MOS tube FET1, so that when the secondary pre-charging circuit 5 is working, the fourth transistor Q4 can provide a voltage to cut off the first MOS tube FET1, so that when the voltage difference between the voltage VAD2 and VAD3 at the capacitor set 4 in the circuit is greater than a preset threshold, VAD3 is the voltage at AD3. voltage, that is, at this time, the current in the pre-charging circuit is still large. Since the fourth transistor Q4 is connected to the base of the first MOS tube FET1, it can provide a cut-off level. At this time, when the AD4 voltage does not reach the voltage when the secondary pre-charging control module stops working, if there is an unexpected level to turn on the first MOS tube FET1, V2 will directly charge the capacitors C1-C6 through the first MOS tube FET1, the second MOS tube FET2, and L1, thereby generating a current impact. Since in the pre-charging device, when the secondary pre-charging circuit 5 is working, the fourth transistor Q4 is turned on, and it can be Figure 7The middle dotted line circuit forces the control terminal level of the first MOS tube FET1 to be set to a low level. Therefore, when the first MOS tube FET1 receives an unexpected control level, the first MOS tube FET1 is forced to be closed by the secondary pre-charge control module, and no current shock will be generated; the circuit design of this hardware fault-tolerant mechanism can effectively improve the stability of the circuit.

[0087] Optional, see Figure 7 The large-capacitor pre-charging circuit also includes a third MOS tube FET3, a first end of the third MOS tube FET3 is connected to the power supply 3, a second end of the third MOS tube FET3 is connected to the second end of the second transistor Q2, and a base of the third MOS tube FET3 is connected to the driving circuit to improve the application range of the circuit.

[0088] Optional, such as Figure 7 As shown, the large-capacitor pre-charging circuit also includes a first fuse 7 and a second fuse 8, wherein the first fuse 7 is located between the third MOS tube FET3 and the power supply 3, and the second fuse 8 is located between the power supply 3 and the first MOS tube FET1, so as to avoid the situation where a large current impacts the pre-charging circuit due to the instability of the power supply 3 and the like, thereby improving the stability of the pre-charging circuit.

[0089] Optionally, the circuit further includes an anti-reverse connection diode. Each MOS tube is connected in parallel with a diode. The diode may be a body diode or a separate device, and has an anti-reverse connection function.

[0090] In an optional embodiment, see Figure 6The secondary pre-charging circuit 5 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12; the first end of the fifth resistor R5 is connected to the anode of the first voltage-stabilizing tube Z1, and the second end of the fifth resistor R5 is connected to the base of the third transistor Q3; the first end of the sixth resistor R6 is connected to the base of the third transistor Q3, and the second end of the sixth resistor R6 is connected to the capacitor set 4; the first end of the seventh resistor R7 is connected to the second end of the third transistor Q3, and the second end of the seventh resistor R7 is connected to the base of the fourth transistor Q4. The first end of the eighth resistor R8 is connected to the base of the fourth transistor Q4, and the second end of the eighth resistor R8 is grounded; the first end of the ninth resistor R9 is connected to the first end of the second transistor Q2, and the second end of the ninth resistor R9 is connected to the base of the fifth transistor Q5; the first end of the tenth resistor R10 is connected to the base of the fifth transistor Q5, and the second end of the tenth resistor R10 is connected to the first end of the fourth transistor Q4; the third control port is connected to the sixth transistor Q6 through the eleventh resistor R11; the first end of the twelfth resistor R12 is connected to the base of the sixth transistor Q6, and the second end of the twelfth resistor R12 is grounded. Optionally, the sixth resistor R6, the seventh resistor R7, the tenth resistor R10 and the eleventh resistor R11 are used for current limiting; the fifth resistor R5, the eighth resistor R8, the ninth resistor R9 and the twelfth resistor R12 are used to provide bias voltages for the corresponding transistors connected in parallel.

[0091] It should be noted that the above-mentioned secondary pre-charging circuit 5 can be provided with multiple sub-secondary pre-charging circuits as needed, and the multiple sub-secondary pre-charging circuits are connected in parallel. The basic structure of the circuit of each sub-secondary pre-charging circuit is the same. As needed, it can adaptably change the resistance value of the resistor in the circuit, but the resistance value of the second current resistor of each circuit in the parallel sub-secondary pre-charging circuit is different, which is convenient for applying the current of different pre-charging circuits; optionally, each sub-secondary pre-charging circuit does not work at the same time. As needed, the working state of the sub-secondary pre-charging circuit can be controlled by controlling the level of the corresponding second control port 6.

[0092] Optionally, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 are respectively PNP transistors, NPN transistors, PNP transistors, and NPN transistors, and may be set to other types as needed. When the primary pre-charging circuit 1 and the secondary pre-charging circuit 5 work simultaneously (see Figure 6 ), the maximum current in the charging process of this circuit is I max=(V1-VAD2) / Ra+(V1-VAD2) / Rb, where V1 is the voltage of the power supply 3, VAD2 is the voltage of the second detection point AD2, and Rb is the resistance of the second current limiting resistor Rb. When the circuit is as follows Figure 7 When the circuit is shown, the maximum current during the charging process in this circuit is I max =(V1-△V1-VAD2) / Ra+(V1-△V1-VAD2) / Rb, wherein △V1 is the voltage drop on the third MOS tube FET3.

[0093] Optional, see Figure 7 When the difference between the voltage at AD3 and the voltage at AD2 is smaller than the difference between the voltage at the first voltage regulator tube Z1 and the voltage drop of the third transistor Q3, the first voltage regulator tube Z1 will be turned off, thereby turning off the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5, that is, the secondary pre-charging circuit 5 stops working. At this time, the pre-charging circuit can only charge the capacitor set 4 through the primary pre-charging circuit 1. For example, the output voltage of the power supply 3 is 12V. When the difference between the voltage at AD3 and the voltage at AD2 is less than 5V, the secondary pre-charging circuit 5 stops working.

[0094] In an optional embodiment, as Figure 8As shown, it is a schematic structural diagram of a large-capacity pre-charge circuit in another optional implementation manner of the present application. In order to further simplify the control of the circuit while ensuring the charging efficiency, the pre-charge circuit includes a three-stage pre-charge circuit 9; the three-stage pre-charge circuit 9 includes a seventh transistor Q7, an eighth transistor Q8, a second zener diode Z2, and a third current-limiting resistor Rc; the base of the seventh transistor Q7 is connected to the first end of the eighth transistor Q8, the first end of the seventh transistor Q7 is connected to the first end of the second transistor Q2, and the second end of the seventh transistor Q7 is connected to the capacitor bank 4 through the third current-limiting resistor Rc; the base of the eighth transistor Q8 is connected to the anode of the second zener diode Z2, and the second end of the eighth transistor Q8 is grounded; the cathode of the zener diode is connected to the capacitor bank 4; the resistance value of the third current-limiting resistor Rc is less than the resistance value of the second current-limiting resistor Rb, so that when the voltage difference between the first detection point AD1 and the second detection point AD2 is less than the second preset threshold, and when the voltage of the second detection point AD2 is greater than the first voltage drop, the first voltage drop is the voltage drop difference between the second zener diode Z2 and the eighth transistor Q8, the large-capacity pre-charge circuit pre-charges the capacitor bank 4 through the first-stage pre-charge circuit 1 and the three-stage pre-charge circuit 9. Since the voltage of the second detection point AD2 is greater than the first voltage drop, the eighth transistor Q8 is turned on, and then the seventh transistor Q7 is turned on. At this time, the V1 output by the pre-charge circuit can charge the capacitor bank 4 through the third MOS transistor FET3, the second transistor Q2, the seventh transistor Q7, and the third current-limiting resistor Rc; optionally, during the pre-charge process, the capacitor bank 4 can be charged through the first-stage pre-charge circuit 1 and the three-stage pre-charge circuit 9, improving the charging efficiency.

[0095] Optionally, when the pre-charge circuit is a circuit as shown in Figure 8 i.e., including a first-stage pre-charge circuit, a second-stage pre-charge circuit, and a three-stage pre-charge circuit; when the current in the circuit is I1, the pre-charge circuit can charge the capacitor bank based on the first-stage pre-charge circuit and the second-stage pre-charge circuit; when the current in the circuit is I2, the pre-charge circuit can charge the capacitor bank based on the first-stage pre-charge circuit and the three-stage pre-charge circuit; of course, since the three-stage pre-charge circuit can include N sub-pre-charge circuits connected in parallel, when the current in the circuit is In, the pre-charge circuit can charge the capacitor bank based on the first-stage pre-charge circuit and the Nth sub-pre-charge circuit, where I1 < I2 <... < In; n is an integer greater than or equal to 3; N is an integer greater than or equal to 2; since the above pre-charge circuit realizes multi-stage controllability of the pre-charge current by combining devices such as zener diodes, current-limiting resistors, and triodes, meeting the requirements of different charging speeds; and using the voltage difference between the voltage V1 of the input power supply and the voltage VAD2 of the capacitor bank as the input of the pre-charge circuit, it can automatically adapt to voltage fluctuations and improve the sensitivity of the pre-charge device.

[0096] In an optional embodiment, the three-stage pre-charging circuit 9 further includes a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15 and a sixteenth resistor R16; the first end of the thirteenth resistor R13 is connected to the base of the eighth transistor Q8, and the second end of the thirteenth resistor R13 is grounded; the first end of the fourteenth resistor R14 is connected to the first end of the eighth transistor Q8, and the second end of the fourteenth resistor R14 is connected to the base of the seventh transistor Q7; the first end of the fifteenth resistor R15 is connected to the first end of the second transistor Q2, and the second end of the fifteenth resistor R15 is connected to the base of the seventh transistor Q7; the second voltage regulator Z2 is connected to the capacitor set 4 through the sixteenth resistor R16. Optionally, the fourteenth resistor R14 and the sixteenth resistor R16 are used for current limiting; the thirteenth resistor R13 and the fifteenth resistor R15 are used to provide bias voltages for the corresponding transistors connected in parallel.

[0097] It should be noted that the above-mentioned three-level pre-charging circuit 9 can be provided with a plurality of sub-three-level pre-charging circuits as needed, and the plurality of sub-three-level pre-charging circuits are connected in parallel, and the basic structure of the circuit of each sub-three-level pre-charging circuit is the same. As needed, the resistance value of the resistor in the circuit can be adaptively changed, but the resistance value of the third current-limiting current resistor of each circuit in the parallel sub-three-level pre-charging circuit is different, which is convenient for applying the current of different pre-charging circuits; optionally, each sub-three-level pre-charging circuit does not work at the same time, and as needed, the working state of the sub-three-level pre-charging circuit can be controlled by configuring the different performances of the transistors, the voltage-stabilizing tubes and the resistors in the three-level pre-charging circuit, for example, changing the resistance value of the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15 and the sixteenth resistor R16 or the voltage drop of the voltage-stabilizing tube, the voltage drop of the transistor.

[0098] Optionally, the seventh transistor Q7 and the eighth transistor Q8 are PNP transistors and NPN transistors respectively, and can also be set to other types as needed. When the primary pre-charging circuit 1 and the tertiary pre-charging circuit 9 work at the same time (see Figure 8 ), the maximum current in the charging process of this circuit is I max =(V1-△V1-VAD2) / Ra+(V1-△V1-VAD2) / Rc, where Rc is the resistance of the third current limiting resistor Rc.

[0099] It should be noted that when the pre-charging circuit of any of the above-mentioned implementation schemes is adopted, when the voltage at AD2 reaches a certain limit, the pre-charging process is completed. At this time, the first control port 2 outputs the level of the first transistor Q1 that is cut off, which can be a low level, thereby closing the first pre-charging circuit 1. Optionally, the present application can adopt the above-mentioned method of monitoring the voltage of the first detection point AD1 and the second detection point AD2 as the type of pre-charging circuit to be turned on, that is, the first-level pre-charging circuit 1 and the second-level pre-charging circuit 5, or the first-level pre-charging circuit 1 and the third-level pre-charging circuit 9, etc. Of course, the present application can also determine the type of pre-charging circuit to be turned on based on monitoring the current value in the large capacitor pre-charging circuit; Optionally, when the current in the pre-charging circuit is greater than the first preset current, the capacitor set can be pre-charged based on the first-level pre-charging circuit 1 and the second-level pre-charging circuit 5. When the current in the pre-charging circuit is greater than the second pre-charging current and less than the first preset current When the current in the precharging circuit is greater than the third precharging current and less than the second preset current, the capacitor set can be precharged based on the first precharging circuit 1 and the second sub-three-level precharging circuit, and so on. When the current in the precharging circuit is greater than the Mth precharging current and less than the M-1th preset current, the capacitor set can be precharged based on the first precharging circuit 1 and the M-1th sub-three-level precharging circuit, where M is an integer greater than or equal to 4; the first preset current is greater than the second preset current, and so on, the M-1th preset current is greater than the Mth precharging current.

[0100] On the other hand, the present application also discloses a large-capacitor pre-charging circuit system, which includes a power supply 3, a control unit and the above-mentioned large-capacitor pre-charging circuit; the pre-charging circuit system can effectively reduce the impact of large current on the capacitor set 4, improve the stability of the circuit, and reduce the cost.

[0101] On the other hand, the present application also discloses a control method for a large-capacitor pre-charging circuit, which is applied to a large-capacitor pre-charging circuit, wherein the large-capacitor pre-charging circuit includes at least one first-level pre-charging circuit 1, and the first-level pre-charging circuit 1 includes a first transistor Q1, a second transistor Q2 and a first current-limiting resistor Ra; the base of the first transistor Q1 is connected to the first control port 2 of the control unit, the first end of the first transistor Q1 is connected to the base of the second transistor Q2, and the second end of the first transistor Q1 is grounded; the first end of the second transistor Q2 is connected to the first end of the first current-limiting circuit, and the second end of the second transistor Q2 is connected to the power supply 3; the second end of the first current-limiting resistor Ra is connected to the capacitor set 4; the method includes the following steps: receiving the driving voltage of the first port and the voltage of the power supply 3; controlling the first transistor Q1 and the second transistor Q2 to be turned on based on the driving voltage of the first port and the voltage of the power supply 3, so that the power supply 3 pre-charges the capacitor set 4 through the first-level pre-charging circuit 1.

[0102] Optionally, the control method may also be based on the above Figure 4-Figure 8 The pre-charging circuit shown is controlled. For the specific control process, please refer to the description in the implementation method of the large-capacitor pre-charging circuit above, which will not be repeated here.

[0103] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A large capacitor pre-charging circuit, characterized in that: It comprises two primary pre-charging circuits (1) connected in parallel; the two primary pre-charging circuits (1) connected in parallel comprise a first primary pre-charging circuit (101) and a second primary pre-charging circuit (102); The primary pre-charging circuit (1) comprises a first transistor, a second transistor and a first current limiting resistor; The base of the first transistor is connected to a first control port (2) of a control unit, the first end of the first transistor is connected to the base of the second transistor, and the second end of the first transistor is grounded; the first end of the second transistor is connected to the first end of the first current limiting resistor, and the second end of the second transistor is connected to a power supply (3); The second end of the first current limiting resistor is connected to the capacitor set (4), so that the power supply (3) pre-charges the capacitor set (4) through the first-level pre-charging circuit (1); The circuit structure of the first-level pre-charging circuit (101) is the same as the circuit structure of the second-level pre-charging circuit (102); The base of the first transistor of the first-stage pre-charging circuit (101) is connected to the first control port (2); The base of the first transistor of the second-stage pre-charging circuit (102) is connected to the second control port (6) of the control unit; The resistance value of the first current limiting resistor of the first primary pre-charging circuit (101) is greater than the resistance value of the first current limiting resistor of the second primary pre-charging circuit (102), so that when the current in the large-capacitor pre-charging circuit is greater than a preset current, the first primary pre-charging circuit (101) is controlled to operate via the first control port (2); otherwise, the second primary pre-charging circuit (102) is controlled to operate via the second control port (6).

2. The large-capacitance precharge circuit according to claim 1, wherein The primary pre-charging circuit (1) further comprises a first resistor, a second resistor, a third resistor and a fourth resistor; The first end of the first resistor is connected to the first control port (2), and the second end of the first resistor is connected to the base of the first transistor; The first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is connected to the second end of the first transistor; A first end of the third resistor is connected to a first end of the first transistor, and a second end of the third resistor is connected to a base of the second transistor; The first end of the fourth resistor is connected to the second end of the third resistor, and the second end of the fourth resistor is connected to the second end of the second transistor.

3. The large-capacitance precharge circuit according to claim 1, wherein Also includes a secondary pre-charging circuit (5); A first detection point is provided on a circuit close to the second end of the second transistor; a second detection point is provided on the capacitor set; The secondary pre-charging circuit (5) comprises a first voltage-stabilizing tube, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a second current-limiting resistor; The cathode of the first voltage regulator tube is connected to the first end of the second transistor, and the anode of the first voltage regulator tube is connected to the first end of the third transistor; The second end of the third transistor is connected to the base of the fourth transistor, and the base of the third transistor is connected to the capacitor set (4); A first terminal of the fourth transistor is connected to the base of the fifth transistor, and a second terminal of the fourth transistor is grounded; The first end of the fifth transistor is connected to the first end of the second transistor, and the second end of the fifth transistor is connected to the first end of the second transistor. connected to the capacitor set (4) via the second current limiting resistor; The base of the sixth transistor is connected to the third control port of the control unit, the first end of the sixth transistor is connected to the base of the fourth transistor, and the second end of the sixth transistor is grounded; The resistance value of the second current limiting resistor is smaller than the resistance value of the first current limiting resistor, so that when the difference between the voltage at the first detection point and the voltage at the second detection point is smaller than a first preset threshold value, the first control port (2) is used to control the operation of the first-level pre-charging circuit (1), and the third control port is used to control the operation of the second-level pre-charging circuit (5).

4. The large-capacitance precharge circuit according to claim 3, wherein It includes a first MOS tube, a second MOS tube and an inductor which are connected in series in sequence; The first MOS tube is connected to the power source (3); The inductor is connected to the capacitor set (4); The first end of the fourth transistor is connected to the gate of the first MOS transistor, so that when the secondary pre-charging circuit (5) is working, the fourth transistor can provide a voltage to cut off the first MOS transistor.

5. The large-capacitance precharge circuit according to claim 4, wherein The secondary pre-charging circuit (5) comprises a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor; A first end of the fifth resistor is connected to the anode of the first voltage regulator tube, and a second end of the fifth resistor is connected to the base of the third transistor; The first end of the sixth resistor is connected to the base of the third transistor, and the second end of the sixth resistor is connected to the capacitor set (4); The first end of the seventh resistor is connected to the second end of the third transistor, and the second end of the seventh resistor is connected to the base of the fourth transistor; A first end of the eighth resistor is connected to the base of the fourth transistor, and a second end of the eighth resistor is grounded; A first end of the ninth resistor is connected to the first end of the second transistor, and a second end of the ninth resistor is connected to the base of the fifth transistor; A first end of the tenth resistor is connected to the base of the fifth transistor, and a second end of the tenth resistor is connected to the first end of the fourth transistor; The third control port is connected to the sixth transistor through the eleventh resistor; A first end of the twelfth resistor is connected to the base of the sixth transistor, and a second end of the twelfth resistor is grounded.

6. The large-capacitance precharge circuit according to claim 4, wherein It includes a three-stage pre-charging circuit (9); The three-stage pre-charging circuit (9) comprises a seventh transistor, an eighth transistor, a second voltage-stabilizing tube and a third current-limiting resistor; The base of the seventh transistor is connected to the first end of the eighth transistor, the first end of the seventh transistor is connected to the first end of the second transistor, and the second end of the seventh transistor is connected to the capacitor set (4) through the third current limiting resistor; The base of the eighth transistor is connected to the anode of the second voltage regulator tube, and the second end of the eighth transistor is grounded; The cathode of the voltage regulator tube is connected to the capacitor set (4); The resistance value of the third current limiting resistor is smaller than the resistance value of the second current limiting resistor, so that when the difference between the voltage at the first detection point and the voltage at the second detection point is smaller than a second preset threshold value, and when the voltage at the second detection point is larger than a first voltage drop, the first voltage drop being the difference between the voltage drop of the second voltage regulator tube and the voltage drop of the eighth transistor, the large capacitor pre-charging circuit pre-charges the capacitor set (4) through the first-stage pre-charging circuit (1) and the third-stage pre-charging circuit (9).

7. The large-capacitance precharge circuit according to claim 6, wherein The three-stage pre-charging circuit (9) further includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor and a sixteenth resistor; A first end of the thirteenth resistor is connected to the base of the eighth transistor, and a second end of the thirteenth resistor is grounded; A first end of the fourteenth resistor is connected to the first end of the eighth transistor, and a second end of the fourteenth resistor is connected to the base of the seventh transistor; A first end of the fifteenth resistor is connected to the first end of the second transistor, and a second end of the fifteenth resistor is connected to the base of the seventh transistor; The second voltage regulator is connected to the capacitor set via a sixteenth resistor.

8. A large capacitor pre-charging circuit system, characterized in that: It comprises a power supply (3), a control unit and a large-capacitor pre-charging circuit as claimed in any one of claims 1 to 7.

9. A control method for a large capacitor pre-charging circuit, characterized in that: A large-capacitor precharging circuit system according to claim 8, wherein the large-capacitor precharging circuit comprises two parallel primary precharging circuits (1), the two parallel primary precharging circuits (1) comprise a first primary precharging circuit (101) and a second primary precharging circuit (102), the primary precharging circuit (1) comprises a first transistor, a second transistor and a first current-limiting resistor; the base of the first transistor is connected to the first control port (2) of the control unit, the first end of the first transistor is connected to the base of the second transistor, and the second end of the first transistor is grounded; the first end of the second transistor is connected to the first end of the first current-limiting resistor, and the second end of the first transistor is grounded. The second ends of the two transistors are connected to a power source (3); the second ends of the first current limiting resistor are connected to a capacitor set (4); the circuit structure of the first primary precharging circuit (101) is the same as the circuit structure of the second primary precharging circuit (102); the base of the first transistor of the first primary precharging circuit (101) is connected to the first control port (2); the base of the first transistor of the second primary precharging circuit (102) is connected to the second control port (6) of the control unit, and the resistance value of the first current limiting resistor of the first primary precharging circuit (101) is greater than the resistance value of the first current limiting resistor of the second primary precharging circuit (102); comprising the following steps: When the current in the large capacitor pre-charging circuit is greater than a preset current, receiving the driving voltage of the first control port (2) and the voltage of the power supply (3); Based on the driving voltage of the first control port (2) and the voltage of the power supply (3), the first transistor and the second transistor are controlled to be turned on, so that the power supply (3) pre-charges the capacitor set (4) through the first primary pre-charging circuit (101); When the current in the large capacitor pre-charging circuit is less than or equal to a preset current, receiving the driving voltage of the second control port (6) and the voltage of the power supply (3); Based on the driving voltage of the second control port (6) and the voltage of the power supply (3), the first transistor and the second transistor are controlled to be turned on, so that the power supply (3) pre-charges the capacitor set (4) through the second first-level pre-charging circuit (102).

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