Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device is provided, which can prevent decomposition reaction of an antireflection film provided on a semiconductor substrate and corrosion of a wiring layer, thereby improving reliability. The device comprises a wiring layer (11), a titanium nitride layer (21) provided on the wiring layer (11), a titanium nitride oxide layer (22) provided on the titanium nitride layer (21), a titanium oxide layer (23) provided on the titanium nitride oxide layer (22), and a surface protection film (31, 32) provided on the titanium oxide layer (23); an opening (11b) is provided which penetrates the titanium nitride layer (21), the titanium nitride oxide layer (22), the titanium oxide layer (23), and the surface protection film (31, 32) to expose a portion of the wiring layer (11); the exposed portion of the wiring layer (11) constitutes a pad (11a).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] It is known that in semiconductor devices such as semiconductor integrated circuits (ICs), an anti-reflection film formed of a titanium nitride (TiN) film or the like is formed on a wiring layer formed of aluminum (Al) or the like provided on a semiconductor substrate, thereby reducing reflection (halo) of light from the substrate when forming a resist pattern for patterning the wiring layer (see patent documents 1-5).

[0003] Patent Documents 1 to 4 disclose forming a single-layer TiN film on a wiring layer as an anti-reflection film. Patent Document 5 discloses forming a stacked structure of a lower titanium (Ti) film and an upper TiN film on a wiring layer, wherein the composition ratio of the TiN film changes continuously. Patent Document 6 discloses forming a barrier metal film under the wiring layer into a three-layer structure of a TiN film sandwiched between Ti films, but there is no disclosure about an anti-reflection film on the wiring layer.

[0004] A surface protection film is formed on the anti-reflection film described in patent documents 1-5. An opening is formed to penetrate the surface protection film and the anti-reflection film, and a portion of the wiring layer exposed in the opening is used as a pad for connection with a bonding wire. The end of the TiN layer serving as the anti-reflection film is exposed on the side wall of the opening. In a high temperature and high humidity bias (THB) environment, when the end of the TiN layer is exposed on the side wall of the opening, TiN reacts with moisture to become titanium oxide (TiO) and expands in volume. As a result, it is pointed out that cracks are formed in the surface protection film or voids in the film, causing corrosion around the pad and other adverse conditions.

[0005] Therefore, Patent Documents 2-4 disclose that the end of the TiN layer is moved back beyond the opening by an etching process different from the etching process for the pad opening, and the end of the TiN layer is covered with a surface protection film so that the TiN layer is not exposed at the side wall of the pad opening.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Laid-Open No. 3-292757

[0009] Patent Document 2: Japanese Patent Application Laid-Open No. 2-205323

[0010] Patent Document 3: Japanese Patent No. 5443827

[0011] Patent Document 4: Japanese Patent No. 5702844

[0012] Patent Document 5: Japanese Patent No. 3460417

[0013] Patent Document 6: Japanese Patent Application Publication No. 2009-88381 Summary of the invention

[0014] Problem that the invention aims to solve

[0015] In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same which can prevent decomposition reaction of an antireflection film provided on a semiconductor substrate, corrosion of a wiring layer, etc., thereby improving reliability.

[0016] Solutions for solving problems

[0017] One embodiment of the present invention is a semiconductor device, the purpose of which is to include: (a) a wiring layer; (b) a titanium nitride layer arranged on the wiring layer; (c) a titanium oxynitride layer arranged on the titanium nitride layer; (d) a titanium oxide layer arranged on the titanium oxynitride layer; and (e) a surface protective film arranged on the titanium oxide layer.

[0018] Another embodiment of the present invention is a method for manufacturing a semiconductor device, the purpose of which is to include the following steps: (a) depositing a metal film for wiring formation on a semiconductor substrate; (b) depositing a titanium nitride layer on the metal film for wiring formation; (c) depositing a titanium layer on the titanium nitride layer; (d) forming a resist pattern on the titanium layer; (e) using the resist pattern as an etching mask to pattern the metal film for wiring formation, thereby forming a wiring layer; (f) oxidizing the upper surface of the titanium layer to form a titanium oxide layer; and (g) diffusing oxygen and nitrogen in the titanium layer to form a titanium oxynitride layer between the titanium nitride layer and the titanium oxide layer.

[0019] Effects of the Invention

[0020] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the same which can prevent a decomposition reaction of an antireflection film provided on a semiconductor substrate and corrosion of a wiring layer, thereby improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is an equivalent circuit diagram of the semiconductor device according to the first embodiment of the present invention.

[0022] Figure 2 It is a schematic plan view of a semiconductor device according to a first embodiment of the present invention.

[0023] Figure 3 yes Figure 2 Cross-sectional view of section AA.

[0024] Figure 4AIt is a cross-sectional view of a process of manufacturing the semiconductor device according to the first embodiment of the present invention.

[0025] Figure 4B A semiconductor device according to the first embodiment of the present invention Figure 4A A cross-sectional view of the subsequent process.

[0026] Figure 4C The semiconductor device according to the first embodiment of the present invention is a successor Figure 4B A cross-sectional view of the subsequent process.

[0027] Figure 5A The semiconductor device according to the first embodiment of the present invention is a successor Figure 4C A cross-sectional view of the subsequent process.

[0028] Figure 5B The semiconductor device according to the first embodiment of the present invention is a successor Figure 5A A cross-sectional view of the subsequent process.

[0029] Figure 5C The semiconductor device according to the first embodiment of the present invention is a successor Figure 5B A cross-sectional view of the subsequent process.

[0030] Figure 6 It is a cross-sectional view of a main part of a semiconductor device according to a comparative example of the first embodiment of the present invention.

[0031] Figure 7 It is a schematic plan view of a semiconductor device according to a comparative example of the first embodiment of the present invention.

[0032] Figure 8 (a) is the spectral profile of the scanning transmission electron microscope (STEM) when the Ti film thickness is 35nm. Figure 8 (b) is Figure 8 STEM image of the case in (a).

[0033] Fig. 9 (a) is the STEM spectrum profile when the Ti film thickness is 15nm. Fig. 9 (b) is Fig. 9 STEM image of the case in (a).

[0034] Fig.10 (a) is the STEM spectrum profile when the Ti film thickness is 5nm. Fig.10 (b) is Fig.10 STEM image of the case in (a).

[0035] Fig.11It is a cross-sectional view of a main part of the semiconductor device according to the first embodiment of the present invention.

[0036] Fig.12 It is a plan view of a main part of a semiconductor device according to a comparative example of the second embodiment of the present invention.

[0037] Fig.13 yes Fig.12 Cross-sectional views of the AA section and the BB section.

[0038] Fig.14 It is a plan view of a main part of a semiconductor device according to a second embodiment of the present invention.

[0039] Fig.15 yes Fig.14 Cross-sectional views of the AA section and the BB section.

[0040] Fig.16A It is a cross-sectional view of a process of manufacturing a semiconductor device according to the second embodiment of the present invention.

[0041] Fig. 16B A semiconductor device according to a second embodiment of the present invention Fig.16A A cross-sectional view of the subsequent process.

[0042] Fig. 16C A semiconductor device according to a second embodiment of the present invention Fig. 16B A cross-sectional view of the subsequent process.

[0043] Fig.17 This is the STEM spectrum profile when the anti-reflection film in the region away from the pad is a TiN layer and a Ti layer.

[0044] Fig.18 This is a STEM spectrum profile when the anti-reflection film in the pad-removing region is a single-layer TiN layer. DETAILED DESCRIPTION

[0045] Below, the first and second embodiments of the present invention are described with reference to the accompanying drawings. In the description of the drawings, the same or similar parts are marked with the same or similar marks, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and plane size, the ratio of the thickness of each layer, etc. are sometimes different from the actual situation. In addition, the drawings may also include parts with different dimensional relationships and ratios. In addition, the embodiments shown below are used to illustrate the devices and methods for concretizing the technical ideas of the present invention. The technical ideas of the present invention do not specify the material, shape, structure, configuration, etc. of the structural components as the following materials, shapes, structures, configurations, etc.

[0046] In addition, the definitions of up and down directions in the following description are only for convenience of explanation and are not intended to limit the technical concept of the present invention. For example, if the object is rotated 90° to observe, up and down will be converted to left and right to read, and if it is rotated 180° to observe, up and down will be reversed to read, which is self-evident.

[0047] (First Embodiment)

[0048] <Structure of Semiconductor Device>

[0049] As a semiconductor device according to the first embodiment of the present invention, a high voltage integrated circuit (hereinafter referred to as "HVIC") for driving a power switching element constituting a bridge circuit for power conversion is exemplified. Figure 1 As shown, the semiconductor device 50 according to the first embodiment of the present invention drives a power converter 60 as one phase of a power conversion bridge circuit. In the power converter 60, a high voltage side switching element S1 and a low voltage side switching element S2 are connected in series to form an output circuit.

[0050] exist Figure 1 In the example, the case where the high-voltage side switch element S1 and the low-voltage side switch element S2 are respectively IGBTs is illustrated, but the high-voltage side switch element S1 and the low-voltage side switch element S2 are not limited to IGBTs, and may also be other power switch elements such as MOSFETs. A freewheeling diode FWD1 is connected in reverse parallel to the high-voltage side switch element S1, and a freewheeling diode FWD2 is connected in reverse parallel to the low-voltage side switch element S2. In addition, it may also be a reverse-conducting IGBT in which the high-voltage side switch element S1 and the freewheeling diode FWD1 are integrated into one chip, and the low-voltage side switch element S2 and the freewheeling diode FWD2 are integrated into another chip.

[0051] The high voltage side switch element S1 and the low voltage side switch element S2 are connected in series between the main power supply VDC as the high voltage on the positive side and the ground potential (GND potential) as the negative side relative to the main power supply VDC to form a half-bridge circuit. The high electrode terminal (collector terminal) of the high voltage side switch element S1 is connected to the main power supply VDC, and the low electrode terminal (emitter terminal) of the low voltage side switch element S2 is connected to the GND potential. The connection point 61 between the low electrode terminal (emitter terminal) of the high voltage side switch element S1 and the high electrode terminal (collector terminal) of the low voltage side switch element S2 is the output point of the power conversion unit 60 as one phase of the bridge circuit for power conversion. A load 67 such as a motor is connected to the connection point 61, and the VS potential at the reference voltage terminal VS is supplied to the load 67.

[0052] The semiconductor device 50 involved in the first embodiment of the present invention outputs a driving signal from the output terminal OUT to turn on and off the gate of the high voltage side switch element S1 to drive it according to the input signal from the input terminal IN. The semiconductor device 50 involved in the first embodiment of the present invention includes a low potential side circuit (low side circuit) 41, a level shift circuit 42 and a high potential side circuit (high side circuit) 43 as at least a part of the circuit. The low side circuit 41, the level shift circuit 42 and the high side circuit 43 can also be monolithically integrated into a single semiconductor chip (semiconductor substrate). Alternatively, the components constituting the low side circuit 41, the level shift circuit 42 and the high side circuit 43 can also be separately integrated into two or more semiconductor chips.

[0053] The low-side circuit 41 operates with the GND potential applied to the ground terminal GND as the reference potential and the VCC potential applied to the low-side power supply terminal VCC as the power supply potential. The low-side circuit 41 generates an on / off signal of the low-side level according to the input signal from the input terminal IN, and outputs it to the level shift circuit 42. The low-side circuit 41 may be a complementary MOS (CMOS) circuit including an nMOS transistor and a pMOS transistor, for example, but is not shown in the figure.

[0054] The level shift circuit 42 operates with the GND potential applied to the ground terminal GND as the reference potential. The level shift circuit 42 converts the low-side level on / off signal from the low-side circuit 41 into a high-side level on / off signal used on the high-side side. The level shift circuit 42 may include an nMOS transistor that functions as a level shifter, a level shift resistor, and a protection diode, but illustration is omitted.

[0055] The high side circuit 43 operates with the VS potential applied to the reference voltage terminal VS as the reference potential and with the VB potential as the first potential applied to the high side power supply terminal VB as the power supply potential. The high side circuit 43 outputs a drive signal from the output terminal OUT according to the on / off signal from the level shift circuit 42 to drive the gate of the high voltage side switch element S1. The high side circuit 43, for example, has a CMOS circuit including an nMOS transistor 46 as an active element and a pMOS transistor 45 as an active element at the output stage. The source terminal of the pMOS transistor 45 is connected to the high side power supply terminal VB. The source terminal of the nMOS transistor 46 is connected to the reference voltage terminal VS. An output terminal OUT is connected between the drain terminal of the pMOS transistor 45 and the drain terminal of the nMOS transistor 46.

[0056] As the semiconductor device 50 according to the first embodiment of the present invention, a bootstrap circuit method is exemplified. Figure 1In the illustrated structure, a bootstrap diode 65 as an external element is connected between the low-side power supply terminal VCC and the high-side power supply terminal VB. In addition, a bootstrap capacitor 66 as an external element is connected between the high-side power supply terminal VB and the reference voltage terminal VS. The bootstrap diode 65 and the bootstrap capacitor 66 constitute a part of the circuit of the driving power supply of the high-voltage side switching element S1.

[0057] The VB potential is the highest potential applied to the semiconductor device 50. In a normal state without being affected by noise, the VB potential is maintained by the bootstrap capacitor 66 to be about 5V to 15V higher than the VS potential as the second potential. The high-voltage side switch element S1 and the low-voltage side switch element S2 are turned on and off complementarily, whereby the VS potential repeatedly rises and falls between the high-potential side potential (for example, about 400V or more and about 2000V or less) of the main power supply VDC and the low-potential side potential (GND potential), fluctuating between 0V and several hundred V, and sometimes becoming a negative potential. In addition, the potential of the low-potential side power supply terminal VCC is about 5V to 15V.

[0058] Figure 2 express Figure 1 Schematic planar layout of the semiconductor device 50 shown. The semiconductor device 50 involved in the first embodiment of the present invention includes a high potential side circuit area (high side circuit area) 51 and a low potential side circuit area (low side circuit area) 53 on one chip. A high voltage junction termination structure (HVJT) 52 is arranged around the high side circuit area 51.

[0059] Figure 2 The high-side circuit area 51 shown has semiconductor elements, passive elements and other elements, but they are omitted from the illustration. There is no limitation on the type, number, positional relationship and the like of the elements included in the high-side circuit area 51. The high-side circuit area 51 has a plurality of pads (high-potential side pads) 11a, 12a, 13a that can be connected to bonding wires. The plurality of high-potential side pads 11a, 12a, 13a are respectively composed of a portion of the plurality of high-potential side wiring layers 11, 12, 13 that is exposed in the plurality of openings 11b, 12b, 13b of the surface protective film (31, 32). The high-side circuit area 51 and Figure 1 The high side circuit 43 shown in the figure corresponds to a plurality of high potential side pads 11a, 12a, 13a and Figure 1 The high-side power supply terminal VB, output terminal OUT, reference voltage terminal VS, etc. shown correspond to each other.

[0060] HVJT 52 electrically separates the high-side circuit area 51 from the low-side circuit area 53. Figure 1 The level shift element of the level shift circuit 42 shown has a withstand voltage structure.

[0061] Figure 2 The low-side circuit area 53 shown has semiconductor elements, passive elements and other elements, but they are omitted from the illustration. There is no limitation on the type, number, positional relationship and the like of the elements included in the low-side circuit area 53. The low-side circuit area 53 is composed of a plurality of pads (low-potential side pads) 14a, 15a, 16a that can be connected to bonding wires. The plurality of low-potential side pads 14a, 15a, 16a are respectively composed of a portion of the plurality of low-potential side wiring layers 14, 15, 16 that is exposed in the openings 14b, 15b, 16b of the surface protective film (31, 32). The low-side circuit area 53 and Figure 1 The low-side circuit 41 shown in the figure corresponds to a plurality of low potential side pads 14a, 15a, 16a and Figure 1 The low-side power supply terminal VCC, input terminal IN, ground terminal GND, etc. shown correspond to each other.

[0062] In addition, in this specification, the plurality of high potential side wiring layers 11, 12, 13 and the plurality of low potential side wiring layers 14, 15, 16 are collectively referred to as "wiring layers" without distinguishing each other's spatial positions, shapes, etc. Similarly, in this specification, the plurality of high potential side pads 11a, 12a, 13a and the plurality of low potential side pads 14a, 15a, 16a are collectively referred to as "pads" without distinguishing each other's spatial positions, etc.

[0063] Figure 3 The upper part of the cross section of the periphery of the high potential side pad 11a as viewed from the AA direction is shown with attention paid to the high potential side pad 11a. The high potential side pad 11a is Figure 2 One of the plurality of high potential side pads 11 a , 12 a , 13 a of the high side circuit region 51 is shown.

[0064] like Figure 3 As shown, the semiconductor device 50 involved in the first embodiment of the present invention has a high potential side wiring layer 11 constituting a high potential side pad 11a. The high potential side wiring layer 11 is one of a plurality of high potential side wiring layers 11, 12, and 13 located at the top of a multilayer wiring structure on a semiconductor substrate. The thickness of the high potential side wiring layer 11 is, for example, about 600 nm or more and about 2000 nm or less. As a material for the high potential side wiring layer 11, a metal material such as aluminum (Al) or an Al alloy having Al as a main component can be used. As an Al alloy, Al-silicon (Si) or Al-Si-copper (Cu) can be listed.

[0065] The upper surface of the high potential side wiring layer 11 has a three-layer structure of a titanium nitride (TiN) layer 21, a titanium oxynitride (TiON) layer 22, and a titanium oxide (TiO) layer 23 provided on the TiON layer 22. The thickness of the TiN layer 21 is, for example, about 30 nm to 40 nm. The thickness of the TiON layer 22 is, for example, about 30 nm to 40 nm. The thickness of the TiO layer 23 is, for example, about 30 nm to 40 nm.

[0066] The TiN layer 21 functions as an antireflection film that prevents reflection (halo) of light from the metal film when forming a resist pattern for patterning the metal film as the high potential side wiring layer 11. The TiON layer 22 is formed by diffusing oxygen (O) and nitrogen (N) in a Ti layer, and the Ti layer is formed on the TiN layer 21, and functions as an antireflection film together with the TiN layer 21. The TiO layer 23 is formed by oxidizing the upper surface of the Ti layer, and the Ti layer is formed on the TiN layer 21, and functions as an antireflection film together with the TiN layer 21.

[0067] A surface protection film (31, 32) is provided on the upper surface of the TiO layer 23. The surface protection film (31, 32) includes a first insulating film 31 provided on the TiO layer 23 and a second insulating film 32 provided on the first insulating film 31. The first insulating film 31 is composed of, for example, a silicon oxide film (SiO2 film) having a thickness of about 200 nm. The first insulating film 31 may also be composed of an insulating film (TEOS film) formed by a chemical vapor deposition (CVD) method using tetraethoxysilane (TEOS) gas of an organic silicon compound. The second insulating film 32 is composed of, for example, a silicon nitride film (Si3N4 film) having a thickness of about 500 nm or more and about 1000 nm or less.

[0068] In addition, there is no particular limitation on the number of layers and materials of the surface protection film (31, 32). For example, the surface protection film (31, 32) may be composed of a single-layer film or a stacked film of three or more layers. The surface protection film (31, 32) may also be a structure including at least any one of a polyimide film, a silicon oxide film (SiO2 film) not containing phosphorus (P) or boron (B) called an "NSG film", a silicon oxide film (PSG film) to which phosphorus is added, a silicon oxide film (BSG film) to which boron is added, and a silicon oxide film (BPSG film) to which phosphorus and boron are added.

[0069] The TiN layer 21, TiON layer 22, TiO layer 23 and surface protection films (31, 32) are provided with openings 11b penetrating the TiN layer 21, TiON layer 22, TiO layer 23 and surface protection films (31, 32). The high potential side pad 11a is composed of a portion of the high potential side wiring layer 11 located at a position exposed in the opening 11b.

[0070] The opening 11b is formed by removing a portion of the TiN layer 21, the TiON layer 22, the TiO layer 23, and the surface protection films (31, 32) using the same etching mask. The end of the second insulating film 32 is set back from the end of the TiN layer 21, the TiON layer 22, the TiO layer 23, and the first insulating film 31 by side etching. The end of the TiN layer 21, the TiON layer 22, the TiO layer 23, and the surface protection films (31, 32) are exposed on the side wall of the opening 11b.

[0071] <Method for manufacturing semiconductor device>

[0072] Next, focus on Figure 3 The cross section shown, see Figure 4A to Figure 5C An example of a method for manufacturing a semiconductor device according to the first embodiment of the present invention is described below. In addition, the method for manufacturing a semiconductor device described below is an example, and it is self-evident that the method for manufacturing a semiconductor device can be implemented by various manufacturing methods including its modified examples other than the manufacturing method described below as long as it is within the scope of the subject matter described in the present invention.

[0073] First, a semiconductor substrate such as a Si substrate is prepared, and then various elements such as semiconductor elements and passive elements are formed on the semiconductor substrate using photolithography, ion implantation, dry etching, CVD, etc., and a multilayer wiring structure is further formed on the semiconductor substrate.

[0074] Then, a wiring forming metal film 10 made of Al or an Al alloy is deposited at the uppermost layer of the multilayer wiring structure by sputtering or the like. Figure 4A As shown in FIG. 1 , a TiN layer 21 having a thickness of about 30 nm to about 40 nm is deposited on the wiring forming metal film 10 by sputtering or the like. Figure 4B As shown, a Ti layer 24 having a thickness of about 30 nm or more and about 40 nm or less is deposited on the TiN layer 21 by a sputtering method or the like. The reflectivity of the TiN layer 21 and the Ti layer 24 is lower than the reflectivity of the wiring forming metal film 10 formed of Al or an Al alloy, and functions as an anti-reflection film. In addition, the thickness of the Ti layer 24 may also be a thickness of 40 nm or more.

[0075] Here, preferably, when sequentially depositing the metal film 10 for wiring formation, the TiN layer 21, and the Ti layer 24, the metal film 10 for wiring formation, the TiN layer 21, and the Ti layer 24 are deposited by a single process (Japanese: 一貫処理). That is, preferably, using the same sputtering apparatus and transporting the wafer between the chambers in a vacuum, the metal film 10 for wiring formation, the TiN layer 21, and the Ti layer 24 are continuously deposited without returning to the atmosphere even once. When the metal film 10 for wiring formation is formed of Al or an Al alloy, the interfaces between the metal film 10 for wiring formation and the TiN layer 21 and between the TiN layer 21 and the Ti layer 24 are in a dense bonding state, thereby preventing peeling during the manufacturing process. In addition, instead of depositing the metal film 10 for wiring formation, the TiN layer 21, and the Ti layer 24 by a single process, it is also possible to sequentially deposit the metal film 10 for wiring formation, the TiN layer 21, and the Ti layer 24 using different sputtering apparatuses.

[0076] Further, when the Ti layer 24 is deposited to a film thickness of less than 30 nm, the following situation occurs: in heat treatment processes such as ozone oxidation for passivating the high-potential-side wiring layer 11 described later and plasma CVD for forming the surface protective films (31, 32), oxygen and nitrogen diffuse and collide with each other in the Ti layer 24, forming the TiON layer 22 with brittle film hardness, and the TiON layer 22 peels off due to the shear stress in the heat treatment process. Therefore, it is preferable to deposit the Ti layer 24 to a film thickness of 30 nm or more.

[0077] Next, as Figure 4C shown, a photoresist film 71 is coated on the Ti layer 24. Then, the photoresist film 71 is patterned using photolithography technology. At this time, the TiN layer 21 and the Ti layer 24 function as an antireflection film, and can prevent the reflection (halo) of light from the metal film 10 for wiring formation. The patterned photoresist film 71 is used as an etching mask, and a part of the metal film 10 for wiring formation, the TiN layer 21, and the Ti layer 24 is selectively removed by dry etching such as reactive ion etching (RIE). Through selective etching removal, the metal film 10 for wiring formation, the TiN layer 21, and the Ti layer 24 are patterned, thereby forming the wiring pattern of the high-potential-side wiring layer 11. By selectively etching and removing the metal film 10 for wiring formation, the wiring patterns of the other high-potential-side wiring layers 12, 13 and the plurality of low-potential-side wiring layers 14, 15, 16 shown in Figure 2 are also formed at the same time, but the illustration is omitted.

[0078] In Figure 4C, the cross section of the portion where the wiring pattern remains without removing the wiring forming metal film 10, the TiN layer 21, and the Ti layer 24 is shown with a focus on the high potential side wiring layer 11, and the other wiring patterns are the same. That is, a multilayer structure is formed in a manner that the TiN layer 21 and the Ti layer 24 are patterned on each of the plurality of high potential side wiring layers 12, 13 and the plurality of low potential side wiring layers 14, 15, 16. The interlayer insulating film is exposed at the portion where the wiring pattern does not exist on the plurality of high potential side wiring layers 11, 12, 13 and the plurality of low potential side wiring layers 14, 15, 16.

[0079] Next, after removing the photoresist film 71 and cleaning the surface of the Ti layer 24, a passivation treatment is performed to oxidize the Ti layer 24 by, for example, oxidizing with ozone at about 300°C. At this time, ozone diffuses from the upper surface of the Ti layer 24, such as Figure 5A As shown, an amorphous structure and anatase titanium oxide (TiO2) layer 24x with a thickness of about 5 nm to about 10 nm is formed. In addition, in the Ti layer 24, ozone from above and nitrogen from below diffuse into each other, thereby forming a TiON layer 22 between the TiN layer 21 and the TiO2 layer 24x.

[0080] Next, a first insulating film 31 such as a silicon oxide film is deposited on the TiO2 layer 24x by a plasma CVD method at a normal pressure of about 380°C or more and about 405°C or less. The first insulating film 31 is also deposited on the multilayer wiring structure exposed at the parts where no wiring pattern exists in the plurality of high potential side wiring layers 11, 12, 13 and the plurality of low potential side wiring layers 14, 15, 16. When the first insulating film 31 is deposited, a TiON layer 22 is sandwiched between the TiN layer 21 and the TiO2 layer 24x, thereby promoting the diffusion of oxygen contained in the TiO2 layer 24x downward, and the oxygen concentration of the TiO2 layer 24x is reduced, as shown in FIG. Figure 5B As shown, a hydrophilic TiO layer 23 is formed. Alternatively, after the first insulating film 31 is deposited, a spin-on glass (SOG) film may be applied on the first insulating film 31 and cured at about 400° C. or higher and 450° C. or lower.

[0081] Next, hydrogen annealing is performed at about 400°C for about 30 minutes. Figure 5C As shown, a second insulating film 32 such as a silicon nitride film is deposited on the first insulating film 31 by a plasma CVD method at about 400°C and about -390 MPa. The second insulating film 32 is also deposited on the first insulating film 31 deposited at locations where no wiring pattern exists on the plurality of high potential side wiring layers 11, 12, 13 and the plurality of low potential side wiring layers 14, 15, 16.

[0082] Next, a mask film such as a silicon nitride film is deposited on the second insulating film 32 by a plasma CVD method or the like, and the mask film is patterned by using a photolithography technique and an etching technique, but the illustration is omitted. The patterned mask film is used as an etching mask for the pad opening, and a portion of the second insulating film 32, the first insulating film 31, the TiO layer 23, the TiON layer 22, and the TiN layer 21 are selectively removed in sequence by dry etching such as RIE. As a result, as shown in FIG. Figure 3 As shown in FIG. 1 , an opening 11b is formed to expose a portion of the high potential side wiring layer 11, and a portion of the high potential side wiring layer 11 exposed in the opening 11b constitutes a high potential side pad 11a. At the side wall of the opening 11b, the second insulating film 32, the first insulating film 31, the TiO layer 23, the TiON layer 22, and the end of the TiN layer 21 are exposed. By this dry etching, a portion of each of the other multiple high potential side wiring layers 12, 13 and the multiple low potential side wiring layers 14, 15, 16 is also exposed, and a plurality of high potential side pads 12a, 13a and a plurality of low potential side pads 14a, 15a, 16a are formed at their respective positions.

[0083] <Comparative Example>

[0084] Here, a semiconductor device according to a comparative example is described. Figure 3 As shown in part in FIG. 1 , the semiconductor device according to the comparative example has a three-layer structure of a TiN layer 21, a TiON layer 22, and a TiO layer 23 on the high potential side wiring layer 11. In contrast, the semiconductor device according to the comparative example is different in that Figure 6 As partially shown in FIG. 1 , the high potential side wiring layer 11 has a two-layer structure of a TiN layer 21 and a high concentration TiO layer 25 .

[0085] That is, regarding the semiconductor device according to the first embodiment of the present invention, as in Figure 4B As shown in part in FIG. 1 , in the manufacturing process, a two-layer structure of a TiN layer 21 and a Ti layer 24 is formed on the high potential side wiring layer 11 as an anti-reflection film, and the result is Figure 3 The three-layer structure of the TiN layer 21, the TiON layer 22 and the TiO layer 23 is shown. On the other hand, in the semiconductor device according to the comparative example, only the single-layer TiN layer 21 is formed as an antireflection film in the manufacturing process, and the Ti layer 24 is not formed. Figure 6 The illustrated structure comprises a two-layer structure of a TiN layer 21 and a high-concentration TiO layer 25 .

[0086] exist Figure 6In the semiconductor device according to the comparative example shown, the end of the high-concentration TiO layer 25 is exposed on the side wall of the opening 11b. The high-concentration TiO layer 25 has a higher oxygen concentration than the TiO layer 23 and is highly hydrophilic. Therefore, in a high-temperature and high-humidity bias (THB) environment, water and OH easily penetrate into the interface between the TiN layer 21 and the high-concentration TiO layer 25. - , which makes it easy to peel off due to the decomposition reaction of the TiN layer 21 and the high-concentration TiO layer 25. In addition, TiN reacts with water to become TiO and expands in volume, thereby forming cracks in the surface protection film (31, 32) or voids in the film, causing decomposition reactions around the high-potential side pad 11a, corrosion of the wiring layer, and other undesirable conditions.

[0087] When the semiconductor device according to the comparative example is applied to HVIC, it is easy to Figure 7 As shown in FIG. 1 , peeling easily occurs around the plurality of high potential side pads 11a, 12a, and 13a due to an anodic oxidation reaction (decomposition reaction). Figure 7 , the regions A1, A2, and A3 where the TiN layer 21 and the high-concentration TiO layer 25 are peeled off are schematically shown. When a semiconductor chip such as an HVIC to which a high voltage of several hundred volts is applied to a plurality of high-potential side pads 11a, 12a, and 13a, a high temperature and high humidity bias (THB) test is performed, many impurity ions, OH in the molding resin - In addition, since the high-concentration TiO layer 25 is super-hydrophilic, the water and OH accumulated near the high-potential side pads 11a, 12a, 13a in the THB environment - Reacts with TiO to form nitrogen in the form of ammonium ions (NH4 + ) is separated from the hydrophobic TiN layer 21. As a result, the inventors of the present invention confirmed that after a precipitate such as Ti(OH)4 is formed at the separated portion, the volume expansion of TiO at the interface with the TiN layer 21 progresses, resulting in voids at the interface and cracks in the surface protection film, resulting in a poor shape of the pad.

[0088] On the other hand, according to the semiconductor device according to the first embodiment of the present invention, Figure 3 As shown in FIG. 1 , although the ends of the TiN layer 21, the TiON layer 22, the TiO layer 23 and the surface protection film (31, 32) are exposed at the side wall of the opening 11b, the TiON layer 22 as a buffer layer sandwiched between the hydrophobic TiN layer 21 and the hydrophilic TiO layer 23 promotes the diffusion of oxygen downward. As a result, the oxygen concentration of the TiO layer 23 decreases, changing from superhydrophilic to hydrophilic, thereby suppressing the rapid acquisition of water and OH from the side wall of the opening 11b. - , thereby inhibiting moisture, OH- The reaction with TiN (anodic oxidation reaction). In addition, the hydrogen bonding between the TiO layer 23 and the TiON layer 22 can be used to prevent the intrusion of moisture. As a result, the volume expansion of TiO and the NH4 + The phenomenon of separation.

[0089] Figure 8 (a) Fig. 9 (a) Fig.10 (a) shows STEM line profiles when the thickness of the Ti layer deposited on the TiN layer in the manufacturing process is 35 nm, 15 nm, and 5 nm, respectively. Figure 8 (b) Fig. 9 (b) Fig.10 (b) indicates that Figure 8 (a) Fig. 9 (a) Fig.10 The STEM image corresponding to (a) is shown in Table 1. The STEM line profile and image are of the sample after all the manufacturing steps including the protective film step have been completed.

[0090] exist Figure 8 (a) Fig. 9 (a) Fig.10 In (a), the detection amount of each element is processed so that the O element in the TEOS (P-TEOS) layer formed by plasma CVD and the Ti element and N element in the TiN layer have the same peak detection intensity. The boundary between the TiO layer 21 and the TiON layer 22 and the boundary between the TiON layer 22 and the TiO layer 23 can be roughly defined as follows.

[0091] First, if Figure 8 As shown in (a), the boundary between the TiO layer 21 and the TiON layer 22 is set to the position a where the concentration gradient of oxygen and nitrogen in the depth direction from the surface protection film 31 side changes from steep to gentle. Next, the boundary between the TiON layer 22 and the TiO layer 23 is set to the position b where the concentration gradient of oxygen and nitrogen in the depth direction from the position a becomes steep. In addition, it is desirable that the nitrogen concentration at the position c where the oxygen concentration and the nitrogen concentration intersect in the TiON layer 22 is less than 1 / 2 of the concentration at the position d where the nitrogen concentration of the TiN layer 21 is the highest.

[0092] like Figure 8 As shown in (a), when the thickness of the Ti layer deposited on the TiN layer is 30 nm or more, the regions with steep concentration gradients of oxygen and nitrogen in the Ti layer do not collide, thereby preventing the interface peeling of the film in the manufacturing process. Figure 8In (b), no peeling is observed at the interface between TiN, TiON, and TiO. Fig. 9 (a) and Fig.10 As shown in (a), when the thickness of the Ti layer deposited on the TiN layer is less than 30nm, the oxygen diffused in the Ti layer and the nitrogen concentration gradient regions with steep gradients collide in the area surrounded by the dotted line. As a result, a brittle TiON layer is generated, which sometimes induces film peeling caused by shear stress caused by high temperature treatment. Fig. 9 (b) and Fig.10 In the area surrounded by the dotted line in (b), the white portion is observed as peeling.

[0093] Therefore, in the manufacturing process of the semiconductor device, it is preferable that the film thickness of the Ti layer 24 deposited on the TiN layer 21 as an anti-reflection film is 30 nm or more. In addition, as a finished product of the semiconductor device, it is preferable that the total film thickness of the TiON layer 22 and the TiO layer 23 corresponding to the film thickness of the Ti layer 24 is 30 nm or more. By setting the film thickness of the Ti layer 24 to be 30 nm or more, the nitrogen concentration at the position where the oxygen concentration and the nitrogen concentration intersect in the TiON layer 22 can be made less than 1 / 2 of the concentration at the position where the nitrogen concentration of the TiN layer 21 is the highest.

[0094] As described above, according to the first embodiment of the present invention, in the manufacturing process of the semiconductor device, a two-layer structure in which the lower layer is a TiN layer 21 and the upper layer is a Ti layer 24 is formed on the wiring forming metal film 10 as an anti-reflection film, thereby reducing the reflection (halo) of light from the wiring forming metal film 10 when forming an anti-etching pattern for patterning multiple high-potential side wiring layers 11, 12, and 13.

[0095] Furthermore, as a finished product of the semiconductor device, a three-layer structure of a TiN layer 21, a TiON layer 22, and a TiO layer 23 is formed on the plurality of high-potential side wiring layers 11, 12, and 13. In a high-temperature and high-humidity bias environment, the TiON layer 22 prevents contact with moisture, OH, and the like. - The reaction of NH4 + Therefore, the volume expansion of the TiO layer 23 can be suppressed. Therefore, it is not necessary to perform the etching process of the TiN layer 21, the TiON layer 22, and the TiO layer 23 functioning as an anti-reflection film and the etching process of the surface protection film 32 separately in order to cover the end of the TiN layer 21 with the surface protection film, thereby suppressing the increase of process man-hours.

[0096] In addition, it is also possible to Fig.11As shown, the surface protection film 32 is formed to cover the opening 11b of the TiN layer 21, the TiON layer 22, and the TiO layer 23. In this case, although the process man-hours increase, the effect of suppressing the volume expansion of the TiO layer 23 can be enhanced.

[0097] (Second Embodiment)

[0098] <Structure of Semiconductor Device>

[0099] As the semiconductor device according to the second embodiment of the present invention, HVIC is exemplified similarly to the semiconductor device according to the first embodiment of the present invention. Fig.12 As shown, the semiconductor device according to the second embodiment of the present invention has wiring layers (high potential side wiring layers) 81, 82, 83 at the top of the multilayer wiring structure on the semiconductor substrate. Parts of the high potential side wiring layers 81, 82 constitute pads (high potential side pads) 81a, 82a. The high potential side pads 81a, 82a are divided by openings 81b, 82b of the surface protection film not shown. Fig.12 In FIG. 8 , the openings 81 b and 82 b of the surface protection film are indicated by single-dot chain lines. The high potential side wiring layer 83 forms a meandering wiring pattern.

[0100] exist Fig.13 The left and right sides are shown from Fig.12 The cross section of the peripheral area of ​​the high potential side pad 81a observed in the AA direction and the cross section of the peripheral area of ​​the high potential side pad 81a observed in the BB direction. Fig.13 In the case of a three-layer structure of the TiN layer 21, the TiON layer 22, and the TiO layer 23 on the high potential side wiring layer 81 provided throughout the entire semiconductor device as shown in FIG. 1 , there is a case where the adhesion between the TiON layer 22 and the TiO layer 23 is low, so that the SOG film is cured, hydrogen annealed, or other heat treatments cause peeling at the interface between the TiON layer 22 and the TiO layer 23. In addition, there is a case where Fig.13 As shown on the right side of FIG. 1 , due to the tensile stress F of the surface protection film (31, 32) after the deposition of the second insulating film 32, the interface peeling of the TiON layer 22 and the TiO layer 23 is externalized, resulting in poor appearance. When the film thickness of the Ti layer 24 on the TiN layer in the manufacturing process is less than 30nm, the interface peeling becomes significant.

[0101] In particular, Fig.12As shown, in area A21 of the wiring pattern formed by the high potential side wiring layer 83, and areas A22, A23, A24 near the ends (corners) of the high potential side wiring layers 81, 82 forming the high potential side pads 81a, 82a, the peeling of the interface between the TiON layer 22 and the TiO layer 23 is easily externalized due to the film stress at the ends of the high potential side wiring layers 81, 82, 83.

[0102] Therefore, in the semiconductor device according to the second embodiment of the present invention, Fig.14 As shown, the anti-reflection film has different structures in the peripheral areas (pad peripheral areas) A31 and A32 of the high potential side pads 81a and 82a and in the areas (pad away areas) A33 that are farther away from the high potential side pads 81a and 82a than the pad peripheral areas A31 and A32. Fig.14 In the figure, the pad peripheral areas A31 and A32 are shaded in gray, and the pad away area A33 is not shaded. The pad away area A33 is an area other than the pad peripheral areas A31 and A32, including the ends of the high potential side wiring layers 81 and 82 constituting the high potential side pads 81a and 82a, and the high potential side wiring layer 83 constituting the wiring pattern.

[0103] The pad peripheral regions A31 and A32 are frame-shaped plane patterns that surround the high potential side pads 81a and 82a. The pad peripheral regions A31 and A32 are set to a range up to a predetermined distance D1 from the openings 81b and 82b. In addition, the pad peripheral regions A31 and A32 are set to be a predetermined distance D2 away from the ends of the high potential side wiring layers 81 and 82. In other words, the pad away region A33 is set to include a predetermined distance D2 from the ends of the high potential side wiring layers 81 and 82. The distance D1 is, for example, 1 μm or more, preferably about 5 μm or more, and the distance D2 is, for example, about 10 μm or more.

[0104] exist Fig.15 The left and right sides are shown from Fig.14 The cross section observed in the AA direction of the pad peripheral area A31 and the cross section observed in the BB direction away from the pad area A33. Fig.15 In the pad peripheral area A31 on the left side of the , a three-layer structure of TiN layer 21, TiON layer 22 and TiO layer 23 is selectively (partially) provided on the high potential side wiring layer 81. Since the TiON layer 22 promotes the diffusion of oxygen downward, the oxygen concentration of the TiO layer 23 decreases, and the TiO layer 23 becomes hydrophilic. Therefore, in the pad peripheral area A31, the rapid moisture absorption is avoided, and the moisture, OH - The intrusion of the high potential side pad 81a can be prevented, thereby preventing the decomposition reaction of the peripheral portion of the high potential side pad 81a or the corrosion of the wiring layer when a high voltage is applied. Fig.14 The pad surrounding region A32 shown also has the same structure as the pad surrounding region A31. It is desirable that the three-layer structure is provided adjacent to the opening 11b.

[0105] On the other hand, Fig.15 In the pad away region A33 on the right side, a two-layer structure of a TiN layer 21 and a high-concentration TiO layer 25 is provided on the high-potential side wiring layer 81. There is no TiON layer between the TiN layer 21 and the high-concentration TiO layer 25, and there is no interface between TiO and TiON that has low adhesion and is easily peeled off. Therefore, peeling and poor appearance can be prevented. In addition, in the pad away region A33, since it is away from the high-potential side pads 81a and 82a, moisture and OH will not enter from the side walls of the high-potential side pads 81a and 82a. - Although the illustration is omitted, Fig.14 In the portion of the pad-distance region A33 shown, where the high potential side wiring layers 81 , 82 , 83 are not provided, the TiN layer 21 and the high concentration TiO layer 25 are provided on the multilayer wiring structure below the high potential side wiring layers 81 , 82 , 83 .

[0106] <Method for manufacturing semiconductor device>

[0107] Next, focus on Fig.15 An example of a method for manufacturing a semiconductor device according to the second embodiment of the present invention is described with reference to the cross section corresponding thereto. Fig.16A As shown, similarly to the process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, a TiN layer 21 and a Ti layer 24 are sequentially deposited on the wiring forming metal film 80 .

[0108] Then, if Fig. 16B As shown, a photoresist film 71 is coated on the Ti layer 24. Then, the photoresist film 71 is patterned using photolithography technology. At this time, the TiN layer 21 and the Ti layer 24 function as anti-reflection films, which can prevent the reflection (halo) of light from the wiring forming metal film 80. The patterned photoresist film 71 is used as an etching mask, and a portion of the wiring forming metal film 80, the TiN layer 21, and the Ti layer 24 are selectively removed by dry etching such as reactive ion etching (RIE), thereby patterning the high potential side wiring layer 81, the TiN layer 21, and the Ti layer 24. In addition, Fig. 16B The portion where the wiring-forming metal film 80 , the TiN layer 21 , and the Ti layer 24 are not removed and remain is shown.

[0109] Next, a photoresist film 72 is applied on the Ti layer 24. Then, the photoresist film 72 is patterned using a photolithography technique. The patterned photoresist film 72 is used as an etching mask, and a dry etching such as RIE is performed. Fig. 16C As shown, the Ti layer 24 in the pad away area A33 is selectively removed, so that the Ti layer 24 remains only in the pad peripheral area A31. Afterwards, the other processes of the manufacturing method of the semiconductor device involved in the second embodiment of the present invention are the same as the manufacturing method of the semiconductor device involved in the first embodiment of the present invention, so repeated descriptions are omitted.

[0110] Fig.17 and Fig.18 The spectral profiles obtained by STEM are shown in the case where a TiN layer and a Ti layer are stacked as an anti-reflection film in the pad away region A33 (comparative example), and in the case where only a single TiN layer is stacked as an anti-reflection film in the pad away region A33 (exemplary example). Fig.17 In the comparative example of , peeling was observed at a position P1 indicated by a dotted line near the boundary between TiO and TiON. Fig.18 In the example of , no sharp change in the concentration gradient near the boundary between TiO and TiN was confirmed, and no peeling was observed.

[0111] As described above, according to the second embodiment of the present invention, similarly to the first embodiment of the present invention, in the manufacturing process of the semiconductor device, a two-layer structure in which the lower layer is a TiN layer 21 and the upper layer is a Ti layer 24 is formed on the wiring forming metal film 80 as an anti-reflection film, thereby reducing the reflection (halo) of light from the wiring forming metal film 80 when forming the resist pattern for patterning the high potential side wiring layers 81 and 82.

[0112] Furthermore, according to the second embodiment of the present invention, a three-layer structure of a TiN layer 21, a TiON layer 22, and a TiO layer 23 is selectively (partially) provided on the high potential side wiring layer 81 in the pad peripheral regions A31 and A32, thereby preventing decomposition reaction of the peripheral portions of the high potential side pads 81a and 82a or corrosion of the wiring layer. On the other hand, in the pad away region A33, a two-layer structure of a TiN layer 21 and a high concentration TiO layer 25 is selectively provided on the high potential side wiring layer 81, thereby preventing peeling and poor appearance during the manufacturing process. In addition, from the viewpoint of suppressing the decomposition reaction of the high potential side pad, it is desirable that the film thickness of the Ti layer 24 is 10 nm or more.

[0113] (Other Embodiments)

[0114] As described above, the present invention is described through the first embodiment and the second embodiment, but it should not be understood that the discussion and drawings constituting part of the present disclosure are used to limit the present invention. Based on the present disclosure, various alternative embodiments, examples, and application technologies will be clear to those skilled in the art.

[0115] For example, in the first and second embodiments of the present invention, a case where a Si substrate is used as a semiconductor substrate is exemplified, but it can also be applied to a semiconductor device using a compound semiconductor substrate such as gallium arsenide (GaAs). Furthermore, it can also be applied to a semiconductor device using a wide bandgap semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN) or diamond. Furthermore, it can also be applied to a semiconductor device using a narrow bandgap semiconductor substrate such as indium antimonide (InSb), a semi-metal substrate, etc.

[0116] Furthermore, although HVIC is exemplified as the semiconductor device according to the first embodiment and the second embodiment of the present invention, the present invention is not limited to HVIC and is particularly effective for semiconductor devices to which a high voltage of several tens of volts or more is applied, for example.

[0117] Description of Reference Numerals

[0118] 10, 80: metal film for wiring formation; 11, 12, 13, 81, 82, 83: high potential side wiring layer (wiring layer); 14, 15, 16: low potential side wiring layer (wiring layer); 11a, 12a, 13a, 81a, 82a: high potential side pad (pad); 11b, 12b, 13b, 14b, 15b, 16b, 81b, 82b: opening; 14a, 15a, 16a: low potential side pad (pad); 21: titanium nitride (TiN) layer; 22: titanium oxynitride (TiON) layer; 23: titanium oxide (TiO) layer; 24: titanium (Ti) layer; 24x: titanium oxide (TiO2) layer; 25: high concentration TiO layer; 41: low potential side circuit (low-side circuit); 42: level shift circuit; 43: high potential side circuit (high-side circuit); 45: pMOS transistor; 46: nMOS transistor; 50: semiconductor device; 51: high potential side circuit area (high-side circuit area); 52: HVIC; 53: low potential side circuit area (low-side circuit area); 60: power conversion unit; 61: connection point; 65: bootstrap diode; 66: bootstrap capacitor; 67: load; 71, 72: photoresist film; A31, A32: pad peripheral area; A33: pad away area; FWD1, FWD2: freewheeling diode; S1: high voltage side switching element; S2: low voltage side switching element.

Claims

1. A semiconductor device, characterized in that: have: Wiring layer; a titanium nitride layer disposed on the wiring layer; a titanium oxynitride layer disposed on the titanium nitride layer; a titanium oxide layer disposed on the titanium oxynitride layer; as well as A surface protection film is provided on the titanium oxide layer.

2. The semiconductor device according to claim 1, wherein: The wiring layer is formed of aluminum or an aluminum alloy.

3. The semiconductor device according to claim 1 or 2, characterized in that: The surface protection film has: A silicon oxide film disposed on the titanium oxide layer; and A silicon nitride film is provided on the silicon oxide film.

4. The semiconductor device according to claim 1 or 2, characterized in that: The total film thickness of the titanium oxynitride layer and the titanium oxide layer is 30 nm or more.

5. The semiconductor device according to claim 1 or 2, characterized in that: An opening is provided which penetrates the titanium nitride layer, the titanium oxynitride layer, the titanium oxide layer, and the surface protection film to expose a portion of the wiring layer, and the exposed portion of the wiring layer constitutes a pad.

6. The semiconductor device according to claim 5, wherein: The pad is a high potential side pad in a high voltage reference circuit.

7. The semiconductor device according to claim 5, wherein: A three-layer structure consisting of the titanium nitride layer, the titanium oxynitride layer, and the titanium oxide layer is selectively provided in the peripheral area of ​​the pad. A two-layer structure composed of the titanium nitride layer and the high-concentration titanium oxide layer is selectively provided in a region farther from the pad than the peripheral region.

8. The semiconductor device according to claim 5, wherein: A three-layer structure including the titanium nitride layer, the titanium oxynitride layer, and the titanium oxide layer is provided adjacent to the opening.

9. A method for manufacturing a semiconductor device, characterized in that: Including the following processes: depositing a metal film for forming wiring on a semiconductor substrate; depositing a titanium nitride layer on the wiring forming metal film; depositing a titanium layer on the titanium nitride layer; forming a resist pattern on the titanium layer; patterning the wiring-forming metal film using the resist pattern as an etching mask to form a wiring layer; oxidizing the upper surface of the titanium layer to form a titanium oxide layer; diffusing oxygen and nitrogen in the titanium layer to form a titanium oxynitride layer between the titanium nitride layer and the titanium oxide layer; and A surface protection film is formed on the titanium oxide layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The titanium layer is deposited to have a film thickness of 30 nm or more.

11. The method for manufacturing a semiconductor device according to claim 9 or 10, characterized in that: The wiring layer, the titanium nitride layer, and the titanium layer are successively formed using the same sputtering device.

12. The method for manufacturing a semiconductor device according to claim 9 or 10, characterized in that: The method further includes the step of selectively removing a portion of each of the surface protection film, the titanium oxide layer, the titanium nitride oxide layer, and the titanium nitride layer, thereby exposing a portion of the wiring layer to form a pad.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The method further includes the following step: after depositing the titanium layer, leaving a portion of the titanium layer in a peripheral region of the pad, and selectively removing another portion of the titanium layer in a region farther from the pad than the peripheral region.

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