Design of fully depleted silicon-on-insulator flash memory

Abstract

The present invention relates to a flash memory system in which one or more circuit blocks utilize a fully depleted silicon-on-insulator transistor design to minimize leakage.

Description

Technical Field

[0001] The present invention relates to a flash non-volatile memory system in which one or more circuit blocks utilize a fully depleted silicon-on-insulator transistor design to minimize leakage and optimize performance. Background Art

[0002] Figure 1 1 shows a prior art non-volatile memory cell 110. The memory cell 110 includes a semiconductor substrate 112 of a first conductivity type, such as a P-type. The substrate 112 has a surface on which a first region 114 (also referred to as a source line SL) of a second conductivity type, such as an N-type, is formed. A second region 116 (also referred to as a drain line) also of an N-type is formed on the surface of the substrate 112. Between the first region 114 and the second region 116 is a channel region 118. A bit line BL 120 is connected to the second region 116. A word line WL 122 is positioned over and insulated from a first portion of the channel region 118. The word line 122 barely overlaps or does not overlap the second region 116 at all. A floating gate FG 124 is over another portion of the channel region 118. The floating gate 124 is insulated from the another portion and is adjacent to the word line 122. The floating gate 124 is also adjacent to the first region 114. The floating gate 124 may overlap the first region 114 to provide coupling of the region 114 to the floating gate 124. A coupling gate CG (also referred to as a control gate) 126 is located above the floating gate 124 and insulated therefrom. An erase gate EG 128 is located above the first region 114 and adjacent to the floating gate 124 and the coupling gate 126 and insulated therefrom. The top corner of the floating gate 124 may point to the inner corner of the T-shaped erase gate 128 to improve erase efficiency. The erase gate 128 is also insulated from the first region 114. The cell 110 is described in more detail in USP 7,868,175, the disclosure of which is incorporated herein by reference in its entirety.

[0003] An exemplary operation of erasing and programming of a prior art non-volatile memory cell 110 is as follows. The cell 110 is erased by a Fowler-Nordheim tunneling mechanism by applying a high voltage on the erase gate 128 while the other terminals are equal to zero volts. Electrons tunnel from the floating gate 124 into the erase gate 128, causing the floating gate 124 to be positively charged, thereby turning on the cell 110 under a read condition. The resulting cell erased state is referred to as a '1' state. The cell 110 is programmed by a source-side hot electron programming mechanism by applying a high voltage on the coupling gate 126, a high voltage on the source line 114, a medium voltage on the erase gate 128, and a programming current on the bit line 120. A portion of the electrons flowing through the gap between the word line 122 and the floating gate 124 gain sufficient energy to be injected into the floating gate 124, causing the floating gate 124 to be negatively charged, thereby turning off the cell 110 under a read condition. The resulting cell programming state is referred to as a '0' state.

[0004] Exemplary voltages that may be used for read, program, and erase operations in memory cell 110 are shown in Table 1 below:

[0005]

[0006] NOTE: "FLT" means float.

[0007] For programming operations, the EG voltage may be applied much higher (e.g., 8V) than the SL voltage (e.g., 5V) to enhance the programming operation. In this case, the unselected CG programming voltage is applied at a higher voltage (CG inhibit voltage) (e.g., 6V) to reduce the undesired erase effect of neighboring memory cells that share the same EG gate of the selected memory cell.

[0008] Another exemplary set of voltages that may be used for read, program, and erase operations in the memory cell 310 (when negative voltages may be used for read and program operations) is shown in Table 2 below:

[0009]

[0010] Another exemplary set of voltages that may be used for read, program, and erase operations in memory cell 310 (when negative voltages may be used for read, program, and erase operations) is shown in Table 3 below:

[0011]

[0012] For programming operations, the EG voltage is applied much higher (e.g., 8-9V) than the SL voltage (e.g., 5V) to enhance the programming operation. In this case, the unselected CG programming voltage is applied at a higher voltage (CG inhibition voltage) (e.g., 5V) to reduce the undesired erase effect of neighboring memory cells that share the same EG gate of the selected memory cell.

[0013] Also known in the art are fully depleted silicon-on-insulator ("FDSOI") transistor designs, such as Figures 2 to 4 As shown. FDSOI advantages include back gate (with buried oxide as gate oxide) to modulate threshold voltage (forward body bias or reverse body bias), ultra-thin undoped channel with higher mobility, and no random doping fluctuations. It has a ground plane on the back gate to adjust the injection and thus the threshold voltage. It also has a fully depleted channel to provide better electrostatic control, lower drain-induced barrier lowering DIBL and short channel effects. It has minimal source-drain junctions. Metal gate and channel length are also used to adjust the threshold voltage.

[0014] Figure 2A FDSOI CMOS circuit cross section 210 is shown. The FDSOI CMOS circuit 210 includes a silicon substrate 211 , a silicon-on-insulator 216 , a FDSOI NMOS transistor 230 , and a FDSOI PMOS transistor 240 .

[0015] FDSOI NMOS transistor 230 includes a gate 218 and source and drain 217. FDSOI NMOS transistor 230 also includes p-well 212, buried oxide layer 213 (which is an insulator) and channel 215. Channel 215 is an undoped fully depleted channel. During operation, buried oxide layer 213 minimizes any leakage from channel 214. FDSOI NMOS transistor 230 also includes p-well back gate terminal 219, which can be used to apply bias to p-well 212 in order to adjust the threshold voltage Vt of NMOS 230.

[0016] FDSOI PMOS transistor 240 includes a gate 228 and source and drain 227. FDSOI PMOS transistor 240 also includes n-well 222, buried oxide layer 223 (which is an insulator) and channel 225. Channel 225 is an undoped fully depleted channel. During operation, buried oxide layer 223 minimizes any leakage from channel 225. FDSOI PMOS transistor 240 also includes n-well back gate terminal 229, which can be used to apply bias to n-well 222 to adjust the threshold voltage Vt of PMOS 240.

[0017] Figure 3 Shown is a FDSOI CMOS circuit cross section 310. The FDSOI CMOS 310 circuit includes a silicon substrate 311, a silicon on insulator 316, a FDSOI NMOS transistor 330, and a FDSOI PMOS transistor 340.

[0018] FDSOI NMOS transistor 330 includes a gate 318 and source and drain 317. FDSOI NMOS transistor 330 also includes an n-well 312, a buried oxide layer 313 (which is an insulator) and a channel 315. Channel 315 is an undoped fully depleted channel. During operation, the buried oxide layer 313 minimizes any leakage from the channel 315. FDSOI NMOS transistor 330 also includes an n-well back gate terminal 319, which can be used to apply a bias to the n-well 312 in order to adjust the threshold voltage Vt of NMOS 330.

[0019] FDSOI PMOS transistor 340 includes a gate 328 and source and drain 327. FDSOI PMOS transistor 340 also includes p-well 312, buried oxide layer 323 (which is an insulator) and channel 325. Channel 325 is an undoped fully depleted channel. During operation, buried oxide layer 323 minimizes any leakage from channel 325. FDSOI PMOS transistor 340 also includes p-well back gate terminal 329, which can be used to apply bias to p-well 322 in order to adjust the threshold voltage Vt of PMOS 340.

[0020] Figure 4 A cross section 410 of a FDSOI and bulk CMOS hybrid MOS circuit is shown. Bulk CMOS refers to standard PMOS and NMOS transistors on bulk silicon. Hybrid MOS circuit 410 includes silicon substrate 411, silicon on insulator 416, FDSOI NMOS transistor 430, and NMOS transistor 440. NMOS transistor 440 is a conventional NMOS transistor, not a FDSOI NMOS transistor.

[0021] FDSOI NMOS transistor 430 includes a gate 418 and source and drain 417. FDSOI NMOS transistor 430 also includes a p-well 412, a buried oxide layer 413 (which is an insulator) and a channel 415. Channel 415 is an undoped fully depleted channel. During operation, the buried oxide layer 413 minimizes any leakage from channel 415. FDSOI NMOS transistor 430 also includes a p-well back gate terminal 419, which can be used to apply a bias to p-well 412 in order to adjust the threshold voltage Vt of NMOS 430.

[0022] NMOS transistor 440 includes a gate 428 and source and drain 427. NMOS transistor 440 also includes a p-well body 422 and a doped channel 423. NMOS transistor 440 also includes a p-well body terminal 429 that can be used to apply a bias to p-well body 422.

[0023] To date, fully depleted silicon-on-insulator transistor designs have not been used in flash memory systems. What is needed is a flash memory system that utilizes a fully depleted silicon-on-insulator transistor design. What is also needed is a partitioned flash memory chip that includes a body region and a FDSOI region to maximize area and minimize leakage. Summary of the invention

[0024] In the embodiments described below, a flash memory device utilizes partitions including body transistors, and the partitions include FDSOI transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a cross-sectional view of a nonvolatile memory cell of the prior art.

[0026] Figure 2 is a cross-sectional view of a prior art FDSOI CMOS circuit.

[0027] Figure 3 is a cross-sectional view of a prior art FDSOI CMOS circuit.

[0028] Figure 4 is a cross-sectional view of a prior art FDSOI CMOS circuit.

[0029] Figure 5 Various types of FDSOI NMOS and PMOS transistors used in embodiments are shown.

[0030] Figure 6 A tube die used in an embodiment is shown.

[0031] Figure 7 The basic components of the array used in the embodiments are shown.

[0032] Figure 8 A decoder is shown for generating different voltages for use with an embodiment.

[0033] Fig. 9 An implementation of a row decoder is shown.

[0034] Fig.10 Another embodiment of a row decoder is shown.

[0035] Fig.11 Another embodiment of a row decoder is shown.

[0036] Fig.12 Another embodiment of a row decoder is shown.

[0037] Fig.13 An implementation of an erase gate decoder is shown.

[0038] Fig.14 An implementation of a source line decoder is shown.

[0039] Fig.15 An implementation of a high voltage logic selector circuit is shown.

[0040] Fig.16 An implementation of a coupled-gate decoder is shown.

[0041] Fig.17 An implementation of a low logic voltage circuit is shown.

[0042] Fig.18 A sensing system that may be used in embodiments is shown.

[0043] Fig.19 An implementation of a sense amplifier is shown.

[0044] Fig. 20 Another embodiment of a sense amplifier is shown.

[0045] Fig.21 Another embodiment of a sense amplifier is shown.

[0046] Fig. 22 Another embodiment of a sense amplifier is shown.

[0047] Fig.23 An implementation of a column decoder is shown. DETAILED DESCRIPTION

[0048] Figure 5 Eight FDSOI transistor types are shown for use in the embodiments described herein.

[0049] The standard fixed bias FDSOI MOS transistor includes a PMOS transistor 510 and an NMOS transistor 550. The FDSOI PMOS transistor 510 includes an n-well biased to the Vdd power supply and optionally to ground potential, in which case the transistor channel length is modified to have a similar threshold voltage level. The FDSOI NMOS transistor 550 includes a p-well biased to ground potential. PMOS 510 and NMOS 550 are normal threshold voltage devices.

[0050] The flipped well fixed bias FDSOI MOS transistor includes a PMOS transistor 520 and an NMOS transistor 560. The FDSOI PMOS transistor 520 includes a p-well biased to a ground potential. The FDSOI NMOS transistor 560 includes an n-well biased to a ground potential. The PMOS 520 and the NMOS 560 are low threshold voltage devices, i.e., their threshold voltages are lower than the threshold voltages of the PMOS 510 and the NMOS 550.

[0051] The standard dynamic bias FDSOI MOS transistor includes a PMOS transistor 530 and an NMOS transistor 570. The FDSOI PMOS transistor 530 includes an n-well biased to a dynamic voltage source Vb_PRW. The FDSOI NMOS transistor 570 includes a p-well biased to a dynamic voltage source Vb_NRW. The dynamic voltage source is used to forward body (well) bias FBB or reverse body bias RBB to optimize performance. For PMOS 530, the dynamic voltage source Vb_PRW varies to a positive voltage of RBB (e.g., up to 3V) and varies to a negative voltage of FBB (e.g., up to -0.5V). For NMOS 570, the dynamic voltage source Vb_NRW varies to a positive voltage of FBB (e.g., 0V to 3V) and varies to a negative voltage of RBB (e.g., 0V to -3V). A deep n-well is required to isolate the p-well from the p-substrate, thereby allowing the p-well to be biased at a high level (e.g., 3V or -3V).

[0052] The flip-well dynamic bias FDSOI MOS transistor includes a PMOS transistor 540 and an NMOS transistor 580. The FDSOI PMOS transistor 540 includes a p-well biased to a dynamic voltage source Vb_PLW. The FDSOI NMOS transistor 580 includes an n-well biased to a dynamic voltage source Vb_NLW. For the PMOS 540, the dynamic voltage source Vb_PLW varies to a positive voltage of the RBB (e.g., 0V to 3V) and varies to a negative voltage of the FBB (e.g., 0V to -3V). For the NMOS 580, the dynamic voltage source Vb_NLW varies to a positive voltage of the FBB (e.g., 0V to 3V) and varies to a negative voltage of the RBB (e.g., 0V to -0.5V). A deep n-well is required to isolate the p-well from the p-substrate, thereby allowing the p-well to be biased at a high level (e.g., 3V or -3V).

[0053] In the following embodiment, Figure 5 One or more of the eight types of FDSOI transistors shown are used in flash memory systems.

[0054] Figure 6 6 shows an embodiment of the architecture of a flash memory system including a die 600. The die 600 includes: a flash memory array 601, which includes the flash memory arrays previously described in Figure 1601; row decoder circuits 602, which are used to access rows in the flash memory array 601 for reading or writing; column decoder circuits 603, which are used to access bytes in the flash memory array 601 for reading or writing; sense circuits 604, which are used to read data from the flash memory array 601; a high voltage (HV) decoder 620, which is composed of an HV decoding block 610 and HV transmission blocks 609 and 611 to deliver voltages and biases required for non-volatile operation of the flash memory array 601; control logic 605, which is used to provide various control functions such as redundancy and built-in self-test; analog circuits 606; body bias control 607, which is used to control the voltage of the body (well) region of the transistor; high voltage charge pump circuit 608, which is used to provide elevated voltages for programming and erasing operations of the flash memory array 601. The chip partitioning for FDSOI and bulk CMOS regions to achieve optimal performance is as follows.

[0055] ● Row decoder 602: Standard Vt, Flip Well Vt, Dynamic Vt FDSOI

[0056] ● Column decoder 603: standard Vt, flip well Vt, dynamic Vt FDSOI

[0057] ● Sensing circuit 604: standard Vt, flip well Vt, dynamic Vt FDSOI

[0058] ● Control logic 605: standard Vt, flip well Vt FDSOI

[0059] ● Analog Circuit 606: Standard Vt, Flip Well Vt, Dynamic Vt FDSOI

[0060] ● Body bias control circuit 607: standard Vt, flip well Vt, dynamic Vt FDSOI

[0061] ● HV charge pump circuit 608: body CMOS and FDSOI are mixed, the FDSOI area includes standard Vt, flip well Vt, dynamic Vt FDSOIHV decoder circuit 620: body CMOS and FDSOI are mixed, the FDSOI area includes standard Vt, flip well Vt, dynamic Vt FDSOI.

[0062] Figure 76. An embodiment of an array 601 is shown in FIG. 6. The array 601 includes a first plurality of sub-arrays 701 and a second plurality of sub-arrays 702. Here, the first plurality of sub-arrays 701 have bias voltages applied to their p-well and n-well regions (to achieve higher performance), and the second plurality of sub-arrays 702 do not have bias voltages applied to their p-well and n-well regions (to achieve less leakage). The array 601 also includes a row decoder 703, a high voltage sub-array source 704, and a high voltage decoder 705.

[0063] Figure 8 A decoder 800 is shown for generating bias control voltages P1_PW, P2_PW, N1_NW and N2_NW, which are used in the following embodiments. The decoder 800 includes a NAND gate 801, an inverter 802 and programmable voltage sources 803, 804, 805 and 806, as shown.

[0064] Fig. 9 A row decoder 900 is shown. The row decoder 900 includes a NAND gate 951, an inverter 952, and PMOS transistors 953, 954, 956, 958, 959, and 961 and NMOS transistors 955, 957, 960, and 962, as shown. The NAND gate 951 and the inverter 952 act as a row address decoder to decode the address signal XPA-D, thereby realizing row address decoding. PMOS 956 and NMOS 957 act as row drivers with strong strength to drive the predetermined signal ZVDD into the word lines WL0-7 of the memory cells. PMOS 954, PMOS 953, and NMOS 955 have dual functions, which can be used as row pre-drivers and can decode the address signals XPZB0-7.

[0065] The NAND gate 951 includes a transistor of type FDSOI PMOS 520 with the p-well biased to P2_PW, and a transistor of type FDSOI NMOS 560 with the n-well biased to N2_NW.

[0066] Inverter 952 includes a transistor of type FDSOI PMOS 520 with its p-well biased to P1_PW, and a transistor of type FDSOI NMOS 560 with its n-well biased to N1_NW.

[0067] PMOS transistors 953, 954, 958, and 959 are transistors of the type FDSOI PMOS 520 whose p-well is biased to P2_PW. PMOS transistors 956 and 961 are transistors of the type FDSOI PMOS 520 whose p-well is biased to P1_PW.

[0068] NMOS transistors 955 and 960 are transistors of the type FDSOI NMOS 560 with the n-well biased to N2_NW. NMOS transistors 957 and 962 are transistors of the type FDSOI NMOS 560 with the n-well biased to N1_NW. The well bias levels of P1_PW / P2_PW / N1_NW / N2_NW enable speed performance using forward biased FBB and reduced leakage using reverse biased RBB.

[0069] Fig.10 Row decoder 1000 is shown. Row decoder 1000 is identical in structure to row decoder 900 except that all transistors are of type FDSOI PMOS 520 with the p-well biased to P1_PW. The well bias level of P1_PW enables speed performance using forward biased FBBs and reduced leakage using reverse biased RBBs.

[0070] Fig.11 A row decoder 1100 is shown. Row decoder 1100 is identical in structure to row decoder 900 except that all transistors are type FDSOI NMOS 560 with n-well biased to P1_NW. The well bias level of P1_NW enables speed performance using forward biased FBBs and reduced leakage using reverse biased RBBs.

[0071] Fig.12 1. Row decoder 1200 is shown. Row decoder 1200 is structurally identical to row decoder 900, except that: NAND gate 951 comprises a transistor of type FDSOI NMOS 550 with p-well biased to P2_PW; inverter 952 comprises a transistor of type FDSOI NMOS 560 with n-well biased to P1_NW; PMOS transistors 953, 956, 958, and 961 are transistors of type FDSOI PMOS 510 with p-well biased to P1_NW; PMOS transistors 954 and 959 are transistors of type FDSOI PMOS 520 with p-well biased to P2_PW; NMOS transistors 955 and 960 are transistors of type FDSOINMOS 510 with n-well biased to P2_PW; and NMOS transistors 957 and 962 are transistors of type FDSOI NMOS 560 with n-well biased to P1_NW. The well bias level of P2_PW / P1_NW is such that speed performance is achieved using forward biased FBB and leakage is reduced using reverse biased RBB.

[0072] Fig.13An erase gate decoder 1300 is shown. In this example, FDSOI transistors are not used in the erase gate decoder 1300, but rather bulk CMOS types. HV PMOS 1301 controls the current from the HV power supply VEGSUP, and HV PMOS 1302 is used for address decoding. HV NMOS 1303 is used as a pull-down device to pull EG 1305 to a low level, or as a pass transistor to transfer the bias level EG_LOW_BIAS 1304 into the EG terminal.

[0073] Fig.14 A source line decoder 1400 is shown. In this example, FDSOI transistors are not used in the source line decoder 1400, but the bulk CMOS type. NMOS 1401 is used to transmit the SL power supply VSLSUP, NMOS 1402 is used to measure (monitor) the voltage on SL 1405, NMOS 1403 is used to transmit the low bias level SLRD_LOW_BIAS when reading or standing by, and NMOS 1404 is used to transmit the low bias level SLP_LOW_BIAS when programming.

[0074] Fig.15 A high voltage circuit selector 1500 is shown which, once enabled, outputs a positive high voltage level on ENHV and / or a negative high voltage level on ENHVNEG. FDSOI transistors are not used in the high voltage logic selector 1500 in this example.

[0075] Fig.16 A coupled gate decoder 1600 is shown. In this example, FDSOI transistors are not used in the coupled gate decoder 1600, but rather bulk CMOS types. HV PMOS 1401 is used to transmit the CG power supply, HV PMOS 1402 is used as address decoding, PMOS 1403 is used to control the current from the CG read power supply VCGRSUP, and HV PMOS 1404 is used to transmit the CG read power supply. PMOS 1405 is used to isolate negative voltage levels. NMOS 1407 is used as address decoding, NMOS 1408 and 1409 are used as negative voltage isolation, and NMOS 1410 is used to transmit the bias level CG_LOW_BIAS into CG 1406. NMOS 1411 is used to transmit the negative voltage supply VHVNEG, and NMOS 1412 is used as a negative common source common gate arrangement.

[0076] Fig.17The low voltage sector enable latch logic 1700 is shown. The low voltage logic 1700 includes latched inverters 1701 and 1702 and NMOS transistors 1703 (word line enable), 1704 (sector enable) and 1705 (for resetting latch 1701 / 1702), all of which are constructed from transistors of the type that utilize p-wells. Alternatively, the inverter 1701 may be constructed from transistors that utilize n-wells.

[0077] Fig.18 A sensing system 1800 is shown, which is similar to Figure 6 The sensing system 1800 includes sense amplifiers 1801 , 1802 , 1803 , and 1804 . Figures 19 to 22 1804. An implementation of sense amplifiers 1801, 1802, 1803, and 1804 is shown in FIG. A reference sector 1810 is used to generate a reference bias from a reference memory cell for sensing. The two inputs of the sense amplifier are coupled to two bit lines of two array planes, for example, sense amplifier 1801 is coupled to the top array plane 1820 and the bottom array plane 1821. One array plane provides the selected bit line (and therefore the selected memory cell with one word line enabled), and the other array plane provides the unselected bit lines for sensing (all word lines are disabled for that array plane) for symmetric bit line sensing.

[0078] Fig.19 Sense amplifier 1900 is shown. Sense amplifier 1900 includes PMOS transistors 1901, 1906, 1907, and 1903 (type FDSOI PMOS 520 with p-well coupled to ground potential), PMOS transistors 1905, 1908, 1909, and 1912 (type n-well coupled to V bias1800 ), NMOS transistors 1902, 1904, 1910, 1911, 1913, and 1914 (type FDSOI NMOS 560 coupled to ground potential as an n-well), and NMOS transistor 1915 (type FDSOI NMOS 550 coupled to ground potential as a p-well). PMOS 1901 and NMOS 1902 (as well as PMOS 1903 and NMOS 1904) are the first (readout) stage of the sense amplifier. PMOS 1901 is mirrored from a reference current Iref (such as from a reference cell or resistor in a reference sector 1810 of the sense system 1800). NMOS 1902 is coupled to a cell current Icell through the bit line of the selected memory cell. The drain of NMOS 1902 is a sense output node 1999, which is equal to the difference between Iref and Icell multiplied by the output impedance at node 1999, that is, Vsensed=Ro*(Icell-Iref). The drain of NMOS 1904 is a reference node 1998. PMOS 1903 is in a disabled state with Ileakpmos (copying the off-state leakage of PMOS 1901), and NMOS 1904 is coupled to the cell current leakage Icellleak of the unselected bit line (the selected bit line with all word lines disabled) through the memory cell. The drain of NMOS 1904 is a sense output node 1999, which is equal to the difference between Ileakpmos and Icellleak multiplied by the output impedance at node 1998, that is, Vrefsen=Ro*(Icellleak-Ileakpmos). The sense node 1999 and the reference node 1998 are precharged to reference voltage levels 1920 and 1921, respectively, at the beginning of sensing. Transistors 1905-1915 are the second (comparison) stage of the sense amplifier. It is a dynamically latched differential amplifier with transistors NMOS 1913 and 1914 as input pairs and sense output node 1999 and reference node 1998 as input terminals. Transistors 1906, 1907, 1910, and 1911 are latched inverters with outputs ON and OP as full voltage level (Vdd / gnd) sense outputs after sensing the difference between sense output node 1999 and reference node 1998. PMOS transistors 1905, 1908, 1909, and 1912 are used to precharge the nodes of the latched inverter to a high power supply level. NMOS 1913 and 1914 are footed input pairs (meaning NMOS transistors connected in series to the latched inverter). NMOS 1915 is an enable bias transistor for the input pair.

[0079] Fig. 20Sense amplifier 2000 is shown. Sense amplifier 2000 is identical in structure to sense amplifier 1900, except that the n-well of NMOS transistor 1913 is coupled to a variable voltage source NL5_NWB, and the n-well of NMOS transistor 1914 is coupled to a variable voltage source NL5_NWB. The variable voltage source is used to dynamically bias the well to optimize speed when active (forward body bias) and reduce leakage when standby (reverse body bias). It can also be used to eliminate threshold voltage shifts of the sense amplifier.

[0080] Fig.21 Sense amplifier 2100 is shown. Sense amplifier 2100 is identical in structure to sense amplifier 1900, except that the p-wells of PMOS transistors 1901, 1903, 1906, and 1907 are coupled to a variable voltage source PL1_PW, and the n-wells of NMOS transistors 1902, 1904, 1910, 1911, 1913, and 1914 are coupled to a variable voltage source NL1_NW. The variable voltage sources are used to optimize speed when active (forward biasing the well) and reduce leakage when idle (reverse biasing the well).

[0081] Fig. 22 A sense amplifier 2200 with FDSOI and body CMOS hybrid area partitioning is shown. The sense amplifier 2200 is structurally identical to the sense amplifier 1900, except that the p-wells of the PMOS transistors 1906 and 1907 are coupled to a variable voltage source PL1_PW, and the n-wells of the NMOS transistors 1910 and 1912 are coupled to a variable voltage source NL1_NW, and the PMOS transistors 2201 and 2202 and the NMOS transistors 2202 and 2204 are body CMOS transistors. The PMOS 2201 and NMOS 2202 and the PMOS 2203 and NMOS 2204 are the body CMOS readout stages of the amplifier. The readout stages are coupled to a high power supply level (due to the body CMOS transistors), such as 1.8v, rather than a logic power supply level, such as Vdd1.2v, in order to achieve a wide sensing range.

[0082] Fig.23 A column decoder 2300 is shown. The column decoder 2300 includes NMOS transistors 2301, 2303, 2305, 2307, and 2309 (type FDSOI NMOS 560 with n-well coupled to N1_NW) for enhancing speed when a column is selected, and NMOS transistors 2302, 2304, 2306, 2308, and 2310 (type FDSOI NMOS 550 with p-well coupled to N1_PW) for reducing leakage when a column is deselected.

Claims

1. A flash memory system, comprising: an array of flash memory cells arranged in rows and columns; and A row decoder for selecting a row of flash memory cells in the array for a read or program operation, the row decoder comprising, for each row in the array: a row address decoder for selecting a row in response to an address signal; An inverter, used for inverting the output of the row address decoder; A row pre-driver, used to receive the output of the row address decoder and the output of the inverter, the row pre-driver comprising: a first fully depleted silicon-on-insulator PMOS transistor including a first terminal, a gate coupled to an output of the row address decoder, and a second terminal coupled to ground; a second fully depleted SOI PMOS transistor including a first terminal coupled to the power supply, a second terminal coupled to the first terminal of the first PMOS transistor, and a gate coupled to the output of the inverter; and a first fully depleted SOI NMOS transistor including a first terminal coupled to the second terminal of the second PMOS transistor, a gate coupled to the output of the inverter, and a second terminal coupled to ground; and a row driver comprising: a second fully depleted silicon-on-insulator NMOS transistor, the second fully depleted silicon-on-insulator NMOS transistor including a first terminal coupled to a voltage source, a second terminal, and a gate coupled to an output of the row pre-driver; and a third fully depleted silicon-on-insulator PMOS transistor, the third fully depleted silicon-on-insulator PMOS transistor including a first terminal coupled to a second terminal of the fully depleted silicon-on-insulator NMOS transistor, a second terminal coupled to ground, and a gate coupled to the output of the row pre-driver to drive a word line in the array; Wherein, each fully depleted silicon-on-insulator NMOS transistor comprises: an n-well located below the buried oxide layer and coupled to a first dynamic voltage source providing a forward body bias or a reverse body bias to the NMOS transistor; and Each fully depleted silicon-on-insulator PMOS transistor includes a p-well located below the buried oxide layer and coupled to a second dynamic voltage source providing a forward body bias or a reverse body bias to the PMOS transistor.

2. The flash memory system of claim 1, wherein the memory cell comprises a source side injection flash memory cell.

3. The flash memory system of claim 2, wherein each source side injection flash memory cell comprises: an erase gate, the erase gate being used to provide erasure; coupling grid; and A source line is used to provide a programming current.

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