Three-dimensional flash memory and methods of manufacturing the same

Abstract

A three-dimensional flash memory and a method of manufacturing the same are disclosed. According to one embodiment, the three-dimensional flash memory can have a structure for integration and can be manufactured by a manufacturing method of efficiently forming a word line.

Description

TECHNICAL FIELD

[0001] The following embodiments relate to a three-dimensional flash memory and a method of manufacturing the same. BACKGROUND

[0002] A flash memory is an electrically erasable programmable read-only memory (EEPROM) whose input and output of data are electrically controlled by F-N tunneling (Fowler-Nordheim tunneling) or hot electron injection.

[0003] In recent flash memories, a three-dimensional structure has been applied in which cells are vertically stacked to increase integration to provide high performance and achieve a low price required by consumers. Referring to Figure 1 and Figure 2 (shows a three-dimensional flash memory according to the related art), the three-dimensional flash memory 100 has a structure including at least one memory cell string 110 including a channel layer 111 extending in a vertical direction and a charge storage layer 112 formed to surround the channel layer 111, a plurality of electrode layers 120 connected to the at least one memory cell string 110 in a horizontal direction and stacked, and a plurality of insulating layers 130 alternately formed between the plurality of electrode layers 120. Hereinafter, since each of the plurality of electrode layers 120 is used as a word line, the plurality of electrode layers 120 will be described as a plurality of word lines 120.

[0004] Here, a contact 121 to be connected to an external wiring will be formed on each of the plurality of word lines 120, and thus, the plurality of word lines 120 have a stepped structure including a stepped portion 122 and a flat portion 123, as shown.

[0005] Here, only the contacts 121 of the plurality of word lines 120 are formed in the stepped portions 122, respectively, and only the at least one memory cell string 110 is formed in the flat portions 123. That is, the at least one memory cell string 110 having a memory function will be formed only on the flat portions 123, and thus, a large amount of area of the three-dimensional flash memory 100 is wasted. In addition, the more the number of steps of the three-dimensional flash memory 100, the higher the proportion of the area of the stepped portions 122 with respect to the total memory area, thereby reducing the overall integration.

[0006] Therefore, there is a need to propose a three-dimensional flash memory technology to improve integration by efficiently using the stepped portions 122.

[0007] In addition, the contacts 121 of the plurality of word lines 120 are formed on the total stepped regions of the plurality of word lines 120, respectively, and thus, a large area of the three-dimensional flash memory 100 is wasted. In addition, the more the number of steps of the three-dimensional flash memory 100, the higher the proportion of the area of the contacts 121 with respect to the total memory area, and thus, the overall integration is reduced.

[0008] Therefore, there is a need to propose a three-dimensional flash memory technology to achieve integration by reducing the area for forming contacts.

[0009] Referring to a method of manufacturing a three-dimensional flash memory according to the related art, Figures 10a to 10d According to the method, as shown in Figure 10a , a photoresist 1030 is formed on a mold structure in which a plurality of word lines 1010 and a plurality of insulating layers 1020 are alternately stacked, and the photoresist 1030 is trimmed, and then, as shown in Figure 10b , an etching operation is performed on an uppermost word line 1011 among the plurality of word lines 1010 to form a portion of a stepped shape. Next, in the method of manufacturing a three-dimensional flash memory according to the related art, as shown in Figure 10c , the photoresist 1030 is trimmed, and then, as shown in Figure 10d , an etching operation is performed on the word line 1011 and a word line 1012 whose surfaces are exposed to form two portions having a stepped shape. In the method of manufacturing a three-dimensional flash memory according to the related art, by repeating the trimming operation and the etching operation as shown up to Figure 10j , and then removing the photoresist 1030 as shown in Figure 10k , the word lines 1010 having a stepped shape can be completed.

[0010] However, in the method of manufacturing a three-dimensional flash memory according to the related art, there is a disadvantage that the etching operation needs to be repeatedly performed one less than the number of steps of the word lines 1010.

[0011] Therefore, there is a need to propose a technology to simplify the manufacturing process of a word line by reducing the number of repetitions of an etching operation. SUMMARY

[0012] TECHNICAL PROBLEM

[0013] According to embodiments, a three-dimensional flash memory and a method of manufacturing the same are proposed to achieve integration by efficiently using a stepped portion.

[0014] Specifically, according to embodiments, a three-dimensional flash memory and a method of manufacturing the same are proposed in which at least one memory cell string is formed in both a planar portion and a stepped portion included in a stepped shape of a plurality of word lines.

[0015] Further, according to embodiments, a three-dimensional flash memory and a method of manufacturing the three-dimensional flash memory are proposed to achieve integration by reducing an area for forming a contact.

[0016] In particular, according to embodiments, a three-dimensional flash memory and a method of manufacturing the three-dimensional flash memory are proposed, in which a contact of each of the plurality of word lines is formed only in a minimized partial area of an entire area of each of the plurality of word lines.

[0017] Further, according to embodiments, a method of manufacturing a three-dimensional flash memory is proposed, in which a manufacturing process is simplified by reducing a number of repetitions of an etching operation for a word line.

[0018] In particular, according to embodiments, a method of manufacturing a three-dimensional flash memory is proposed, in which a plurality of word lines is prepared by dividing the plurality of word lines into an upper word line group and a lower word line group stacked in a stepped shape in sequence, and then simultaneously performing an etching operation for each of the upper word line group and the lower word line group, thereby significantly reducing a number of repetitions of an etching operation for a word line.

[0019] Further, according to embodiments, a three-dimensional flash memory manufactured according to the above-described method of manufacturing a three-dimensional flash memory is proposed.

[0020] In particular, according to embodiments, a three-dimensional flash memory having a structure including a portion having a different height from other portions in a stepped shape having an equal-pitch width and an equal-pitch height when the stepped shape is formed by using a plurality of word lines is proposed.

[0021] Further, according to embodiments, a three-dimensional flash memory having a structure including a portion having a different width from other portions in a stepped shape having an equal-pitch width and an equal-pitch height when the stepped shape is formed by using a plurality of word lines is proposed.

[0022] Further, according to embodiments, a three-dimensional flash memory having a structure including a portion having a different height from other portions in a stepped shape having an equal-pitch width and an equal-pitch height when the stepped shape is formed by using a plurality of word lines and a portion having a different width is proposed.

[0023] Solution to the problem

[0024] According to an embodiment, a three-dimensional flash memory for implementing integration includes at least one memory cell string extending in a vertical direction and including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer, and a plurality of word lines orthogonally connected to the at least one memory cell string and stacked and extending in a horizontal direction, wherein the plurality of word lines extend in different lengths from each other to form a stair shape including a stepped portion and a flat portion, and wherein the at least one memory cell string is formed in both the flat portion and the stepped portion.

[0025] A contact of each of the plurality of word lines can be formed only in a minimized partial area of each of a plurality of steps of the stepped portion.

[0026] The minimized partial area can include an area corresponding to a cross-sectional area of the contact of each of the plurality of word lines.

[0027] For each step of the stepped portion, the at least one memory cell string formed in the stepped portion can be located in a same column as the contact of each word line formed in the stepped portion.

[0028] According to an embodiment, a three-dimensional flash memory for implementing integration includes at least one memory cell string extending in a direction and including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer, and a plurality of word lines orthogonally connected to the at least one memory cell string, wherein a contact of each of the plurality of word lines is formed only in a minimized partial area of an entire area of each of the plurality of word lines.

[0029] Since the contact of each of the plurality of word lines is formed only in the minimized partial area of the entire area of each of the plurality of word lines, the plurality of word lines can provide a space at which at least one additional memory cell string not arranged in a same array as the at least one memory cell string is formed.

[0030] Since the at least one additional memory cell string is formed in the space, the plurality of word lines can be shared by the at least one memory cell string and the at least one additional memory cell string.

[0031] The minimized partial area at which the contact of each of the plurality of word lines is formed can include an area in which the entire area of each of the plurality of word lines is located in a same row.

[0032] According to an embodiment, a method of manufacturing a three-dimensional flash memory for efficiently forming a word line includes preparing a plurality of word lines stacked in a horizontal direction by dividing the plurality of word lines into an upper word line group and a lower word line group, wherein the upper word line group and the lower word line group have different horizontal sizes and are sequentially stacked in a stepped shape such that at least a portion of an upper surface of each of the upper word line group and the lower word line group is exposed, forming a photoresist on at least a portion of the upper surface of the upper word line group and at least a portion of the upper surface of the lower word line group, and simultaneously performing an etching operation on each of the upper word line group and the lower word line group on which the photoresist is formed.

[0033] The lower word line group can have a greater horizontal size than the upper word line group.

[0034] The preparing of the plurality of word lines by dividing the plurality of word lines into the upper word line group and the lower word line group can include determining a horizontal size of the lower word line group to include an etching stop distance to prevent etching of a lowermost word line in the upper word line group when performing the etching operation on the lower word line group.

[0035] The preparing of the plurality of word lines by dividing the plurality of word lines into the upper word line group and the lower word line group can include arranging an etching stop protection layer between the upper word line group and the lower word line group to prevent etching of an uppermost word line in the lower word line group when performing the etching operation on the upper word line group.

[0036] The simultaneously performing of the etching operation on each of the upper word line group and the lower word line group can be repeatedly performed based on a number of steps by which word lines included in the upper word line group are stacked and a number of steps by which word lines included in the lower word line group are stacked.

[0037] Disclosed advantageous effects

[0038] According to embodiments, a three-dimensional flash memory and a method of manufacturing the three-dimensional flash memory can be proposed to achieve integration by efficiently using a stepped portion.

[0039] Specifically, according to embodiments, a three-dimensional flash memory and a method of manufacturing the three-dimensional flash memory can be proposed in which at least one memory cell string is formed in both a planar portion and a stepped portion included in a stepped shape of a plurality of word lines.

[0040] Further, according to embodiments, a three-dimensional flash memory and a method of manufacturing the three-dimensional flash memory can be proposed to achieve integration by reducing an area for forming a contact.

[0041] Specifically, according to embodiments, a three-dimensional flash memory and a method of manufacturing the three-dimensional flash memory can be proposed in which a contact of each of the plurality of word lines is formed only in a minimized partial area of an entire area of each of the plurality of word lines.

[0042] Further, according to an embodiment, a method of manufacturing a three-dimensional flash memory can be proposed, in which a manufacturing process is simplified by reducing the number of repetitions of an etching operation on a word line.

[0043] In particular, according to an embodiment, a method of manufacturing a three-dimensional flash memory can be proposed, according to which a plurality of word lines is prepared by dividing the plurality of word lines into an upper word line group and a lower word line group stacked in a stepped shape in sequence, and then simultaneously performing an etching operation on each of the upper word line group and the lower word line group, thereby significantly reducing the number of repetitions of the etching operation on the word line.

[0044] Further, according to an embodiment, a three-dimensional flash memory manufactured according to the above-described method of manufacturing a three-dimensional flash memory can be proposed.

[0045] In particular, according to an embodiment, a three-dimensional flash memory having a structure including a portion having a different height from other portions in a stepped shape having an equal-pitch width and an equal-pitch height when the stepped shape is formed by using a plurality of word lines can be proposed.

[0046] Further, according to an embodiment, a three-dimensional flash memory having a structure including a portion having a different width from other portions in a stepped shape having an equal-pitch width and an equal-pitch height when the stepped shape is formed by using a plurality of word lines can be proposed.

[0047] Further, according to an embodiment, a three-dimensional flash memory having a structure including a portion having a different height from other portions in a stepped shape having an equal-pitch width and an equal-pitch height when the stepped shape is formed by using a plurality of word lines and a portion having a different width can be proposed. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 is a plan view of a three-dimensional flash memory according to the related art.

[0049] Figure 2 is a cross-sectional view of a three-dimensional flash memory according to the related art.

[0050] Figure 3 is a plan view of a three-dimensional flash memory according to an embodiment.

[0051] Figure 4 is a cross-sectional view of a three-dimensional flash memory according to an embodiment.

[0052] Figure 5 is a flowchart of a method of manufacturing a three-dimensional flash memory according to an embodiment.

[0053] Figures 6a to 6i is a diagram for describing a method of manufacturing a three-dimensional flash memory according to an embodiment.

[0054] Figure 7 is a plan view of a three-dimensional flash memory according to an embodiment.

[0055] Figure 8a and Figure 8b is a cross-sectional view of a three-dimensional flash memory according to an embodiment.

[0056] Figure 9 is a flowchart of a method of manufacturing a three-dimensional flash memory according to an embodiment.

[0057] Figures 10a to 10k is a diagram for describing a method of manufacturing a three-dimensional flash memory according to the related art.

[0058] Figure 11 is a flowchart of a method of manufacturing a three-dimensional flash memory according to an embodiment.

[0059] Figures 12a to 12k is a diagram for describing a method of manufacturing a three-dimensional flash memory according to an embodiment.

[0060] Figures 13a to 13c shows a three-dimensional flash memory manufactured using the method of manufacturing a three-dimensional flash memory described with reference to Figure 11 DETAILED DESCRIPTION

[0061] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the inventive concept is not limited to the embodiments. In addition, the same reference numerals are used throughout the drawings to refer to the same elements.

[0062] The terms used in the present specification are those used by the one of ordinary skill in the art to appropriately express embodiments of the inventive concept, and the terms can be changed according to the intention of the one of ordinary skill in the art, precedents, or customs. Therefore, the terms used in the specification should be defined based on the description of the inventive concept.

[0063] Figure 3 is a plan view of a three-dimensional flash memory according to an embodiment, Figure 4 is a cross-sectional view of a three-dimensional flash memory according to an embodiment.

[0064] With reference to Figure 3 and Figure 4 , the three-dimensional flash memory 300 can include at least one string of memory cells 310, 320, 330 extending vertically, and a plurality of word lines 340 connected orthogonally to the at least one string of memory cells 310, 320, 330 and stacked and extending in a horizontal direction.

[0065] ​The at least one memory cell string 310, 320, 330 can include at least one channel layer 311 and at least one charge storage layer 312 surrounding the at least one channel layer 311. The at least one channel layer 311 can include single-crystal silicon or polycrystal silicon extending in a vertical direction, and can be formed using a selective epitaxial growth process or a phase transition epitaxial process in which a substrate (not shown) is used as a seed. Also, the at least one channel layer 311 can have a hollow tube shape and further include a buried layer (not shown) therein.

[0066] The at least one charge storage layer 312 can include an element having a storage function of storing charges from a current flowing through the plurality of word lines 340, and can have, for example, an oxide-nitride-oxide (ONO) structure. Hereinafter, although the at least one charge storage layer 312 is described as including only a vertical element, the inventive concept is not limited thereto, and the at least one charge storage layer 312 can further include a horizontal element.

[0067] Also, although not shown in the drawings, at least one tunnel insulating layer (not shown) surrounding the at least one memory cell string 310, 320, 330 and extending vertically can be disposed outside the at least one memory cell string 310, 320, 330. The at least one tunnel insulating layer can include an insulating material having a high-k characteristic (for example, an insulating material such as Al2O3, HfO2, TiO2, La2O5, BaZrO3, Ta2O5, ZrO2, Gd2O3, or Y2O3).

[0068] The plurality of word lines 340 have a function of applying a voltage to the at least one memory cell string 310, 320, 330, and can include a conductive material such as W, Ti, Ta, Cu, or Au. The plurality of word lines 340 can extend at different lengths from each other to form a stepped shape including a stepped portion 350 and a flat portion 360. For example, among the plurality of word lines 340, a first word line 341 in a lowermost portion can have a longest horizontal length, a second word line 341 located above the first word line 341 can have a second longest horizontal length, and a third word line 343 in an uppermost portion can have a shortest horizontal length, thereby forming a stepped shape including a stepped portion 350 and a flat portion 360.

[0069] Specifically, the three-dimensional flash memory 300 according to the embodiment is characterized in that the at least one memory cell string 310, 320, 330 is formed in both the planar portion 360 and the stepped portion 350. For example, the first memory cell string 310 and the second memory cell string 320 can be formed in the stepped portion 350, and the third memory cell string 330 can be formed in the planar portion 360. Accordingly, unlike the three-dimensional flash memory according to the related art in which the at least one memory cell string is formed only in the planar portion 360, the overall integration of the three-dimensional flash memory 300 according to the embodiment can be improved.

[0070] Here, the contacts 341-1, 342-1 of the plurality of word lines 340 can be formed only in a minimized partial area in each of the plurality of steps 351, 352 constituting the stepped portion 350. Hereinafter, the minimized partial area can refer to an area corresponding to a cross-sectional area of each of the contacts 341-1 and 341-2 of the plurality of word lines 340, for example, an area having an area equal to the cross-sectional area of each of the contacts 341-1 and 341-2 of the plurality of word lines 340 among the total area of each of the plurality of steps 351 and 352.

[0071] Further, for each of the plurality of steps 351 and 352 constituting the stepped portion 350, the at least one memory cell string 310, 320 formed in the stepped portion 350 can be located in the same column as the contact 341-1, 342-1 of the word line 341, 342 formed in the stepped portion 350. For example, the first memory cell string 310 formed in the step 351 of the first word line 341 and the contact 341-1 of the first word line 341 can be located in the same column, and the second memory cell string 320 formed in the step 352 of the second word line 342 and the contact 342-1 of the second word line 342 can be located in the same column.

[0072] Since, for each of the plurality of steps 351, 352 constituting the stepped portion 350, the at least one memory cell string 310, 320 formed in the stepped portion 350 is located in the same column as each contact 341-1, 342-1 of each word line 341, 342 formed in the stepped portion 350, the external wiring 370 connected to each contact 341-1, 342-1 of the word line 341, 342 formed in the stepped portion 350 and the drain line 380 connected to the at least one memory cell string 310, 320 formed in the stepped portion 350 can also be located in the same column.

[0073] Further, the three-dimensional flash memory 300 can further include a plurality of interlayer insulation layers 390 between the plurality of word lines 340. However, the inventive concept is not limited thereto, and instead of the plurality of interlayer insulation layers 380, a plurality of air gaps can be arranged to space the plurality of word lines 340 apart from each other.

[0074] As described above, the three-dimensional flash memory 300 according to the embodiment can include at least one of the memory cell strings 310, 320 in the stepped portions 350 of the plurality of word lines 340, and thus, can include more memory cell strings 310, 320, 330 than the structure according to the related art in which the memory cell strings are not formed in the stepped portions 350. Accordingly, the integration of the three-dimensional flash memory 300 can be significantly increased.

[0075] Figure 5 is a flowchart of a method of manufacturing a three-dimensional flash memory according to an embodiment. Figures 6a to 6i is a diagram for describing a method of manufacturing a three-dimensional flash memory according to an embodiment. Hereinafter, as a main body for performing the method of manufacturing a three-dimensional flash memory, an automated and mechanized manufacturing system can be used, and the three-dimensional flash memory manufactured in the following described operations (S510 to S540) has the structure described with reference to Figure 3 and Figure 4 .

[0076] Referring to Figure 5 , in operation S510, the manufacturing system according to the embodiment prepares a semiconductor structure 600 in which a plurality of word lines 610 and a plurality of insulation layers 620 are alternately stacked, as shown in Figure 6a .

[0077] Next, in operation S520, the manufacturing system forms at least one memory cell string 630 (including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer) extending vertically in the entire region of the semiconductor structure 600, except for a minimum portion region 601, 602, 603 in which a contact 611, 612, 613 of the plurality of word lines 610 is to be formed, respectively.

[0078] Hereinafter, the minimum portion region 601, 602, 603 can refer to a region having an area equal to a cross-sectional area of the contact 611, 612, 613 of the plurality of word lines 610, for example, a region in the entire region of each of a plurality of steps 614, 615, 616 to be included in a stepped shape.

[0079] For example, by taking into account the arrangement of the minimized partial regions 601, 602, 603, the manufacturing system can form at least one vertical hole 604, 605, 606 in a vertical direction in the entire region of the semiconductor structure 600 except for the minimized partial regions 601, 602, 603, so that the minimized partial regions 601, 602, 603 are respectively included in a plurality of steps 614, 615, 616 to be included in a ladder shape (the plurality of word lines 610 will have the ladder shape), as shown in Figure 6b and Figure 6c Then, the manufacturing system forms at least one memory cell string 630 in the at least one vertical hole 604, 605, 606, as shown in Figure 6d and Figure 6e .

[0080] Here, in the operation of forming the at least one vertical hole 604, 605, 606, the manufacturing system can form at least one vertical hole 604, 605, 606 in a vertical direction for each of the plurality of steps 604, 605, 606, so that the at least one vertical hole 604, 605, 606 is located in the same column as the minimized partial regions 601, 602, 603 respectively included in the plurality of steps 614, 615, 616 to be formed in operation S530 (to be described later).

[0081] Next, in operation S530, the manufacturing system etches a specific region including the minimized partial regions 601, 602, 603 in a ladder shape, as shown in Figure 6f and Figure 6g For example, the manufacturing system can form a ladder shape including a step portion 640 including a plurality of steps 614, 615, 616 and a flat portion 650 by etching a specific region including the minimized partial regions 601, 602, 603 in a ladder shape.

[0082] Operation S530 can be performed by repeatedly performing a trimming operation and an etching operation based on the number of steps of the plurality of steps 614, 615, 616 to be formed, and the etching method used in operation S530 can be an etching method that allows the at least one memory cell string 630 and the plurality of word lines 610 to be etched at the same time. That is, in operation S530, the manufacturing system can use an etching method that allows the material of the at least one memory cell string 630 and the material of the plurality of word lines 610 to be etched at the same depth at the same time.

[0083] Next, in operation S540, the manufacturing system can form respective contacts 611, 612, 613 of the plurality of word lines 610 in the minimized partial regions 601, 602, 603, as shown in Figure 6h and Figure 6i Here, the manufacturing system can form external wiring connected to the respective contacts 611, 612, 613 of the plurality of word lines 610 and a drain line connected to the at least one memory cell string 630 at the same time as forming the contacts 611, 612, 613 of the plurality of word lines 610.

[0084] Figure 7 is a plan view of a three-dimensional flash memory according to an embodiment, Figure 8a and Figure 8b is a cross-sectional view of a three-dimensional flash memory according to an embodiment.

[0085] Referring to Figures 7 to 8b , a three-dimensional flash memory 700 according to an embodiment includes at least one memory cell string 720 extending in one direction and a plurality of word lines 730 on a substrate 710. In the three-dimensional flash memory 700, a drain line can be disposed on and connected to the at least one memory cell string 720, and each of the plurality of word lines 730 can be connected to external wiring through a contact 731. Hereinafter, the drain line and the external wiring are shown only in Figure 7 and are omitted in Figure 8a and Figure 8b

[0086] The at least one memory cell string 720 can include at least one channel layer 721 and at least one charge storage layer 722 surrounding the at least one channel layer 721. The at least one channel layer 721 can include single-crystal silicon or polycrystal silicon and can be formed using a selective epitaxial growth process or a phase transition epitaxial process in which the substrate 710 is used as a seed crystal.

[0087] The at least one charge storage layer 722 can include an element that stores a charge from a current flowing through the plurality of word lines 730 and can have, for example, an oxide-nitride-oxide (ONO) structure. Although the at least one charge storage layer 722 is described below as including only vertical elements extending in a direction orthogonal to the substrate 710, the inventive concept is not limited thereto, and the at least one charge storage layer 722 can also include horizontal elements parallel to and contacting the plurality of word lines 730.

[0088] ​The plurality of word lines 730 are connected to the at least one memory cell string 720 in a vertical direction and can be alternately arranged with respect to the plurality of insulating layers 740. The plurality of word lines 730 can include a conductive material such as tungsten, titanium, tantalum, and the plurality of insulating layers 740 can include various insulating materials.

[0089] The plurality of word lines 730 are formed in a stepped shape and can be connected to an external wiring via a contact 731 formed in each of the stepped shape. In particular, the contacts 731 of the plurality of word lines 730 are characterized in that they are respectively formed only in a minimized partial area of an entire area of each of the plurality of word lines 730. The contact 731 of each of the plurality of word lines 730 formed in the minimized partial area as described below refers to the contact 731 formed only in an area corresponding to a cross section of the contact 731 in the entire area of each of the plurality of word lines 730.

[0090] In addition, the minimized partial area in which the contact 731 of each of the plurality of word lines 730 is formed can be an area located in the same row in the entire area of each of the plurality of word lines 730. That is, when the contact 731 is formed only in an area corresponding to a cross section of the contact 731 in the entire area of each of the plurality of word lines 730, the contact 731 can be formed in an area located in the same row in each of the plurality of word lines 730.

[0091] As described above, since the contact 731 of each of the plurality of word lines 730 is formed only in a minimized partial area of an entire area of each of the plurality of word lines 730, a space 751 at which at least one other memory cell string 750 not arranged in the same array as the at least one memory cell string 720 can be provided. Accordingly, the three-dimensional flash memory 700 can include more memory cell strings 720, 750, and thus have a higher degree of integration. The same array as the at least one memory cell string 720 below refers to a group of memory cell strings including the at least one memory cell string 720 and memory cell strings arranged in the same column as the at least one memory cell string 720, and thus the at least one other memory cell string 750 not arranged in the same array as the at least one memory cell string 720 can refer to a memory cell string arranged in a different column from the at least one memory cell string 720.

[0092] Here, since the at least one other memory cell string 750 is formed in the space 751, the plurality of word lines 730 can be shared by the at least one memory cell string 720 and the at least one other memory cell string 750. Hereinafter, the plurality of word lines 730 shared by the at least one memory cell string 720 and the at least one other memory cell string 750 means that the plurality of word lines 730 are used to provide current to both the at least one memory cell string 720 and the at least one other memory cell string 750.

[0093] According to the three-dimensional flash memory 700 according to the embodiment, since the contact 731 of each of the plurality of word lines 730 is formed as described only in the minimized partial region of the entire region of each of the plurality of word lines 730, the space 751 is provided at which the at least one other memory cell string 750 is formed which is not arranged in the same array as the at least one memory cell string 720, and thus, the three-dimensional flash memory 700 can include a large number of memory cell strings 720, 750. Accordingly, the integration of the three-dimensional flash memory 700 can be significantly increased.

[0094] Figure 9 is a flowchart of a method of manufacturing a three-dimensional flash memory according to an embodiment. Hereinafter, as a main body for performing the method of manufacturing a three-dimensional flash memory, an automated and mechanized manufacturing system can be used, and the three-dimensional flash memory manufactured in the following described operations (S910 to S940) has the structure described with reference to Figures 7 to 8b .

[0095] Referring to Figure 9 , the manufacturing system according to the embodiment prepares a mold structure in which a plurality of word lines and a plurality of insulating layers are alternately stacked in operation S910.

[0096] Next, in operation S920, the manufacturing system forms at least one memory cell string including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer in a direction, in a region of the mold structure except for a minimized partial region in which a contact of each of the plurality of word lines is to be formed.

[0097] For example, the manufacturing system can form a vertical hole in a remaining region except for the minimized partial region at which the contact of each of the plurality of word lines is to be formed, such that a substrate included in the mold structure is exposed, and then can deposit the at least one charge storage layer in the vertical hole and fill the at least one channel layer in the vertical hole, thereby forming the at least one memory cell string.

[0098] Here, the minimized partial region in which the contact of each of the plurality of word lines is to be formed can be a region of each of the plurality of word lines corresponding to a cross section of the contact among the entire region of each of the plurality of word lines, and can be a region in the same row on the region of each of the plurality of word lines.

[0099] Further, in operation S920, to provide a space in which at least one other memory cell string not arranged in the same array as the at least one memory cell string is to be formed, the manufacturing system can form at least one memory cell string extending in one direction in a remaining region, and then form the at least one other memory cell string in the space in one direction.

[0100] Therefore, in operation S920, the at least one other memory cell string can extend in one direction such that the plurality of word lines are shared between the at least one memory cell string and the at least one other memory cell string.

[0101] As described above, in operation S920, the manufacturing system leaves only a minimized partial region of the entire region of each of the plurality of word lines as a region for forming a contact, and thus, a memory cell string can be formed in the entire region except for the minimized partial region, thereby further improving the integration of the memory cell string.

[0102] Next, in operation S930, the manufacturing system etches the minimized partial region in which the contact of each of the plurality of word lines is to be formed in a staircase shape.

[0103] Next, in operation S940, the manufacturing system forms the contact of each of the plurality of word lines in the etched region.

[0104] Figure 11 is a flowchart of a method of manufacturing a three-dimensional flash memory according to an embodiment. Figures 12a to 12k is a diagram for describing a method of manufacturing a three-dimensional flash memory according to an embodiment. Hereinafter, as a subject for performing the method of manufacturing a three-dimensional flash memory, a manufacturing system that is automated and mechanized can be used.

[0105] Referring to Figures 11 to 12k , the manufacturing system prepares the stacked plurality of word lines 1210 in a horizontal direction by dividing the plurality of word lines 1210 into an upper word line group 1220 and a lower word line group 1230 in operation S1110, as shown in Figure 12a .

[0106] The upper word line group 1220 and the lower word line group 1230 can be prepared by sequentially stacking them with different horizontal sizes in a stepped shape such that at least a portion of their upper surfaces 1221 and 1231 is exposed. For example, the upper word line group 1220 and the lower word line group 1230 can be provided by sequentially stacking them, respectively, where the horizontal size of the lower word line group 1230 is greater than that of the upper word line group 1220 such that at least a portion of the upper surfaces 1221, 1231 is exposed.

[0107] Here, the operation S1110 refers not only to an operation of preparing only the plurality of word lines 1210 but also to an operation of preparing a mold structure including a plurality of insulating layers 1223, 1233 alternately included between the plurality of word lines 1210 and a vertical string 1240 including a channel layer 1241 and a charge storage layer 1242. Accordingly, the upper word line group 1220 can include upper word lines 1222 and upper insulating layers 1223 alternately included between the upper word lines 1222, the lower word line group 1230 can include lower word lines 1232 and lower insulating layers 1233 alternately included between the lower word lines 1232, and the upper word line group 1220 and the lower word line group 1230 can share one vertical string 1240.

[0108] For example, in the operation S1110, the manufacturing system can prepare the plurality of word lines 1210 having a stepped form and divided into the upper word line group 1220 and the lower word line group 1230 by etching a portion 1211, 1212 of the mold structure in which the plurality of word lines 1222, 1232 and the plurality of insulating layers 1223, 1233 are alternately stacked and the vertical string 1240 is formed in a vertical direction as shown in Figure 12b and Figure 12c Figure 12a

[0109] As another example, in the operation S1110, the manufacturing system can prepare the plurality of word lines 1210 having a stepped form and divided into the upper word line group 1220 and the lower word line group 1230 by stacking an upper mold structure in which upper word lines 1222 having a smaller horizontal size than the lower word lines 1232 and upper insulating layers 1223 are alternately stacked and an upper vertical string is formed in a vertical direction on a lower mold structure in which the lower word lines 1232 and the lower insulating layers 1233 are alternately stacked and a lower vertical string is formed in a vertical direction as shown in Figure 12d and Figure 12e Figure 12a

[0110] ​​​​Specifically, in operation S1110, the manufacturing system can determine the horizontal dimension of the lower word line group 1230 to include the etch stop distance 1250 to prevent the bottommost word line in the upper word line group 1220 from being etched when the etch operation is performed on the lower word line group 1230 in operation S1130, which will be described later. This will be described in more detail below.

[0111] Furthermore, in operation S1110, the manufacturing system may arrange an etch stop protection layer 1260 between the upper word line group 1220 and the lower word line group 1230 to prevent the uppermost word line in the lower word line group 1230 from being etched when the upper word line group 1220 is etched in operation S1130, which will be described later. This will also be described in more detail below.

[0112] Next, in operation S1120, the manufacturing system forms photoresist 1270, 1280 on at least a portion of the upper surface 1221 of the upper letter group 1220 and at least a portion of the upper surface 1231 of the lower letter group 1230, such as... Figure 12f As shown.

[0113] Next, in operation S1130, the manufacturing system simultaneously performs etching operations on the upper word line group 1220 and the lower word line group 1230 on which photoresist 1270 and 1280 are formed, such as... Figure 12h As shown.

[0114] Here, before operating S1130, the manufacturing system can trim the photoresist 1270 and 1280 to an equal spacing width, so that the stepped shape to be formed by the multiple letter lines 1210 will have this equal spacing width, such as... Figure 12g As shown.

[0115] Operation S1130 can be repeated based on the number of steps stacked on the upper word line 1222 included in the upper word line group 1220 and the number of steps stacked on the lower word line 1232 included in the lower word line group 1230, so that a three-dimensional flash memory including word lines 1210 with a stepped shape can be manufactured.

[0116] Similarly, when repeating operation S1130, the manufacturing system can additionally repeat the operations of trimming photoresist 1270 and 1280, such as... Figures 12h to 12j As shown, this allows word lines 1210 to have a stepped shape.

[0117] As described above, since the horizontal dimension of the lower character line group 1230 is determined to include the etch stop distance 1250, such as Figure 12h As shown, when the etching operation is performed on the lower word line group 1230, the incorrect etching of the lowest word line 1224 in the upper word line group 1220 can be prevented.

[0118] Further, as described above, since the etch stop protection layer 1260 is disposed between the upper word line group 1220 and the lower word line group 1230, as shown in Figure 12h , when the etching operation is performed on the upper word line group 1220, the erroneous etching of the uppermost word line 1234 in the lower word line group 1230 can be prevented.

[0119] Although determining the horizontal size of the lower word line group 1230 to include the etch stop distance 1250 and disposing the etch stop protection layer 1260 between the upper word line group 1220 and the lower word line group 1230 are both described as being performed in operation S1110, the inventive concept is not limited thereto, and any one of them can be performed.

[0120] When only determining the horizontal size of the lower word line group 1230 to include the etch stop distance 1250 is performed in operation S1110, the completed three-dimensional flash memory is as shown in Figure 13a . When only disposing the etch stop protection layer 1260 between the upper word line group 1220 and the lower word line group 1230 is performed in operation S1110, the completed three-dimensional flash memory is as shown in Figure 13b . When both determining the horizontal size of the lower word line group 1230 to include the etch stop distance 1250 and disposing the etch stop protection layer 1260 between the upper word line group 1220 and the lower word line group 1230 are performed in operation S1110, the completed three-dimensional flash memory is as shown in Figure 13c . This will be described in more detail below.

[0121] Next, in operation S1140, the manufacturing system can remove the photoresists 1270, 1280, as shown in Figure 12k , to complete the manufacturing of the three-dimensional flash memory including the word lines 1210 having the stepped shape.

[0122] Figures 13a to 13c A three-dimensional flash memory manufactured using the method of manufacturing a three-dimensional flash memory described with reference to Figure 11 is shown.

[0123] With reference to Figure 13a , the three-dimensional flash memory 1310 according to an embodiment includes a word line having a step and manufactured in operations S1110 to S1130 described above with reference to Figures 11 to 12f . Specifically, since the manufacturing system determines the horizontal size of the lower word line group to include the etch stop distance 1311 in operation S1110, when forming the stepped shape having the equal-pitch width and equal-pitch height using the plurality of word lines 1320, the three-dimensional flash memory 1310 includes a portion 1321 having a width different from other portions of the stepped shape.

[0124] That is, the portion 1321 having a different width from other portions can be formed by the etching stop distance 1311 to prevent unnecessary etching of the lowermost word line 1322 included in the upper word line group among the plurality of word lines 1320 in a process of performing an etching operation on the plurality of word lines 1320.

[0125] Referring to Figure 13b , the three-dimensional flash memory 1330 according to another embodiment includes word lines having a staircase shape and manufactured in the operations S1110 to S1130 described above with reference to Figures 11 to 12f . Specifically, since the manufacturing system arranges the etching stop protection layer 1331 between the upper word line group and the lower word line group in operation S1110, when a staircase shape having an equal-pitch width and an equal-pitch height is formed using the plurality of word lines 1340, the three-dimensional flash memory 1310 includes a portion 1341 having a different height from other portions of the staircase shape.

[0126] That is, the portion 1341 having a different height from other portions can be formed by the etching stop protection layer 1331 to prevent unnecessary etching of the uppermost word line 1342 included in the lower word line group among the plurality of word lines 1340 in a process of performing an etching operation on the plurality of word lines 1340.

[0127] Referring to Figure 13c , the three-dimensional flash memory 1350 according to an embodiment includes word lines having a staircase shape and manufactured in the operations S1110 to S1130 described above with reference to Figures 11 to 12f . Specifically, since the manufacturing system arranges the etching stop protection layer 1352 between the upper word line group and the lower word line group while determining the horizontal size of the lower word line group to include the etching stop distance 1351 in operation S1110, when a staircase shape having an equal-pitch width and an equal-pitch height is formed using the plurality of word lines 1360, the three-dimensional flash memory 1350 includes a portion 1361 having a different width from other portions of the staircase shape and a portion 1362 having a different height from other portions of the staircase shape.

[0128] The portion 1361 having a different width can be formed by the etching stop distance 1351 to prevent unnecessary etching of the lowermost word line 1363 included in the upper word line group among the plurality of word lines 1360 in a process of performing an etching operation on the plurality of word lines 1360, and the portion 1362 having a different height can be formed by the etching stop protection layer 1352 to prevent unnecessary etching of the uppermost word line 1364 included in the lower word line group among the plurality of word lines 1360 in a process of performing an etching operation on the plurality of word lines 1360.

[0129] As described above, the method of manufacturing a three-dimensional flash memory according to the present embodiment, when manufacturing a three-dimensional flash memory including a total of six steps of word lines, performs only two etching operations (five etching operations are performed in the method of manufacturing a three-dimensional flash memory according to the related art), thus the number of repetitions of etching operations can be significantly reduced, thus simplifying the manufacturing process.

[0130] While the inventive concept has been particularly shown and described with reference to examples thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims. For example, even when the above-described techniques are performed in a different order from the above-described method, and / or components such as the above-described systems, structures, devices, and circuits are combined or composed in a form different from the above-described method or are replaced or substituted by other components or equivalents thereof, appropriate results can be obtained.

[0131] Therefore, other implementations, other embodiments, and claims and equivalents also fall within the scope of the claims described below.

Claims

1.A three-dimensional flash memory implementing integration, the three-dimensional flash memory comprising: at least one memory cell string extending vertically and including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer; and a plurality of word lines orthogonally connected to the at least one memory cell string and stacked, and extending in a horizontal direction, wherein the plurality of word lines extend with different lengths from each other to form a stair shape including a stepped portion and a flat portion, wherein the at least one memory cell string including the at least one channel layer and the at least one charge storage layer and capable of performing storage is formed in both the flat portion and the stepped portion, wherein a length of the memory cell string formed in the flat portion is greater than a length of the memory cell string formed in the stepped portion, and a length of the memory cell string formed in a higher step of the stepped portion is greater than a length of the memory cell string formed in a lower step of the stepped portion. 2.The three-dimensional flash memory of claim 1, wherein a contact of each of the plurality of word lines is formed only in a minimized partial area of each of a plurality of steps of the stepped portion. 3.The three-dimensional flash memory of claim 2, wherein the minimized partial area includes an area corresponding to a cross-sectional area of the contact of each of the plurality of word lines. 4.The three-dimensional flash memory of claim 1, wherein for each step of the stepped portion, the at least one memory cell string formed in the stepped portion and a contact of each word line formed in the stepped portion are located in a same column. 5.A three-dimensional flash memory implementing integration, the three-dimensional flash memory comprising: at least one memory cell string extending in a direction and including at least one channel layer and at least one charge storage layer surrounding the at least one channel layer; and a plurality of word lines orthogonally connected to the at least one memory cell string, wherein a contact of each of the plurality of word lines is formed only in a minimized partial area of an entire area of each of the plurality of word lines corresponding to a cross-sectional area of the contact of each of the plurality of word lines, and wherein the plurality of word lines have a stair shape only in the minimized partial areas, and the minimized partial areas are arranged in a same row such that the plurality of word lines provide a space in an area adjacent to the minimized partial areas at which at least one other memory cell string arranged in a first array is formed, the first array being different from a second array in which the at least one memory cell string is arranged. 6.The three-dimensional flash memory of claim 5, wherein the plurality of word lines are shared by the at least one memory cell string and the at least one other memory cell string due to the at least one other memory cell string being formed in the space. 7.A method of manufacturing a three-dimensional flash memory, the method comprising: ​ ​ forming a plurality of word lines, a plurality of insulating layers, and an etch stop protection layer stacked in a vertical direction, wherein an upper word line group includes first word lines among the plurality of word lines and first insulating layers among the plurality of insulating layers, the first word lines and the first insulating layers are alternately stacked, a lower word line group includes second word lines among the plurality of word lines and second insulating layers among the plurality of insulating layers, the second word lines and the second insulating layers are alternately stacked, the etch stop protection layer is formed between the upper word line group and the lower word line group and is different from the plurality of insulating layers, wherein the upper word line group and the lower word line group have different horizontal sizes and are sequentially stacked in a first stair shape such that at least a portion of an upper surface of each of the upper word line group and the lower word line group is exposed; forming a photoresist on at least a portion of the upper surface of the upper word line group and at least a portion of the upper surface of the lower word line group; and performing an etching operation on each of the upper word line group and the lower word line group, for which the etch stop protection layer is provided therebetween and on which the photoresist is formed, simultaneously to form a second stair shape such that at least a portion of an upper surface of each of the first word lines and the second word lines is exposed, wherein after the second stair shape is formed, a maximum width of the etch stop protection layer in a horizontal direction is the same as a maximum width of a lowermost word line among the upper word line group in the horizontal direction. 8.The method of claim 7, wherein the lower word line group has a larger horizontal size than the upper word line group. 9.The method of claim 7, wherein forming the plurality of word lines and the etch stop protection layer includes determining a horizontal size of the lower word line group to include an etch stop distance to prevent etching a lowermost word line among the upper word line group when the etching operation is performed on the lower word line group. 10.The method of claim 7, wherein the etch stop protection layer between the upper word line group and the lower word line group prevents etching an uppermost word line among the lower word line group when the etching operation is performed on the upper word line group. 11.The method of claim 7, wherein performing the etching operation on each of the upper word line group and the lower word line group simultaneously is repeatedly performed based on a number of steps by which the first word lines included in the upper word line group are stacked and a number of steps by which the second word lines included in the lower word line group are stacked.

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