Semiconductor device and semiconductor module

Abstract

The present invention relates to a semiconductor device, which comprises: a semiconductor substrate, which has an active area through which a main current flows, and an end area around the active area; a polyimide film, which is arranged on the active area and on the end area; and a passivation film, which is arranged as a lower film of the polyimide film, the end area includes a voltage-resistant holding area and an outermost peripheral area arranged in sequence from the active area side, the polyimide film is arranged to exclude the cutting residue of the outermost peripheral area, and the passivation film is arranged as a lower film at least in the area where the polyimide film is arranged.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and in particular to a semiconductor device used in the field of power electronics such as an inverter device. Background Art

[0002] Semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), and diodes have an active region through which the main current flows and a terminal region for maintaining a withstand voltage. In the terminal region, an insulating film and a passivation film are provided on a semiconductor substrate for the purpose of maintaining the withstand voltage and protecting the semiconductor device, and an organic coating film, i.e., polyimide, is provided on the insulating film and the passivation film for the purpose of protecting the electrode and improving the insulation.

[0003] For example, Patent Document 1 Figure 1 and Patent Document 2 Figure 4 Such a structure is disclosed. Figure 1 In the peripheral voltage-resistant region, a nitride film as an insulating film and a first passivation film is formed on a semiconductor substrate, and a polyimide film is formed on the nitride film as a second passivation film.

[0004] Generally, polyimide has photosensitivity, but due to fluctuations in photosensitivity, it is difficult to form the end face of the polyimide film to be flush with the end face of the metal layer in the manufacturing process.

[0005] Although not explicitly stated in Patent Document 1, Figure 4 In the voltage-resistant end area, at the edge of the semiconductor device, the polyimide film extends over the semiconductor substrate in a manner covering the insulating film, so that the polyimide film and the semiconductor substrate are in contact. Currently, this is the structure of the edge of a common semiconductor device.

[0006] Patent Document 1: Japanese Patent No. 5720647

[0007] Patent Document 2: Japanese Patent No. 5943819 Summary of the invention

[0008] Currently, since the polyimide film is in contact with the semiconductor substrate at the end edge of the semiconductor device, when the semiconductor device is encapsulated by a resin encapsulation material such as epoxy resin, if thermal stress is applied, the stress caused by the expansion and contraction of the resin encapsulation material and polyimide will concentrate on the semiconductor substrate at the end of the polyimide film, and the semiconductor substrate may crack.

[0009] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device which reduces stress in a semiconductor substrate at an end portion of a polyimide film and improves reliability.

[0010] The semiconductor device involved in the present invention comprises: a semiconductor substrate, which has an active area through which a main current flows and an end area around the active area; a polyimide film, which is arranged on the active area and on the end area; and a passivation film, which is arranged as a lower layer film of the polyimide film, the end area includes a voltage-resistant holding area and an outermost peripheral area arranged in sequence from the active area side, the polyimide film is arranged to exclude the cutting residue of the outermost peripheral area, and the passivation film is arranged as a lower layer film at least in the area where the polyimide film is arranged.

[0011] Effects of the Invention

[0012] According to the semiconductor device according to the present invention, when thermal stress is applied to the semiconductor device, the passivation film functions as a stress buffer layer, and can reduce the stress applied to the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a cross-sectional view showing a partial structure of an end region and an active region of the semiconductor module according to the first embodiment of the present invention.

[0014] Figure 2 This is a partial cross-sectional view showing the outermost peripheral region of a chip of the semiconductor device according to the first embodiment of the present invention.

[0015] Figure 3 This is a partial cross-sectional view showing the outermost peripheral region of a chip of a semiconductor device according to a second embodiment of the present invention.

[0016] Figure 4 This is a partial cross-sectional view showing the outermost peripheral region of a chip of a semiconductor device according to a third embodiment of the present invention.

[0017] Figure 5 This is a partial cross-sectional view showing the outermost peripheral region of a chip of a semiconductor device according to a fourth embodiment of the present invention.

[0018] Figure 6 This is a partial cross-sectional view showing the outermost peripheral region of a chip of a semiconductor device according to a fifth embodiment of the present invention.

[0019] Figure 7 This is a partial cross-sectional view showing the outermost peripheral region of a chip of a semiconductor device according to a sixth embodiment of the present invention.

[0020] Figure 8This is a partial cross-sectional view showing the outermost peripheral region of a chip of a semiconductor device according to a seventh embodiment of the present invention.

[0021] Fig. 9 This is a partial cross-sectional view showing the outermost peripheral region of a chip of a semiconductor device according to an eighth embodiment of the present invention.

[0022] Fig.10 This is a partial cross-sectional view showing the outermost peripheral region of a chip of a semiconductor module according to a ninth embodiment of the present invention.

[0023] Fig.11 This is a partial cross-sectional view showing the outermost peripheral region of a chip of a semiconductor module according to a tenth embodiment of the present invention.

[0024] Fig.12 This is a partial cross-sectional view showing the outermost peripheral region of a chip of a semiconductor module according to Embodiment 11 of the present invention.

[0025] Fig.13 This is a partial cross-sectional view showing the outermost peripheral region of a chip of a semiconductor device according to Embodiment 12 of the present invention. DETAILED DESCRIPTION

[0026] <Foreword>

[0027] In the following description, the "active region" refers to the region where the main current flows when the semiconductor device is turned on, and the "terminal region" refers to the region around the active region. In addition, in the following, "outside" is the direction toward the periphery of the semiconductor device, and "inside" is the direction opposite to "outside". In addition, in the following description, regarding the conductivity type of impurities, N type is usually defined as the "first conductivity type", and P type, which is the opposite conductivity type to N type, is defined as the "second conductivity type", but the opposite definition may also be used.

[0028] In addition, the drawings are schematically shown, and the size and position of the images shown in different drawings may not be accurately recorded, and can be appropriately changed. In addition, in the following description, the same structural elements are marked with the same reference numerals and illustrated, and their names and functions are also the same. Therefore, their detailed description may be omitted sometimes. In addition, in this specification, in the case of "above" and "covering" such as, it is not excluded that there are inclusions between the structural elements. For example, in the case of "B set on A" or "A covers B", it may mean that other structural elements C are set between A and B, or other structural elements C are not set. In addition, in the following description, sometimes "upper", "lower", "side", "bottom", "table" or "back" are used to indicate specific positions and directions. These terms are used only for convenience to facilitate the understanding of the contents of the implementation method, and have nothing to do with the direction during actual implementation.

[0029] <Implementation Method 1>

[0030] Figure 1 is a cross-sectional view showing a part of the structure of the terminal region and the active region of the diode module 200 according to the first embodiment of the present invention. Figure 2 FIG. 2 is a partial cross-sectional view showing the outermost peripheral region of the diode chip 100 sealed in the diode module 200 by resin. Figure 2 In the figure, only characteristic structures are shown for convenience.

[0031] like Figure 1 As shown, the semiconductor substrate 1 of the diode module 200 is roughly divided into two regions, an active region and an end region, and the end region is divided into a withstand voltage holding region and a chip outermost peripheral region in order from the active region side. In addition, the chip outermost peripheral region includes a dicing residue, which is a dicing residue of a dicing cut portion that is contacted by a dicing blade when the semiconductor substrate 1 is divided to form a semiconductor chip.

[0032] Figure 1 The semiconductor substrate 1 shown is, for example, a silicon (Si) substrate, and has layers including a relatively high concentration (N + ) of N-type (first conductivity type) impurities and a buffer layer 13 containing relatively low concentration (N - )'s drift layer 12 of N-type impurities.

[0033] Moreover, the upper portion of the drift layer 12 has: an anode 9, which includes P-type (second conductivity type) impurities arranged in the active region; a plurality of guard rings 10, which are concentrically arranged in the voltage-resistant maintaining region so as to surround the active region and include P-type impurities; and a field blocking layer 11, which is arranged further outside the outermost guard ring 10 and includes N-type impurities.

[0034] In addition, a silicon oxide film 2 is provided on the front surface side of the semiconductor substrate 1 in a manner covering from the edge of the anode 9 to the inner edge of the field blocking layer 11, and an interlayer insulating film 3 is provided on the silicon oxide film 2. A metal anode electrode 14 is provided on the anode 9, and a metal field blocking electrode 5 is provided on the inner edge of the field blocking layer 11. A portion of the anode electrode 14 and the field blocking electrode 5 climbs onto the interlayer insulating film 3, and a passivation film 4 is provided in a manner covering the anode electrode 14, the field blocking electrode 5 and the interlayer insulating film 3. The edge of the passivation film 4 extends to the outermost peripheral region of the chip, and its end face is flush with the end face of the semiconductor substrate 1.

[0035] Furthermore, a polyimide film 6 is provided on the active region and the terminal region excluding the cutout residual portion, and the entire semiconductor substrate 1 including the polyimide film 6 is encapsulated by a resin encapsulation material 7 such as epoxy resin.

[0036] Here, the passivation film 4 uses a silicon oxide film (TEOS oxide film) formed using TEOS (tetraethoxysilane) whose Young's modulus and linear expansion coefficient are closer to polyimide and epoxy resin than silicon, that is, the semiconductor substrate 1. That is, the physical property values ​​of each material are as follows.

[0037] Silicon: Young's modulus 185 [GPa], linear expansion coefficient 2.3 [ppm / °C]

[0038] TEOS acidified film: Young's modulus 80.1 [Gpa], linear expansion coefficient 9 [ppm / ℃]

[0039] Polyimide: Young's modulus 5 [GPa], linear expansion coefficient 54 [ppm / °C]

[0040] Epoxy resin: Young's modulus 16 [GPa], linear expansion coefficient 18 [ppm / °C]

[0041] In this way, a passivation film 4 is formed as a lower film of the polyimide film 6, and the edge of the passivation film 4 extends to the outermost peripheral area of ​​the chip. Therefore, even when thermal stress is applied to the diode chip 100, since the material properties of the passivation film 4 are closer to those of the polyimide film 6 and the resin packaging material 7 than the semiconductor substrate 1, the deformation of the semiconductor substrate 1 will also be reduced. Moreover, the passivation film 4 itself acts as a buffer film when it is subjected to stress. Therefore, the stress in the semiconductor substrate 1 at the edge of the polyimide film 6 is reduced, which can suppress the occurrence of cracks.

[0042] Furthermore, when a TEOS oxide film is used as the passivation film 4 , since the adhesion between the TEOS oxide film and the polyimide film is low, the stress in the semiconductor substrate 1 can be further reduced by utilizing this property.

[0043] That is, the interface adhesion between the TEOS oxide film and polyimide is weaker than the interface adhesion between polyimide and silicon and the interface adhesion between epoxy resin and polyimide, and the polyimide film 6 and the passivation film 4 become easily peeled off. When thermal stress is applied to the diode chip 100, the peeling at the interface between the polyimide film 6 and the passivation film 4 is promoted, so that the stress is dispersed on the surface of the semiconductor substrate 1, thereby reducing the stress inside the semiconductor substrate 1.

[0044] In addition, when the polyimide film 6 and the passivation film 4 are peeled off, the electrode protection function and the insulation improvement function of the polyimide film 6 may also be reduced. However, since the function of reducing the stress in the semiconductor substrate 1 is improved, the trade-off relationship between these functions is taken into consideration in the design of the semiconductor device to achieve optimization of the specifications of the semiconductor device.

[0045] In addition, in this embodiment 1, a diode is used as an example, but in terms of the basic structure of the terminal region, IGBT and MOSFET are also the same as diodes, so the structure of the terminal region of this embodiment 1 can also be applied to IGBT and MOSFET, and can also be applied to all semiconductor devices having the same terminal region.

[0046] <Implementation Method 2>

[0047] Figure 3 is a partial cross-sectional view showing the chip outermost peripheral region of the diode chip 100A according to the second embodiment of the present invention, and Figure 2 Likewise, for the sake of convenience, only characteristic structures are shown.

[0048] like Figure 3 As shown, the diode chip 100A is provided with an interlayer insulating film 3 as a lower film of the passivation film 4 in the outermost peripheral region of the chip.

[0049] The interlayer insulating film 3 is formed of, for example, a silicon oxide film, a BPSG (boro-phospho silicate glass) film, a PSG (phospho-silicate glass) film, etc. formed by a CVD (chemical vapor deposition) method. After a silicon oxide film 2 (thermal oxide film) is formed in a withstand voltage holding region of a semiconductor substrate 1 by, for example, a thermal oxidation method (wet oxidation), when the interlayer insulating film 3 is formed on the silicon oxide film 2, the interlayer insulating film 3 is also formed simultaneously in the outermost peripheral region of the chip.

[0050] In this way, by providing the interlayer insulating film 3 as the lower film of the passivation film 4, the stress buffering function for the semiconductor substrate 1 can be strengthened, and the stress in the semiconductor substrate 1 can be further reduced. That is, in the case of the CVD method, it is not limited to the silicon oxide film, and various films can be formed. By selecting a film with a physical property value closer to that of the polyimide film 6 and the passivation film 4, the stress buffering function for the semiconductor substrate 1 can be strengthened.

[0051] Furthermore, by providing the interlayer insulating film 3 as a lower film of the passivation film 4 , the height difference between the passivation film 4 covering the field stop electrode 5 and the base can be reduced, thereby suppressing cracks in the passivation film 4 .

[0052] That is, if thermal stress is applied in a state where the diode chip 100A is packaged with epoxy resin or the like, the field blocking electrode 5 is plastically deformed, and stress is applied to the passivation film 4 alone, and cracks may be generated at the corner CP where stress is most likely to be concentrated. By suppressing the deformation of the field blocking electrode 5 to a minimum, the generation of cracks can be suppressed. By providing the interlayer insulating film 3 to reduce the height difference between the passivation film 4 and the substrate, the thickness of the field blocking electrode 5 is relatively thinned, and the deformation amount of the field blocking electrode 5 is reduced. Therefore, the generation of cracks can be suppressed compared with the diode chip 100 of the first embodiment.

[0053] <Implementation Method 3>

[0054] Figure 4 is a partial cross-sectional view showing the chip outermost peripheral region of the diode chip 100B according to the third embodiment of the present invention, and Figure 2 Likewise, for the sake of convenience, only characteristic structures are shown.

[0055] like Figure 4 As shown, in the outermost peripheral region of the chip, the diode chip 100B includes an interlayer insulating film 3 in contact with the passivation film 4 as a lower film of the passivation film 4 , and a silicon oxide film 2 provided as a lower film of the interlayer insulating film 3 .

[0056] The silicon oxide film 2 is formed by thermal oxidation (wet oxidation). After the silicon oxide film 2 is formed by thermal oxidation on the voltage-resistant holding area of ​​the semiconductor substrate 1 and the outermost peripheral area of ​​the chip, any one of a silicon oxide film, a BPSG film and a PSG film is formed on the silicon oxide film 2 by, for example, a CVD (chemical vapor deposition) method as an interlayer insulating film 3.

[0057] In this way, by providing the interlayer insulating film 3 and the silicon oxide film 2 as the lower layer film of the passivation film 4 , the stress buffering function for the semiconductor substrate 1 can be enhanced, and the stress in the semiconductor substrate 1 can be further reduced.

[0058] Furthermore, by providing the interlayer insulating film 3 and the silicon oxide film 2 as the lower film of the passivation film 4 , the height difference between the passivation film 4 covering the field stop electrode 5 and the base can be reduced, thereby suppressing cracks in the passivation film 4 .

[0059] <Implementation Method 4>

[0060] Figure 5 is a partial cross-sectional view showing the chip outermost peripheral region of a diode chip 100C according to a fourth embodiment of the present invention, and Figure 2 Likewise, for the sake of convenience, only characteristic structures are shown.

[0061] like Figure 5 As shown, in the outermost peripheral area of ​​the chip, the diode chip 100C has an interlayer insulating film 3 in contact with the passivation film 4 as a lower film of the passivation film 4, a polysilicon film 31 set as a lower film of the interlayer insulating film 3, and a silicon oxide film 2 set as a lower film of the polysilicon film 31.

[0062] The polysilicon film 31 is formed by, for example, a CVD method. After a silicon oxide film 2 is formed by a thermal oxidation method in a withstand voltage holding region of the semiconductor substrate 1 and in an outermost peripheral region of the chip, the polysilicon film 31 is formed by a CVD method on the silicon oxide film 2 in the outermost peripheral region of the chip. Since polysilicon does not function as a conductor without being doped with impurities and becomes an insulator, the polysilicon film 31 is formed without being doped with impurities in the fourth embodiment.

[0063] After the polysilicon film 31 is formed, a silicon oxide film, a BPSG film, or a PSG film is formed as an interlayer insulating film 3 on the silicon oxide film 2 in the withstand voltage holding region of the semiconductor substrate 1 and on the polysilicon film 31 in the outermost region of the chip.

[0064] In this way, by providing the interlayer insulating film 3 , the polysilicon film 31 , and the silicon oxide film 2 as the lower film of the passivation film 4 , the stress buffering function for the semiconductor substrate 1 can be enhanced, and the stress in the semiconductor substrate 1 can be further reduced.

[0065] Furthermore, by providing the interlayer insulating film 3 , the polysilicon film 31 , and the silicon oxide film 2 as the lower film of the passivation film 4 , the height difference between the passivation film 4 covering the field stop electrode 5 and the base can be reduced, thereby suppressing cracks in the passivation film 4 .

[0066] In addition, the polysilicon film is a film used for forming the gate electrode of IGBT, MOSFET, etc. When the structure of the terminal region of the fourth embodiment is applied to IGBT and MOSFET, the formation of the polysilicon film 31 can be taken into account in the process of forming the gate electrode, and there is no need to provide an additional process for forming the polysilicon film 31. In addition, in this case, the polysilicon film 31 is doped with impurities to become a conductor like the gate electrode, but since the polysilicon film 31 is provided in the field blocking electrode formation region where the depletion layer does not extend, it does not affect the performance of the semiconductor device due to being a conductor.

[0067] <Implementation method 5>

[0068] Figure 6 is a partial cross-sectional view showing the chip outermost peripheral region of a diode chip 100D according to a fifth embodiment of the present invention, and Figure 2 Likewise, for the sake of convenience, only characteristic structures are shown.

[0069] like Figure 6 As shown, in the outermost area of ​​the chip, as the lower layer of the passivation film 4, the diode chip 100D has an interlayer insulating film 3 in contact with the passivation film 4, a silicon oxide film 2 arranged under the interlayer insulating film 3, and a dummy electrode 51 arranged concentrically with the field blocking electrode 5 on the interlayer insulating film 3, and the passivation film 4 also covers the dummy electrode 51.

[0070] The dummy electrode 51 is made of the same material as the field stop electrode 5 , for example, AlSi, and is formed by the same manufacturing method, for example, vapor deposition or sputtering.

[0071] In this way, by providing the dummy electrode 51 below the passivation film 4 in the outermost peripheral region of the chip, the stress buffering function for the semiconductor substrate 1 can be enhanced, and the stress in the semiconductor substrate 1 can be further reduced.

[0072] In addition, AlSi is an electrode material used in the manufacture of semiconductor devices. Figure 1 The anode electrode 14 shown in the figure can be formed in conjunction with the dummy electrode 51 in the process of forming the anode electrode 14 , and there is no need to provide an additional process for forming the anode electrode 14 . This is also the same as the field stop electrode 5 .

[0073] <Implementation Method 6>

[0074] Figure 7 is a partial cross-sectional view showing the outermost peripheral region of a diode chip 100E according to the sixth embodiment of the present invention, and Figure 2 Likewise, for the sake of convenience, only characteristic structures are shown.

[0075] like Figure 7 As shown, in the outermost area of ​​the chip, as the lower layer of the passivation film 4, the diode chip 100E has an interlayer insulating film 3 in contact with the passivation film 4, a silicon oxide film 2 arranged under the interlayer insulating film 3, and a plurality of dummy electrodes 51 arranged concentrically with the field blocking electrode 5 on the interlayer insulating film 3, and the passivation film 4 also covers the plurality of dummy electrodes 51.

[0076] In this way, by providing a plurality of dummy electrodes 51 under the passivation film 4 in the outermost peripheral region of the chip, the stress buffering function for the semiconductor substrate 1 can be enhanced, and the stress in the semiconductor substrate 1 can be further reduced.

[0077] Furthermore, by providing a plurality of dummy electrodes 51 , the concavities and convexities of the passivation film 4 increase, and the polyimide film 6 fits the concavities and convexities, and the polyimide film 6 is difficult to peel off due to the anchor effect, thereby improving the adhesion of the polyimide film 6 .

[0078] The anchor effect is an effect in which the effective area of ​​the film bonded to the surface increases due to the unevenness of the surface, thereby improving the bonding force.

[0079] <Implementation Method 7>

[0080] Figure 8 is a partial cross-sectional view showing the chip outermost peripheral region of a diode chip 100F according to a seventh embodiment of the present invention, and Figure 2 Likewise, for the sake of convenience, only characteristic structures are shown.

[0081] like Figure 8 As shown, in the diode chip 100F, the passivation film 4 , the interlayer insulating film 3 , and the silicon oxide film 2 are not provided at the dicing residue portion in the outermost peripheral region of the chip, and the surface of the semiconductor substrate 1 is exposed.

[0082] In this way, the surface of the semiconductor substrate 1 is exposed at the cut residue portion in the outermost peripheral area of ​​the diode chip 100F, but this portion is a cut portion in the wafer state and is a cutting margin portion during cutting, which means that the surface of the semiconductor substrate 1 is exposed at the cut portion.

[0083] Since the surface of the semiconductor substrate 1 is exposed at the dicing section, the cutting edge (blade) for dicing directly cuts the semiconductor substrate 1 during dicing, which can reduce chipping of the cut surface and extend the life of the cutting edge.

[0084] <Implementation Method 8>

[0085] Fig. 9 is a partial cross-sectional view showing the chip outermost peripheral region of the diode chip 100G according to the eighth embodiment of the present invention, and Figure 2 Likewise, for the sake of convenience, only characteristic structures are shown.

[0086] like Fig. 9 As shown, in the outermost area of ​​the chip, as the lower layer of the passivation film 4, the diode chip 100G has an interlayer insulating film 3 in contact with the passivation film 4, a silicon oxide film 2 arranged under the interlayer insulating film 3, and the shape of the end edge of the polyimide film 6 is a gently inclined surface convex downward.

[0087] Thus, by setting the edge of the polyimide film 6 in the outermost peripheral area of ​​the chip to a gently inclined surface, the chip can be aligned with the outermost peripheral area of ​​the polyimide film 6. Figure 4 Compared with the polyimide film 6 having a steeply rising edge portion like the diode chip 100B shown, the stress applied to the edge portion of the semiconductor substrate 1 is reduced.

[0088] In addition, Fig. 9 In the figure, the shape of the edge of the polyimide film 6 is a downwardly convex inclined surface, but it is not limited to this shape and may be a simple inclined surface. As long as the film thickness gradually decreases toward the outside, it may be any shape, including a step shape.

[0089] <Implementation Method 9>

[0090] Fig.10 is a partial cross-sectional view showing the outermost peripheral region of a chip of a diode module 200A according to a ninth embodiment of the present invention, and Figure 2 Likewise, for the sake of convenience, only characteristic structures are shown.

[0091] Fig.10 The diode module 200A shown is for use with Figure 8 The diode chip 100F of the seventh embodiment described above is a semiconductor chip that is resin-encapsulated. In the diode module 200A, a polyimide film 6 is provided on the active region and the terminal region excluding the cut-off residue, and the entire semiconductor substrate 1 including the polyimide film 6 is encapsulated by a resin encapsulation material 7 such as epoxy resin.

[0092] The diode chip 100F has a passivation film 4 formed as a lower film of the polyimide film 6 in the outermost area of ​​the chip. Therefore, even when thermal stress is applied to the diode chip 100F, the deformation of the semiconductor substrate 1 is reduced because the material properties of the passivation film 4 are closer to those of the polyimide film 6 and the resin packaging material 7 than the semiconductor substrate 1. In addition, the passivation film 4 itself acts as a buffer film when subjected to stress. Therefore, the stress in the semiconductor substrate 1 at the end edge of the polyimide film 6 is reduced, which can suppress the occurrence of cracks.

[0093] Therefore, even when thermal stress is applied to the diode module 200A in which the diode chip 100F is encapsulated by the resin encapsulation material 7 , stress applied to the diode chip 100F by the resin encapsulation material 7 can be reduced, and cracks in the polyimide film 6 can be suppressed, thereby improving reliability.

[0094] In addition, although the diode module 200A is described above as including the diode chip 100F, it is not limited to the diode chip 100F and may also include Figure 2 to Figure 7 and Fig. 9 Any of the diode chips 100A to 100E and 100G shown.

[0095] <Implementation Method 10>

[0096] Fig.11 is a partial cross-sectional view showing the outermost peripheral region of a chip of a diode module 200B according to a tenth embodiment of the present invention, and Figure 2 Likewise, for the sake of convenience, only characteristic structures are shown.

[0097] Fig.11 The diode module 200B shown is for use with Figure 8 The diode chip 100F of the seventh embodiment described above is a resin-sealed semiconductor chip. In the diode module 200B, the upper passivation film 41 is provided so as to cover the surface of the polyimide film 6 of the diode chip 100F and the surface of the chip outermost peripheral region.

[0098] The upper passivation film 41 uses a TEOS oxide film. The interface adhesion between the TEOS oxide film and the epoxy resin is weaker than the interface adhesion between the epoxy resin and the polyimide. When the diode chip 100F is encapsulated by the resin encapsulation material 7, the resin encapsulation material 7 and the upper passivation film 41 are in a state of being easily peeled off. When thermal stress is applied to the diode module 200B, peeling is promoted at the interface between the resin encapsulation material 7 and the upper passivation film 41, which can further reduce the stress on the diode chip 100F from the resin encapsulation material 7, and can suppress the generation of cracks in the polyimide film 6, thereby improving reliability.

[0099] In addition, although the diode module 200B is described above as including the diode chip 100F, it is not limited to the diode chip 100F and may also include Figure 2 to Figure 7 and Fig. 9 In any of the diode chips 100A to 100E and 100G shown, the same effects as described above can be obtained by providing the upper passivation film 41 so as to cover the surface of the polyimide film 6 and the surface of the outermost peripheral region of the chip.

[0100] <Implementation Method 11>

[0101] Fig.12 is a partial cross-sectional view showing the outermost peripheral region of a chip of a diode module 200C according to Embodiment 11 of the present invention, and Figure 2 Likewise, for the sake of convenience, only characteristic structures are shown.

[0102] Fig.12 The diode module 200C shown is for use with Figure 8 The diode chip 100F of the seventh embodiment described above is a resin-sealed semiconductor chip. In the diode module 200C, the stress buffering film 15 is provided so as to cover the surface of the polyimide film 6 of the diode chip 100F and the surface of the chip outermost peripheral region.

[0103] The stress buffer film 15 uses silicone gel or silicone rubber which is generally used as an insulating packaging material for semiconductor products.

[0104] By coating silicone gel or silicone rubber on the surface of the polyimide film 6 of the diode chip 100F and the surface of the outermost area of ​​the chip to form a stress buffer film 15, the stress exerted on the diode chip 100F from the resin packaging material 7 can be further reduced, the generation of cracks in the polyimide film 6 can be suppressed, and reliability can be improved.

[0105] <Implementation Method 12>

[0106] Fig.13 is a partial cross-sectional view showing the outermost peripheral region of a diode chip 100H according to Embodiment 12 of the present invention, and Figure 2 Likewise, for the sake of convenience, only characteristic structures are shown.

[0107] like Fig.13 As shown, the diode chip 100H is provided with a dummy region between the withstand voltage holding region and the cut residual portion at the outermost peripheral region of the chip.

[0108] The dummy region has a dummy electrode 52 disposed concentrically with the field blocking electrode 5 disposed in the withstand voltage holding region, and the passivation film 4 also covers the dummy electrode 52. The polyimide film 6 is disposed on the active region and the terminal region except for the cut residue, and the passivation film 4, the interlayer insulating film 3 and the silicon oxide film 2 are the lower films of the polyimide film 6.

[0109] The dummy electrode 52 is provided on the interlayer insulating film 3 , but also has a portion penetrating the interlayer insulating film 3 and the silicon oxide film 2 to reach the field stop layer 11 provided on the upper layer portion of the semiconductor substrate 1 .

[0110] The dummy electrode 52 is made of the same material as the field stop electrode 5 , for example, AlSi, and is formed by the same manufacturing method, for example, vapor deposition or sputtering.

[0111] In addition, AlSi is an electrode material used in the manufacture of semiconductor devices. Figure 1 The anode electrode 14 shown in the figure can be formed in conjunction with the dummy electrode 52 in the process of forming the anode electrode 14 , and there is no need to provide an additional process for forming the anode electrode 14 . This is also the same as the field stop electrode 5 .

[0112] As described above, by providing a dummy area having a dummy electrode 52 in the outermost area of ​​the chip, when thermal stress is applied to the diode chip 100H and cracks are generated in the passivation film 4, when the cracks develop into the withstand voltage maintaining area, the electrical characteristics of the diode chip 100H including the withstand voltage may be reduced. However, the dummy electrode 52 provided in the dummy area is a metal layer, which is a ductile material. Therefore, even when cracks are generated in the passivation film 4, large plastic deformation will not occur before causing damage, and the cracks will not propagate at a high speed. The development of the cracks to the withstand voltage maintaining area can be delayed, and the development of the cracks can be prevented in the dummy area. Therefore, it can be expected that the reliability of the diode chip 100H will be improved and the life of the diode chip 100H will be extended.

[0113] <Application to Silicon Carbide Semiconductor Devices>

[0114] In the above-described embodiments 1 to 12, the semiconductor substrate 1 is set as a Si substrate and the diode chips 100 to 100H are set as Si semiconductor devices. However, by setting the semiconductor substrate 1 to a wide-bandgap semiconductor substrate such as a silicon carbide semiconductor substrate, the size of the terminal region can be reduced, thereby miniaturizing the semiconductor device.

[0115] In addition, semiconductor devices using wide bandgap materials such as silicon carbide (SiC) can be used for high temperature and high withstand voltage applications.

[0116] Although the present invention has been described in detail, the above invention is in all aspects illustrative and the present invention is not limited thereto. It should be understood that numerous modifications not shown in the examples are conceivable without departing from the scope of the present invention.

[0117] Furthermore, the present invention can freely combine the various embodiments within the scope of the invention, and can appropriately modify or omit the various embodiments.

Claims

1. A semiconductor device comprising: A semiconductor substrate having an active region through which a main current flows and a terminal region around the active region; A polyimide film disposed on the active area and on the terminal area; as well as a passivation film provided as a lower film of the polyimide film, The terminal region includes a withstand voltage maintaining region and an outermost peripheral region which are sequentially arranged from the active region side. The polyimide film is provided so as to exclude the cut residue in the outermost peripheral area. The passivation film is provided as a lower film at least in a region where the polyimide film is provided, and is provided so as to extend toward the outer periphery of the semiconductor substrate beyond the polyimide film to the outermost peripheral region of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein An interlayer insulating film is provided, and the interlayer insulating film is provided as a lower layer film of the passivation film in the outermost peripheral region.

3. The semiconductor device according to claim 2, wherein: A thermal oxide film is provided in the outermost peripheral region as a lower layer film of the interlayer insulating film.

4. The semiconductor device according to claim 3, wherein: The invention further includes a polysilicon film provided between the interlayer insulating film and the thermal oxide film in the outermost peripheral region.

5. The semiconductor device according to claim 2, wherein: The withstand voltage holding region has a field blocking electrode provided concentrically with the active region on the interlayer insulating film. The outermost peripheral region has at least one dummy electrode provided concentrically with the field stop electrode on the interlayer insulating film.

6. The semiconductor device according to claim 5, wherein: The at least one dummy electrode includes a plurality of dummy electrodes arranged in a concentric shape.

7. The semiconductor device according to claim 2, wherein: The withstand voltage holding region has a field blocking electrode provided concentrically with the active region on the interlayer insulating film. The end region further includes a dummy region disposed between the pressure-resistant holding region and the cutting residual portion, The dummy region includes a dummy electrode provided concentrically with the field stop electrode on the interlayer insulating film.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The edge portion of the polyimide film has a shape in which the film thickness gradually decreases toward the outside.

9. The semiconductor device according to any one of claims 1 to 7, wherein: The passivation film is formed of a TEOS oxide film.

10. The semiconductor device according to claim 1, wherein The semiconductor substrate is a silicon carbide semiconductor substrate. 11 . A semiconductor module comprising the semiconductor device according to claim 1 encapsulated by a resin encapsulation material.

12. The semiconductor module according to claim 11, wherein: The invention further comprises an upper passivation film provided so as to cover the surface of the polyimide film and the surface of the outermost peripheral region.

13. The semiconductor module according to claim 12, wherein: The upper passivation film is formed of a TEOS oxide film.

14. The semiconductor module according to claim 11, wherein: The invention further comprises a stress buffer film provided so as to cover the surface of the polyimide film and the surface of the outermost peripheral region.

15. The semiconductor module according to claim 14, wherein: The stress buffer film is formed of silicone gel or silicone rubber.

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