Semiconductor modules for power

Abstract

A semiconductor module for electric power is provided to suppress current imbalance between semiconductor switch elements. The semiconductor module for electric power includes: a bus bar, the bus bar is bonded with the first main electrode of each semiconductor switch element; a heat dissipation metal substrate, the heat dissipation metal substrate is bonded with the second main electrode of each semiconductor switch element; and a control gate terminal, the control gate terminal is connected to the gate pad of each semiconductor switch element through a bonding wire, and at least two of the plurality of semiconductor switch elements are adjacently arranged on the heat dissipation metal substrate to form a bridge arm electrically connected in parallel.

Description

Technical Field

[0001] The present application relates to a semiconductor module for electric power. Background Art

[0002] In electric vehicles such as electric vehicles and plug-in hybrid vehicles, a power conversion device such as an inverter is used to drive the motor with a high voltage battery, and the power conversion device includes a power semiconductor module for converting power through a switching operation. The power semiconductor module includes a semiconductor switching element that performs a switching operation on a heat-dissipating metal substrate, and the semiconductor switching element is connected to an external terminal and sealed with a sealing material such as resin or gel.

[0003] Semiconductor switch elements generate losses corresponding to current and voltage during conduction and switching operations. Rated power is set in semiconductor switch elements to prevent the temperature rise associated with the losses from exceeding the destruction temperature of the semiconductor switch elements and surrounding components. Generally speaking, in power semiconductor modules for power conversion devices for large currents and high voltages, large-sized semiconductor switch elements are used to ensure the rated power of the power semiconductor modules. However, from the perspective of manufacturing technology or yield of semiconductor switch elements, there is a limit to the increase in the size of semiconductor switch elements. In power semiconductor modules that pursue large power capacity, multiple semiconductor switch elements are connected in parallel to suppress the heat generation of each semiconductor switch element.

[0004] If multiple semiconductor switching elements are connected in parallel, current imbalance will occur between the semiconductor switching elements during switching due to deviation of the control signal, etc. If current imbalance occurs between the semiconductor switching elements, a large loss will occur in some of the semiconductor switching elements. Therefore, it is necessary to use large semiconductor switching elements or a large number of semiconductor switching elements, thereby increasing the size and cost of the power semiconductor module. In contrast, a technology has been proposed to reduce the inductance deviation between the control signal wirings through the structure of the control signal substrate in the module to suppress the deviation of the control signal (for example, refer to Patent Document 1).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. 2019 / 064874

[0008] In a conventional power semiconductor module, when there is a current imbalance due to a variation in ground potential between semiconductor switching elements or a variation in parasitic inductance between semiconductor switching elements, there is a technical problem that the current imbalance cannot be suppressed. Summary of the invention

[0009] The present application is made to solve the above-mentioned technical problems, and its purpose is to provide a semiconductor module for power, which reduces the deviation of control signals, ground potential and parasitic inductance between semiconductor switch elements through a simple structure, thereby suppressing the current imbalance between semiconductor switch elements.

[0010] The power semiconductor module disclosed in the present application includes: a plurality of semiconductor switch elements, each of which has a first main electrode and a gate pad on the front side and a second main electrode on the back side; a bus bar, to which the first main electrodes of each semiconductor switch element are bonded; a heat dissipation metal substrate, to which the second main electrodes of each semiconductor switch element are bonded; and a control gate terminal, to which the control gate terminal is connected to the gate pads of each semiconductor switch element through a bonding wire, and at least two of the plurality of semiconductor switch elements are arranged adjacent to each other on the heat dissipation metal substrate to form a bridge arm electrically connected in parallel.

[0011] The power semiconductor module disclosed in the present application includes: a plurality of semiconductor switch elements, each of which has a first main electrode and a gate pad on the front side and a second main electrode on the back side; a bus bar, the bus bar being bonded with the first main electrodes of each semiconductor switch element; a heat dissipation metal substrate, the heat dissipation metal substrate being bonded with the second main electrodes of each semiconductor switch element; and a control gate terminal, the control gate terminal being connected to the gate pads of each semiconductor switch element through a bonding wire. At least two of the plurality of semiconductor switch elements are arranged adjacent to each other on the heat dissipation metal substrate to form a bridge arm electrically connected in parallel. Therefore, the deviation of the control signal, the deviation of the ground potential and the deviation of the parasitic inductance between the semiconductor switch elements can be reduced through a simple structure, thereby suppressing the current imbalance between the semiconductor switch elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 FIG. 1 is a diagram showing the appearance of a power semiconductor module according to the first embodiment.

[0013] Figure 2 It is a diagram showing the internal structure of the power semiconductor module according to the first embodiment, with the resin mold removed.

[0014] Figure 3 This is an equivalent circuit diagram of the power semiconductor module according to the first embodiment.

[0015] Figure 4 This is a diagram showing the appearance of a power semiconductor module according to the second embodiment.

[0016] Figure 5It is a diagram showing the internal structure of the power semiconductor module according to the second embodiment, with the resin mold removed.

[0017] Figure 6 This is an equivalent circuit diagram of a power semiconductor module according to the second embodiment.

[0018] Figure 7 This is a diagram showing the appearance of a power semiconductor module according to a third embodiment.

[0019] Figure 8 FIG. 1 is a diagram showing the internal structure of a power semiconductor module according to a third embodiment, with the resin mold removed.

[0020] Fig. 9 This is a diagram showing the appearance of a power semiconductor module according to a fourth embodiment.

[0021] Fig.10 This is a diagram showing the internal structure of the power semiconductor module according to the fourth embodiment, with the resin module removed.

[0022] Fig.11 1 is a diagram showing the internal structure of the power semiconductor module according to the fourth embodiment, with the resin mold, the negative arm N bus bar, and the control ground terminal removed.

[0023] Fig.12 1 is a diagram showing the internal structure of the power semiconductor module according to the fourth embodiment, excluding the resin mold, the negative arm N bus bar, the control ground terminal, and the intermediate bus bar.

[0024] (Explanation of symbols)

[0025] 1, 1a, 1b, 1c Resin molded parts;

[0026] 2, 2a, 2b P busbar;

[0027] 3, 3a, 3b N busbar;

[0028] 4, 4a, 4b, 4c, 4d control grounding terminal;

[0029] 5, 5a, 5b, 5c, 5d, 5e control gate terminals;

[0030] 6, 6a, 6b, 6c, 6d heat dissipating metal substrate;

[0031] 7a, 7b, 7c, 7d, 7e, 7f, 7g, 7h, 7i, 7j, 7k, 7l, 7m, 7n semiconductor switching elements;

[0032] 8, 8a, 8b, 8c, 8d, 8e, 8f, 8g, 8h bonding wire;

[0033] 9a, 9b, 9c, 9d, 9e, 9f, 9g, 9h, 9i, 9j, 9k, 9l, 9m, 9n source electrode;

[0034] 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i, 10j, 10k, 10l, 10m, 10n gate pads;

[0035] 11a, 11b positive bridge arm P busbar;

[0036] 12 Negative bridge arm N busbar;

[0037] 13a, 13b AC busbars;

[0038] 14 intermediate busbars;

[0039] 21a, 21b, 21c, 21d, 21e, 21f P-side parasitic inductance;

[0040] 22, 22a P-side common inductor;

[0041] 23a, 23b, 23c, 23d, 23e, 23f N-side parasitic inductance;

[0042] 24, 24a N-side common inductor;

[0043] 25a, 25b, 25c, 25d, 25e, 25f gate control signal parasitic inductance;

[0044] 26, 26a, gate control signal shared inductor;

[0045] 27, 27a ground control signal common inductor;

[0046] 28a, 28b P-side primary common inductance;

[0047] 29a, 29b N-side primary common inductor;

[0048] 30a, 30b primary common inductor of gate control signal;

[0049] 100, 200, 300, 400 semiconductor modules for power use;

[0050] 1000 baseline. DETAILED DESCRIPTION

[0051] Hereinafter, a power semiconductor module according to an embodiment of the present application will be described in detail with reference to the accompanying drawings. In addition, in each figure, the same reference numerals represent the same or corresponding parts.

[0052] Implementation Method 1

[0053] Figure 1 FIG. 1 is a diagram showing the appearance of a power semiconductor module 100 according to the first embodiment. Figure 2 1 is a diagram showing the internal structure of the power semiconductor module 100 according to the first embodiment, with the resin module 1 removed. The power semiconductor module 100 according to the first embodiment includes a resin mold 1, a P bus bar 2, an N bus bar 3, a control ground terminal 4, a control gate terminal 5, a heat dissipating metal substrate 6, a semiconductor switch element 7a, a semiconductor switch element 7b, and a bonding wire 8. The semiconductor switch element 7a includes a source electrode 9a and a gate pad 10a on the front surface, and includes a drain electrode (not shown) on the back surface. The semiconductor switch element 7b includes a source electrode 9b and a gate pad 10b on the front surface, and includes a drain electrode (not shown) on the back surface. The semiconductor switch element 7a and the semiconductor switch element 7b are adjacently arranged on the heat dissipating metal substrate 6, and the drain electrodes of the semiconductor switch element 7a and the semiconductor switch element 7b are bonded to the heat dissipating metal substrate 6 and electrically connected. An N bus bar 3 is arranged on the semiconductor switch element 7a and the semiconductor switch element 7b, and the source electrode 9a of the semiconductor switch element 7a and the source electrode 9b of the semiconductor switch element 7b are bonded to the N bus bar 3 and electrically connected. As a result, the drain electrodes and the source electrodes of the semiconductor switch element 7a and the semiconductor switch element 7b are electrically connected in parallel to form a set of bridge arms. The N bus bar 3 is connected to the control ground terminal 4, and one end is output to the outside of the resin mold 1. The gate pad 10a of the semiconductor switch element 7a and the gate pad 10b of the semiconductor switch element 7b are electrically connected with a bonding wire 8, and the end of the bonding wire 8 is electrically connected to the control gate terminal 5, and the control gate terminal 5 is output to the outside of the resin mold 1. The power semiconductor module 100 is sealed by the resin mold 1.

[0054] The semiconductor switch element 7a and the semiconductor switch element 7b are joined to the heat-dissipating metal substrate 6 by welding, but the method is not limited thereto, and other joining methods such as silver sintering (Japanese: Ag sintering) may also be used. The heat-dissipating metal substrate 6 is a copper heat sink, but the method is not limited thereto, and other substrate materials such as a DBC (Direct Bonded Copper) substrate in which a ceramic insulating substrate, which is an insulating material joined by brazing or the like, and a copper base plate are joined together may also be used.

[0055] The power semiconductor module 100 is sealed by, for example, a transfer-molded resin mold 1. However, the present invention is not limited thereto, and a resin case filled with gel may be used instead of the resin mold 1.

[0056] Figure 3FIG. 1 is an equivalent circuit diagram of the power semiconductor module 100 according to the first embodiment. Figure 3 MOSFET (metal oxide semiconductor field effect transistor) is shown as the semiconductor switch element 7a and the semiconductor switch element 7b, but it is not limited to this, and it can also be an IGBT (insulated gate bipolar transistor) or a bipolar transistor. When an IGBT or a bipolar transistor is used, the part that serves as the "drain" is the "collector" and the part that serves as the "source" is the "emitter" in the description. In addition, Figure 3 , the structure in which the parasitic diode of MOSFET is used as the return diode is shown. However, when a semiconductor switch element having no parasitic diode such as an IGBT is used, a structure in which the return diode is connected in anti-parallel with respect to the semiconductor switch element may be formed.

[0057] exist Figure 3 , the P-side parasitic inductance 21a, the N-side parasitic inductance 23a, and the gate control signal parasitic inductance 25a are parasitic inductances of the wiring connected to the semiconductor switch element 7a, and the P-side parasitic inductance 21b, the N-side parasitic inductance 23b, and the gate control signal parasitic inductance 25b are parasitic inductances of the wiring connected to the semiconductor switch element 7b. As other inductance components, the P-side common inductance 22, the N-side common inductance 24, the gate control signal common inductance 26, and the ground control signal common inductance 27 of the power semiconductor module 100, which are shared by the semiconductor switch element 7a and the semiconductor switch element 7b, are shown.

[0058] Next, the structure and effects of the power semiconductor module 100 according to the first embodiment are described. There are two main reasons for the current imbalance between the semiconductor switch element 7a and the semiconductor switch element 7b. The first reason is caused by the deviation of the parasitic inductance between the PN electrodes. Figure 3 When the sum of the inductance components of the P-side parasitic inductance 21a and the N-side parasitic inductance 23a of the semiconductor switch element 7a is set to La, the sum of the inductance components of the P-side parasitic inductance 21b and the N-side parasitic inductance 23b of the semiconductor switch element 7b is set to Lb, the time variation of the current when the semiconductor switch element 7a is switched is set to dIa / dt, and the time variation of the current when the semiconductor switch element 7b is switched is set to dIb / dt, the drain-source voltage of the semiconductor switch element 7a and the semiconductor switch element 7b generates a voltage difference shown by ΔVds in equation (1).

[0059] ΔVds=La(dIa / dt)-Lb(dIb / dt) (1)

[0060] In the semiconductor switch element, if the drain-source voltage changes, the on-current changes, so the current imbalance occurs due to the voltage difference ΔVds between the drain and the source. The current imbalance can be suppressed by adding an inductor specifically to suppress the deviation of the parasitic inductance between the PN electrodes of the semiconductor switch element 7a and the semiconductor switch element 7b, but the addition of the inductor will increase the surge voltage and complicate the structure.

[0061] In the power semiconductor module 100 according to the first embodiment, as Figure 2 As shown, semiconductor switch elements 7a and semiconductor switch elements 7b are adjacently arranged and bonded on a heat-dissipating metal substrate 6, and N busbars 3 are arranged and bonded on the semiconductor switch elements 7a and semiconductor switch elements 7b, so that the drain electrodes and source electrodes of the semiconductor switch elements 7a and semiconductor switch elements 7b are electrically connected in parallel. The parasitic inductance of the semiconductor switch element increases in proportion to the length of the current path and decreases in inverse proportion to the area of ​​the current path. In the power semiconductor module 100, the distance between the semiconductor switch elements 7a and semiconductor switch elements 7b as the current path is shortened, and the connection is realized by using a busbar with a larger area of ​​the current path instead of a connection realized by a general bonding wire, so that the P-side parasitic inductance 21a, 21b and the N-side parasitic inductance 23a, 23b are reduced. As a result, the sum of the inductance components of the P-side parasitic inductance 21a and the N-side parasitic inductance 23a, i.e., La, and the sum of the inductance components of the P-side parasitic inductance 21b and the N-side parasitic inductance 23b, i.e., Lb, are reduced, and the voltage difference ΔVds between the drain and the source is reduced, thereby suppressing the current imbalance. The shorter the distance between the semiconductor switch element 7a and the semiconductor switch element 7b, the more the current imbalance can be suppressed. Therefore, the distance between the closest points of the semiconductor switch element 7a and the semiconductor switch element 7b is set to within 5 mm, for example.

[0062] The second reason for the current imbalance between the semiconductor switch element 7a and the semiconductor switch element 7b is the deviation of the gate voltage caused by the deviation of the ground potential and the deviation of the control signal. The deviation of the ground potential between the semiconductor switch elements is caused by the deviation of the product of the N-side parasitic inductance 23a and dIa / dt and the product of the N-side parasitic inductance 23b and dIb / dt. The deviation of the control signal is caused by the magnetic coupling between the gate control signal parasitic inductance 25a and the gate control signal parasitic inductance 25b and each parasitic inductance in the circuit. The magnitude of the influence of the magnetic coupling is proportional to the magnitude of the inductance value and the magnitude of the time change of the current flowing in each parasitic inductance in the circuit.

[0063] In the power semiconductor module 100 according to the first embodiment, as Figure 2As shown, semiconductor switch element 7a and semiconductor switch element 7b are arranged adjacent to and joined on heat-dissipating metal substrate 6, and N bus bar 3 is arranged and joined on semiconductor switch element 7a and semiconductor switch element 7b, so that N-side parasitic inductance 23a, 23b is small and deviation of ground potential can be suppressed.

[0064] In addition, in the semiconductor switch element 7a and the semiconductor switch element 7b arranged adjacently, the gate pad 10a and the gate pad 10b are connected to the bonding wire 8, and the end of the bonding wire 8 is connected to the control gate terminal 5. Here, the gate control signal parasitic inductance 25a is a parasitic inductance generated by the bonding wire 8 between the gate pad 10a of the semiconductor switch element 7a and the gate pad 10b of the semiconductor switch element 7b. In the power semiconductor module 100 according to the first embodiment, the semiconductor switch element 7a and the semiconductor switch element 7b are arranged adjacently, and the distance between the gate pad 10a of the semiconductor switch element 7a and the gate pad 10b of the semiconductor switch element 7b is short, so the gate control signal parasitic inductance 25a can be suppressed. In addition, the gate control signal parasitic inductance 25b is a parasitic inductance generated from the bonding wire 8 to the gate pad 10b of the semiconductor switch element 7b, which can be almost ignored. The magnitude of the influence of the magnetic coupling is proportional to the inductance value, so the control signal deviation can be suppressed. In the power semiconductor module 100 according to the first embodiment, the variation in ground potential can be suppressed, the variation in control signal can be suppressed, and therefore the variation in gate voltage can be suppressed, and the current imbalance can be suppressed.

[0065] In addition, among the magnetic fluxes generated by the power semiconductor module 100, the magnetic flux generated by the PN current is the largest, and the PN current is the dominant factor in the magnetic coupling between the gate control signal parasitic inductance 25a and the gate control signal parasitic inductance 25b and each parasitic inductance in the circuit. Therefore, if the N bus bar 3, the heat dissipation metal substrate 6, and the bonding wire 8 are arranged so that the conduction direction of the PN current flowing in the N bus bar 3 and the heat dissipation metal substrate 6 is orthogonal to the direction of the current flowing in the bonding wire 8, the deviation of the control signal can be further suppressed, and the current imbalance can be further suppressed. In the case where it is difficult to arrange the N bus bar 3, the heat dissipation metal substrate 6, and the bonding wire 8 so that the conduction direction of the PN current is orthogonal to the direction of the current flowing in the bonding wire 8 due to layout constraints, the current imbalance can be suppressed as long as the conduction direction of the PN current and the direction of the current flowing in the bonding wire 8 are at least different directions that are not parallel. That is, the N bus bar 3 and the bonding wire 8 may be configured so that the direction of the current flowing in the N bus bar 3 is different from the direction of the current flowing in the bonding wire 8, and the heat dissipating metal substrate 6 and the bonding wire 8 may be configured so that the direction of the current flowing in the heat dissipating metal substrate 6 is different from the direction of the current flowing in the bonding wire 8.

[0066] In addition, the semiconductor switch element 7a and the semiconductor switch element 7b include source electrodes 9a, 9b and gate pads 10a, 10b on the front side and drain electrodes on the back side, but it is sufficient to include a first main electrode of any one of the source electrodes 9a, 9b and the drain electrode as the main electrode on the front side and include the other second main electrode on the back side. In the case where the drain electrode and the gate pads 10a, 10b are included on the front side and the source electrodes 9a, 9b are included on the back side, the positive and negative sides of the busbars are reversed, and the control ground terminal 4 is connected to the heat dissipating metal substrate 6.

[0067] In the power semiconductor module 100 according to the first embodiment, the number of semiconductor switching elements is set to two, and the same effect can be obtained as long as it is two or more. In addition, since the current imbalance is affected by the time variation of the current, the influence of the current imbalance becomes larger when the switching speed is fast. Therefore, in the case of applying not only silicon Si (Silicon) but also wide-bandgap semiconductors with a wider bandgap than silicon, i.e., silicon carbide SiC (Silicon Carbide), gallium nitride GaN (Gallium Nitride), or semiconductor switching elements and return diodes formed of diamond that can operate at high speed, the power semiconductor module 100 according to the first embodiment can obtain more significant effects.

[0068] As described above, the power semiconductor module 100 according to the first embodiment includes: a plurality of semiconductor switch elements 7a, 7b, each of which has a first main electrode 9a, 9b and a gate pad 10a, 10b on the front surface and a second main electrode on the back surface; a bus bar 3 to which the first main electrodes 9a, 9b of the semiconductor switch elements 7a, 7b are bonded; a heat dissipation metal substrate 6 to which the second main electrodes of the semiconductor switch elements 7a, 7b are bonded; and a control gate terminal 5 connected to the gate pads 10a, 10b of the semiconductor switch elements 7a, 7b through a bonding wire 8. At least two of the plurality of semiconductor switch elements 7a, 7b are adjacently arranged on the heat dissipation metal substrate 6 to form one arm electrically connected in parallel. Therefore, without adding unnecessary components, the deviation of the control signal, the deviation of the ground potential, and the deviation of the parasitic inductance between the semiconductor switch elements 7a, 7b can be reduced, thereby suppressing the current imbalance between the semiconductor switch elements 7a, 7b.

[0069] Implementation Method 2

[0070] Figure 4 FIG. 2 is a diagram showing the appearance of a power semiconductor module 200 according to the second embodiment. Figure 5The figure shows the internal structure of the power semiconductor module 200 according to the second embodiment without the resin module 1a. The power semiconductor module 200 according to the second embodiment is a structure in which the power semiconductor module 100 according to the first embodiment is arranged in mirror symmetry with the reference line 1000 as the axis of symmetry.

[0071] The power semiconductor module 200 according to the second embodiment includes a resin mold 1a, P bus bars 2a, 2b, N bus bar 3a, control ground terminal 4a, control gate terminal 5a, heat dissipation metal substrate 6a, semiconductor switch elements 7c, 7d, 7e, 7f and bonding wires 8a, 8b. The semiconductor switch elements 7c, 7d, 7e, 7f are connected to one heat dissipation metal substrate 6a and to one N bus bar 3a. The semiconductor switch element 7c and the semiconductor switch element 7d are arranged adjacent to each other on the heat dissipation metal substrate 6a, and the drain electrodes of the semiconductor switch element 7c and the semiconductor switch element 7d are bonded to the heat dissipation metal substrate 6a and electrically connected. The N bus bar 3a is arranged on the semiconductor switch element 7c and the semiconductor switch element 7d, and the source electrode 9c of the semiconductor switch element 7c and the source electrode 9d of the semiconductor switch element 7d are bonded to the N bus bar 3a and electrically connected. In addition, semiconductor switch element 7e and semiconductor switch element 7f are arranged adjacent to each other on heat-dissipating metal substrate 6a, and the drain electrodes of semiconductor switch element 7e and semiconductor switch element 7f are bonded and electrically connected to heat-dissipating metal substrate 6a. N bus bar 3a is arranged on semiconductor switch element 7e and semiconductor switch element 7f, and source electrode 9e of semiconductor switch element 7e and source electrode 9f of semiconductor switch element 7f are bonded and electrically connected to N bus bar 3a. Gate pad 10c of semiconductor switch element 7c and gate pad 10d of semiconductor switch element 7d are connected to bonding wire 8a, and the end of bonding wire 8a is connected to control gate terminal 5a. In addition, gate pad 10e of semiconductor switch element 7e and gate pad 10f of semiconductor switch element 7f are connected to bonding wire 8b, and the end of bonding wire 8b is also connected to the control gate terminal 5a.

[0072] In the power semiconductor module 200 of the second embodiment, the structures of the semiconductor switch elements 7c, 7d, the N bus bar 3a and the heat dissipation metal substrate 6a are the same as the structures of the semiconductor switch elements 7a, 7b, the N bus bar 3 and the heat dissipation metal substrate 6 in the power semiconductor module 100 of the first embodiment. Thus, the current imbalance between the semiconductor switch element 7c and the semiconductor switch element 7d can be suppressed, similarly to the current imbalance between the semiconductor switch element 7a and the semiconductor switch element 7b in the power semiconductor module 100 of the first embodiment. The structures of the semiconductor switch elements 7e, 7f and the heat dissipation metal substrate 6a are mirror-symmetrical to the structures of the semiconductor switch elements 7c, 7d and the heat dissipation metal substrate 6a, and are the same as the structures of the semiconductor switch elements 7a, 7b, the N bus bar 3 and the heat dissipation metal substrate 6 in the power semiconductor module 100 of the first embodiment. Therefore, the current imbalance between the semiconductor switch element 7e and the semiconductor switch element 7f can be suppressed, similarly to the current imbalance between the semiconductor switch element 7a and the semiconductor switch element 7b in the power semiconductor module 100 of the first embodiment.

[0073] Next, the effect of the power semiconductor module 200 according to the second embodiment alone, that is, the effect of suppressing the current imbalance between the semiconductor switching elements 7c and 7d and the semiconductor switching elements 7e and 7f, will be described. Figure 6 FIG. 2 is an equivalent circuit diagram of a power semiconductor module 200 according to Embodiment 2. Figure 6In the figure, the P-side parasitic inductance 21c, the N-side parasitic inductance 23c and the gate control signal parasitic inductance 25c are parasitic inductances of the wiring connected to the semiconductor switch element 7c, the P-side parasitic inductance 21d, the N-side parasitic inductance 23d and the gate control signal parasitic inductance 25d are parasitic inductances of the wiring connected to the semiconductor switch element 7d, the P-side parasitic inductance 21e, the N-side parasitic inductance 23e and the gate control signal parasitic inductance 25e are parasitic inductances of the wiring connected to the semiconductor switch element 7e, and the P-side parasitic inductance 21f, the N-side parasitic inductance 23f and the gate control signal parasitic inductance 25f are parasitic inductances of the wiring connected to the semiconductor switch element 7f. As other inductance components, the P-side primary common inductance 28a, the N-side primary common inductance 29a, and the gate control signal primary common inductance 30a of the power semiconductor module 200, which are shared by the semiconductor switch element 7c and the semiconductor switch element 7d, are shown, and the P-side primary common inductance 28b, the N-side primary common inductance 29b, and the gate control signal primary common inductance 30b of the power semiconductor module 200, which are shared by the semiconductor switch element 7e and the semiconductor switch element 7f, are shown. In addition, the P-side common inductance 22a, the N-side common inductance 24a, the gate control signal common inductance 26a, and the ground control signal common inductance 27a of the power semiconductor module 200, which are shared by the semiconductor switch elements 7c, 7d, 7e, and 7f, are shown.

[0074] Regarding the deviation of the parasitic inductance between PN, the P-side parasitic inductance 21c, 21d, 21e, 21f and the N-side parasitic inductance 23c, 23d, 23e, 23f are suppressed to be extremely small, and the current imbalance caused by these parasitic inductances can be suppressed. In the power semiconductor module 200 of the second embodiment, the electrodes of the semiconductor switch elements 7c, 7d and the semiconductor switch elements 7e, 7f are connected to a heat dissipating metal substrate 6a and an N bus bar 3a and connected in parallel, so that the P-side primary shared inductance 28a, 28b and the N-side primary shared inductance 29a, 29b are small, and the current imbalance can be suppressed.

[0075] In addition, in the power semiconductor module 200, the arrangement of the first semiconductor switch element unit composed of the semiconductor switch elements 7c and 7d and the second semiconductor switch element unit composed of the semiconductor switch elements 7e and 7f, the arrangement of the P bus bar 2a and the P bus bar 2b, the structure of the N bus bar 3a, and the structure of the heat dissipating metal substrate 6a are mirror-symmetrical with reference line 1000 as the axis of symmetry, so that the conduction paths of the current in the semiconductor switch elements 7c and 7d and the semiconductor switch elements 7e and 7f are mirror-symmetrical. As a result, the deviation between the P-side primary common inductance 28a and the P-side primary common inductance 28b and the deviation between the N-side primary common inductance 29a and the N-side primary common inductance 29b can be suppressed, and the current imbalance between the semiconductor switch elements 7c and 7d and the semiconductor switch elements 7e and 7f can be further suppressed.

[0076] Here, although the structure of the heat dissipating metal substrate 6a is mirror-symmetrical with reference line 1000 as the axis of symmetry, it is sufficient as long as the portion of the path for the switching current to flow is mirror-symmetrical. In addition, the control gate terminal 5a and the control ground terminal 4a that do not serve as the path for the switching current to flow do not need to be mirror-symmetrical. In addition, when a fixing point or the like is required for manufacturing, it is not necessary to set the position to be mirror-symmetrical as long as it does not affect the path for the switching current to flow.

[0077] In addition, the configuration of the semiconductor switch elements 7c, 7d and the semiconductor switch elements 7e, 7f, the configuration of the P bus bar 2a and the P bus bar 2b, the structure of the N bus bar 3a, and the structure of the heat dissipating metal substrate 6a are mirror-symmetrical with the reference line 1000 as the symmetry axis. Therefore, the deviation of the N-side primary common inductance 29a and the N-side primary common inductance 29b can be suppressed, and thus the deviation of the ground potential between the semiconductor switch elements 7c, 7d, 7e, and 7f can be suppressed.

[0078] In addition, the portion of the first bonding wire 8a connecting the gate pad 10c of the semiconductor switch element 7c and the gate pad 10d of the semiconductor switch element 7d, and the portion of the second bonding wire 8b connecting the gate pad 10e of the semiconductor switch element 7e and the gate pad 10f of the semiconductor switch element 7f are arranged at positions that are mirror-symmetrical with respect to the reference line 1000 as the axis of symmetry. As a result, the deviation of the parasitic inductance of the bonding wire 8a, i.e., the primary common inductance of the gate control signal 30a, and the parasitic inductance of the bonding wire 8b, i.e., the primary common inductance of the gate control signal 30b, can be suppressed, and the deviation of the influence of the magnetic coupling generated between the bonding wire 8a and each parasitic inductance and the deviation of the influence of the magnetic coupling generated between the bonding wire 8b and each parasitic inductance can be made consistent, so that the deviation of the control signal can be suppressed. As a result, the deviation of the gate voltage between the semiconductor switch elements 7c, 7d and the semiconductor switch elements 7e, 7f can be suppressed, and the current imbalance can be suppressed.

[0079] Implementation 3

[0080] Figure 7 FIG. 1 is a diagram showing the appearance of a power semiconductor module 300 according to the third embodiment. Figure 8 1 is a diagram showing the internal structure of the power semiconductor module 300 according to the third embodiment, from which the resin module 1b is removed. The power semiconductor module 300 according to the third embodiment is different from the power semiconductor module 200 according to the second embodiment in that the bonding wire 8c connected to the gate pad 10c of the semiconductor switch element 7c and the gate pad 10d of the semiconductor switch element 7d are connected to the control gate terminal 5b, the bonding wire 8d connected to the gate pad 10e of the semiconductor switch element 7e and the gate pad 10f of the semiconductor switch element 7f are connected to the control gate terminal 5c, the first control gate terminal, i.e., the control gate terminal 5b, and the second control gate terminal, i.e., the control gate terminal 5c, are mirror-symmetrical with respect to the reference line 1000 as the axis of symmetry, and the first bonding wire, i.e., the bonding wire 8c, and the second bonding wire, i.e., the bonding wire 8d, are mirror-symmetrical with respect to the reference line 1000 as the axis of symmetry. In addition, although the shapes of the N bus bar 3b, the control ground terminal 4b and the heat dissipating metal substrate 6b are different from those in the power semiconductor module 200 according to the second embodiment, the shapes of the N bus bar 3b and the heat dissipating metal substrate 6b are mirror-symmetrical with the reference line 1000 as the symmetry axis, which is the same as the power semiconductor module 200 according to the second embodiment.

[0081] In the power semiconductor module 200 according to the second embodiment, the current flowing through the bonding wire 8a and the bonding wire 8b flows to one control gate terminal 5a. Figure 6 A large current flows in the gate control signal common inductor 26a shown. At this time, a voltage difference is generated in the gate control signal common inductor 26a of the control gate terminal 5a, which, for example, becomes the cause of an erroneous turn-on operation caused by an increase in the gate voltage of each of the semiconductor switch elements 7c, 7d, 7e, and 7f, restricting the switching speed. In the power semiconductor module 300 according to the third embodiment, by connecting the first bonding wire, i.e., the bonding wire 8c, and the second bonding wire, i.e., the bonding wire 8d, to different control gate terminals, respectively, the current flowing in one control gate terminal is reduced, thereby suppressing the voltage difference generated at the control gate terminal. As a result, faster switching can be achieved.

[0082] Implementation 4

[0083] Fig. 9 FIG. 4 is a diagram showing the appearance of a power semiconductor module 400 according to a fourth embodiment. Fig.10 1 is a diagram showing the internal structure of a power semiconductor module 400 according to the fourth embodiment, with the resin module 1 c removed. Fig.11 1 is a diagram showing the internal structure of a power semiconductor module 400 according to the fourth embodiment, with the resin mold 1 c , the negative arm N bus bar 12 , and the control ground terminal 4 c removed. Fig.12 1 is a diagram showing the internal structure of a power semiconductor module 400 according to the fourth embodiment, with the resin mold 1 c , the negative arm N bus bar 12 , the control ground terminal 4 c , and the intermediate bus bar 14 removed.

[0084] The power semiconductor module 400 according to the fourth embodiment has two bridge arms consisting of semiconductor switching elements, namely a positive bridge arm and a negative bridge arm, so that the positive bridge arm and the negative bridge arm are connected in series, and the shape is called a "2-in-1 module". The power semiconductor module 400 according to the fourth embodiment is based on the power semiconductor module 200 according to the second embodiment and the power semiconductor module 200 according to the second embodiment is turned upside down so that two power semiconductor modules are arranged side by side.

[0085] When the upper half of the power semiconductor module 400 according to the fourth embodiment is compared with the power semiconductor module 200 according to the second embodiment, although the P bus bars 2a and 2b are replaced by the AC bus bars 13a and 13b, and the N bus bar 3a is replaced by the negative arm N bus bar 12, the resin mold 1c, the AC bus bars 13a and 13b, the negative arm N bus bar 12, the control ground terminal 4c, the control gate terminal 5d, the heat dissipating metal substrate 6c, the semiconductor switch elements 7g, 7h, 7i, 7j, and the bonding wires 8e and 8f are arranged in the same manner as the power semiconductor module 200 according to the second embodiment. The drain electrodes of the semiconductor switch elements 7g, 7h, 7i, and 7j are connected to one heat dissipating metal substrate 6c, and the heat dissipating metal substrate 6c is connected to the AC bus bars 13a and 13b. The source electrodes 9g, 9h, 9i, 9j of the semiconductor switch elements 7g, 7h, 7i, 7j are connected to a negative bridge arm N bus bar 12, and the negative bridge arm N bus bar 12 is connected to the control ground terminal 4c. The gate pad 10g of the semiconductor switch element 7g and the gate pad 10h of the semiconductor switch element 7h are connected to a bonding wire 8e, and the end of the bonding wire 8e is connected to the control gate terminal 5d. In addition, the gate pad 10i of the semiconductor switch element 7i and the gate pad 10j of the semiconductor switch element 7j are connected to a bonding wire 8f, and the end of the bonding wire 8f is also connected to the control gate terminal 5d.

[0086] When the lower half of the power semiconductor module 400 according to the fourth embodiment is compared with the power semiconductor module 200 according to the second embodiment, although the P bus bars 2a and 2b are replaced by the positive arm P bus bars 11a and 11b, and the N bus bar 3a is replaced by the intermediate bus bar 14, the resin mold 1c, the positive arm P bus bars 11a and 11b, the intermediate bus bar 14, the control ground terminal 4d, the control gate terminal 5e, the heat dissipating metal substrate 6d, the semiconductor switch elements 7k, 71, 7m, 7n, and the bonding wires 8g and 8h are configured in the same manner as the power semiconductor module 200 according to the second embodiment. The drain electrodes of the semiconductor switch elements 7k, 71, 7m, and 7n are connected to one heat dissipating metal substrate 6d, and the heat dissipating metal substrate 6d is connected to the positive arm P bus bars 11a and 11b. The source electrodes 9k, 9l, 9m, 9n of the semiconductor switch elements 7k, 7l, 7m, 7n are connected to an intermediate bus bar 14, and the intermediate bus bar 14 is connected to the control ground terminal 4d and the heat dissipating metal substrate 6c. The gate pad 10k of the semiconductor switch element 7k and the gate pad 10l of the semiconductor switch element 7l are connected to a bonding wire 8g, and the end of the bonding wire 8g is connected to the control gate terminal 5e. In addition, the gate pad 10m of the semiconductor switch element 7m and the gate pad 10n of the semiconductor switch element 7n are connected to a bonding wire 8h, and the end of the bonding wire 8h is also connected to the control gate terminal 5e.

[0087] The semiconductor switch elements 7k, 71, 7m, and 7n are connected in parallel through the heat dissipation metal substrate 6d and the intermediate bus bar 14 to form a positive bridge arm, and the semiconductor switch elements 7g, 7h, 7i, and 7j are connected in parallel through the heat dissipation metal substrate 6c and the negative bridge arm N bus bar 12 to form a negative bridge arm. The heat dissipation metal substrate 6c, which becomes the drain potential of the negative bridge arm, is connected to the intermediate bus bar 14, which becomes the source potential of the positive bridge arm, thereby connecting the positive bridge arm and the negative bridge arm with the heat dissipation metal substrate 6c as a connection point. The AC bus bars 13a and 13b, which serve as AC electrodes, are connected to the heat dissipation metal substrate 6c, which serves as a connection point between the positive bridge arm and the negative bridge arm. The intermediate bus bar 14 is arranged to overlap with the negative bridge arm N bus bar 12, and the intermediate bus bar 14 and the negative bridge arm N bus bar 12 are a double-layer structure.

[0088] Next, the structure and effect of the power semiconductor module 400 according to the fourth embodiment are described. The directions of the currents flowing in the middle bus bar 14 and the negative arm N bus bar 12 are opposite, and the middle bus bar 14 and the negative arm N bus bar 12 are overlapped, so the currents flowing in the middle bus bar 14 and the negative arm N bus bar 12 act in a manner of canceling out the parasitic inductance. Here, the middle bus bar 14 is the source potential of the semiconductor switch elements 7k, 7l, 7m, and 7n, that is, the ground potential, and the parasitic inductance of the middle bus bar 14 can be reduced, thereby suppressing the current imbalance in the semiconductor switch elements 7k, 7l, 7m, and 7n. Similarly, the negative arm N bus bar 12 is the source potential of the semiconductor switch elements 7g, 7h, 7i, and 7j, that is, the ground potential, and the parasitic inductance of the negative arm N bus bar 12 can be reduced, thereby suppressing the current imbalance in the semiconductor switch elements 7g, 7h, 7i, and 7j. In addition, by reducing the sum of parasitic inductances between PNs, surge voltage associated with switching can be suppressed, thereby achieving high-speed switching.

[0089] The present application describes various exemplary embodiments, but various features, methods, and functions described in one or more embodiments are not limited to application to specific embodiments and can be applied to the embodiments alone or in various combinations.

[0090] Therefore, numerous modifications not shown are contemplated within the technical scope disclosed in this application, including, for example, modifications, additions, or omissions of at least one component, and also including extraction of at least one component and combination with components of other embodiments.

Claims

1. A semiconductor module for electric power, characterized in that: include: A plurality of semiconductor switch elements, each of which has a first main electrode and a gate pad on a front surface and a second main electrode on a back surface; a bus bar to which the first main electrodes of the semiconductor switching elements are connected; a heat-dissipating metal substrate to which the second main electrodes of the semiconductor switch elements are bonded; as well as a control gate terminal connected to each of the gate pads of the semiconductor switch elements via a bonding wire, At least two of the plurality of semiconductor switch elements are arranged adjacent to each other on the heat dissipating metal substrate to form a bridge arm electrically connected in parallel. The bus bar, the heat dissipating metal substrate and the bonding wire are configured so that the direction of the current flowing in the bus bar is different from the direction of the current flowing in the bonding wire, and the direction of the current flowing in the heat dissipating metal substrate is different from the direction of the current flowing in the bonding wire.

2. The power semiconductor module according to claim 1, wherein: The distance between the closest points of at least two of the semiconductor switch elements arranged adjacent to each other is within 5 mm.

3. The power semiconductor module according to claim 1 or 2, wherein: The gate pads of at least two adjacently arranged semiconductor switch elements are connected to one of the plurality of bonding wires. All of the bonding wires are connected to one of the control gate terminals.

4. The power semiconductor module according to claim 1 or 2, wherein: The gate pads of at least two adjacently arranged semiconductor switch elements are connected to one of the plurality of bonding wires. Each of the bonding wires is connected to a different control gate terminal.

5. The power semiconductor module according to claim 1 or 2, characterized in that: A first semiconductor switch element unit composed of at least two adjacently arranged semiconductor switch elements and a second semiconductor switch element unit composed of at least two adjacently arranged semiconductor switch elements are arranged to be mirror-symmetrical with the reference line as an axis of symmetry.

6. The power semiconductor module according to claim 5, wherein: The structure of the busbar is mirror-symmetrical with the reference line as a symmetry axis.

7. The power semiconductor module according to claim 5, wherein: A first bonding wire among the bonding wires and a second bonding wire among the bonding wires are arranged in mirror symmetry with respect to the symmetry axis.

8. The power semiconductor module according to claim 6, wherein: A first bonding wire among the bonding wires and a second bonding wire among the bonding wires are arranged in mirror symmetry with respect to the symmetry axis.

9. The power semiconductor module according to claim 1 or 2, wherein: The power semiconductor module includes a freewheeling diode connected in antiparallel to the semiconductor switching element.

10. The power semiconductor module according to claim 9, wherein: The freewheeling diode is formed of a wide bandgap semiconductor having a wider bandgap than silicon.

11. The power semiconductor module according to claim 1 or 2, wherein: The semiconductor switching element is formed of a wide bandgap semiconductor having a wider bandgap than silicon.

12. The power semiconductor module according to claim 10, wherein: The wide bandgap semiconductor is any one of silicon carbide, gallium nitride, and diamond.

13. The power semiconductor module according to claim 11, wherein: The wide bandgap semiconductor is any one of silicon carbide, gallium nitride, and diamond.

14. The power semiconductor module according to claim 1 or 2, wherein: The power semiconductor module includes two bridge arms. One of the bridge arms as a positive bridge arm and the other of the bridge arms as a negative bridge arm are connected in series with each other, The power semiconductor module includes an AC electrode connected to a connection point between the positive bridge arm and the negative bridge arm.

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