Method for manufacturing solar cell and solar cell

Abstract

The present application is applicable to the field of solar cell technology, and provides a method for manufacturing a solar cell and a solar cell. The method for manufacturing a solar cell includes: making a silicon wafer into a cell substrate for a circuit to be manufactured, the cell substrate includes a plurality of spaced first regions and a plurality of spaced second regions, the first region intersecting the second region; preparing a silicon nitride layer in the first region; printing a first slurry on the silicon nitride layer; printing a second slurry in the second region; sintering the cell substrate printed with the first slurry and the second slurry, so that the main grid sintered by the first slurry is embedded in the silicon nitride layer, and the secondary grid sintered by the second slurry forms a gold-semiconductor contact with the silicon wafer, and the secondary grid overlaps the main grid. In this way, the main grid has better weldability, and the composite loss under the main grid is reduced.

Description

Technical Field

[0001] The present application belongs to the technical field of solar cells, and in particular to a method for manufacturing a solar cell and a solar cell. Background Art

[0002] In the related art, a battery printing paste is prepared for a silicon nitride film. The paste burns through the silicon nitride film during the sintering process and forms a gold-semiconductor contact with the silicon substrate, thereby forming a conductive channel. The secondary grid collects the current in the silicon substrate and converges it into the main grid. The current in the main grid flows to the external circuit through the welding strip welded on the main grid. However, too large a gold-semiconductor contact surface and embedding depth will lead to an increase in the composite loss, while too small a gold-semiconductor contact surface and embedding depth will lead to poor weldability of the main grid. Based on this, how to make solar cells so that the composite loss is low and the main grid weldability is good has become a problem that needs to be solved urgently. Summary of the invention

[0003] The present application provides a method for manufacturing a solar cell and a solar cell, aiming to solve the problem of how to manufacture a solar cell so that the recombination loss is low and the main grid weldability is good.

[0004] In a first aspect, the present application provides a method for manufacturing a solar cell, comprising:

[0005] The silicon wafer is made into a battery substrate for a circuit to be manufactured, wherein the battery substrate comprises a plurality of spaced first regions and a plurality of spaced second regions, wherein the first regions intersect with the second regions;

[0006] preparing a silicon nitride layer in the first region;

[0007] printing a first slurry on the silicon nitride layer;

[0008] printing a second slurry in the second area;

[0009] The battery substrate printed with the first paste and the second paste is sintered so that the main grid sintered by the first paste is embedded in the silicon nitride layer, and the auxiliary grid sintered by the second paste forms a gold semi-contact with the silicon wafer, and the auxiliary grid overlaps the main grid.

[0010] Optionally, preparing a silicon nitride layer in the first region includes:

[0011] preparing a suspension of silicon nitride;

[0012] attaching the suspension to the first area;

[0013] Baking the battery substrate to which the suspension is attached;

[0014] The battery substrate is sintered and baked.

[0015] Optionally, preparing a suspension of silicon nitride comprises:

[0016] Silicon nitride powder, polyethylene glycol and polyvinyl pyrrolidone are mixed to prepare the suspension.

[0017] Optionally, attaching the suspension to the first area comprises:

[0018] The suspension is attached to the first area by using a printing process or a spraying process.

[0019] Optionally, in the step of baking the battery substrate to which the suspension is attached, the baking temperature ranges from 100° C. to 600° C., and / or the baking time ranges from 10 min to 30 min.

[0020] Optionally, in the step of sintering and baking the battery substrate, the sintering temperature ranges from 700° C. to 800° C., and / or the sintering time ranges from 1 min to 5 min.

[0021] Optionally, the silicon nitride layer has a thickness ranging from 0.3 μm to 5 μm.

[0022] In a second aspect, the solar cell provided in the present application is manufactured using any of the above methods.

[0023] In a third aspect, the solar cell provided in the present application comprises: a cell substrate, a silicon nitride layer, a main grid and a sub-grid, wherein the cell substrate is made of a silicon wafer, the cell substrate comprises a plurality of spaced first regions and a plurality of spaced second regions, the first regions intersect with the second regions, the silicon nitride layer is located in the first region, the main grid is sintered by a first slurry printed on the silicon nitride layer, the main grid is embedded in the silicon nitride layer, the sub-grid is sintered by a second slurry printed in the second region, the sub-grid forms a gold semi-contact with the silicon wafer, and the sub-grid overlaps the main grid.

[0024] Optionally, the silicon nitride layer has a thickness ranging from 0.3 μm to 5 μm.

[0025] In the manufacturing method of the solar cell and the solar cell of the embodiment of the present application, the first area of ​​the silicon wafer is provided with a silicon nitride layer, so that the first slurry printed on the silicon nitride layer is embedded in the silicon nitride layer during sintering, so that the main grid sintered by the first slurry has a higher tensile force, and then the main grid has better weldability. At the same time, there is no direct contact between the main grid and the silicon wafer, and the carriers cannot reach the metal interface, so that the recombination loss under the main grid is less. Moreover, the auxiliary grid forms a gold semi-contact with the silicon wafer and overlaps with the main grid, which can transmit the collected current to the main grid, thereby ensuring the normal operation of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the present application;

[0027] Figure 2 is a schematic structural diagram of a solar cell according to an embodiment of the present application;

[0028] Figure 3 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the present application;

[0029] Figure 4 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the present application;

[0030] Figure 5 It is a schematic diagram of the process of manufacturing a solar cell according to an embodiment of the present application.

[0031] Description of main component symbols:

[0032] Solar cell 10 , cell substrate 11 , silicon nitride layer 12 , front silicon nitride layer 121 , back silicon nitride layer 122 , main grid 13 , front main grid 131 , back main grid 132 , auxiliary grid 14 . DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0034] See also Figure 1 and Figure 2 , the method for manufacturing the solar cell 10 of the embodiment of the present application comprises:

[0035] Step S11: manufacturing a silicon wafer into a battery substrate 11 for manufacturing a circuit, wherein the battery substrate 11 includes a plurality of spaced first regions and a plurality of spaced second regions, wherein the first regions intersect with the second regions;

[0036] Step S12: preparing a silicon nitride layer 12 in the first region;

[0037] Step S13: printing a first slurry on the silicon nitride layer 12;

[0038] Step S14: printing a second slurry in the second area;

[0039] Step S15: Sintering the battery substrate 11 printed with the first slurry and the second slurry, so that the main grid 13 sintered by the first slurry is embedded in the silicon nitride layer 12, and the auxiliary grid 14 sintered by the second slurry forms a gold semi-contact with the silicon wafer, and the main grid 13 and the auxiliary grid 14 are overlapped.

[0040] The solar cell 10 of the embodiment of the present application includes: a cell substrate 11, a silicon nitride layer 12, a main grid 13 and a sub-grid 14, the cell substrate 11 is made of a silicon wafer, the cell substrate 11 includes a plurality of spaced first regions and a plurality of spaced second regions, the first regions intersect with the second regions, the silicon nitride layer 12 is located in the first region, the main grid 13 is sintered by a first slurry printed on the silicon nitride layer 12, the main grid 13 is embedded in the silicon nitride layer 12, the sub-grid 14 is sintered by a second slurry printed in the second region, and the sub-grid 14 forms a gold semi-contact with the silicon wafer.

[0041] In the method for manufacturing the solar cell 10 of the embodiment of the present application, a silicon nitride layer 12 is provided in the first area of ​​the silicon wafer, so that the first slurry printed on the silicon nitride layer 12 is embedded in the silicon nitride layer 12 during sintering, so that the main grid 13 sintered by the first slurry has a higher tensile force, and thus the main grid 13 has better weldability. At the same time, there is no direct contact between the main grid 13 and the silicon wafer, and the carriers cannot reach the metal interface, so that the recombination loss under the main grid 13 is less. Moreover, the auxiliary grid 14 forms a gold semi-contact with the silicon wafer and overlaps with the main grid 13, which can transmit the collected current to the main grid 13, thereby ensuring the normal operation of the battery.

[0042] Specifically, the first region is a region corresponding to the main grid 13. In this embodiment, one first region corresponds to one main grid 13. The orthographic projection of each main grid 13 on the battery substrate 11 is located in a corresponding first region.

[0043] It can be understood that in other embodiments, one first region may correspond to a plurality of bus bars 13. The orthographic projections of the plurality of bus bars 13 on the battery substrate 11 are located in a corresponding first region.

[0044] Specifically, the second region is a region corresponding to the auxiliary grid 14. In this embodiment, one second region corresponds to one auxiliary grid 14. The orthographic projection of each auxiliary grid 14 on the battery substrate 11 is located in a corresponding second region.

[0045] In this embodiment, the extension directions of the first regions are parallel to each other, the extension directions of the second regions are parallel to each other, and the extension direction of the first region is perpendicular to the extension direction of the second region. In this way, the auxiliary grid 14 and the main grid 13 are vertically overlapped, which is more regular and is conducive to improving production efficiency.

[0046] In this embodiment, the silicon nitride layer 12 includes a front silicon nitride layer 121 and a back silicon nitride layer 122, the main grid 13 includes a front main grid 131 and a back main grid 132, and the sub-grid includes a front sub-grid and a back sub-grid. The first region includes a front first region and a back first region. The second region includes a front second region and a back second region. The front silicon nitride layer 121 is located in the front first region, and the front main grid 131 is arranged on the side of the front silicon nitride layer 121 away from the battery substrate 11. The front sub-grid is located in the front second region. The front main grid 131 overlaps the front sub-grid. The back silicon nitride layer 122 is located in the back first region, and the back main grid 132 is arranged on the side of the back silicon nitride layer 122 away from the battery substrate 11.

[0047] In this embodiment, steps S12 to S15 are used to manufacture a front silicon nitride layer 121, a front main grid 131 and a front sub-grid on the front side of the battery substrate 11, and steps S12 to S15 are used to manufacture a back silicon nitride layer 122, a back main grid 132 and a back sub-grid on the back side of the battery substrate 11.

[0048] It can be understood that in other embodiments, steps S12-S15 can be used to manufacture the front silicon nitride layer 121, the front main grid 131 and the front sub-grid only on the front side of the battery substrate 11; steps S12-S15 can also be used to manufacture the back silicon nitride layer 122, the back main grid 132 and the back sub-grid only on the back side of the battery substrate 11.

[0049] In this embodiment, the first slurry and the second slurry are both silver slurries, so that the main grid 13 and the auxiliary grid 14 have better conductivity.

[0050] It is understood that in other embodiments, the first slurry may be aluminum slurry, copper slurry or other slurries. The second slurry may be aluminum slurry, copper slurry or other slurries. The first slurry and the second slurry may be different.

[0051] Specifically, in step S11 , the silicon wafer may be subjected to texturing treatment, diffusion treatment, laser SE treatment, etching treatment, annealing treatment, PERC treatment, PECVD treatment, etc. to manufacture the battery substrate 11 .

[0052] Specifically, in this embodiment, the burn-through capability of the second slurry is smaller than the burn-through capability of the first slurry.

[0053] In this way, the main grid 13 sintered from the first slurry is embedded deeper in the silicon nitride layer 12, so that the main grid 13 has higher tensile strength and weldability. At the same time, the auxiliary grid 14 sintered from the second slurry is embedded shallower in the battery substrate 11, which can avoid burning through the PN junction and reduce the composite loss.

[0054] Optionally, the thickness of the silicon nitride layer 12 is in the range of 0.3 μm-5 μm. For example, 0.3 μm, 0.32 μm, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 3 μm, 3.7 μm, 4 μm, 4.8 μm, 5 μm. In this way, the thickness of the silicon nitride layer 12 is within a suitable range, which can prevent the main gate 13 from passing through the silicon nitride layer 12 and contacting the silicon wafer due to the silicon nitride layer 12 being too thin, thereby reducing the composite loss under the main gate 13, and can also avoid the waste of raw materials caused by the silicon nitride layer 12 being too thick.

[0055] See also Figure 3 Optionally, step S12 includes:

[0056] Step S121: preparing a suspension of silicon nitride;

[0057] Step S122: attaching the suspension to the first area;

[0058] Step S123: baking the battery substrate 11 to which the suspension is attached;

[0059] Step S124: sintering and baking the battery substrate 11.

[0060] In this way, by baking and sintering the battery substrate 11 with the suspension attached to the first region, the silicon nitride layer 12 is prepared in the first region with high efficiency.

[0061] It is understood that in other embodiments, the silicon nitride layer 12 may also be deposited in the first region using a coating device.

[0062] Furthermore, a preset mask can be covered on the battery substrate 11, and the battery substrate covered with the mask is placed in a coating device, the first area of ​​the battery substrate 11 is exposed from the mask, and the area of ​​the battery substrate 11 except the first area is covered by the mask; SiH4 and NH3 are introduced into the coating device to deposit a silicon nitride layer 12 in the first area.

[0063] Furthermore, the coating equipment can be a plasma enhanced chemical vapor deposition (PECVD) equipment, so that the deposition speed is faster and the quality of the silicon nitride layer 12 is better.

[0064] Furthermore, before step S12, a mask may be prepared in the area other than the first area of ​​the battery substrate 11. After step S12, the mask may be removed for subsequent fabrication. In this way, the gap between the mask and the battery substrate 11 is small, and the gas is prevented from entering the area other than the first area through the gap between the mask and the battery substrate 11 during vapor deposition.

[0065] See also Figure 4 Optionally, step S121 includes:

[0066] Step S1211: Mix silicon nitride powder, polyethylene glycol and polyvinyl pyrrolidone to prepare a suspension.

[0067] In this way, the preparation of silicon nitride suspension can be achieved with high efficiency.

[0068] Specifically, the silicon nitride powder, polyethylene glycol and polyvinyl pyrrolidone can be placed in a containing tank, and the silicon nitride powder, polyethylene glycol and polyvinyl pyrrolidone placed in the containing tank are stirred, so that the silicon nitride powder, polyethylene glycol and polyvinyl pyrrolidone can be fully mixed.

[0069] Furthermore, the silicon nitride powder, polyethylene glycol and polyvinyl pyrrolidone can be placed in the containing tank at the same time; or the silicon nitride powder, polyethylene glycol and polyvinyl pyrrolidone can be placed in the containing tank in different orders. The order of placing the three is not limited here.

[0070] Specifically, the weight ratio of silicon nitride powder, polyethylene glycol, and polyvinyl pyrrolidone may be 1:(0.1-0.5):(0.1-0.5), for example, 1:0.1:0.1, 1:0.1:0.2, 1:0.1:0.3, 1:0.1:0.4, 1:0.1:0.5, 1:0.2:0.1, 1:0.3:0.1, 1:0.3:0.1, 1:0.4:0.1, 1:0.5:0.1, 1:0.4:0.3, 1:0.2:0.3.

[0071] See also Figure 5 Optionally, step S122 includes:

[0072] Step S1221: Adhere the suspension to the first area using a printing process or a spraying process.

[0073] In this way, the suspension can be efficiently and accurately attached to the first region, which is beneficial to improving production efficiency and ensuring that the silicon nitride layer 12 is located in the first region.

[0074] Specifically, the printing process may be screen printing.

[0075] Specifically, before step S122, a preset shielding member may be covered on the battery substrate 11, so that the first area is exposed from the shielding member, and the area of ​​the battery substrate 11 other than the first area is shielded by the shielding member. In this way, it can be prevented that the suspension liquid accidentally enters the area of ​​the battery substrate 11 other than the first area during the process of attaching the suspension liquid to the first area, thereby ensuring that the silicon nitride layer 12 is located in the first area.

[0076] Specifically, before step S122, a mask may be prepared on the battery substrate 11 in areas other than the first area, so that the first area is exposed from the mask, and the areas other than the first area of ​​the battery substrate 11 are covered by the mask. After step S124, the mask may be removed for subsequent production. In this way, it is possible to avoid the suspension from accidentally entering areas other than the first area of ​​the battery substrate 11 during the process of attaching the suspension to the first area, and it is also possible to avoid the suspension from entering areas other than the first area through the gap between the mask and the battery substrate 11, thereby ensuring that the silicon nitride layer 12 is located in the first area.

[0077] Specifically, after step S1221, the suspension outside the first area can be wiped or sucked away, so that the suspension outside the first area can be cleaned in time to avoid the formation of the silicon nitride layer 12 outside the first area.

[0078] Optionally, in step S123, the baking temperature ranges from 100°C to 600°C, for example, 100°C, 101°C, 105°C, 110°C, 150°C, 200°C, 280°C, 350°C, 430°C, 560°C, and 600°C. In this way, the baking temperature is within a suitable range, and adverse reactions caused by too high a baking temperature can be avoided, and insufficient baking caused by too low a baking temperature can also be avoided.

[0079] Optionally, in step S123, the range of the baking time is 10 min-30 min, such as 10 min, 11 min, 15 min, 17 min, 20 min, 22 min, 25 min, 29 min, 30 min. In this way, the baking time is within a suitable range, avoiding too long baking time leading to low efficiency, and avoiding too short baking time leading to insufficient baking.

[0080] Optionally, before step S123 , a protective gas may be introduced into the baking chamber to remove impurity gases in the baking chamber, thereby preventing the battery substrate 11 or the suspension from reacting with the impurity gases at high temperature, thereby preventing the generation of other substances that affect the preparation of the silicon nitride layer 12 .

[0081] Optionally, in step S124, the sintering temperature ranges from 700° C. to 800° C. For example, 700° C., 702° C., 715° C., 720° C., 735° C., 744° C., 750° C., 765° C., 780° C., 792° C., and 800° C. In this way, the sintering temperature is within a suitable range, and excessive energy consumption due to too high a sintering temperature is avoided, and poor sintering effect due to too low a sintering temperature is also avoided.

[0082] Optionally, in step S124, the sintering time ranges from 1 min to 5 min, such as 1 min, 1.2 min, 1.5 min, 2 min, 2.4 min, 3 min, 3.6 min, 4 min, 4.8 min, and 5 min. In this way, the sintering time is within a suitable range, avoiding the sintering time being too long and resulting in low efficiency, and avoiding the sintering effect being too short and resulting in poor effect.

[0083] Optionally, before step S124, a protective gas may be introduced into the sintering chamber to remove the impurity gas in the sintering chamber, thereby preventing the battery substrate 11 or silicon nitride from reacting with the impurity gas at high temperature, thereby preventing the generation of other substances that affect the preparation of the silicon nitride layer 12.

[0084] In this embodiment, the battery substrate 11 with the suspension attached thereto can be placed in an oven for baking. The baked battery substrate 11 can be placed in a tunnel furnace for sintering. In this way, the baking advantages of the oven and the sintering advantages of the tunnel furnace can be fully utilized, so that the baking and sintering effects are better.

[0085] In one example, the thickness of the silicon nitride layer 12 is 3 μm, the baking temperature is 500° C., the baking time is 20 min, the sintering temperature is 760° C., and the sintering time is 3 min.

[0086] It is understood that in other embodiments, baking and sintering can be performed in the same device. In this way, there is no need to frequently transfer the battery substrate 11, which is conducive to improving production efficiency. Specifically, a heating lamp can be provided in the chamber. The temperature in the chamber can be controlled by adjusting the power of the heating lamp and adjusting the number of heating lamps turned on.

[0087] Optionally, in step S13, the orthographic projection of the silicon nitride layer 12 on the battery substrate 11 covers and exceeds the orthographic projection of the printing area of ​​the first slurry on the battery substrate 11. In this way, there is a certain distance between the edge of the printing area of ​​the first slurry and the edge of the silicon nitride layer 12, so as to prevent the first slurry from flowing to the battery substrate 11 along the side of the silicon nitride layer.

[0088] In this embodiment, both printing the first slurry and printing the second slurry adopt a screen printing process.

[0089] The solar cell 10 of the embodiment of the present application is manufactured by using any of the above methods.

[0090] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for manufacturing a solar cell, characterized in that: include: The silicon wafer is made into a battery substrate for a circuit to be manufactured, wherein the battery substrate comprises a plurality of spaced first regions and a plurality of spaced second regions, wherein the first regions intersect with the second regions; Prepare a silicon nitride layer in the first region, wherein the thickness of the silicon nitride layer is in a range of 0.3 μm to 5 μm; printing a first slurry on the silicon nitride layer; printing a second paste in the second area, wherein the burn-through capability of the second paste is smaller than the burn-through capability of the first paste; Sintering the battery substrate printed with the first slurry and the second slurry, so that the main grid sintered by the first slurry is embedded in the silicon nitride layer and separated from the silicon wafer, and the auxiliary grid sintered by the second slurry forms a gold semi-contact with the silicon wafer, and the auxiliary grid overlaps the main grid; The silicon nitride layer includes a front silicon nitride layer and a back silicon nitride layer, the main gate includes a front main gate and a back main gate, and the auxiliary gate includes a front auxiliary gate and a back auxiliary gate.

2. The method for manufacturing a solar cell according to claim 1, characterized in that: Preparing a silicon nitride layer in the first region comprises: preparing a suspension of silicon nitride; attaching the suspension to the first area; Baking the battery substrate to which the suspension is attached; The battery substrate is sintered and baked.

3. The method for manufacturing a solar cell according to claim 2, characterized in that: A suspension of silicon nitride is prepared, comprising: Silicon nitride powder, polyethylene glycol and polyvinyl pyrrolidone are mixed to prepare the suspension.

4. The method for manufacturing a solar cell according to claim 2, characterized in that: The method of attaching the suspension to the first region comprises: The suspension is attached to the first area by using a printing process or a spraying process.

5. The method for manufacturing a solar cell according to claim 2, characterized in that: In the step of baking the battery substrate with the suspension attached thereto, the baking temperature ranges from 100° C. to 600° C., and / or the baking time ranges from 10 min to 30 min.

6. The method for manufacturing a solar cell according to claim 2, characterized in that: In the step of sintering and baking the battery substrate, the sintering temperature ranges from 700° C. to 800° C., and / or the sintering time ranges from 1 min to 5 min.

7. A solar cell, characterized in that: The method is prepared by any one of claims 1 to 6.

8. A solar cell, characterized in that: include: A battery substrate, a silicon nitride layer, a main grid and a secondary grid, wherein the battery substrate is made of a silicon wafer, the battery substrate comprises a plurality of spaced first regions and a plurality of spaced second regions, the first regions intersect with the second regions, the silicon nitride layer is located in the first region, the main grid is sintered by a first slurry printed on the silicon nitride layer, the main grid is embedded in the silicon nitride layer and is separated from the silicon wafer, the secondary grid is sintered by a second slurry printed in the second region, the burn-through capability of the second slurry is less than the burn-through capability of the first slurry, the secondary grid forms a gold semi-contact with the silicon wafer, and the secondary grid overlaps the main grid; the thickness of the silicon nitride layer ranges from 0.3 μm to 5 μm; wherein the silicon nitride layer comprises a front silicon nitride layer and a back silicon nitride layer, the main grid comprises a front main grid and a back main grid, and the secondary grid comprises a front secondary grid and a back secondary grid.

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