Method for modifying photoresist profile and adjusting critical dimension

Abstract

Embodiments for processing a substrate are provided, and the embodiments include a method of trimming a photoresist to provide a photoresist profile with smooth sidewall surfaces and adjusting the critical dimensions of patterned features and / or subsequently deposited dielectric layers. The method can include: depositing a sacrificial structure layer on a substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a rough photoresist profile on the sacrificial structure layer. The method further includes: trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while exposing a second portion of the sacrificial structure layer; etching the second portion of the sacrificial structure layer to form a patterned feature disposed on the substrate; and depositing a dielectric layer on the patterned feature.

Description

[0001] Background

[0002] Field

[0003] Embodiments of the present disclosure generally relate to methods for semiconductor processing. In particular, embodiments of the present disclosure relate to methods for trimming a photoresist layer and depositing a conformal dielectric film.

[0004] Description of Related Art

[0005] Dielectric layers have been used in applications such as barrier layers or spacers in the manufacture of modern semiconductor devices. Dielectric layers can be deposited over features (e.g., trenches or vias) in a patterned substrate using deposition processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Subsequently, the dielectric layer is etched anisotropically to form spacers on either side of the feature. While methods of depositing spacers using the ALD process can provide a conformal layer over the feature due to the self-limiting nature of the ALD process, it is challenging to form a highly conformal dielectric layer across a patterned substrate and a blanket substrate at zero pattern load using the CVD process due to the associated reaction mechanisms.

[0006] As features are scaled, due to the limitations of 193 immersion lithography, achieving desired critical dimension (CD) targets can be challenging. To achieve CD targets and desired profiles, multi-patterning techniques such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) are used for various applications to build state-of-the-art semiconductor devices. Photoresist (PR) patterning can be accomplished in a variety of ways. In the traditional process recording (POR) method, lithography-etch-lithography-etch (LELE) or lithography-freeze-lithography-etch (LFLE) can be used to transfer the pattern to the underlying hard mask. In other methods, self-aligned multi-patterning processes are used, where the hard mask is patterned with PR and conformal spacers are deposited on the photoresist or spinon carbon, commonly referred to as mandrels. Self-aligned multi-patterning techniques are cost-effective compared to traditional patterning techniques since the lithography step, which is an expensive step in the manufacture of semiconductor devices, is eliminated.

[0007] During PR exposure and development, the PR profile is not smooth along the sidewalls and is generally very wavy and rough. This non-smooth profile transfers to subsequently deposited films, such as the deposition of conformal spacers. That is, the conformal spacers will follow the same shape or profile as the underlying PR layer and adopt a similar wavy and rough surface. After spacer etch-back and PR mandrel removal, the spacer sidewalls will also be very rough, and the transferable pattern will cause many CD variations and linewidth roughness issues in the device.

[0008] Accordingly, a method for trimming a photoresist is needed to provide a profile with a modified smooth surface and adjust the critical dimensions. There is also a need to deposit a dielectric layer in high aspect ratio trenches with a reduced pattern loading. SUMMARY OF THE INVENTION

[0009] An embodiment for processing a substrate is provided, and the embodiment includes a method for trimming a photoresist to provide a photoresist profile with a smooth sidewall surface and adjust or modulate the critical dimensions (CDs) of patterned features and / or subsequently deposited dielectric layers.

[0010] In one or more embodiments, the method includes: depositing a sacrificial structure layer on a substrate; depositing a photoresist on the sacrificial structure layer; and patterning the photoresist to create a rough photoresist profile on the sacrificial structure layer. The method further includes: trimming the photoresist with a plasma to create a refined photoresist profile covering a first portion of the sacrificial structure layer while exposing a second portion of the sacrificial structure layer; etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate; and depositing a dielectric layer on the patterned features. In some embodiments, the refined photoresist profile has a linewidth roughness of about to about and a line edge roughness of about to about In other embodiments, trimming of the photoresist and deposition of the dielectric layer can occur in the same processing chamber, such as a PE-CVD chamber. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the present disclosure, briefly summarized above and discussed in more detail below, can be understood by reference to the illustrative embodiments of the present disclosure depicted in the drawings. However, it should be noted that the drawings only show typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure, as the present disclosure may permit other equivalent embodiments.

[0012] Figure 1 A schematic diagram depicting a substrate processing system that can be used to perform the method according to one or more embodiments described and discussed herein.

[0013] Figure 2 A flowchart depicting a process associated with an exemplary self-aligned double patterning (SADP) process according to one or more embodiments described and discussed herein.

[0014] Figures 3A to 3G Shows a cross-sectional view of structures formed at different pitches by the Figure 2 process depicted according to one or more embodiments described and discussed herein.

[0015] For purposes of facilitating understanding, the same reference numerals are used to denote the same elements common to the figures where possible. The figures are not drawn to scale and may be simplified for clarity. Elements and features conceived of in one embodiment may be advantageously incorporated into other embodiments without further recitation. Detailed Description

[0016] Embodiments for processing a substrate are provided, and the embodiments include methods of trimming a photoresist to provide a photoresist profile with smooth sidewall surfaces and adjusting or modulating the critical dimension (CD) of patterned features and / or a subsequently deposited dielectric layer. The method can include: depositing a sacrificial structure layer on a substrate; depositing a photoresist on the sacrificial structure layer; and patterning the photoresist to produce a rough photoresist profile on the sacrificial structure layer. The method further includes: trimming the photoresist with a plasma to produce a first refined photoresist profile covering a first portion of the sacrificial structure layer while exposing a second portion of the sacrificial structure layer; etching the second portion of the sacrificial structure layer to form a patterned feature disposed on the substrate; and depositing a dielectric layer on the patterned feature. In some examples, trimming of the photoresist and deposition of the dielectric layer occur in the same processing chamber, such as a plasma enhanced chemical vapor deposition (PE-CVD) chamber.

[0017] Exemplary systems and / or chambers that can be used to practice the embodiments of the present disclosure can include any suitable thin film deposition system. Examples of suitable systems include: System, The system can use DxZ TM Processing chamber, PRODUCER HARP TM Processing chamber, PRECISION System, PRODUCER TM System, PRODUCER GT TM Processing chamber, PRODUCER SE TM Processing chamber, PRODUCER TM CVD processing chamber, PRODUCER SACVD TM Processing chamber, and XP PRECISION TM A CVD processing chamber, and the above-described chamber and system are available from Applied Materials, Inc. of Santa Clara, California. Other tools capable of performing a PE-CVD process can also be adapted to benefit from the embodiments described herein. Additionally, any system capable of advantageously implementing the PE-CVD process described herein can be used. In one or more embodiments, a remote plasma system (RPS) can be in fluid communication with any processing chamber and used during the methods described and discussed herein. The device descriptions provided herein are illustrative and should not be construed or interpreted as limiting the scope of the embodiments described herein. The process can be performed on any substrate, such as a 200 mm, 300 mm, or 450 mm substrate or other media suitable for semiconductor processing.

[0018] Figure 1 A schematic diagram of a substrate processing system 132 is depicted, and the substrate processing system 132 can be used to perform the methods according to the embodiments described and discussed herein. The substrate processing system 132 includes a processing chamber 100 coupled to a gas panel 130 and a controller 110. The processing chamber 100 generally includes a top 124, sides 101, and a bottom wall 122 that define an internal processing space 126. A support pedestal 150 for supporting a substrate 190 is positioned within the internal processing space 126 of the processing chamber 100. The support pedestal 150 is supported by a spindle 160 and can be made of aluminum, ceramic, and other suitable materials such as stainless steel. A displacement mechanism (not shown) can be used to move the support pedestal 150 vertically within the processing chamber 100.

[0019] The support pedestal 150 can include an embedded heater element 170 that is adapted to control the temperature of the substrate 190 supported on the surface 192 of the support pedestal 150. The support pedestal 150 can be resistively heated by applying an electric current from a power supply 106 to the embedded heater element 170. The current supplied from the power supply 106 is regulated by the controller 110 to control the heat generated by the embedded heater element 170, thereby maintaining the substrate 190 and the support pedestal 150 at a substantially constant temperature during film deposition. The supplied current can be adjusted to selectively control the temperature of the support pedestal 150.

[0020] The temperature of the support base 150 can be: about 30 °C, about 40 °C, about 50 °C, about 80 °C, about 100 °C, about 150 °C, about 200 °C, about 250 °C, about 300 °C, or about 400 °C, up to about 450 °C, about 500 °C, about 600 °C, about 700 °C, about 800 °C, or about 1,000 °C. For example, the temperature of the support base can be: about 30 °C to about 1,000 °C, about 50 °C to about 1,000 °C, about 50 °C to about 800 °C, about 50 °C to about 700 °C, about 50 °C to about 600 °C, about 50 °C to about 550 °C, about 50 °C to about 500 °C, about 50 °C to about 400 °C, about 100 °C to about 1,000 °C, about 100 °C to about 800 °C, about 100 °C to about 700 °C, about 100 °C to about 600 °C, about 100 °C to about 550 °C, about 100 °C to about 500 °C, about 100 °C to about 400 °C, about 200 °C to about 1,000 °C, about 200 °C to about 800 °C, about 200 °C to about 700 °C, about 200 °C to about 600 °C, about 200 °C to about 550 °C, about 200 °C to about 500 °C, about 200 °C to about 400 °C, about 400 °C to about 1,000 °C, about 400 °C to about 800 °C, about 400 °C to about 700 °C, about 400 °C to about 600 °C, or about 400 °C to about 500 °C.

[0021] A temperature sensor 172, such as a thermocouple, can be embedded in the support base 150 to monitor the temperature of the support base 150. The controller 110 uses the measured temperature to control the power supplied to the embedded heater element 170 to maintain the substrate 190 at a desired temperature.

[0022] A vacuum pump 102 is coupled to a port formed in the bottom of the processing chamber 100. The vacuum pump 102 is used to maintain a desired gas pressure in the processing chamber 100. The vacuum pump 102 also evacuates post - processing gases and processing by - products from the processing chamber 100.

[0023] A gas distribution assembly 120 having a plurality of apertures 128 is disposed above the support base 150 at the top of the processing chamber 100. The apertures 128 can have different sizes, numbers, distributions, shapes, designs, and diameters to facilitate the inflow of various processing gases into the processing chamber 100. The gas distribution assembly 120 is connected to a gas panel 130, which allows various gases to be supplied into the internal processing space 126 during the process. A plasma is formed from the processing gas mixture exiting the gas distribution assembly 120 to enhance the thermal decomposition of the processing gas, causing material deposition on the surface 191 of the substrate 190.

[0024] The gas distribution assembly 120 and the support base 150 can form a pair of spaced-apart electrodes within the internal processing space 126. One or more RF power supplies 140 can provide a biasing potential to the gas distribution assembly 120 through a matching network 138 to facilitate the generation of a plasma between the gas distribution assembly 120 and the support base 150. Alternatively, the RF power supply 140 and the matching network 138 can be coupled to the gas distribution assembly 120, the support base 150, or both the gas distribution assembly 120 and the support base 150, or to an antenna (not shown) disposed outside the processing chamber 100. In one or more embodiments, the RF power supply 140 is capable of providing power in the range from about 10 watts to about 3,000 watts at a frequency from about 50 kHz to about 13.6 MHz. In other embodiments, the RF power supply 140 is capable of providing power in the range from about 500 watts to about 1,800 watts at a frequency from about 50 kHz to about 13.6 MHz.

[0025] The controller 110 includes a central processing unit (CPU) 112, a memory 116, and support circuitry 114 for controlling process sequences and regulating the gas flow from the gas panel 130. The CPU 112 can be any form of general-purpose computer processor usable in an industrial setting. Software routines can be stored in the memory 116, such as random access memory, read-only memory, floppy disk, or hard disk drive, or other forms of digital storage. The support circuitry 114 is coupled to the CPU 112 in a conventional manner and can include a cache, clock circuits, input / output systems, power supplies, and the like. Bidirectional communication between the controller 110 and the various components of the substrate processing system 132 is handled through a number of signal cables collectively referred to as the signal bus 118.

[0026] Figure 2 is a flowchart of a process 200 related to an exemplary self-aligned double patterning (SADP) process in accordance with embodiments of the present disclosure. Figures 3A to 3G is shown by Figure 2 a cross-sectional view of a structure formed by the process 200 depicted in. For illustrative purposes, the self-aligned double patterning process is selected, and variations are contemplated. The concepts of the present disclosure are equally applicable to other deposition processes or patterning schemes, such as self-aligned triple patterning (SATP) processes, self-aligned quadruple patterning (SAQP) processes, via / hole shrink processes, back-end-of-line (BEOL), or any combination of the above processes, which may use protective spacers or protective sacrificial layers according to the needs of various semiconductor processes, such as NAND flash applications, DRAM applications, or CMOS applications.

[0027] As Figure 3AAs shown, process 200 begins with the formation of a sacrificial structure layer 320 on a substrate 300. The sacrificial structure layer 320 has an upper surface 323. The sacrificial structure layer 320 can be a silicon-based material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or polysilicon. The material selection contemplated for the sacrificial structure layer 320 can vary depending on the etch / ash rate relative to the resist layer to be formed on the material.

[0028] Although the substrate 300 is shown as a single body, the substrate 300 can contain one or more materials for forming semiconductor devices such as metal contacts, trench isolation, gates, bit lines, or any other interconnect features. The substrate 300 can be a material stack or layer stack, including one or more of the following: crystalline silicon, silicon oxide, silicon oxynitride, silicon nitride, strained silicon, silicon germanium, tungsten, titanium nitride, doped or undoped polysilicon, doped or undoped silicon wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, germanium, gallium arsenide, glass, sapphire, low-k dielectrics, and any combination of the foregoing. In embodiments where a memory application is desired, the substrate 300 can include a silicon substrate material, an oxide material, and a nitride material, with or without polysilicon sandwiched therebetween.

[0029] At block 204, a photoresist layer 330 (such as a photoresist material) is deposited on a portion of the upper surface 323 of the sacrificial structure layer 320, and the photoresist layer 330 is patterned at a desired pitch, as Figure 3B depicted. The surface 331 of the photoresist layer 330 (such as the sidewalls between each of the segments of the photoresist layer 330) is typically very rough, wavy, or otherwise uneven after being etched.

[0030] At block 206, the photoresist layer 330 is trimmed by a plasma process to modify the photoresist profile and modulate the critical dimension (CD). Once trimmed, the photoresist layer 330 has a smooth, straight, or otherwise flat surface 332, such as the sidewalls of each of the segments of the photoresist layer 330, as Figure 3C depicted. The upper surface 323 of the sacrificial structure layer 320 extends between adjacent surfaces 332 and extends to the outer edge of the substrate 300. The plasma process can be performed in the same plasma-enhanced CVD (PE-CVD) chamber as any other deposition process described and discussed herein.

[0031] Plasma is generated in a continuous mode by using various sources such as radio frequency (RF), microwave, ECR, or a combination of the foregoing, and the plasma process can be or include capacitively coupled plasma (CCP) or inductively coupled plasma (ICP). The plasma source can be continuous plasma or pulsed plasma. Plasma can be generated at a frequency of about 100 kHz to about 2.4 GHz and a power of about 10 watts to about 1,000 watts. The duty cycle of the plasma can be about 3% to 100%. The processing chamber can have an internal chamber pressure of about 10 mTorr to about 50 Torr. One or more process gases and / or carrier gases can be activated by the plasma and exposed to the photoresist layer 330 during the trimming process. Exemplary process gases can be or include: hydrogen (H2), ammonia (NH3), hydrazine (N2H4), nitrous oxide (N2O), oxygen (O2), one or more hydrocarbons (e.g., methane (CH4), ethylene (C2H4), acetylene (C2H2)), nitrogen trifluoride (NF3), chlorine (Cl2), nitrogen (N2), carbon dioxide (CO2), carbon monoxide (CO), water or water vapor (H2O), ions of the foregoing, plasmas of the foregoing, or any combination of the foregoing. Exemplary carrier gases can be or include argon (Ar), helium (He), neon (Ne), nitrogen (N2), or any combination of the foregoing gases.

[0032] In one or more examples, a photoresist (PR) layer having an uneven (e.g., wavy or rough) PR profile with a mushroom head can be trimmed to have a straight or slightly tapered PR profile. In some examples, the plasma process for trimming the PR can be performed under the following conditions: the internal chamber pressure is about 5 Torr, the plasma is RF CCP with a frequency of about 13.56 MHz, the plasma power is about 200 watts, and the plasma duty cycle is about 20%. In other examples, the plasma process for trimming the PR can be performed under the following conditions: the internal chamber pressure is about 0.5 Torr, the plasma is RF ICP with a frequency of about 2.4 GHz, the plasma power is about 500 watts, and the plasma duty cycle is about 100%.

[0033] During the plasma process, the PR profile is modulated and the desired CD is achieved. Adjustment of the PR trimming profile helps to improve the line width roughness and line edge roughness on the surface 332. In one or more embodiments, each of the line width roughness and line edge roughness on the surface 332 can independently be about about or about to about about or about For example, each of the line width roughness and line edge roughness on the surface 332 can independently be from about to about about to about about to about about to about about to about about to about about to about about to about about to about about to about or from about to about This profile adjustment helps to implement the spacer-on-spacer multiple patterning technique on next-generation front-end semiconductor devices.

[0034] In one or more embodiments, at block 208, one or more suitable lithography and etching processes are performed by using the photoresist layer 330 as a mask to form the patterned feature 321 from the sacrificial structure layer 320 on the substrate 300. The patterned feature 321 can have an aspect ratio of from about 1:1 to about 50:1, such as from about 2:1 to about 20:1, from about 3:1 to about 10:1, or from about 4:1 to about 8:1. In the present disclosure, the term "aspect ratio" refers to the ratio of the height dimension to the width dimension of the patterned feature.

[0035] The patterned feature 321 on the substrate 300 provides the patterned region 301, while the open region without the patterned feature 321 provides the blank region 303, as Figure 3D shown. The patterned feature 321 can be used to form, for example, a gate stack or an interconnect such as a via or a trench. The patterned feature 321 is sometimes referred to as a placeholder, a mandrel, or a core, and has a specific line width and / or pitch based on the photoresist material used. The width of the patterned feature 321 can be adjusted by subjecting the photoresist layer 330 to a trimming process. After the pattern has been transferred into the sacrificial structure layer 320, any remaining photoresist and hard mask material (if used) are removed using a suitable photoresist stripping process.

[0036] In other embodiments, the lithography and etching processes at block 208 can be omitted, and one or more dielectric layers can be deposited conformally directly on and over a photoresist layer 330 that forms patterned features (not shown). These patterned features can have an aspect ratio of from about 1:1 to about 50:1, such as from about 3:1 to about 10:1.

[0037] At block 210, a dielectric layer 340 is deposited conformally on the patterned features 321 (patterned region 301) and the exposed upper surface 325 (blank region 303) of the substrate 300, as Figure 3E shown. When the dielectric layer 340 is deposited using the improved process conditions to be discussed below, the dielectric layer 340 will achieve good step coverage with substantially zero pattern loading on the surface of the substrate 300. For example, the percentage of film thickness between different surfaces with characteristic differences is less than 3%. Generally, for a thermal CVD process, the pattern loading is high, and the deposited layer in the blank region is usually thicker compared to the region with densely packed patterned features. This is partly due to the difference in the exposed surface area of the substrate and the mass-dominated reaction related to the reactant supply. The patterned region (e.g., patterned region 301) has a larger deposition surface than the open or blank region (e.g., blank region 303) on which the dielectric layer 340 is deposited. In some cases, the patterned region 301 can have an exposed vertical surface with a multiplicative factor greater than 2 larger than that of the blank region 303, such as about 3, about 4, about 5, about 8, about 10, about 15, about 20, or greater. The difference in the exposed surface area of the substrate can cause the deposition rate to vary between the patterned region 301 and the blank region 303.

[0038] In a spacer application, since the feature CD is determined by the thickness of the spacer, the pattern loading can cause CD differences at different positions. The improved process conditions of the present disclosure allow the dielectric layer 340 to be deposited on the patterned region 301 and the blank region 303 of the substrate 300 at substantially the same deposition / reactivity rate. Since the deposition / reactivity rate is the same for both the patterned region 301 and the blank region 303, the variation in film thickness between these regions is zero or can be reduced to a minimum. Thus, the dielectric layer 340 can be formed conformally or otherwise deposited on the patterned region 301 and the blank region 303 with zero pattern loading.

[0039] Dielectric layer 340 that can benefit from the present disclosure includes a silicon-containing dielectric material, such as silicon oxide, silicon oxynitride, or silicon nitride. The dielectric layer 340 can be carbon-doped, hydrogen-doped, and / or contain other compounds or elements (such as n-type or p-type dopants) to customize the properties of the film. In some embodiments, the dielectric layer 340 can be a carbon-based material, such as an amorphous carbon (a-C) layer.

[0040] Deposition of the dielectric layer 340 is performed in a processing chamber by exposing the substrate to deposition precursors at a low temperature. In some embodiments, during the deposition of the dielectric layer 340, an adjustment gas that is a chemical reaction byproduct in the deposition process of the dielectric layer 340 flows synchronously with the deposition precursors (e.g., co-flow mode). During the deposition process, there is no plasma excitation in the substrate processing region. Depending on the application, the deposition precursor can be one or more of any suitable precursors. In embodiments where a silicon-containing dielectric material is desired, the deposition precursor can include a silicon-containing precursor. The processing chamber can be a CVD chamber or any suitable heat treatment chamber.

[0041] Suitable silicon-containing precursors can include silane, halogenated silane, organosilane, and any combination of the foregoing. Silane can include silane (SiH4) and higher silanes with the empirical formula Si x H (2x+2) (such as disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H 10 ), or other higher-order silanes), one or more chlorosilanes (such as polysilane), or any combination of the foregoing. Other silicon-containing precursors can also be used, such as octamethylcyclotetrasiloxane (OMCTS), methyldiethoxysilane (MDEOS), bis(tert-butylamino)silane (BTBAS), tris(dimethylamino)silane (TrisDMAS), tetrakis(dimethylamino)silane (TetraDMAS), tris(diethylamino)silane (TrisDEAS), tetrakis(diethylamino)silane (TetraDEAS), dichlorosilane, trichlorosilane, dibromosilane, silicon tetrachloride, silicon tetrabromide, or a combination of the foregoing, or an organosilicon compound with an oxygen atom to silicon atom ratio of 0 to about 6. Suitable organosilicon compounds can be siloxane compounds, halogenated siloxane compounds including one or more halogen moieties (e.g., fluoride, chloride, bromide, or iodide) (such as tetrachlorosilane, dichlorodiethoxysilane, chlorotriethoxysilane, hexachlorodisiloxane, and / or octachlorotrisiloxane), and aminosilanes, such as trimethylsilylamine (TSA), hexamethyldisilazane (HMDS), silatrane, tetrakis(dimethylamino)silane, bis(diethylamino)silane, tris(dimethylamino)chlorosilane, methylsilazane, or any combination of the foregoing.

[0042] In an embodiment where the dielectric layer 340 is a carbon-based material, the deposition precursor can be a carbon-containing precursor, such as a hydrocarbon compound. The hydrocarbon compound can be a partially or fully doped derivative of the hydrocarbon compound, including fluorine-containing, oxygen-containing, hydroxyl-containing, and boron-containing derivatives of the hydrocarbon compound. Suitable hydrocarbon compounds can include one or more of the following compounds, for example: alkanes, such as methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10 ) and its isomer isobutane, pentane (C5H 12 ) and its isomers isopentane and neopentane, hexane (C6H 14 ) and its isomers 2-methylpentane, 3-methylpentane, 2,3-dimethylbutane, and 2,2-dimethylbutane, isomers of the foregoing, derivatives of the foregoing, or any combination of the foregoing. Other suitable hydrocarbons can include: alkenes, such as ethylene, propylene, butene and its isomers, pentene and its isomers, etc.; dienes, such as butadiene, isoprene, pentadiene, hexadiene, etc.; and halogenated alkenes, including vinyl fluoride, vinylidene fluoride, trifluoroethylene, tetrafluoroethylene, vinyl chloride, dichloroethylene, trichloroethylene, tetrachloroethylene, etc. Similarly, alkynes such as acetylene (C2H2), propyne (C3H4), butyne (C4H6), vinylacetylene, and derivatives of the foregoing can be used as carbon precursors. Other cyclic hydrocarbons can be used, such as benzene, styrene, toluene, xylene, ethylbenzene, acetophenone, methyl benzoate, phenyl acetate, phenylacetylene (C8H6), phenol, cresol, furan, α-terpinene, cymene, 1,1,3,3-tetramethylbutylbenzene, tert-butyl ether, tert-butyl ethylene, methyl methacrylate, and tert-butylfurfuryl ether, compounds or radicals having the chemical formula C3H2 and / or C5H4, halogenated aromatic compounds, including monofluorobenzene, difluorobenzene, tetrafluorobenzene, hexafluorobenzene, and the like. Halogenated hydrocarbons can also be used, such as carbon tetrachloride (CCl4), diiodomethane (CH2I2), one or more chlorofluorocarbons (CFCs), bromotrichloromethane (BrCCl3), 1,1-dichloroethylene, bromobenzene, or derivatives of the foregoing.

[0043] As discussed above, the conditioning gas is a chemical reaction by-product in the deposition process of the dielectric layer 340. Therefore, the conditioning gas is selected depending on the deposition process and the chemicals used for the deposition precursor. The conditioning gas may or may not participate in the chemical reaction. In an embodiment where the deposition precursor is a silicon-containing precursor using silane, the substrate is exposed to the deposition precursor and the conditioning gas, and the deposition precursor is reacted to form a chemical reaction by-product. In this case, the chemical reaction by-product is the same as the conditioning gas. For example, in the exemplary reaction of SiH4 + 2O2 → SiO2 + 2H2O, the products are SiO2 and water (H2O), and the by-products may include hydrogen gas (H2). In this case, the conditioning gas may be hydrogen gas or include hydrogen gas.

[0044] In an embodiment where the deposition precursor is a silicon-containing precursor or includes a silicon-containing precursor, the flow rate of the silicon-containing precursor is controlled to provide a partial pressure of the silicon-containing precursor in the processing chamber. The partial pressure of the deposition precursor in the processing chamber is an indicator of the concentration of the reacted precursor at or near the substrate surface. In an embodiment using a 300 mm substrate, the silicon-containing precursor may be provided at a flow rate of about 10 sccm to about 10,000 sccm, such as about 20 sccm to about 5,000 sccm, for example about 50 sccm to about 2,000 sccm. The flow rate can be adjusted such that the partial pressure of the silicon-containing precursor is controlled within a range from about 10 Torr to about 100 Torr, for example about 20 Torr to about 90 Torr, about 40 Torr to about 80 Torr, or about 40 Torr to about 60 Torr. The partial pressure of the silicon-containing precursor can be greater (e.g., 100 Torr or higher), as long as the partial pressure of the silicon-containing precursor does not negatively affect the mean free path length of the gas molecules and thus affect the diffusion rate of the precursor into the trenches between the patterned features 321.

[0045] Similarly, the flow rate of the conditioning gas is controlled to provide a partial pressure of the conditioning gas in the processing chamber. The conditioning gas can be provided at a flow rate approximately the same as that of the deposition precursor. The flow rate can be adjusted such that the partial pressure of the conditioning gas is controlled within a range of about 10 Torr to about 100 Torr, for example about 20 Torr to about 90 Torr, about 40 Torr to about 80 Torr, or about 40 Torr to about 60 Torr. In various embodiments where the silicon-containing precursor and the conditioning gas co-flow into the processing chamber, the conditioning gas and the silicon-containing precursor can be provided at a volume flow ratio (conditioning gas: silicon-containing precursor) of about 1:2 to about 1:6 (e.g., about 1:4).

[0046] In some embodiments, no carrier gas / inert gas is used during the deposition process. In this case, the chamber pressure can be substantially equal to the partial pressure of the silicon-containing precursor, or the combined pressure of the deposition precursor and the conditioning gas. In either case, the flow rate of the precursor / conditioning gas and the increased partial pressure enable the precursor / gas to diffuse or penetrate into the bottom of the trenches between the patterned features 321.

[0047] In some cases, a carrier gas can be used to carry the silicon-containing precursor to the processing chamber. In some cases, an inert gas can be used to help maintain the processing chamber at a specific pressure. In some cases, a dilution gas can be used to control the density and deposition rate of the dielectric layer 340. Suitable carrier / inert / dilution gases can include: helium, argon, hydrogen (H2), ammonia, nitrogen (N2), krypton, xenon, or any combination of the foregoing. In some cases, a p-type or n-type dopant gas such as diborane (B2H6), phosphine (PH3), arsine (AsH3), or any combination of the foregoing can be used during the deposition process. In any case, a combination of the precursor (e.g., deposition gas and conditioning gas) with the carrier / inert / dilution gas or dopant gas can be used to set the total pressure of the processing chamber.

[0048] The total pressure can be: about 20 Torr, about 30 Torr, about 50 Torr, about 80 Torr, or about 100 Torr, up to about 150 Torr, about 200 Torr, about 250 Torr, about 300 Torr, about 400 Torr, about 500 Torr, about 600 Torr, or greater. For example, the total pressure can be in the range of: about 20 Torr to about 600 Torr, about 20 Torr to about 500 Torr, about 20 Torr to about 400 Torr, about 20 Torr to about 300 Torr, about 20 Torr to about 200 Torr, about 20 Torr to about 100 Torr, about 20 Torr to about 50 Torr, about 50 Torr to about 600 Torr, about 50 Torr to about 500 Torr, about 50 Torr to about 400 Torr, about 50 Torr to about 300 Torr, about 50 Torr to about 200 Torr, about 50 Torr to about 100 Torr, about 50 Torr to about 80 Torr, about 100 Torr to about 600 Torr, about 100 Torr to about 500 Torr, about 100 Torr to about 400 Torr, about 100 Torr to about 300 Torr, about 100 Torr to about 200 Torr, or about 100 Torr to about 150 Torr.

[0049] During the deposition process, the substrate 300 can be maintained at a temperature of about 550 °C or lower, such as about 500 °C or lower, such as about 250 °C to about 480 °C. In one or more examples, the substrate 300 is maintained at a temperature of about 350 °C to about 450 °C. The substrate 300 can be spaced from the nozzle panel by about 50 mils, about 80 mils, or about 100 mils, up to about 120 mils, about 150 mils, about 200 mils, about 250 mils, or about 300 mils, where the precursor and / or gas enter the processing chamber at the nozzle panel. When the precursor / adjusting gas is maintained at a constant flow rate, the spacing between the substrate and the nozzle panel can be controlled to increase the gas velocity, which in turn helps the diffusion of the precursor to the bottom of the trench between the patterned features 321. In one or more embodiments, the flow rate and the spacing can be controlled such that the precursor / adjusting gas flows at a rate of about 0.1 L / min to 1 L / min. In either case, the partial pressure, the substrate temperature, and the flow parameters can be adjusted such that the dielectric layer 340 is deposited at a rate of about to about such as about to about .

[0050] The deposited dielectric layer 340 can have a thickness of about about about or about to about about about about about about or about For example, the deposited dielectric layer 340 can have a thickness of about to about about to about about to about about to about about to about about to about about to about about to about about to about about to about about to about about to about about to about about to about about to about about to about about to about about to about about to about or about to about

[0051] Note that the process conditions described herein can be modified to handle substrates of different sizes. The above process conditions can be applied to other deposition precursors such as carbon-containing precursors, or can be modified according to the material of the dielectric layer 340. Those of ordinary skill in the art can modify the flow rate and / or other parameters to deposit the desired dielectric layer.

[0052] An increased partial pressure of one or more deposition precursors and a conditioning gas allows the deposition process to be carried out in a saturation regime, which means that the deposition precursors and the conditioning gas are provided in an amount that exceeds the amount required for the deposition reaction to occur at the patterned region 301 and the blank region 303. In one or more embodiments, the deposition precursors and the conditioning gas are provided in an amount that is at least 20% or more, such as about 50% to about 300% greater than the amount of the deposition precursors and the conditioning gas that can be consumed at the patterned region 301 and the blank region 303. In other words, the patterned region 301 and the blank region 303 are exposed to an excess of the deposition precursors and the conditioning gas. Without being bound by any particular theory, since the supply of the deposition precursors and the conditioning gas is much higher than the consumption of the precursors in both the patterned region 301 and the blank region 303, the saturation regime can cause a reduction in the thickness difference between the patterned region 301 and the blank region 303. Since at a given temperature, a higher concentration of the deposition precursors can lead to an increase in the deposition rate, and a higher concentration of the conditioning gas (e.g., a chemical reaction byproduct of the deposition process) can lead to a decrease in the deposition rate, the saturation regime will allow the concentration of the deposition precursors and the concentration of the conditioning gas to be maintained at the same level over the patterned region 301 and the blank region 303. Therefore, the deposition rate between the patterned region 301 and the blank region 303 will be substantially the same, thereby achieving a reduced or substantially zero pattern loading for the thermal CVD process.

[0053] At block 212, after conformally depositing dielectric layer 340 on patterned feature 321 using the improved deposition process discussed at block 210, a portion of dielectric layer 340 is anisotropically etched (vertically etched) such that dielectric layer 340 (or at least a portion of dielectric layer 340) remains on the sidewalls of patterned feature 321. In particular, the dielectric layer 340 on the upper surface 327 of patterned feature 321 and the dielectric layer 340 on the exposed surface of substrate 300 (e.g., blank area 303) are removed to expose upper surface 327 of patterned feature 321 and upper surface 325 of substrate 300. Thus, the remaining dielectric layer 340 forms sidewall spacer 341 and protects the sidewalls of patterned feature 321, as Figure 3F shown. Due to the improved deposition process of dielectric layer 340, the formed sidewall spacer 341 can have a uniform thickness on the substrate surface and provide a constant CD for multi-patterning applications.

[0054] At block 214, patterned feature 321 is removed using a plasma etching process or other suitable wet stripping process, leaving sidewall spacer 341 disposed on upper surface 325 of substrate 300, as Figure 3G shown. The plasma etching process can be performed by contacting substrate 300 with a plasma generated from a fluorine-based etching chemistry to remove patterned feature 321. The etching chemistry is selective such that sidewall spacer 341 is not damaged during the etching / stripping process. When removing patterned feature 321, sidewall spacer 341 can act as a hard mask for etching underlying layers, layer stacks, or structures.

[0055] In summary, embodiments of the present disclosure provide methods for processing substrates. In one or more embodiments, a method is provided that includes trimming a photoresist to provide a photoresist profile with smooth sidewall surfaces and adjusting or modulating the critical dimension (CD) of a patterned feature and / or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on a substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a rough photoresist profile on the sacrificial structure layer. The method further includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while exposing a second portion of the sacrificial structure layer, etching the second portion of the sacrificial structure layer to form a patterned feature disposed on the substrate, and depositing a dielectric layer on the patterned feature. In some examples, trimming the photoresist and depositing the dielectric layer occur in the same processing chamber, such as a PE-CVD chamber.

[0056] Embodiments of the present disclosure further relate to any one or more of paragraphs 1-16 below:

[0057] 1. A method for processing a substrate, comprising: depositing a sacrificial structure layer on the substrate; depositing a photoresist on the sacrificial structure layer; patterning the photoresist to create a rough photoresist profile on the sacrificial structure layer; trimming the photoresist with a plasma to create a refined photoresist profile that covers a first portion of the sacrificial structure layer while exposing a second portion of the sacrificial structure layer; etching the second portion of the sacrificial structure layer to form a patterned feature disposed on the substrate; and depositing a dielectric layer on the patterned feature.

[0058] 2. A method for processing a substrate, comprising: depositing a sacrificial structure layer on the substrate; depositing a photoresist on the sacrificial structure layer; patterning the photoresist to create a rough photoresist profile on the sacrificial structure layer; trimming the photoresist with a plasma to create a refined photoresist profile that covers a first portion of the sacrificial structure layer while exposing a second portion of the sacrificial structure layer, wherein the refined photoresist profile has a line width roughness of about to about and a line edge roughness of about to about ; etching the second portion of the sacrificial structure layer to form a patterned feature disposed on the substrate; and depositing a dielectric layer on the patterned feature, wherein trimming the photoresist and depositing the dielectric layer occur in the same processing chamber.

[0059] 3. A method for processing a substrate, comprising: depositing a sacrificial structure layer on the substrate; depositing a photoresist on the sacrificial structure layer; patterning the photoresist to create a rough photoresist profile on the sacrificial structure layer; trimming the photoresist with a plasma to create a refined photoresist profile that covers a first portion of the sacrificial structure layer while exposing a second portion of the sacrificial structure layer, wherein the refined photoresist profile has a line width roughness of about to about and a line edge roughness of about to about ; etching the second portion of the sacrificial structure layer to form a patterned feature disposed on the substrate; removing the photoresist from the patterned feature; and depositing a dielectric layer on the patterned feature.

[0060] 4. The method according to any one of paragraphs 1 to 3, wherein the refined photoresist profile comprises sidewall surfaces that are smoother or less wavy than the sidewall surfaces of the rough photoresist profile.

[0061] 5. The method according to any one of paragraphs 1 to 4, wherein trimming the photoresist further comprises: modulating the critical dimension of the patterned feature or a subsequently deposited dielectric layer.

[0062] 6. The method according to any one of paragraphs 1 to 5, wherein the refined photoresist profile has a line width roughness of about to about Line width roughness.

[0063] 7. The method according to any one of paragraphs 1 to 6, wherein the refined photoresist profile has about to about line edge roughness.

[0064] 8. The method according to any one of paragraphs 1 to 7, wherein trimming the photoresist and depositing the dielectric layer occur in the same processing chamber.

[0065] 9. The method according to any one of paragraphs 1 to 8, wherein the processing chamber is a plasma enhanced chemical vapor deposition (PE-CVD) chamber.

[0066] 10. The method according to any one of paragraphs 1 to 9, wherein the plasma is a capacitively coupled plasma (CCP).

[0067] 11. The method according to any one of paragraphs 1 to 10, wherein the plasma is an inductively coupled plasma (ICP).

[0068] 12. The method according to any one of paragraphs 1 to 11, wherein the plasma is generated at a frequency in the range of about 100 kHz to about 2.4 GHz.

[0069] 13. The method according to any one of paragraphs 1 to 12, wherein the plasma is generated at a power in the range of about 10 watts to about 1,000 watts.

[0070] 14. The method according to any one of paragraphs 1 to 13, wherein the plasma is generated in a processing chamber having a pressure in the range of about 10 mTorr to about 50 Torr.

[0071] 15. The method according to any one of paragraphs 1 to 14, wherein trimming the photoresist further comprises: exposing the photoresist to a processing gas comprising hydrogen (H2), ammonia, nitrous oxide, oxygen (O2), hydrocarbons, nitrogen trifluoride, chlorine (Cl2), nitrogen (N2), carbon dioxide, carbon monoxide, water, ions of any of the foregoing, plasmas of any of the foregoing, or any combination of any of the foregoing.

[0072] 16. The method according to any one of paragraphs 1 to 15, further comprising: removing the photoresist from the patterned features before depositing the dielectric layer on the patterned features.

[0073] Although the foregoing is directed to embodiments of the present disclosure, other and further embodiments can be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims. All documents described herein are incorporated herein by reference, including any priority documents and / or test procedures, so long as they are not inconsistent herewith. From the foregoing general description and specific embodiments, it will be apparent that while the forms of the present disclosure have been illustrated and described, various modifications can be made without departing from the spirit and scope of the present disclosure. Accordingly, it is not intended to limit the present disclosure thereby. Similarly, for purposes of U.S. law, the term "comprising" is considered synonymous with the term "including". Likewise, whenever a transitional phrase "comprising" precedes a composition, element, or group of elements, it should be understood that we also contemplate the same composition or group of elements preceded by the transitional phrases "consisting essentially of", "consisting of", "selected from the group consisting of", or "is", and vice versa.

[0074] Certain embodiments and features have been described using a set of upper numerical limits and a set of lower numerical limits. It should be understood that ranges including any combination of any two values are contemplated, e.g., any lower value with any higher value, any combination of any two lower values, and / or any combination of any two higher values, unless otherwise indicated. Certain lower limits, upper limits, and ranges appear in one or more of the claims below.

Claims

1. A method for processing a substrate, comprising: Deposit a sacrificial structure layer on the substrate; Deposit a photoresist on the sacrificial structure layer; Pattern the photoresist to create a rough photoresist profile on the sacrificial structure layer; Trim the photoresist with plasma to create a refined photoresist profile covering a first portion of the sacrificial structure layer while exposing a second portion of the sacrificial structure layer; Etch the second portion of the sacrificial structure layer to form a patterned feature disposed on the substrate; Deposit a dielectric layer on the upper surface and side surfaces of the patterned feature, and on the upper surface of the substrate in contact with the upper surface of the substrate; Anisotropically etch a portion of the dielectric layer, including: Removing the dielectric layer on the upper surface of the patterned feature; Removing the dielectric layer on the upper surface of the substrate; and Leaving at least a portion of the dielectric layer on the side surfaces, wherein the portion of the dielectric material on the side surfaces forms sidewall spacers disposed on the upper surface of the substrate; and Remove the patterned feature while leaving the sidewall spacers disposed on the upper surface of the substrate in contact with the upper surface of the substrate.

2. The method according to claim 1, wherein the refined photoresist profile comprises sidewall surfaces that have a smoother or less wavy surface than the sidewall surfaces of the rough photoresist profile.

3. The method according to claim 1, wherein further refining the photoresist comprises: Modulate the critical dimension of the patterned feature or the subsequently deposited dielectric layer.

4. The method according to claim 1, wherein the refined photoresist profile has to line width roughness and to line edge roughness.

5. The method according to claim 1, wherein refining the photoresist and depositing the dielectric layer occur in the same processing chamber.

6. The method according to claim 5, wherein the processing chamber is a plasma enhanced chemical vapor deposition chamber.

7. The method according to claim 1, wherein the plasma is capacitively coupled plasma (CCP) or inductively coupled plasma (ICP).

8. The method according to claim 1, wherein the plasma is generated at a frequency in the range of 100 kHz to 2.4 GHz and a power in the range of 10 watts to 1,000 watts.

9. The method according to claim 1, wherein the plasma is generated in a processing chamber having a pressure in the range of 10 mTorr to 50 Torr.

10. The method according to claim 1, wherein further refining the photoresist comprises: Expose the photoresist to a process gas comprising: hydrogen (H2), ammonia, nitrous oxide, oxygen (O2), hydrocarbons, nitrogen trifluoride, chlorine (Cl2), nitrogen (N2), carbon dioxide, carbon monoxide, water, ions of any of the foregoing, plasmas of any of the foregoing, or any combination of any of the foregoing.

11. The method according to claim 1, further comprising: Remove the photoresist from the patterned feature before depositing the dielectric layer on the patterned feature.

12. A method for processing a substrate, comprising: Deposit a sacrificial structure layer on the substrate; Deposit a photoresist on the sacrificial structure layer; Pattern the photoresist to create a rough photoresist profile on the sacrificial structure layer; The photoresist is trimmed with a plasma to produce a trimmed photoresist profile covering a first portion of the sacrificial structure layer while exposing a second portion of the sacrificial structure layer, wherein the trimmed photoresist profile has to line width roughness and to line edge roughness; Etch the second portion of the sacrificial structure layer to form a patterned feature disposed on the substrate; Deposit a dielectric layer on the upper surface and side surfaces of the patterned feature, and on the upper surface of the substrate in contact with the upper surface of the substrate, wherein trimming the photoresist and depositing the dielectric layer occur in the same processing chamber; Anisotropically etch a portion of the dielectric layer, including: Removing the dielectric layer on the upper surface of the patterned feature; Removing the dielectric layer on the upper surface of the substrate; and Leaving at least a portion of the dielectric layer on the side surfaces, wherein the portion of the dielectric material on the side surfaces forms sidewall spacers disposed on the upper surface of the substrate; and Remove the patterned feature while leaving the sidewall spacers disposed on the upper surface of the substrate in contact with the upper surface of the substrate.

13. The method according to claim 12, wherein the refined photoresist profile comprises sidewall surfaces having a smoother or less wavy surface than the sidewall surfaces of the rough photoresist profile.

14. The method according to claim 12, wherein further refining the photoresist comprises: Modulate the critical dimension of the subsequently deposited dielectric layer.

15. The method according to claim 12, wherein the processing chamber is a plasma-enhanced chemical vapor deposition chamber.

16. The method according to claim 12, wherein the plasma is a capacitively coupled plasma (CCP) or an inductively coupled plasma (ICP).

17. The method according to claim 12, wherein the plasma is generated at a frequency in the range of 100 kHz to 2.4 GHz and a power in the range of 10 watts to 1,000 watts.

18. The method according to claim 12, wherein the plasma is generated in a processing chamber having a pressure in the range of 10 mTorr to 50 Torr.

19. The method according to claim 12, wherein further refining the photoresist comprises: Expose the photoresist to a processing gas, the processing gas including: hydrogen (H2), ammonia, nitrous oxide, oxygen (O2), hydrocarbons, nitrogen trifluoride, chlorine (Cl2), nitrogen (N2), carbon dioxide, carbon monoxide, water, ions of any of the foregoing, plasmas of any of the foregoing, or any combination of any of the foregoing.

20. A method for processing a substrate, comprising: Deposit a sacrificial structure layer on the substrate; Deposit a photoresist on the sacrificial structure layer; Pattern the photoresist to create a rough photoresist profile on the sacrificial structure layer; The photoresist is trimmed with plasma to produce a trimmed photoresist profile covering a first portion of the sacrificial structure layer while exposing a second portion of the sacrificial structure layer, wherein the trimmed photoresist profile has to line width roughness and to line edge roughness; Etch the second portion of the sacrificial structure layer to form a patterned feature disposed on the substrate; Remove the photoresist from the patterned feature; Deposit a dielectric layer on the upper surface and side surfaces of the patterned feature and on the upper surface of the substrate and in contact with the upper surface of the substrate; Anisotropically etch a portion of the dielectric layer, including: Removing the dielectric layer on the upper surface of the patterned feature; Removing the dielectric layer on the upper surface of the substrate; and Leaving at least a portion of the dielectric layer on the side surfaces, wherein the portion of the dielectric material on the side surfaces forms sidewall spacers disposed on the upper surface of the substrate; and Remove the patterned feature while leaving the sidewall spacers disposed on the upper surface of the substrate and in contact with the upper surface of the substrate.

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