Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: a substrate, the substrate including a first region and a second region arranged along a first direction; a channel structure located on the substrate and extending along the second direction; a gate structure located on the substrate; a conductive structure located on the first gate structure, the conductive structure having a first opening, the first opening being located at a boundary between the first region and the second region; an isolation opening located in the first gate structure, the first opening exposing the isolation opening; and a first isolation structure located in the first opening and the isolation opening. By forming a conductive structure located on the first gate structure, the conductive structure having a first opening, and using the conductive structure to self-align and etch the first gate structure, it is ensured that the conductive structure finally formed can be accurately connected to the first gate structure after being cut, thereby avoiding the problem of adding an additional gate structure to meet electrical requirements, reducing the width of the transmission gate circuit structure, and improving the integration of the finally formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the key dimensions of components are constantly decreasing, and the circuit density inside the integrated circuit is increasing. This development makes it impossible for the wafer surface to provide enough area to make the required interconnection lines.

[0003] In order to meet the needs of interconnection lines after the reduction of critical dimensions, the conduction between different metal layers or metal layers and substrates is currently achieved through interconnection structures. The interconnection structure includes interconnection lines and connection plugs formed in contact holes. The connection plugs are connected to semiconductor devices, and the interconnection lines realize the connection between the connection plugs, thereby forming a circuit. The connection plugs in the transistor structure include connection plugs located on the surface of the gate structure, which are used to connect the gate to the external circuit; and connection plugs located on the surface of the source and drain doping regions, which are used to connect the source region or drain region of the transistor to the external circuit.

[0004] However, the performance of the semiconductor structure formed in the prior art still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the integration of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent to each other; a channel structure located on the substrate and extending along a second direction, and the second direction is perpendicular to the first direction; a first gate structure located on the substrate and the channel structure, the first gate structure spanning the channel structure along the first direction; a conductive structure located on the first gate structure, the conductive structure having a first opening therein, the first opening being located on the first gate structure, and the first opening being located at a boundary between the first region and the second region; an isolation opening located in the first gate structure, the first opening exposing the isolation opening; and a first isolation structure located in the first opening and the isolation opening.

[0007] Optionally, the channel structure includes: a plurality of fins extending along the second direction; the first gate structure spans across the plurality of fins along the first direction, and the first gate structure covers a portion of the sidewalls and top surfaces of the fins.

[0008] Optionally, the channel structure includes: an isolation structure extending along the second direction, and a first fin structure and a second fin structure respectively located on both sides of the isolation structure, the side walls of the first fin structure and the second fin structure respectively contact the side walls of the isolation structure, the first fin structure is located on the first region, the second fin structure is located on the second region, the isolation structure is located at the boundary between the first region and the second region, the first fin structure includes several layers of first channel layers along the normal direction of the substrate surface, the second fin structure includes several layers of second channel layers along the normal direction of the substrate surface, and the first gate structure covers the first channel layer and the second channel layer and a portion of the top surface of the isolation structure along the first direction.

[0009] Optionally, the conductive structure includes: a first conductive plug, a second conductive plug, a first conductive layer and a second conductive layer, the first conductive layer is located on the first conductive plug, the second conductive layer is located on the second conductive plug, the first conductive plug and the first conductive layer are located on the first region, the second conductive plug and the second conductive layer are located on the second region, the first conductive layer and the second conductive layer extend along the second direction, and the first opening is located between the first conductive layer and the second conductive layer.

[0010] Optionally, it also includes: a first dielectric layer located on the first gate structure, the first conductive plug and the second conductive plug are located in the first dielectric layer; a second dielectric layer located on the first dielectric layer, the first conductive plug and the second conductive plug, the first conductive layer and the second conductive layer are located in the second dielectric layer.

[0011] Optionally, the conductive structure includes: a first conductive plug and a second conductive plug, the first conductive plug is located on the first region, the second conductive plug is located on the second region, the first conductive plug and the second conductive plug extend along the second direction, and the first opening is located between the first conductive plug and the second conductive plug.

[0012] Optionally, the method further includes: a first dielectric layer located on the first gate structure, and the first conductive plug and the second conductive plug are located in the first dielectric layer.

[0013] Optionally, it also includes: a second dielectric layer located on the first dielectric layer, the first conductive plug, the second conductive plug and the first isolation structure; a first conductive layer and a second conductive layer located in the second dielectric layer, the first conductive layer being located on the first conductive plug, and the second conductive layer being located on the second conductive plug; a second opening located in the second dielectric layer, the second opening exposing the top surface of the first isolation structure; and a second isolation structure located in the second opening.

[0014] Optionally, the material of the first conductive plug and the second conductive plug includes metal, and the metal includes one or more combinations of copper, tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0015] Optionally, the material of the first conductive layer and the second conductive layer includes metal, and the metal includes one or more combinations of copper, tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0016] Optionally, a material of the first isolation structure includes: one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0017] Optionally, a material of the second isolation structure includes: one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0018] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent to each other; forming a channel structure extending along a second direction on the substrate, and the second direction is perpendicular to the first direction; forming a gate structure on the substrate and the channel structure, the first gate structure spanning the channel structure along the first direction; forming a conductive structure on the first gate structure, the conductive structure having a first opening, the first opening being located on the first gate structure, and the first opening being located at a boundary between the first region and the second region; etching the first gate structure at the bottom of the first opening to form an isolation opening in the first gate structure; and forming a first isolation structure in the isolation opening and the first opening.

[0019] Optionally, the channel structure includes: a plurality of fins extending along the second direction; the first gate structure spans across the plurality of fins along the first direction, and the first gate structure covers a portion of the sidewalls and top surfaces of the fins.

[0020] Optionally, the channel structure includes: an isolation structure extending along the second direction, and a first fin structure and a second fin structure respectively located on both sides of the isolation structure, the side walls of the first fin structure and the second fin structure respectively contact the side walls of the isolation structure, the first fin structure is located on the first region, the second fin structure is located on the second region, the isolation structure is located at the boundary between the first region and the second region, the first fin structure includes several layers of first channel layers along the normal direction of the substrate surface, the second fin structure includes several layers of second channel layers along the normal direction of the substrate surface, and the first gate structure covers the first channel layer and the second channel layer and a portion of the top surface of the isolation structure along the first direction.

[0021] Optionally, the conductive structure includes: a first conductive plug, a second conductive plug, a first conductive layer and a second conductive layer, the first conductive layer is located on the first conductive plug, the second conductive layer is located on the second conductive plug, the first conductive plug and the first conductive layer are located on the first region, the second conductive plug and the second conductive layer are located on the second region, the first conductive layer and the second conductive layer extend along the second direction, and the first opening is located between the first conductive layer and the second conductive layer.

[0022] Optionally, the method for forming the first opening, the first conductive plug, the second conductive plug, the first conductive layer structure and the second conductive layer includes: forming a first dielectric layer on the first gate structure; forming an initial conductive plug in the first dielectric layer, the initial conductive plug is located on the first region and the second region, and the bottom of the initial conductive plug is in contact with the top of the first gate structure; forming a second dielectric layer on the first dielectric layer and the initial conductive plug; forming a first conductive layer and a second conductive layer separated from each other in the second dielectric layer, the first conductive layer and the second conductive layer are located on the initial conductive plug; etching the second dielectric layer to form an initial first opening between the first conductive layer and the second conductive layer, the initial first opening exposing the top surface of the initial conductive plug; etching the initial first opening to expose the initial plug structure until the top surface of the first gate structure is exposed, thereby forming the first conductive plug, the second conductive plug and the first opening.

[0023] Optionally, the method for forming the first opening, the first conductive plug, the second conductive plug, the first conductive layer and the second conductive layer includes: forming a first dielectric layer on the first gate structure; forming the first conductive plug and the second conductive plug in the first dielectric layer, the first conductive plug is located on the first region, and the second conductive plug is located on the second region; forming a second dielectric layer on the first dielectric layer, the first conductive plug and the second conductive plug; forming a first conductive layer and a second conductive layer in the second dielectric layer, the first conductive layer is located on the first conductive plug, and the second conductive layer is located on the second conductive plug; etching the first dielectric layer and the second dielectric layer until the top surface of the first gate structure is exposed to form the first opening.

[0024] Optionally, the method for forming the first opening, the first conductive plug, the second conductive plug, the first conductive layer and the second conductive layer includes: forming a first dielectric layer on the first gate structure; forming a second dielectric layer on the first dielectric layer, and forming the first conductive plug, the second conductive plug, the first conductive layer and the second conductive layer in the first dielectric layer and the second dielectric layer; etching the first dielectric layer and the second dielectric layer until the top surface of the first gate structure is exposed to form the first opening.

[0025] Optionally, the method for forming the first isolation structure includes: forming an initial first isolation structure in the first opening, in the isolation opening, on the second dielectric layer, on the first conductive layer, and on the second conductive layer; and flattening the initial first isolation structure until the second dielectric layer, the first conductive layer, and the top surfaces of the second conductive layer are exposed to form the first isolation structure.

[0026] Optionally, the conductive structure includes: a first conductive plug and a second conductive plug, the first conductive plug is located on the first region, the second conductive plug is located on the second region, the first conductive plug and the second conductive plug extend along the second direction, and the first opening is located between the first conductive plug and the second conductive plug.

[0027] Optionally, the method for forming the first opening, the first conductive plug and the second conductive plug includes: forming a first dielectric layer on the first gate structure; forming the first conductive plug and the second conductive plug in the first dielectric layer, the first conductive plug is located on the first region, and the second conductive plug is located on the second region; etching the first dielectric layer until the top surface of the first gate structure is exposed to form the first opening.

[0028] Optionally, the method for forming the first isolation structure includes: forming an initial first isolation structure in the first opening, in the isolation opening, on the first dielectric layer, on the first conductive plug, and on the second conductive plug; and flattening the initial first isolation structure until the top surfaces of the first dielectric layer, the first conductive plug, and the second conductive plug are exposed to form the first isolation structure.

[0029] Optionally, after forming the first isolation structure, the method further includes: forming a second dielectric layer on the first dielectric layer, the first conductive plug, the second conductive plug and the first isolation structure; forming a first conductive layer and a second conductive layer in the second dielectric layer, the first conductive layer being located on the first conductive plug, and the second conductive layer being located on the second conductive plug; etching the second dielectric layer until the top surface of the first isolation structure is exposed, forming a second opening in the second dielectric layer; and forming a second isolation structure in the second opening.

[0030] Optionally, the material of the first conductive plug and the second conductive plug includes metal, and the metal includes one or more combinations of copper, tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0031] Optionally, the material of the first conductive layer and the second conductive layer includes metal, and the metal includes one or more combinations of copper, tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0032] Optionally, a material of the first isolation structure includes: one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0033] Optionally, a material of the second isolation structure includes: one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0034] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0035] In the formation method of the technical solution of the present invention, a conductive structure is first formed on the first gate structure, the conductive structure has a first opening, and the first gate structure is self-aligned and etched using the conductive structure to ensure that the conductive structure finally formed can be accurately connected to the first gate structure after being cut off, thereby avoiding the problem of adding an additional gate structure to meet electrical requirements, reducing the width of the transmission gate circuit structure, and improving the integration of the finally formed semiconductor structure.

[0036] In the structure formed by the technical solution of the present invention, a conductive structure is formed on the first gate structure, and the conductive structure has a first opening. The first gate structure is self-aligned and etched using the conductive structure to ensure that the conductive structure finally formed can be accurately connected to the first gate structure after being cut off, thereby avoiding the problem of additionally adding a gate structure to meet electrical requirements, reducing the width of the transmission gate circuit structure, and improving the integration of the finally formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figures 1 to 3 It is a schematic diagram of the structure of a semiconductor structure;

[0038] Figures 4 to 17 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention.

[0039] Fig.18 It is a schematic structural diagram of each step of another embodiment of the method for forming a semiconductor structure of the present invention.

[0040] Figures 19 to 22 It is a schematic structural diagram of each step of another embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0041] As the background technology, the performance of the semiconductor structure formed in the prior art still needs to be improved.

[0042] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0043] Please refer to Figure 1 , including: providing a substrate 100; forming a first fin 101, a second fin 102, a third fin 103 and a fourth fin 104 extending along a first direction X on the substrate 100; forming a first gate structure 105, a second gate structure 106 and a third gate structure 107 on the substrate 100, wherein the first gate structure 105, the second gate structure 106 and the third gate structure 107 respectively cross the first fin 101, the second fin 102, the third fin 103 and the fourth fin 104 along a second direction Y.

[0044] Please refer to Figure 2, etching and removing a portion of the second gate structure 106 to form a fourth gate structure 108 and a fifth gate structure 109, wherein the fourth gate structure 108 spans the first fin 101 and the second fin 102, and the fifth gate structure 109 spans the third fin 103 and the fourth fin 104; etching and removing a portion of the third gate structure 107 to form a sixth gate structure 110 and a seventh gate structure 111, wherein the sixth gate structure 110 spans the first fin 101 and the second fin 102, and the seventh gate structure 111 spans the third fin 103 and the fourth fin 104.

[0045] Please refer to Figure 3 , a first conductive plug 112 and a first conductive layer 113 located on the first conductive plug 112 are formed on the first gate structure 105; a second conductive plug 114 and a second conductive layer 115 located on the second conductive plug 114 are formed on the fourth gate structure 108; a third conductive plug 116 and a third conductive layer 117 located on the third conductive plug 116 are formed on the seventh gate structure 111.

[0046] In the present embodiment, the structure finally formed is a standard transmission gate circuit structure. Since the process step of cutting the second gate structure 106 (Gate Cut) is performed before forming the conductive plug and the conductive layer, the position of the gate cut may not be accurate enough, which may lead to the problem that the position of the conductive plug formed subsequently overlaps with the position of the gate cut. Therefore, an additional third gate structure 107 is required to meet the electrical requirements, which will increase the width of the overall transmission gate circuit structure, thereby reducing the integration of the semiconductor structure finally formed.

[0047] On this basis, the present invention provides a semiconductor structure and a method for forming the same, by first forming a conductive structure on the first gate structure, the conductive structure having a first opening, and then using the conductive structure to self-align and etch the first gate structure, thereby ensuring that the conductive structure finally formed can be accurately connected to the cut-off gate structure, thereby avoiding the problem of additionally adding a gate structure to meet electrical requirements, reducing the width of the transmission gate circuit structure, and improving the integration of the finally formed semiconductor structure.

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0049] Figures 4 to 17 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0050] Please refer to Figure 4 , providing a substrate 200, wherein the substrate 200 includes a first region I and a second region II arranged along a first direction X, wherein the first region I and the second region II are adjacent to each other.

[0051] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0052] Please refer to Figure 5 and Figure 6 , Figure 6 yes Figure 5 Schematic diagram of the cross section along line AA, Figure 5 for Figure 6 In the top view in which the isolation layer is omitted, a channel structure extending along a second direction Y is formed on the substrate 200, and the second direction Y is perpendicular to the first direction X.

[0053] In this embodiment, the channel structure includes: a plurality of fins 201 extending along the second direction Y.

[0054] In this embodiment, the material of the fin 201 is silicon; in other embodiments, the material of the substrate may also be silicon germanium.

[0055] Please continue to refer to Figure 6 After the channel structure is formed, an isolation layer 202 is formed on the substrate 200 , wherein the isolation layer 202 covers a portion of the sidewall surface of the fin, and a top surface of the isolation layer 202 is lower than a top surface of the fin 201 .

[0056] The material of the isolation layer 202 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride. In this embodiment, the material of the isolation layer 202 is silicon oxide.

[0057] Please refer to Figure 7 and Figure 8 , Figure 8 yes Figure 7 Schematic diagram of the cross section along line BB, Figure 7 for Figure 8 In the top view of the isolating layer is omitted, a first gate structure 203 is formed on the substrate 200 and the channel structure, and the first gate structure 203 crosses the channel structure along the first direction X.

[0058] In this embodiment, the method further includes: forming a second gate structure 204 on the substrate 200 and the channel structure, wherein the second gate structure 204 crosses the channel structure along the first direction X.

[0059] In this embodiment, the first gate structure 203 and the second gate structure 204 span across a number of the fins 201 along the first direction X, and the first gate structure 203 and the second gate structure 204 cover a portion of the sidewalls and top surfaces of the fins 201 .

[0060] After forming the first gate structure 203 and the second gate structure 204, the method further includes: forming a conductive structure on the first gate structure 203, wherein the conductive structure has a first opening, the first opening is located on the first gate structure, and the first opening is located at the boundary between the first region I and the second region II; the conductive structure includes: a first conductive plug, a second conductive plug, a first conductive layer, and a second conductive layer, the first conductive layer is located on the first conductive plug, the second conductive layer is located on the second conductive plug, the first conductive plug and the first conductive layer are located on the first region I, the second conductive plug and the second conductive layer are located on the second region II, the first conductive layer and the second conductive layer extend along the second direction Y, and the first opening is located between the first conductive layer and the second conductive layer. For the specific formation process of the conductive structure, please refer to Figures 9 to 13 .

[0061] Please refer to Fig. 9 , Fig. 9 and Figure 8 A first dielectric layer 205 is formed on the first gate structure 203 in the same viewing direction.

[0062] In this embodiment, the material of the first dielectric layer 205 is silicon oxide; in other embodiments, the material of the first dielectric layer can also be low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 2.5).

[0063] Please refer to Fig.10 , an initial conductive plug 206 is formed in the first dielectric layer 205 , the initial conductive plug 206 is located on the first region I and the second region II, and the bottom of the initial conductive plug 206 contacts the top of the first gate structure 203 .

[0064] In this embodiment, the method for forming the initial conductive plug includes: forming a conductive plug opening in the first dielectric layer, wherein the conductive plug opening exposes a portion of the top surface of the first gate structure; and forming the initial conductive plug in the conductive plug opening.

[0065] Please refer to Fig.11 , a second dielectric layer 207 is formed on the first dielectric layer 205 and the initial conductive plug 206 .

[0066] In this embodiment, the material of the second dielectric layer 207 is silicon oxide; in other embodiments, the material of the second dielectric layer can also be low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 2.5).

[0067] Please refer to Fig.12 A first conductive layer 208 and a second conductive layer 209 separated from each other are formed in the second dielectric layer 207 , and the first conductive layer 208 and the second conductive layer 209 are located on the initial conductive plug 206 .

[0068] In this embodiment, the material of the first conductive layer 208 and the second conductive layer 209 is metal, and the metal is copper; in other embodiments, the material of the first conductive layer and the second conductive layer can also be one or more combinations of tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0069] Please refer to Fig.13 , etching the second dielectric layer 207 to form an initial first opening (not shown) between the first conductive layer 208 and the second conductive layer 209, wherein the initial first opening exposes the top surface of the initial conductive plug 206; etching the initial first opening to expose the initial plug structure 206 until the top surface of the first gate structure 203 is exposed, thereby forming the first conductive plug 210, the second conductive plug 211 and the first opening 212.

[0070] By first forming a conductive structure on the first gate structure 203, the conductive structure has a first opening 212, and then using the conductive structure to self-align and etch the first gate structure 203, it is ensured that the conductive structure finally formed can be accurately connected to the first gate structure 203 after being cut off, thereby avoiding the problem of adding an additional gate structure to meet electrical requirements, reducing the width of the transmission gate circuit structure, and improving the integration of the finally formed semiconductor structure.

[0071] In this embodiment, the material of the first conductive plug 210 and the second conductive plug 211 includes metal, and the metal is copper; in other embodiments, the material of the first conductive plug and the second conductive plug may also include one or more combinations of tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0072] In other embodiments, the method for forming the first opening, the first conductive plug, the second conductive plug, the first conductive layer and the second conductive layer may further include: forming a first dielectric layer on the first gate structure; forming the first conductive plug and the second conductive plug in the first dielectric layer, the first conductive plug being located on the first region, and the second conductive plug being located on the second region; forming a second dielectric layer on the first dielectric layer, the first conductive plug and the second conductive plug; forming a first conductive layer and a second conductive layer in the second dielectric layer, the first conductive layer being located on the first conductive plug, and the second conductive layer being located on the second conductive plug; etching the first dielectric layer and the second dielectric layer until the top surface of the first gate structure is exposed to form the first opening.

[0073] In other embodiments, the method for forming the first opening, the first conductive plug, the second conductive plug, the first conductive layer and the second conductive layer may further include: forming a first dielectric layer on the first gate structure; forming a second dielectric layer on the first dielectric layer, and forming the first conductive plug, the second conductive plug, the first conductive layer and the second conductive layer in the first dielectric layer and the second dielectric layer; etching the first dielectric layer and the second dielectric layer until the top surface of the first gate structure is exposed to form the first opening.

[0074] Please refer to Fig.14 In this embodiment, the process of forming the conductive structure further includes: forming a third conductive plug 213 on the second gate structure 204; and forming a third conductive layer 214 on the third conductive plug 213.

[0075] Please refer to Fig.15 , the first gate structure 203 at the bottom of the first opening 212 is etched to form an isolation opening 215 in the first gate structure 203 .

[0076] In this embodiment, the first gate structure 203 at the bottom of the first opening 212 is etched until the top surface of the isolation layer 202 is exposed, thereby forming the isolation opening 215 .

[0077] In this embodiment, the process of etching the first gate structure 203 is a wet etching process; in other embodiments, the process of etching the first gate structure may also be a dry etching process.

[0078] Please refer to Fig.16 and Fig.17 , Fig.17 yes Fig.16 Schematic diagram of the cross section along the CC line, Fig.17 for Fig.16The top view of the isolation layer, the first dielectric layer, the second dielectric layer and the first isolation structure is omitted, and a first isolation structure 216 is formed in the isolation opening 215 and the first opening 212 .

[0079] In this embodiment, the method for forming the first isolation structure 216 includes: forming an initial first isolation structure (not shown) in the first opening 212, in the isolation opening 215, on the second dielectric layer 207, on the first conductive layer 208, and on the second conductive layer 209; and flattening the initial first isolation structure until the top surfaces of the second dielectric layer 207, the first conductive layer 208, and the second conductive layer 209 are exposed, thereby forming the first isolation structure 216.

[0080] In this embodiment, the material of the first isolation structure 216 is silicon oxide; in other embodiments, the material of the first isolation structure may also be one or more combinations of silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0081] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig.17 , comprising: a substrate 200, the substrate 200 comprising a first region I and a second region II arranged along a first direction X, the first region I and the second region II being adjacent to each other; a channel structure located on the substrate 200 and extending along a second direction Y, wherein the second direction Y is perpendicular to the first direction X; a first gate structure 203 located on the substrate 200 and the channel structure, the first gate structure 203 spanning the channel structure along the first direction X; a conductive structure located on the first gate structure 203, the conductive structure having a first opening 212 therein, the first opening 212 being located on the first gate structure 203, and the first opening 212 being located at a boundary between the first region I and the second region II; an isolation opening 215 located in the first gate structure 203, the first opening 212 exposing the isolation opening 215; and a first isolation structure 216 located in the first opening 212 and the isolation opening 215.

[0082] In this embodiment, the channel structure includes: a plurality of fins 201 arranged along the second direction Y; the first gate structure 203 spans across the plurality of fins 201 along the first direction X, and the first gate structure 203 covers part of the sidewalls and top surfaces of the fins 201 .

[0083] In this embodiment, the conductive structure includes: a first conductive plug 210, a second conductive plug 211, a first conductive layer 208 and a second conductive layer 209, the first conductive layer 208 is located on the first conductive plug 210, the second conductive layer 209 is located on the second conductive plug 211, the first conductive plug 210 and the first conductive layer 208 are located on the first region I, the second conductive plug 211 and the second conductive layer 209 are located on the second region II, the first conductive layer 208 and the second conductive layer 209 extend along the second direction Y, and the first opening 212 is located between the first conductive layer 208 and the second conductive layer 209.

[0084] In this embodiment, it also includes: a first dielectric layer 205 located on the first gate structure 203, and the first conductive plug 210 and the second conductive plug 211 are located in the first dielectric layer 205; a second dielectric layer 207 located on the first dielectric layer 205, the first conductive plug 210 and the second conductive plug 211, and the first conductive layer 208 and the second conductive layer 209 are located in the second dielectric layer 207.

[0085] In this embodiment, the material of the first conductive plug 210 and the second conductive plug 211 includes metal, and the metal is copper; in other embodiments, the material of the first conductive plug and the second conductive plug may also include one or more combinations of tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0086] In this embodiment, the material of the first conductive layer 208 and the second conductive layer 209 includes metal, and the metal is copper; in other embodiments, the material of the first conductive layer and the second conductive layer may also include one or more combinations of tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0087] In this embodiment, the material of the first isolation structure 216 is silicon oxide; in other embodiments, the material of the first isolation structure may also be one or more combinations of silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0088] Fig.18 It is a structural schematic diagram of a semiconductor structure forming process according to another embodiment of the present invention.

[0089] Please refer to Fig.18This embodiment continues to explain the method for forming a semiconductor structure based on the above embodiment. The difference between this embodiment and the above embodiment is that: the channel structure includes: an isolation structure 300 extending along the second direction Y, and a first fin structure and a second fin structure respectively located on both sides of the isolation structure 300, the side walls of the first fin structure and the second fin structure are respectively in contact with the side walls of the isolation structure 300, the first fin structure is located on the first region I, the second fin structure is located on the second region II, the isolation structure 300 is located at the boundary between the first region I and the second region II, the first fin structure includes several layers of first channel layers 301 along the normal direction of the surface of the substrate 200, and the second fin structure includes several layers of second channel layers 302 along the normal direction of the surface of the substrate 200.

[0090] In this embodiment, the material of the first channel layer 301 and the second channel layer 302 is silicon; in other embodiments, the material of the first channel layer and the second channel layer may also be germanium silicon.

[0091] In this embodiment, the isolation opening 212 exposes the top surface of the isolation structure 300 , and the bottom of the first isolation structure 216 is in contact with the top of the isolation structure 300 .

[0092] Correspondingly, an embodiment of the present invention further provides a semiconductor structure, please refer to Fig.18 , comprising: a substrate 200, the substrate 200 comprising a first region I and a second region II arranged along a first direction X, the first region I and the second region II being adjacent to each other; a channel structure extending along a second direction Y on the substrate 200, wherein the second direction Y is perpendicular to the first direction X; a first gate structure 203 on the substrate 200 and the channel structure, the first gate structure 203 spanning the channel structure along the first direction X; a conductive structure on the first gate structure 203, the conductive structure having a first opening 212 therein, the first opening 212 being located on the first gate structure 203, and the first opening 212 being located at a boundary between the first region I and the second region II; an isolation opening 215 in the first gate structure 203, the first opening 212 exposing the isolation opening 215; and a first isolation structure 216 located in the first opening 212 and the isolation opening 215.

[0093] In this embodiment, the channel structure includes: an isolation structure 300 extending along the second direction Y, and a first fin structure and a second fin structure respectively located on both sides of the isolation structure 300, the side walls of the first fin structure and the second fin structure are respectively in contact with the side walls of the isolation structure 300, the first fin structure is located on the first region I, the second fin structure is located on the second region II, the isolation structure 300 is located at the boundary between the first region I and the second region II, the first fin structure includes several layers of first channel layers 301 along the normal direction of the surface of the substrate 200, the second fin structure includes several layers of second channel layers 302 along the normal direction of the surface of the substrate 200, and the first gate structure 203 covers the first channel layer 301 and the second channel layer 302, as well as a portion of the top surface of the isolation structure 300 along the first direction X.

[0094] In this embodiment, the conductive structure includes: a first conductive plug 210, a second conductive plug 211, a first conductive layer 208 and a second conductive layer 209, the first conductive layer 208 is located on the first conductive plug 210, the second conductive layer 209 is located on the second conductive plug 211, the first conductive plug 210 and the first conductive layer 208 are located on the first region I, the second conductive plug 211 and the second conductive layer 209 are located on the second region II, the first conductive layer 208 and the second conductive layer 209 extend along the second direction Y, and the first opening 212 is located between the first conductive layer 208 and the second conductive layer 209.

[0095] In this embodiment, it also includes: a first dielectric layer 205 located on the first gate structure 203, and the first conductive plug 210 and the second conductive plug 211 are located in the first dielectric layer 205; a second dielectric layer 207 located on the first dielectric layer 205, the first conductive plug 210 and the second conductive plug 211, and the first conductive layer 208 and the second conductive layer 209 are located in the second dielectric layer 207.

[0096] In this embodiment, the material of the first conductive plug 210 and the second conductive plug 211 includes metal, and the metal is copper; in other embodiments, the material of the first conductive plug and the second conductive plug may also include one or more combinations of tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0097] In this embodiment, the material of the first conductive layer 208 and the second conductive layer 209 includes metal, and the metal is copper; in other embodiments, the material of the first conductive layer and the second conductive layer may also include one or more combinations of tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0098] In this embodiment, the material of the first isolation structure 216 is silicon oxide; in other embodiments, the material of the first isolation structure may also be one or more combinations of silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0099] Figures 19 to 22 It is a structural schematic diagram of a semiconductor structure forming process according to another embodiment of the present invention.

[0100] This embodiment further describes the method for forming a semiconductor structure based on the above embodiment. The difference between this embodiment and the above embodiment is that: when forming the first gate structure 203 and the second gate structure 204 (such as Figure 7 After that, the method further includes: forming a conductive structure on the first gate structure 203, the conductive structure including: a first conductive plug 210 and a second conductive plug 211, the first conductive plug 210 is located on the first region I, the second conductive plug 211 is located on the second region II, the first conductive plug 210 and the second conductive plug 211 extend along the second direction Y, and the first opening 212 is located between the first conductive plug 210 and the second conductive plug 211. The formation process of the conductive structure will be described in detail below with reference to the accompanying drawings.

[0101] Please refer to Fig.19 , forming a first dielectric layer 205 on the first gate structure 203; forming the first conductive plug 210 and the second conductive plug 211 in the first dielectric layer 205, the first conductive plug 210 is located on the first region I, and the second conductive plug 211 is located on the second region II; etching the first dielectric layer 205 until the top surface of the first gate structure 203 is exposed, thereby forming the first opening 212.

[0102] In this embodiment, the material of the first conductive plug 210 and the second conductive plug 211 includes metal, and the metal is copper; in other embodiments, the material of the first conductive plug and the second conductive plug may also include one or more combinations of tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0103] Please refer to Fig. 20, the first gate structure 203 at the bottom of the first opening 212 is etched to form an isolation opening 215 in the first gate structure 203 .

[0104] In this embodiment, the process of etching the first gate structure 203 is a wet etching process; in other embodiments, the process of etching the first gate structure may also be a dry etching process.

[0105] Please refer to Fig.21 , a first isolation structure 216 is formed in the isolation opening 215 and the first opening 212 .

[0106] In this embodiment, the method for forming the first isolation structure 216 includes: forming an initial first isolation structure (not shown) in the first opening 212, in the isolation opening 215, on the first dielectric layer 205, on the first conductive plug 210, and on the second conductive plug 211; and planarizing the initial first isolation structure until the top surfaces of the first dielectric layer 205, the first conductive plug 210, and the second conductive plug 211 are exposed, thereby forming the first isolation structure 216.

[0107] In this embodiment, the material of the first isolation structure 216 is silicon oxide; in other embodiments, the material of the first isolation structure may also be one or more combinations of silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0108] Please refer to Fig. 22 After forming the first isolation structure 216, a second dielectric layer 207 is formed on the first dielectric layer 205, the first conductive plug 210, the second conductive plug 211 and the first isolation structure 216; a first conductive layer 208 and a second conductive layer 209 are formed in the second dielectric layer 207, the first conductive layer 208 is located on the first conductive plug 210, and the second conductive layer 209 is located on the second conductive plug 211; the second dielectric layer 207 is etched until the top surface of the first isolation structure 216 is exposed, and a second opening (not shown) is formed in the second dielectric layer 207; and a second isolation structure 400 is formed in the second opening.

[0109] In this embodiment, the material of the second dielectric layer 207 is silicon oxide; in other embodiments, the material of the second dielectric layer can also be low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 2.5).

[0110] In this embodiment, the material of the first conductive layer 208 and the second conductive layer 209 includes metal, and the metal is copper; in other embodiments, the material of the first conductive layer and the second conductive layer may also include one or more combinations of tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0111] In this embodiment, the material of the second isolation structure 400 is silicon oxide; in other embodiments, the material of the second isolation structure may also be one or more combinations of silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0112] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig. 22 , comprising: a substrate 200, the substrate 200 comprising a first region I and a second region II arranged along a first direction X, the first region I and the second region II being adjacent to each other; a channel structure located on the substrate 200 and extending along a second direction Y, wherein the second direction Y is perpendicular to the first direction X; a first gate structure 203 located on the substrate 200 and the channel structure, the first gate structure 203 spanning the channel structure along the first direction X; a conductive structure located on the first gate structure 203, the conductive structure having a first opening 212 therein, the first opening 212 being located on the first gate structure 203, and the first opening 212 being located at a boundary between the first region I and the second region II; an isolation opening 215 located in the first gate structure 203, the first opening 212 exposing the isolation opening 215; and a first isolation structure 216 located in the first opening 212 and the isolation opening 215.

[0113] In this embodiment, the channel structure includes: a plurality of fins 201 arranged along the second direction Y; the first gate structure 203 spans across the plurality of fins 201 along the first direction X, and the first gate structure 203 covers part of the sidewalls and top surfaces of the fins 201 .

[0114] In this embodiment, the conductive structure includes: a first conductive plug 210 and a second conductive plug 211, the first conductive plug 210 is located on the first region I, the second conductive plug 211 is located on the second region II, the first conductive plug 210 and the second conductive plug 211 extend along the second direction Y, and the first opening 212 is located between the first conductive plug 210 and the second conductive plug 211.

[0115] In this embodiment, the first dielectric layer 205 is further included and is located on the first gate structure 203 . The first conductive plug 210 and the second conductive plug 211 are located in the first dielectric layer 205 .

[0116] In this embodiment, the present invention further includes: a second dielectric layer 207 located on the first dielectric layer 205, the first conductive plug 210, the second conductive plug 211 and the first isolation structure 216; a first conductive layer 208 and a second conductive layer 209 located in the second dielectric layer 207, wherein the first conductive layer 208 is located on the first conductive plug 210, and the second conductive layer 209 is located on the second conductive plug 211; a second opening located in the second dielectric layer 207, wherein the second opening exposes the top surface of the first isolation structure 216; and a second isolation structure 400 located in the second opening.

[0117] In this embodiment, the material of the first conductive plug 210 and the second conductive plug 211 includes metal, and the metal is copper; in other embodiments, the material of the first conductive plug and the second conductive plug may also include one or more combinations of tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0118] In this embodiment, the material of the first conductive layer 208 and the second conductive layer 209 includes metal, and the metal is copper; in other embodiments, the material of the first conductive layer and the second conductive layer may also include one or more combinations of tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

[0119] In this embodiment, the material of the first isolation structure 216 is silicon oxide; in other embodiments, the material of the first isolation structure may also be one or more combinations of silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0120] In this embodiment, the material of the second isolation structure 400 is silicon oxide; in other embodiments, the material of the second isolation structure may also be one or more combinations of silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

[0121] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent to each other; a channel structure located on the substrate and extending along a second direction, wherein the second direction is perpendicular to the first direction; a first gate structure located on the substrate and the channel structure, wherein the first gate structure crosses the channel structure along the first direction; A conductive structure located on the first gate structure, wherein the conductive structure has a first opening therein, the first opening is located on the first gate structure, and the first opening is located at a boundary between the first region and the second region; an isolation opening in the first gate structure, the first opening exposing the isolation opening; a first isolation structure located in the first opening and the isolation opening; wherein, The channel structure includes: an isolation structure extending along the second direction, and a first fin structure and a second fin structure respectively located on both sides of the isolation structure, the side walls of the first fin structure and the second fin structure are respectively in contact with the side walls of the isolation structure, the first fin structure is located on the first region, the second fin structure is located on the second region, the isolation structure is located at the boundary between the first region and the second region, the first fin structure includes several layers of first channel layers along the normal direction of the substrate surface, the second fin structure includes several layers of second channel layers along the normal direction of the substrate surface, and the first gate structure covers the first channel layer and the second channel layer and a portion of the top surface of the isolation structure along the first direction.

2. The semiconductor structure according to claim 1, wherein: The conductive structure includes: a first conductive plug, a second conductive plug, a first conductive layer and a second conductive layer, the first conductive layer is located on the first conductive plug, the second conductive layer is located on the second conductive plug, the first conductive plug and the first conductive layer are located on the first region, the second conductive plug and the second conductive layer are located on the second region, the first conductive layer and the second conductive layer extend along the second direction, and the first opening is located between the first conductive layer and the second conductive layer.

3. The semiconductor structure according to claim 2, characterized in that: Also includes: a first dielectric layer located on the first gate structure, wherein the first conductive plug and the second conductive plug are located in the first dielectric layer; A second dielectric layer is located on the first dielectric layer, the first conductive plug and the second conductive plug, and the first conductive layer and the second conductive layer are located in the second dielectric layer.

4. The semiconductor structure according to claim 1, wherein: The conductive structure includes: a first conductive plug and a second conductive plug, the first conductive plug is located on the first region, the second conductive plug is located on the second region, the first conductive plug and the second conductive plug extend along the second direction, and the first opening is located between the first conductive plug and the second conductive plug.

5. The semiconductor structure according to claim 4, characterized in that: Also includes: A first dielectric layer is located on the first gate structure, and the first conductive plug and the second conductive plug are located in the first dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that: Also includes: a second dielectric layer located on the first dielectric layer, the first conductive plug, the second conductive plug and the first isolation structure; a first conductive layer and a second conductive layer located in the second dielectric layer, wherein the first conductive layer is located on the first conductive plug, and the second conductive layer is located on the second conductive plug; a second opening located in the second dielectric layer, wherein the second opening exposes a top surface of the first isolation structure; A second isolation structure is located in the second opening.

7. The semiconductor structure according to claim 2 or 4, characterized in that: The material of the first conductive plug and the second conductive plug includes metal, and the metal includes one or more combinations of copper, tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

8. The semiconductor structure according to claim 2 or 6, characterized in that: The material of the first conductive layer and the second conductive layer includes metal, and the metal includes one or more combinations of copper, tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

9. The semiconductor structure according to claim 1, wherein: The material of the first isolation structure includes: one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

10. The semiconductor structure according to claim 6, wherein: The material of the second isolation structure includes: one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

11. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent to each other; forming a channel structure extending along a second direction on the substrate, wherein the second direction is perpendicular to the first direction; forming a first gate structure on the substrate and the channel structure, wherein the first gate structure crosses the channel structure along the first direction; forming a conductive structure on the first gate structure, wherein the conductive structure has a first opening, the first opening is located on the first gate structure, and the first opening is located at a boundary between the first region and the second region; Etching the first gate structure at the bottom of the first opening to form an isolation opening in the first gate structure; A first isolation structure is formed in the isolation opening and the first opening.

12. The method for forming a semiconductor structure according to claim 11, wherein: The channel structure includes: a plurality of fins extending along the second direction; the first gate structure spans across the plurality of fins along the first direction, and the first gate structure covers a portion of sidewalls and top surfaces of the fins.

13. The method for forming a semiconductor structure according to claim 11, wherein: The channel structure includes: an isolation structure extending along the second direction, and a first fin structure and a second fin structure respectively located on both sides of the isolation structure, the side walls of the first fin structure and the second fin structure are respectively in contact with the side walls of the isolation structure, the first fin structure is located on the first region, the second fin structure is located on the second region, the isolation structure is located at the boundary between the first region and the second region, the first fin structure includes several layers of first channel layers along the normal direction of the substrate surface, the second fin structure includes several layers of second channel layers along the normal direction of the substrate surface, and the first gate structure covers the first channel layer and the second channel layer and a portion of the top surface of the isolation structure along the first direction.

14. The method for forming a semiconductor structure according to claim 11, wherein: The conductive structure includes: a first conductive plug, a second conductive plug, a first conductive layer and a second conductive layer, the first conductive layer is located on the first conductive plug, the second conductive layer is located on the second conductive plug, the first conductive plug and the first conductive layer are located on the first region, the second conductive plug and the second conductive layer are located on the second region, the first conductive layer and the second conductive layer extend along the second direction, and the first opening is located between the first conductive layer and the second conductive layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the first opening, the first conductive plug, the second conductive plug, the first conductive layer structure and the second conductive layer comprises: forming a first dielectric layer on the first gate structure; forming an initial conductive plug in the first dielectric layer, the initial conductive plug is located on the first region and the second region, and the bottom of the initial conductive plug is in contact with the top of the first gate structure; forming a second dielectric layer on the first dielectric layer and the initial conductive plug; forming a first conductive layer and a second conductive layer separated from each other in the second dielectric layer, the first conductive layer and the second conductive layer are located on the initial conductive plug; etching the second dielectric layer to form an initial first opening between the first conductive layer and the second conductive layer, the initial first opening exposing the top surface of the initial conductive plug; etching the initial first opening to expose the initial conductive plug until the top surface of the first gate structure is exposed, thereby forming the first conductive plug, the second conductive plug and the first opening.

16. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the first opening, the first conductive plug, the second conductive plug, the first conductive layer and the second conductive layer includes: forming a first dielectric layer on the first gate structure; forming the first conductive plug and the second conductive plug in the first dielectric layer, wherein the first conductive plug is located on the first region and the second conductive plug is located on the second region; forming a second dielectric layer on the first dielectric layer, the first conductive plug and the second conductive plug; forming a first conductive layer and a second conductive layer in the second dielectric layer, wherein the first conductive layer is located on the first conductive plug and the second conductive layer is located on the second conductive plug; etching the first dielectric layer and the second dielectric layer until the top surface of the first gate structure is exposed to form the first opening.

17. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the first opening, the first conductive plug, the second conductive plug, the first conductive layer and the second conductive layer includes: forming a first dielectric layer on the first gate structure; forming a second dielectric layer on the first dielectric layer, and forming the first conductive plug, the second conductive plug, the first conductive layer and the second conductive layer in the first dielectric layer and the second dielectric layer; etching the first dielectric layer and the second dielectric layer until the top surface of the first gate structure is exposed to form the first opening.

18. The method for forming a semiconductor structure according to claim 15, 16 or 17, wherein: The method for forming the first isolation structure includes: forming an initial first isolation structure in the first opening, in the isolation opening, on the second dielectric layer, on the first conductive layer, and on the second conductive layer; and flattening the initial first isolation structure until the second dielectric layer, the first conductive layer, and the top surfaces of the second conductive layer are exposed to form the first isolation structure.

19. The method for forming a semiconductor structure according to claim 11, wherein: The conductive structure includes: a first conductive plug and a second conductive plug, the first conductive plug is located on the first region, the second conductive plug is located on the second region, the first conductive plug and the second conductive plug extend along the second direction, and the first opening is located between the first conductive plug and the second conductive plug.

20. The method for forming a semiconductor structure according to claim 19, wherein: The method for forming the first opening, the first conductive plug and the second conductive plug includes: forming a first dielectric layer on the first gate structure; forming the first conductive plug and the second conductive plug in the first dielectric layer, wherein the first conductive plug is located on the first region and the second conductive plug is located on the second region; etching the first dielectric layer until the top surface of the first gate structure is exposed to form the first opening.

21. The method for forming a semiconductor structure according to claim 20, wherein: The method for forming the first isolation structure includes: forming an initial first isolation structure in the first opening, in the isolation opening, on the first dielectric layer, on the first conductive plug, and on the second conductive plug; and flattening the initial first isolation structure until the top surfaces of the first dielectric layer, the first conductive plug, and the second conductive plug are exposed to form the first isolation structure.

22. The method for forming a semiconductor structure according to claim 20, wherein: After forming the first isolation structure, the method further includes: forming a second dielectric layer on the first dielectric layer, the first conductive plug, the second conductive plug and the first isolation structure; forming a first conductive layer and a second conductive layer in the second dielectric layer, wherein the first conductive layer is located on the first conductive plug and the second conductive layer is located on the second conductive plug; etching the second dielectric layer until the top surface of the first isolation structure is exposed, forming a second opening in the second dielectric layer; and forming a second isolation structure in the second opening.

23. The method for forming a semiconductor structure according to claim 14 or 19, wherein: The material of the first conductive plug and the second conductive plug includes metal, and the metal includes one or more combinations of copper, tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

24. The method for forming a semiconductor structure according to claim 14 or 22, wherein: The material of the first conductive layer and the second conductive layer includes metal, and the metal includes one or more combinations of copper, tantalum nitride, tantalum, titanium, titanium nitride, cobalt, ruthenium, ruthenium nitride, tungsten and aluminum.

25. The method for forming a semiconductor structure according to claim 11, wherein: The material of the first isolation structure includes: one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

26. The method for forming a semiconductor structure according to claim 22, wherein: The material of the second isolation structure includes: one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide and aluminum nitride.

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