Hot zone tagging and hot zone outlier detection

Abstract

Methods, devices, and systems for improving read performance under frequently changing device temperature conditions by detecting hot zone tags and hot zone outliers in a memory device. A plurality of hot zones can be configured for the memory device. A first temperature corresponding to opening a storage block of the memory device for programming can be measured. A second temperature corresponding to closing the storage block for programming can subsequently be measured. A range between the first temperature and the second temperature can be determined. The range can span the hot zones for N ≥ 2. Finally, the storage block can be assigned to a hot zone containing the second temperature on condition that N meets a threshold.

Description

Background Technology

[0001] During the operation of electronic memory storage devices, it is desirable to reduce the resource overhead used to manage frequent temperature changes. For example, it is desirable to reduce data regeneration operations whenever the system experiences a cross-temperature event. A "cross-temperature event" refers to an event determined by the temperature difference between an open block and a closed block, or between closing the first block and closing the second block. Cross-temperature events can become particularly problematic under certain operating conditions, such as:

[0002] 1. High amplitude and high or low frequency temperature changes.

[0003] 2. Temperature changes on a small number (relative to the total memory capacity) of frequently accessed programmable memory blocks.

[0004] 3. Temperature changes that occur during frequent power cycles or software or hardware device resets.

[0005] Existing methods mark which blocks or pages are to be flushed based on the write (programming) temperature of the data within them. They maintain a temperature range table for write and read operations and flush data when the write temperature is above or below a predetermined threshold to reduce the bit error rate (BER). However, they prematurely close programmed blocks (before they become full of programmed data) whenever a crossover temperature event is detected. In the presence of high-frequency temperature variations, this can saturate the storage system's management resources, resulting in an overall increase in read / write latency. Summary of the Invention

[0006] This disclosure relates to a method for improving read performance under frequently changing device temperature conditions by detecting hotspot tags and hotspot outliers. Hotspots can be configured for a memory device. A first temperature corresponding to opening a memory block for programming can be measured, and a second temperature corresponding to closing the memory block for programming can be subsequently measured. The range between the first and second temperatures can be determined across hotspots of N≥2. A memory block can be assigned to a hotspot containing the second temperature, provided that N satisfies a threshold.

[0007] This disclosure also relates to an apparatus for improving read performance under frequently changing device temperature conditions by detecting hotspot tags and hotspot outliers. The apparatus may include a non-volatile memory array, a controller, and logic configured to implement the disclosed solution. The logic may measure a first temperature corresponding to opening a memory block of the non-volatile memory array for programming, wherein the first temperature is located within the first of a plurality of pre-configured hotspots. "Pre-configured hotspot" refers to a setting made in the memory device prior to programming the block and associated with a device temperature range. The number and range of these hotspots may be customized according to the specific type of memory and / or memory device.

[0008] The logic can also measure a second temperature corresponding to the shutdown of the memory block for programming, wherein the second temperature is located within the second of the plurality of pre-configured hot zones in the N-hop neighborhood of the first pre-configured hot zone, where N ≥ 1. "N-hop neighborhood" refers to a plurality of neighboring hot zones configured on one or both sides of a particular hot zone. For example, the N-hop neighborhood for zone R may contain only N hot zones adjacent to R at lower temperatures, or it may contain N hot zones adjacent to R and above R and N hot zones adjacent to R and below R. Unless otherwise specified, the term N-hop neighborhood should be understood to include one or both of these options. The logic can then assign the memory block to the second of the pre-configured hot zones. The plurality of pre-configured hot zones can be configured such that memory read parameters for the hot zones in the N-hop neighborhood are compatible.

[0009] This disclosure relates to a system for improving read performance under frequently changing device temperature conditions by detecting hotspot tags and hotspot outliers. The system includes a memory array and a controller. The controller can measure a first temperature when a block of the memory array is open and a second temperature when the block is closed. Given that the range between the first and second temperatures spans 1 ≤ N ≤ M adjacent hotspots among a plurality of pre-configured hotspots, the controller can assign a tag corresponding to one of the pre-configured hotspots containing the second temperature to the block. Finally, the controller can relocate blocks containing the same tag to be adjacent within the memory array. Attached Figure Description

[0010] To facilitate identification of any particular element or action, one or more of the most significant digits in the reference numerals refer to the drawing number in which the element is first introduced.

[0011] Figure 1 This is a block diagram depicting a storage system 100 according to one embodiment.

[0012] Figure 2 This is a block diagram depicting a storage device 200 in one embodiment.

[0013] Figure 3A A memory array 300 according to one embodiment is depicted.

[0014] Figure 3B Additional aspects of a memory array 300 according to one embodiment are described.

[0015] Figure 4 Describe an instance of a programming temperature change of 400°C in a storage device.

[0016] Figure 5 A block marker routine 500 is described according to one embodiment.

[0017] Figure 6A A block marker routine 600a according to one embodiment is described.

[0018] Figure 6B A hot outlier block processing routine 600b is described according to one embodiment.

[0019] Figure 7 A block marker routine 700 according to one embodiment is described.

[0020] Figure 8 A block relocation routine 800 according to one embodiment is described.

[0021] Figure 9A A block marker routine 900a according to one embodiment is described.

[0022] Figure 9B The block marker routine 900b is described according to one embodiment. Detailed Implementation

[0023] Modern electronic storage devices utilize single-level memory cells (SLCs), multi-level memory cells (MLCs), three-level memory cells (TLCs), and four-level memory cells (QLCs) to store programmed data. These types of memory cells, particularly TLCs and QLCs, are sensitive to temperature variations that cross certain thresholds, referred to herein as cross-temperature events. Cross-temperature events can have small or large amplitudes and may occur at low or high frequencies. Existing methods associate hotspot tags with open memory blocks and close all such blocks upon detecting a cross-temperature event (potentially prematurely, before the block is fully programmed). This can, for example, lead to poor utilization of the memory device's storage capacity and increased write amplification. It can also put pressure on memory management resources.

[0024] This document describes embodiments of systems and techniques for managing cross-temperature events and adjusting memory read parameters in a more operationally efficient manner than existing methods (e.g., consuming fewer machine resources, such as processor cycles and memory). Write amplification and read performance can also be improved. Devices utilizing these techniques can adapt to changing temperature conditions faster and more efficiently than existing methods.

[0025] In one embodiment, blocks with common or similar read parameters are logically grouped using a relational table based on the hot zones of the blocks being closed. Programmed blocks are associated with groups based on the hot zone labels assigned to them when they are closed. Blocks are not closed prematurely (before they are fully programmed). Techniques for identifying and relocating thermal outlier blocks are also described. A “thermal outlier block” refers to a block identified as having experienced an extreme cross-temperature event.

[0026] In summary, several hot zone labels are maintained for the programmed block. When block programming is complete (when block is closed), the block is assigned to a hot zone label. Cross-temperature events are monitored and detected. When a temperature change is detected across several (e.g., more than two, and more generally, N) adjacent hot zones, the block is marked as a thermal outlier for priority relocation. "Priority relocation" refers to the removal of data from the block's priority settings.

[0027] For example, several hotspot tags can be dynamically assigned to blocks corresponding to pre-configured programmed temperature ranges that are predictable for the device over time. Each hotspot tag thus associates a closed block with a temperature range. Each hotspot tag is assigned a read parameter that will be applied when reading a block with that tag. Hotspot tags are assigned to blocks based on the temperature measured when the block is closed for programming. If more than two hotspots overlap during the programming of an open block, the block is marked as a thermal outlier. This can trigger the relocation of the block and the association of the block with a specific hotspot tag indicating its outlier state (e.g., triggering a more stringent BER test on the block). The “bit error rate,” or BER, refers to a measurement of the number of erroneous bits out of the total number of bits processed. In some embodiments, the BER is calculated after the Error Correction Code (ECC) decoder has made one or more attempts to correct one or more erroneous bits.

[0028] Table 1 below depicts an exemplary association structure for hot zones and hot zone labels.

[0029]

[0030]

[0031] Table 1: Hot Zone Labels

[0032] During block reading, a second temperature is measured. This temperature can be the ambient temperature of the memory device or the temperature of components of the memory device, such as memory chips or memory dies. Read parameters are obtained from the hotspot tags assigned to the block when the block is closed for programming, and these read parameters are applied when the block is read.

[0033] Hysteresis can be used to manage hot zones to mitigate temperature measurement noise in environments where temperatures change rapidly and / or frequently during block programming. Each hot zone is associated with a set of read parameters. It is assigned the read parameters corresponding to the block's closing temperature when the open block is closed, or associated with an outlier block hot zone if the range between the temperatures measured when the block is opened and when it is closed meets a threshold (e.g., spanning more than N hot zones). Hysteresis is inherent in this process because cross-temperature events occurring between these two measurements do not cause premature block closure.

[0034] In some embodiments, hot zones can be dynamically created such that if a block is closed at a temperature that does not correspond to an existing hot zone, a new hot zone for said temperature can be created due to the closure of the block.

[0035] Unlike existing methods, blocks are not necessarily shut down in the event of cross-temperature events. Instead, the hot zone label assigned to the block is determined by temperature when the block is shut down. The number of managed and / or pre-configured hot zones can vary depending on the implementation and usage of the memory device.

[0036] Blocks programmed to be closed within the same hot zone are assigned the same hot zone label (the hot zone label containing the closing temperature). This means that a block programmed across two (or possibly more) adjacent hot zones will be assigned the same hot zone label as a block programmed in only one hot zone, provided that both blocks are closed within the same hot zone. However, blocks with an on and off temperature range spanning more than N adjacent hot zones (where N can be configured to ≥1) can be treated as thermal outlier blocks. These thermal outlier blocks can be marked for priority relocation (meaning the 'eviction' of data from these blocks to other blocks that are not thermal outlier blocks).

[0037] Therefore, logical groups of blocks can be distinguished based on the hot zone labels assigned to the blocks. Block groups can also be distinguished by secondary stress effects. If an additional stress event is detected on the memory, such as a long power-off cycle or excessive operation at high temperatures (e.g., above 85°C), then blocks programmed after such events will not be assigned the same hot zone labels as those already shut down, even if they are shut down within the hot zone of existing shut-down blocks. In effect, blocks shut down after an additional stress event can be assigned hot zone labels indicating that their state may be less reliable. The hot zone labels assigned to such blocks can be the same hot zone labels used for the blocks being shut down, but with additional markings to indicate that they may have been less reliable than blocks assigned the same hot zone labels before the stress event. Alternatively, such blocks can be identified using the hot zone labels associated with blocks with thermal outliers.

[0038] If the test indication data for this memory block remains erroneous beyond a threshold level after a stress event, the assignment of hot zone tags can be adjusted as described to account for the increased unreliability of the memory. For example, detecting an extreme cross-temperature event can trigger the memory device to schedule this test and update the read parameters associated with all hot zones / hot zone tags. An "extreme cross-temperature event" refers to a cross-temperature event that, for a specific type of memory device and its application, is identified as something that may degrade the reliability or performance of the memory device. This may include detecting that the device temperature is dangerously hot or cold at any time period or threshold time period, or detecting an excessive range between the temperature at which the block is opened and the temperature at which the block is closed. Testing / updating for a specific hot zone tag can occur only after an extreme cross-temperature event when the block is closed in the associated hot zone. In this way, at least for blocks closed after an extreme cross-temperature event, read parameters are maintained and updated after the extreme cross-temperature event. Depending on the implementation, how the programmed memory blocks are organized or distributed, and other factors, some cross-temperature events may not trigger updates to the read parameters.

[0039] Multiple thermal zones can be configured for the memory device. A first temperature corresponding to opening a memory block for programming can be measured. Subsequently, a second temperature corresponding to closing the memory block for programming can be measured. A range between the first and second temperatures can be determined. This range can span thermal zones where N ≥ 2. A memory block can be assigned to a thermal zone containing the second temperature, provided that N satisfies a threshold.

[0040] If N does not meet the threshold, a storage block can be marked as a hot outlier. Marking a storage block as a hot outlier triggers data evacuation from the storage block. "Data evacuation" refers to copying data from one block and programming the copied data into another block. Each of the pre-configured hot zones can have a range of approximately 25°C. Read parameters applicable to storage blocks assigned to a specific hot zone can be specifically applied to the blocks assigned to that hot zone. Hot zones can be configured such that for at least one subset M ≥ 2 of a hot zone, the read parameters for any N neighboring hot zones of subset M are compatible, meaning they can be used to read from blocks assigned to any hot zone in the neighboring group.

[0041] A device comprising a non-volatile memory array, a controller, and logic can be configured to implement the disclosed techniques. The device logic can measure a first temperature corresponding to opening a memory block for programming within the non-volatile memory array, wherein the first temperature is located within a first of a plurality of pre-configured hot zones. The device logic can also measure a second temperature corresponding to closing a memory block for programming, wherein the second temperature is located within a second of the plurality of pre-configured hot zones in an N-hop neighborhood (N≥1) of the first pre-configured hot zone. The device logic can then assign a memory block to the second pre-configured hot zone. The plurality of pre-configured hot zones can be configured such that memory read parameters for the hot zones in the N-hop neighborhood are compatible.

[0042] The device logic also detects cross-temperature events and updates read parameters for one or more pre-configured hotspots as a result. Read parameters can be updated based on conditions where the cross-temperature event is an extreme cross-temperature event. The device logic can test the BER for memory blocks closed after a cross-temperature event, distinguishing between memory blocks closed after and before the cross-temperature event. Memory blocks closed after and before a cross-temperature event can be assigned to the same hotspot but are distinguished from each other. BER testing can be performed based on the condition that a memory block closed after a cross-temperature event is the first memory block closed after the cross-temperature event in a specific hotspot. To distinguish between memory blocks closed after and before a cross-temperature event, a new hotspot label can be created associated with the same hotspot assigned to the memory block closed before the cross-temperature event, but marked to invoke additional read verification on the associated memory block.

[0043] The device logic can deactivate the hotspot tags of blocks programmed before the cross-temperature event, such that a memory block closed after the cross-temperature event cannot be assigned to the hotspot tag of a memory block closed before the cross-temperature event (but is instead assigned to, for example, a hotspot tag for an additional read verification flag). BER testing and differentiation may involve (a) applying read parameters assigned to a memory block closed before the cross-temperature event to read data from a memory block closed after the cross-temperature event, (b) comparing the BERs used for the memory blocks closed before and after the cross-temperature event, and (c) differentiating a memory block closed after the cross-temperature event from a memory block closed before the cross-temperature event if the comparison satisfies a threshold. Differentiating a memory block closed after the cross-temperature event from a memory block closed before the cross-temperature event can be independent of the time interval of the cross-temperature event. For example, in some embodiments, any detection of an extreme cross-temperature event, regardless of its duration, may be sufficient to trigger the differentiation process.

[0044] A system including a memory array and a controller can operate the controller to measure a first temperature when a block of the memory array is opened, measure a second temperature when the block is closed, and assign a hot zone label to the block corresponding to one of a plurality of pre-configured hot zones containing the second temperature. The assignment of hot zone labels for hot zones containing the second temperature can be conditional on the range between the first and second temperatures spanning 1 ≤ N ≤ M adjacent hot zones in the pre-configured hot zones. If this condition is not met, then the block can, for example, be assigned to a hot zone label for a thermal outlier block. The controller can relocate blocks assigned to the same hot zone label to be adjacent within the memory array.

[0045] As mentioned, the controller can mark blocks spanning more than M adjacent hot zones between the first and second temperatures as thermal outlier blocks. The controller can siphon data from thermal outlier blocks with high priority. The controller can detect extreme cross-temperature events. The controller can distinguish, for example, blocks that were closed after an extreme cross-temperature event and assigned a specific hot zone label from blocks that were closed before the extreme cross-temperature event and also have said specific hot zone labels, in a manner previously described. The controller can then relocate blocks with specific labels that were closed after the extreme cross-temperature event to be adjacent in the memory array, unlike blocks with specific labels that were closed before the extreme cross-temperature event. The controller can distinguish between blocks closed before and after an extreme cross-temperature event when the BER (Bit Rate) for the first block closed after the extreme cross-temperature event is worse than the BER for one of the blocks closed before the extreme cross-temperature event.

[0046] Figure 1This is a schematic block diagram illustrating one embodiment of a storage system 100, which can utilize embodiments of the disclosed technology to identify the last programmed memory page in one or more memory blocks. Storage system 100 includes a storage device 200, a storage controller 104, a memory die 116, a host 102, a user application 106, a storage client 108, a logical address space 114, metadata 118, a flash translation layer 124, a data bus 122, a bus 120, at least one host 110, and a network 112.

[0047] A "storage client" refers to any hardware, software, firmware, or logical component or module configured to communicate with a storage device in order to use storage services. Instances of storage clients include, but are not limited to, operating systems, file systems, database applications, database management systems ("DBMS"), server applications, servers, volume managers, kernel-level processes, user-level processes, applications, mobile applications, threads, processes, and the like.

[0048] "Hardware" refers to the functional elements embodied in analog and / or digital circuit systems. "Firmware" refers to the logic embodied as processor-executable instructions stored on volatile and / or non-volatile memory media. "Software" refers to the logic implemented as processor-executable instructions in electronic memory (e.g., reading / writing volatile or non-volatile memory media). "Logic" refers to electronic memory circuitry, non-transitory machine-readable media, and / or circuitry configured by means of its material and / or material energy to contain control and / or programmed signals and / or settings and values ​​(e.g., resistance, impedance, capacitance, inductance, current / voltage ratings, etc.) that can be applied to affect the operation of a device. Magnetic media, electronic circuits, electrical memory, and optical memory (both volatile and non-volatile), as well as firmware, are examples of logic. Logic specifically excludes pure signals or software itself (however, it does not exclude machine memory containing software and thus forming a material configuration). "Volatile memory" is an abbreviation for volatile memory media. In some embodiments, volatile memory refers to volatile memory media and logic, controllers, processors, state machines and / or other peripheral circuitry that manages the volatile memory media and provides access to the volatile memory media.

[0049] A "data block" refers to the smallest physical quantity of storage space on a physical storage medium that can be accessed and / or addressed using storage commands. The physical storage medium can be volatile memory media, non-volatile memory media, persistent storage devices, flash storage media, hard disk drives, or the like. Some conventional storage devices divide the physical storage medium into volumes or logical partitions (also called partitions). Each volume or logical partition can contain multiple sectors. One or more sectors are organized into blocks (also called data blocks). For example, those with... In some storage systems that interface with an operating system, data blocks are called clusters. In other storage systems, such as those that interface with UNIX, Linux, or similar operating systems, data blocks are simply called blocks. A data block or cluster represents the smallest physical quantity of storage space on the storage medium managed by the storage controller. A block storage device associates n data blocks, numbered from 0 to n, with logical block addresses (LBAs) available for user data storage throughout the physical storage medium. In some block storage devices, logical block addresses can range from 0 to n per volume or logical partition. In conventional block storage devices, a logical block address directly maps to one and only one data block. "User data" refers to data stored or recorded on a host-booted non-volatile storage device.

[0050] "Storage operation" refers to an operation performed on a memory cell to change or obtain a data value represented by the state characteristics of the memory cell. Examples of storage operations include (but are not limited to) reading data from a memory cell (or sensing the state of a memory cell), writing data to a memory cell (or programming data), and / or erasing data stored in a memory cell.

[0051] "Storage command" refers to any command related to storage operations. Examples of storage commands include, but are not limited to, read commands, write commands, maintenance commands, diagnostic commands, test mode commands, countermeasure commands, and any other commands that the storage controller may receive from the host or issue to another component, device, or system.

[0052] "Countermeasure" refers to a method, process step, or action configured to mitigate a negative attribute, factor, or condition. It should be noted that in some cases, a feasible countermeasure is not to take action against an identified negative attribute, factor, or condition. While inaction may be considered passive activity, such a response to a negative attribute, factor, or condition is referred to herein as a countermeasure. In some embodiments, a countermeasure is specific to an instruction for a particular problem or issue. Examples of usable countermeasures include actively changing the die temperature of an erase block, relocating data to another storage location, adjusting alarm thresholds, using a separate cell voltage distribution (CVD) table to manage one or more physical erase blocks, and taking no action.

[0053] "Countermeasure command" refers to a storage command configured to implement countermeasures to mitigate or reverse the degradation of storage blocks and / or the health of degraded storage blocks.

[0054] A "characteristic" refers to any property, trait, quality, or attribute of an object or thing. Instances of characteristics include, but are not limited to, condition, readiness for use, unreadiness for use, size, weight, composition, set of features, and the like.

[0055] "Volatile memory medium" refers to a variable physical feature configured to retain binary values ​​representing zero or one, wherein the variable physical feature reverts to a default state where it no longer represents the binary value when main power is removed or unless main power is used to refresh the displayed binary value. Examples of volatile memory media include, but are not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), double data rate random access memory (DDR RAM), or other random access solid-state memories. Although volatile memory media is referred to herein as "memory medium," in various embodiments, volatile memory media may be more generally referred to as volatile memory. In some embodiments, data stored in volatile memory media may be addressed at the byte level, which means that data in volatile memory media is organized into data bytes (8 bits), each having a unique address (e.g., a logical address).

[0056] "Memory" means any hardware, circuit, component, module, logic, device, or apparatus configured, programmed, designed, arranged, or engineered to hold data. Some types of memory require a constant power supply to store and retain data. Other types of memory retain and / or store data when power is unavailable.

[0057] "Uncorrectable BER" ​​refers to a measure of the ratio of the number of uncorrectable and erroneous bits to a given number of bits being processed. Uncorrectable bits are considered uncorrectable after trying one or more error correction techniques (e.g., using error-correcting codes (ECC), using Bose, Chaudhuri, Hocquenghem (BCH) codes, using low-density parity-check (LDPC) algorithms, and the like).

[0058] A "failure bit count" is a measurement of the number of erroneous bits for a given unit of measurement. An erroneous bit is a bit stored as a value, but when the same bit is read or sensed, it indicates a different value. Failure bit counts can be measured for data blocks (e.g., 4K), erase blocks, pages, logical erase blocks, regions, namespaces, or the like. In other words, a failure bit count can be the number of distinct bits between data written to a data block, physical erase block, or other memory unit group and data subsequently read from that data block, physical erase block, or other memory unit group.

[0059] Storage system 100 includes at least one storage device 200 connected by bus 120, including storage controller 104 and one or more memory dies 116. In some embodiments, storage system 100 may include two or more storage devices. "Storage device" means any hardware, system, subsystem, circuit, component, module, non-volatile memory medium, hard disk drive, storage array, apparatus, or device configured, programmed, designed, or engineered to store data for a period of time and to retain data in the storage device when the storage device is not using power from a power source. Examples of storage devices include, but are not limited to, hard disk drives, flash memory, MRAM memory, solid-state storage devices, j-board clusters (JBOD), j-board clusters (JBOF), external hard disks, internal hard disks, and the like.

[0060] A "memory die" refers to a small piece of semiconductor material on which a given functional circuitry is fabricated. Typically, integrated circuits are mass-produced on a single wafer of electronic-grade silicon (EGS) or other semiconductors (e.g., GaAs) through processes such as photolithography. The wafer is diced (divided) into many pieces, each containing a copy of the circuitry. Each of these pieces is called a die or memory die. (Search "die (integrated circuit)" on Wikipedia.com, accessed October 9, 2019, November 18, 2019.) In one embodiment, a memory die is a die containing one or more functional circuitries for operation as a non-volatile memory medium and / or an array of non-volatile memory.

[0061] "Non-volatile memory medium" refers to any hardware, device, component, element, or circuit configured to maintain a changeable physical characteristic used to represent a binary value of zero or one after the main power supply is removed. Examples of changeable physical characteristics include, but are not limited to, the threshold voltage of a transistor, the resistance level of a memory cell, the current level through a memory cell, magnetic pole orientation, spin-transfer torque, and the like. The changeable physical characteristics are such that, once set, the physical characteristics remain sufficiently fixed so that the variable physical characteristics can be measured, detected, or sensed when reading, retrieving, or sensing binary values ​​when the main power supply for the non-volatile memory medium is unavailable. In other words, a non-volatile memory medium is a storage medium configured such that data stored on the non-volatile memory medium can be retrieved after the power supply for the non-volatile memory medium has been removed and subsequently restored. A non-volatile memory medium may contain one or more non-volatile memory elements, which may include, but are not limited to, chips, packages, planes, memory dies, and the like. Examples of non-volatile memory media include, but are not limited to: ReRAM, memristor memory, programmable metallized cell memory, phase-change memory (PCM, PCME, PRAM, PCRAM, bidirectional universal memory, chalcogenide RAM, or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nanometer random access memory (nanometer RAM or NRAM), nanowire-based memory, silicon-oxide-based sub-10 nanometer processing memory, graphene memory, silicon-oxide-nitride-oxide-silicon (SONOS), programmable metallized cell (PMC), conductive bridged RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disk, magnetic tape), optical storage media, or the like. Although non-volatile memory media are referred to herein as “memory media,” in different embodiments, non-volatile memory media may be more generally referred to as non-volatile memory. Because non-volatile memory media can store data when power is removed, they are also referred to as recording media, non-volatile recording media, non-volatile storage media, storage devices, non-volatile memory, volatile memory media, non-volatile memory medium, non-volatile storage devices, or the like. In some embodiments, data stored in a non-volatile memory medium can be addressed at the block level, meaning that the data in the non-volatile memory medium is organized into data blocks, each with a unique logical address (e.g., LBA). In other embodiments, data stored in a non-volatile memory medium can be addressed at the byte level, meaning that the data in the non-volatile memory medium is organized into data bytes (8 bits), each with a unique address (e.g., logical address). An example of a byte-addressable non-volatile memory medium is a storage class memory (SCM).

[0062] "Non-volatile storage medium" means any hardware, device, component, element, or circuit configured to retain a changeable physical characteristic for representing a binary value of zero or one after the removal of mains power. The term "non-volatile storage medium" is used interchangeably with the term "non-volatile memory medium" herein.

[0063] "Non-volatile memory" is an abbreviation for non-volatile memory medium. In some embodiments, non-volatile memory medium refers to non-volatile memory medium and logic, controllers, processors, state machines, and / or other peripheral circuitry that manages the non-volatile memory medium and provides access to the non-volatile memory medium.

[0064] A "non-volatile memory array" refers to a collection of non-volatile memory cells (also called memory cells or non-volatile memory units) organized into an array structure with rows and columns. Memory arrays can be addressed using row identifiers and column identifiers.

[0065] A "memory cell" refers to a type of storage medium configured to represent one or more binary values ​​by means of the determinable physical characteristics of the storage medium when sensing, reading, or detecting the storage medium to determine the binary value last stored in the memory cell. The terms "memory cell" and "storage unit" are used interchangeably herein.

[0066] A “memory cell” refers to a type of storage medium configured to represent one or more binary values ​​by means of a determinable characteristic of the storage medium when sensing, reading, or detecting the storage medium to determine the binary value stored or represented by the determinable characteristic of the memory cell. The terms “memory cell” and “memory unit” are used interchangeably herein. The type of determinable characteristic used to store data in a memory cell can vary depending on the type of memory or storage technology used. For example, in a flash memory cell in which each memory cell contains a transistor having a source lead, a drain lead, and a gate, a determinable characteristic is the voltage level that causes the memory cell to conduct current between the drain and source leads when applied to the gate. In this example, the voltage level is referred to herein as the threshold voltage. The threshold voltage may also be referred to as the control gate reference voltage (CGRV), the read voltage, or the reference voltage. Examples of determinable physical characteristics include, but are not limited to, the threshold voltage of a transistor, the resistance level of the memory cell, the current level through the memory cell, magnetic pole orientation, spin-transfer torque, etc. The terms “memory cell” and “memory unit” are used interchangeably herein. "Threshold voltage" refers to the voltage level that allows the transistor to conduct current between the drain and source electrodes when applied to the gate electrode.

[0067] Each storage device 200 may include two or more memory dies 116, such as flash memory, nanometer random access memory (“nano RAM or NRAM”), magnetoresistive RAM (“MRAM”), dynamic RAM (“DRAM”), phase-change RAM (“PRAM”), etc. In other embodiments, data storage device 200 may include other types of non-volatile and / or volatile data storage devices, such as dynamic RAM (“DRAM”), static RAM (“SRAM”), magnetic data storage devices, optical data storage devices, and / or other data storage technologies. Memory dies 116 may be configured in a non-volatile memory array 126. A “memory array” refers to a collection of memory cells (also called memory units) organized into an array structure with rows and columns. Memory arrays can be addressed using row identifiers and column identifiers.

[0068] Therefore, a nonvolatile memory array is a memory array having memory cells configured such that the characteristics of the memory cells used to represent the stored data (e.g., threshold voltage level, resistance level, conductivity, etc.) remain the properties of the memory cells without the need for a power supply to maintain those characteristics.

[0069] Memory arrays can be addressed using row identifiers and column identifiers. Those skilled in the art will recognize that a memory array can comprise a set of memory cells within a plane, a set of memory cells within a memory die, a set of memory cells within a plane set, a set of memory cells within a set of memory dies, a set of memory cells within a memory package, a set of memory cells within a memory package set, or have other known memory cell set architectures and configurations. A "plane" refers to a partition of a die that allows certain memory operations to be performed on two planes using certain physical row addresses and certain physical column addresses.

[0070] A memory array can comprise a collection of memory cells at several organizational levels within a storage or memory system. In one embodiment, in-plane memory cells can be organized into a memory array. In one embodiment, multiple in-plane memory cells of a memory die can be organized into a memory array. In one embodiment, memory cells within multiple memory dies of a memory device can be organized into a memory array. In one embodiment, memory cells within multiple memory devices of a storage system can be organized into a memory array.

[0071] Storage device 200 (also referred to herein as a storage device) may be a component within host 102 as depicted herein and may be connected using data bus 122, such as a Peripheral Component Interconnect High Speed ​​(“PCI-e”) bus, a Serial Advanced Technology Attachment (“Serial ATA”) bus, or the like. In another embodiment, storage device 200 is external to host 102 and connected to a Universal Serial Bus (“USB”) connection, an Institute of Electrical and Electronics Engineers (“IEEE”) 1394 bus (“FireWire”), etc. In other embodiments, storage device 200 is connected to host 102 using an external electrical or optical bus extension or bus networking solution such as Unlimited Bandwidth or PCI High Speed ​​Advanced Switching (“PCIe-AS”) using a Peripheral Component Interconnect (“PCI”) High Speed ​​bus.

[0072] In various embodiments, the storage device 200 may be in the form of a dual in-line memory module (“DIMM”), daughter card, or micromodule. In another embodiment, the storage device 200 is a component within a rack-mount blade. In yet another embodiment, the storage device 200 is contained within a package directly integrated into a higher-level assembly (e.g., a motherboard, laptop computer, graphics processor). A “processor” refers to any circuit system, component, chip, die, package, or module configured to receive, interpret, decode, and execute machine instructions. Examples of processors may include (but are not limited to) central processing units, general-purpose processors, special-purpose processors, graphics processing units (GPUs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), system-on-a-chip (SoCs), virtual processors, processor cores, etc. In another embodiment, individual components including the storage device 200 are directly integrated into a higher-level assembly without intermediate packaging.

[0073] In another embodiment, the data storage device 200 may be connected to the host 102 via a data network, rather than being directly connected to the host 102 as a DAS. For example, the data storage device 200 may include a storage area network (“SAN”) storage device, a network attached storage (“NAS”) device, a network share, etc. In one embodiment, the storage system 100 may include a data network, such as the Internet, a wide area network (“WAN”), a metropolitan area network (“MAN”), a local area network (“LAN”), a token ring, a wireless network, a Fibre Channel network, a SAN, NAS, ESCON, etc., or any combination of networks. The data network may also include networks from the IEEE 802 family of network technologies, such as Ethernet, token ring, Wi-Fi, Wi-Max, and the like. The data network may include servers, switches, routers, cables, wireless equipment, and other devices for facilitating networking between the host 102 and the data storage device 200.

[0074] Storage system 100 includes at least one host 102 connected to storage device 200. "Host" means any computing device or computer apparatus or computer system configured to send and receive storage commands. Examples of hosts include, but are not limited to, computers, laptops, mobile devices, electrical appliances, virtual machines, enterprise servers, desktop computers, tablet computers, mainframes, and the like.

[0075] Multiple hosts 102 may be used and may include: servers, storage controllers of storage area networks (“SANs”), workstations, personal computers, laptops, handheld computers, supercomputers, computer clusters, network switches, routers or home appliances, databases or storage devices, data acquisition or data capture systems, diagnostic systems, testing systems, robots, portable electronic devices, wireless devices, or the like. In another embodiment, host 102 may be a client, and storage device 200 may operate autonomously to serve data requests sent from host 102. In this embodiment, computer networks, system buses, direct-attached storage (DAS), or other communication components suitable for connecting a computer to autonomous storage device 200 may be used to connect host 102 and storage device 200.

[0076] The depicted embodiments illustrate user application 106 communicating with storage client 108 (as part of host 102). In one embodiment, user application 106 is a software application that operates on or in conjunction with storage client 108.

[0077] Storage client 108 manages files and data and utilizes the functionality and features of storage controller 104 and associated memory die 116. Representative examples of storage clients include, but are not limited to, servers, file systems, operating systems, database management systems (“DBMS”), volume managers, and the like. Storage client 108 communicates with storage controller 104 within storage device 200. In some embodiments, storage client 108 may include a remote storage client operating on host 110 or otherwise accessible via network 112. Storage clients may include, but are not limited to, operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.

[0078] Storage client 108 may present logical address space 114 to host 102 and / or user application 106. Logical address space 114 may contain multiple (e.g., a series) logical addresses. As used herein, a logical address refers to any identifier used to reference memory resources (e.g., data), including but not limited to logical block address (LBA), cylinder / head / sector (CHS) address, filename, object identifier, inode, universally unique identifier (UUID), globally unique identifier (GUID), hash code, signature, index entry, range, degree, or the like.

[0079] A "logical address space" refers to the logical representation of a memory resource. A logical address space may contain multiple (e.g., a series) logical addresses. A "logical address" is any identifier used to reference a memory resource (e.g., data), including but not limited to logical block addresses (LBAs), cylinder / head / sector (CHS) addresses, filenames, object identifiers, inodes, universally unique identifiers (UUIDs), globally unique identifiers (GUIDs), hash codes, signatures, index entries, ranges, degrees, or the like. A logical address does not indicate the physical location of data on the storage medium, but rather an abstract reference to the data. A "logical block address" is the value associated with the address of each of n logical blocks in a block storage device that are used to make user data available throughout the storage medium. In some block storage devices, logical block addresses (LBAs) can range from 0 to n per volume or partition. In a block storage device, each LBA directly maps to a specific data block, and each data block maps to a specific set of physical sectors on the physical storage medium.

[0080] In one embodiment, the device driver of host 102 (and / or storage client 108) may maintain metadata 118 within storage client 108, such as a logical-to-physical address mapping structure, to map logical addresses of logical address space 114 to storage locations on memory die 116. In another embodiment, such metadata 118 may be stored and maintained by storage controller 104. The device driver may be configured to provide storage services to one or more storage clients.

[0081] Storage client 108 may include a flash translation layer 124. A "flash translation layer" refers to the logic within a flash memory device that includes an abstract logic-to-physical address translation that provides logical block addresses (LBAs) used by the storage client and physical block addresses where the storage controller stores data. The logic-to-physical translation layer maps logical block addresses (LBAs) to the physical addresses of data stored on the solid-state storage medium. This mapping allows data to be referenced in the logical block address space using logical identifiers, such as block addresses. The logical identifiers do not indicate the physical location of the data on the solid-state storage medium, but rather are abstract references to the data.

[0082] Flash translation layer 124 receives processed data and one or more control signals to determine the flash translation layer queue depth. Flash translation layer 124 may determine appropriate physical addresses to send data and commands to memory die 116 and volatile memory. In some embodiments, storage client 108 may include flash translation layer 124 and manage metadata 118 associated with flash translation layer 124. In one embodiment, flash translation layer 124 also receives data output from memory die 116.

[0083] In one embodiment, storage system 100 includes one or more clients connected to one or more hosts 110 via one or more computer networks 112. Host 110 may be: a server, a storage controller for a SAN, a workstation, a personal computer, a laptop computer, a handheld computer, a supercomputer, a computer cluster, a network switch, a router or home appliance, a database or storage device, a data acquisition or data capture system, a diagnostic system, a testing system, a robot, a portable electronic device, a wireless device, or the like. Network 112 may include the Internet, a wide area network (“WAN”), a metropolitan area network (“MAN”), a local area network (“LAN”), a token ring, a wireless network, a Fibre Channel network, a SAN, network-attached storage (“NAS”), ESCON, etc., or any combination of networks. Network 112 may also include networks from the IEEE 802 family of network technologies, such as Ethernet, token ring, WiFi, WiMax, and the like.

[0084] Network 112 may include servers, switches, routers, cables, radios, and other instruments used to facilitate networking of host 102 or a host with host 110 or a client. In one embodiment, storage system 100 includes multiple hosts communicating as peers via network 112. In another embodiment, storage system 100 includes multiple memory devices communicating as peers via network 112. Those skilled in the art will recognize other computer networks that include one or more computer networks and associated instruments having single or redundant connections between one or more clients, or other computers having one or more memory devices or one or more memory devices connected to one or more hosts. In one embodiment, storage system 100 includes two or more memory devices connected to host 110 via network 112 without host 102.

[0085] In one embodiment, storage client 108 communicates with storage controller 104 via a host interface that includes input / output (I / O) interfaces. For example, storage device 200 may support ATA interface standards, ATA Packet Interface (“ATAPI”) standards, Small Computer System Interface (“SCSI”) standards, and / or Fibre Channel standards maintained by the International Committee for Information Technology Standards (“INCITS”).

[0086] In some embodiments, the storage medium of the memory device is divided into volumes or partitions. Each volume or partition may contain multiple sectors. Traditionally, a sector is 512 bytes of data. One or more sectors are organized into blocks (which are interchangeably referred to herein as both blocks and data blocks).

[0087] In one example embodiment, the data block contains eight sectors, and the block is 4KB. For example, those with... In some storage systems that interface with an operating system, a data block is called a cluster. In other storage systems, such as those that interface with UNIX, Linux, or similar operating systems, a data block is simply called a block. A block, data block, or cluster represents the smallest physical quantity of storage space on a storage medium managed by a storage manager, such as a storage controller, storage system, storage unit, storage device, or the like.

[0088] In some embodiments, the storage controller 104 may be configured to store data on one or more asymmetric write-once storage media (e.g., solid-state storage cells within the memory die 116).

[0089] "Write-once storage medium" refers to a storage medium, such as a memory cell, that must be reinitialized (e.g., erased) before new data is written or programmed onto it or before any changes are made to the data. In other words, data on a write-once storage medium cannot be overwritten, and the medium must be erased before any subsequent data is written to it.

[0090] A "read scan operation" refers to a maintenance operation performed to identify, mitigate, avoid, or count errors in data or memory cells and / or other components of a non-volatile storage device. Read scan operations are interchangeably referred to as "read scans" or "read scan operations." In one embodiment, a read scan operation involves reading data from memory cells in a memory block, or sensing the determinable physical characteristics or memory state of said memory cells. Next, the read scan operation checks the memory state of the memory cells for any errors, corrects as many errors as possible, and determines the BER (Bit Rate). Subsequently, the read scan operation determines whether the BER meets a threshold, such as a read BER threshold. In one embodiment, the read scan operation reads data from each logical page or word line of the memory block. In another embodiment, the read scan operation selects less than all logical pages of the memory block. In other words, the read scan operation may sample logical pages of the memory block from which data is read for the read scan operation. If the read BER threshold is met, the read scan operation may perform a data cleanup operation or a data refresh operation. In some embodiments, a read scan operation may always include a data cleanup operation or a data refresh operation. In other embodiments, performing a data cleanup operation or a data refresh operation may be conditional upon the BER meeting the read BER threshold. In this embodiment, the read scan operation may be referred to as a "read cleanup" or "read cleanup operation." In these embodiments, the read scan operation may conditionally include data cleanup operations. In some embodiments, the read scan operation may operate as a foreground process, meaning that the read scan operation interrupts or delays the non-volatile storage device's service to host read or write commands. Furthermore, the read scan operation may need to complete work on a specific storage block, thereby delaying host read commands for data on said specific storage block. Therefore, the read scan operation may affect the quality of service (QoS) level between the host and the non-volatile storage device.

[0091] As used herein, an "asymmetric" storage medium refers to a storage medium that has different latency for different storage operations. Many types of solid-state storage media (e.g., memory dies) are asymmetric; for example, a read operation may be much faster than a write / programming operation, and a write / programming operation may be much faster than an erase operation (e.g., a read storage medium may be hundreds of times faster than an erase and tens of times faster than a program storage medium). The memory die 116 may be partitioned into memory partitions (e.g., erase blocks) that can be erased as groups to take into account, in particular, the asymmetric nature of the memory die 116 or the like.

[0092] Therefore, modifying a single data segment in situ may involve erasing the entire erase block containing the data and rewriting the modified data along with the original, unchanged data to the erase block. This can result in inefficient write amplification, potentially causing excessive wear on the memory die 116. "Write amplification" refers to a measurement of write programming operations performed on a non-volatile memory device that results in any data and (specifically) user data being written more times than initially written in the first case. In some embodiments, write amplification may count the number of write operations performed by the non-volatile memory device to manage and maintain the data stored on the non-volatile memory device. In other embodiments, write amplification measures the amount of data, or the number of bits, written beyond the initial storage of data on the non-volatile memory device.

[0093] Therefore, in some embodiments, the storage controller 104 may be configured to write data off-site. As used herein, “off-site” data writing means writing data to a different media storage location, rather than overwriting data “in-situ” (e.g., overwriting the initial physical location of the data). Off-site data modification avoids write amplification because it is not necessary to erase and re-copy existing valid data on the erase block containing the data to be modified. “Valid data” refers to data in a storage block that is stored by the host and should be retained and maintained until the host indicates that the data is no longer needed and can or should be deleted. Furthermore, off-site data writing removes the erase operation from the latency path of many storage operations (e.g., the erase latency is no longer part of the main path of the write operation).

[0094] The storage manager manages data blocks, specifically addressing specific data blocks for read, write, or sustain operations. A block storage device associates n blocks, numbered from 0 to n, with logical addresses that can be used to store user data across the storage medium. In some block storage devices, logical addresses can range from 0 to n per volume or partition.

[0095] In conventional block storage devices, logical addresses are directly mapped to specific data blocks on the physical storage medium. In conventional block storage devices, each data block is mapped to a specific set of physical sectors on the physical storage medium. However, some storage devices do not directly or necessarily associate logical addresses with specific physical data blocks. These storage devices can emulate conventional block storage interfaces to maintain compatibility with block storage client 108.

[0096] In one embodiment, the storage controller 104 provides a block I / O emulation layer, which acts as a block device interface or API. In this embodiment, the storage client 108 communicates with the storage device via this block device interface. In one embodiment, the block I / O emulation layer receives commands and logical addresses from the storage client 108 according to this block device interface. Therefore, the block I / O emulation layer provides compatibility between the storage device and the block storage client 108.

[0097] In one embodiment, storage client 108 communicates with storage controller 104 via a host interface that includes a direct interface. In this embodiment, the storage devices directly exchange information specific to the non-volatile storage device. A “non-volatile storage device” refers to any hardware, apparatus, component, element, or circuitry configured to maintain changeable physical characteristics used to represent binary values ​​of zero or one after the mains power is removed. Examples of non-volatile storage devices include, but are not limited to, hard disk drives (HDDs), solid-state drives (SSDs), non-volatile memory media, and the like.

[0098] Storage devices using a direct interface can store data in memory die 116 using a variety of organizational structures, including (but not limited to) blocks, sectors, pages, logical blocks, logical pages, erase blocks, logical erase blocks, ECC codewords, logical ECC codewords, or any other format or structure that is advantageous to the technical characteristics of memory die 116.

[0099] The storage controller 104 receives logical addresses and commands from the storage client 108 and performs corresponding operations relative to the memory die 116. The storage controller 104 may support block I / O emulation, direct interface, or both. "Storage controller" refers to any hardware, device, component, element, or circuitry configured to manage data operations on a non-volatile memory medium, and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, or the like. In some embodiments, the storage controller is configured to store data on and / or read data from a non-volatile memory medium to transfer data to / from a non-volatile memory device, etc.

[0100] Figure 2 This is a block diagram of storage device 200. Storage device 200 may include storage controller 104 and non-volatile memory array 126. Each memory die 116 in non-volatile memory array 126 may include die controller 202 and at least one memory cell array 210 in the form of a three-dimensional array, as well as read / write circuitry 214.

[0101] The memory controller 104 and / or die controller 202 may be incorporated into the logic 218 that implements the disclosed solution. "Die controller" refers to control logic dedicated to a specific memory die. The die controller may be discrete logic (e.g., different circuitry or circuit package) or may be a subset of logic within a more general memory controller.

[0102] The memory cell array 210 is addressable via word lines corresponding to rows via row decoder 212 and via bit lines via column decoder 216. A "word line" refers to a structure within the memory array containing a set of memory cells. The memory array is configured such that operational memory cells of a word line are read or sensed during a read operation. Similarly, the memory array is configured such that operational memory cells of a word line are read or sensed during a read operation.

[0103] The read / write circuitry 214 includes multiple sensing blocks SB1, SB2, ..., SBp (sensing circuitry) that enable parallel reading or programming of memory cell pages. "Parallel" refers to two or more operations that overlap in time. Parallel operations include (but are not limited to) operations that are co-latent in time, and also refer to operations that overlap at any time interval. In some embodiments, each memory cell across a row of the memory array forms a physical page together.

[0104] A “bit line” refers to a circuit structure configured to deliver voltage and / or conduct current to a column of a memory array. In one embodiment, the column comprises a NAND string or a memory string and may also be referred to as a channel. In one embodiment, the column is referred to as a NAND string and the NAND string comprises a channel. In one embodiment, the bit line is connected to the NAND string at the drain terminal or drain side. The memory array may have one bit line for each memory cell along the word lines of the memory array.

[0105] A physical page may contain memory cells for a single plane or for a single memory die along a row of a memory array. In one embodiment, a memory die comprises a memory array consisting of two planes of equal size. In one embodiment, a physical page of one plane of a memory die contains four data blocks (e.g., 16KB). In one embodiment, a physical page of a memory die (also referred to as a "die page") comprises two planes, each containing four data blocks (e.g., 32KB).

[0106] Commands and data that cause storage operation 128 to occur are transmitted between host 102 and storage controller 104 via data bus 122 and between storage controller 104 and one or more memory dies 116 via bus 120.

[0107] The memory cell array 210 can be two-dimensional (2D arrangement in a single manufacturing plane) or three-dimensional (3D arrangement in multiple manufacturing planes). The memory cell array 210 may include one or more arrays of memory cells comprising a 3D array. In one embodiment, the memory cell array 210 may include a monolithic three-dimensional memory structure (3D array) where multiple memory levels are formed on (and not in) a single substrate, such as a wafer, without any intervening substrate. The memory cell array 210 may include any type of non-volatile memory monolithically formed in one or more physical levels of a memory cell array having an operational region disposed on a silicon substrate. The memory cell array 210 may be in a non-volatile solid-state driver having circuitry associated with the operation of the memory cells (whether the associated circuitry is on or within the substrate).

[0108] "Circuit system" means a circuit system having at least one discrete circuit, a circuit system having at least one integrated circuit, a circuit system having at least one application-specific integrated circuit, a circuit system forming a general-purpose computing device configured by a computer program (e.g., a general-purpose computer configured by a computer program that performs at least part of the processes or devices described herein, or a microprocessor configured by a computer program that performs at least part of the processes or devices described herein), a circuit system forming a memory device (e.g., in the form of random access memory), or a circuit system forming a communication device (e.g., a modem, a communication switch, or an optoelectronic instrument).

[0109] Word lines may comprise segments of layers containing memory cells disposed above a substrate. Multiple word lines may be formed on a single layer by means of trenches or other non-conductive isolation features.

[0110] The die controller 202 cooperates with the read / write circuitry 214 to perform memory operations on the memory cells of the memory cell array 210, and includes a state machine 204, an address decoder 206, and power control 208. The state machine 204 provides chip-level control of memory operations.

[0111] Address decoder 206 provides an address interface between the address interface used by the host or storage controller 104 and the hardware address used by row decoder 212 and column decoder 216. Power control 208 controls the power and voltage supplied to various control lines during memory operation. Power control 208 and / or read / write circuitry 214 may include drivers for word lines, source-gate select (SGS) transistors, drain-gate select (DGS) transistors, bit lines, substrate (in a 2D memory structure), charge pumps, and source lines. In some embodiments, power control 208 may detect sudden power failures and take preventative action. Power control 208 may include various first voltage generators (e.g., drivers) to generate the voltages described herein. In one approach, a sensing block may include bit line drivers and sensing amplifiers.

[0112] In some implementations, some of the components may be combined. In various designs, in addition to the memory cell array 210, one or more of the components (alone or in combination) may be considered as at least one control circuit or memory controller configured to perform the techniques described herein. For example, the control circuit may include any one or a combination of the following: die controller 202, state machine 204, address decoder 206, column decoder 216, power control 208, sense blocks SB1, SB2, ..., SBp, read / write circuitry 214, memory controller 104, etc.

[0113] In one embodiment, host 102 is a computing device (e.g., laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming storage controller 104 to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces and / or one or more input / output devices for communicating with one or more processors, and other components well known in the art.

[0114] Associated circuitry is typically used for the operation of memory cells and for communicating with memory cells. As a non-limiting example, a memory device may have circuitry for controlling and driving memory cells to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory cells and / or on a separate substrate. For example, a memory controller for memory read / write operations may be located on a separate memory controller chip and / or positioned on the same substrate as the memory cells.

[0115] Those skilled in the art will recognize that the disclosed techniques and apparatus are not limited to the described two-dimensional and three-dimensional exemplary structures, but encompass all relevant memory structures as described herein and as understood by those skilled in the art.

[0116] Figure 3A A memory array 300 is depicted according to one embodiment. In the illustrated embodiment, the memory array 300 is organized into logical erase blocks (LEBs) as illustrated by logical erase block 317 (also referred to herein as “meta-blocks”, “superblocks”, or “memory meta-blocks”). A “memory meta-block” refers to a block spanning multiple memory dies and / or memory planes. These LEBs contain multiple physical erase blocks (PEBs) illustrated by physical erase block 0 304, physical erase block n 306, physical erase block 0 307, physical erase block n 310, physical erase block 0 311, and physical erase block n 314. A “physical erase block” refers to the smallest memory cell within a given memory die that can be erased at a given time (e.g., due to wiring of memory cells on the memory die).

[0117] Physical erase blocks can be located in individual memory dies, illustrated as die 0 301, die 1 302, and die n 303. In some embodiments, the dies are divided into planes. A plane can be understood as a partition of the die that allows certain memory operations to be performed in parallel using certain physical row addresses and certain physical column addresses.

[0118] Those skilled in the art understand the relationship and differences between physical erase blocks and logical erase blocks, and that one or both can be referred to by the shorthand terms erase block, block, or storage block. Those skilled in the art understand from the context in which an erase block is mentioned that it refers to a physical erase block or a logical erase block (or meta-block or superblock). The concepts and techniques used in the art and the concepts and techniques set forth in the claims are equally applicable to physical erase blocks or logical erase blocks.

[0119] "Erase block" refers to either a logical erase block or a physical erase block. In one embodiment, a physical erase block represents the smallest memory cell within a given memory die that can be erased at a given time (e.g., due to wiring of memory cells on the memory die). In one embodiment, a logical erase block represents the smallest memory cell or block that can be erased by a memory controller in response to receiving an erase command. In this embodiment, when the memory controller receives an erase command specifying a particular logical erase block, the memory controller can erase each physical erase block within the logical erase block simultaneously. It should be noted that physical erase blocks within a given logical erase block can be considered contiguous in the physical address space, even if they reside on separate dies. Therefore, the term "contiguous" can be applied not only to data stored on the same physical medium but also to data stored on separate media. "Simultaneously" refers to any parallel or partially parallel operations in time.

[0120] A “memory block” refers to a group of memory cells organized such that storage operations can be performed on the group of memory cells in parallel. This organization of memory cells can be implemented at the physical or logical level. Thus, in one embodiment, a memory block may include, for example, physical pages of word lines, logical pages containing physical pages spanning a plane and / or memory die, a physical erase block containing a set of physical pages, a logical erase block (LEB) containing a set of logical pages, or the like. A memory block may be referred to herein as a “block,” a “memory block,” or an LEB.

[0121] As used herein, a “physical” structure, such as a physical page, physical word line, physical erase block, physical plane, physical memory die, or the like, refers to a single physical structure that a system’s controller, manager, module, or other logical component can control and / or communicate at one or more levels within a physical abstraction of the organization of a device, system, or equipment. Similarly, a “logical” structure, such as a logical page, logical word line, logical erase block, logical plane, logical memory die, or the like, refers to a single physical structure of the same type that a system’s controller, manager, module, or other logical component can control and / or communicate at one or more levels within a physical abstraction of the organization of a device, system, or equipment. It should be noted that one or the other, or both, of a “physical” structure and a “logical” structure may have distinct addresses that can be used to identify a “physical” structure or a “logical” structure relative to other structures of similar nature and type.

[0122] "Logical erase block" is another term for a memory block. In some embodiments, a logical erase block refers to a collection of logical pages spanning a plane, memory die, and / or chip. Because physical pages may not be directly coupled to each other, this organization of memory cells is considered 'logical'. However, physical pages are operated on in parallel as if they were single pages. Similarly, multiple physical erase blocks can be operated on in parallel as if they were single erase blocks, and are therefore called logical erase blocks. The terms logical erase block, meta-block, and superblock are used interchangeably herein. A "logical page" refers to a collection of physical pages that are considered as single pages for memory operations. A "physical page" means that a physical page represents the smallest block of memory within a given memory die that can be written to in a single operation.

[0123] For example, the logical erase block 317 is further divided into multiple logical pages (logical pages 316), which in turn contain multiple physical pages, such as physical page 0 305, physical page n 308, physical page 0 309, physical page n 312, physical page 0 313, and physical page n 315. A physical page may contain multiple packets, which can be grouped into error correction code (ECC) blocks.

[0124] In one embodiment, a physical page represents the smallest block of storage within a given die that can be written to at a given time. In one embodiment, a logical page is the smallest writable block of storage supported by a storage controller. (In one embodiment, the storage controller may include a buffer configured to store up to one logical page of data; as the buffer is filled, the storage controller may write the contents of the buffer to a single logical page in parallel.) In some cases, when accessing multiple dies in parallel, partitioning logical pages across multiple dies can result in faster access times for the data set. Logical pages can be configured to map to any physical page on a die or across multiple memory dies, just like logical erase blocks.

[0125] In some embodiments, the storage controller 104 may associate metadata (also known as media characteristics) with one or more of storage blocks (logical erase blocks, physical erase blocks, logical pages, and / or physical pages). "Media characteristics (erase)" refers to an attribute or statistic of a particular set of storage cells, such as the programming / erasing cycle count of the storage cell set, the read count of the storage cell set, the retention time since the previous write to the storage cell set (also known as data retention time), the dwell time of the storage cell set for example, logical or physical erase blocks (e.g., the time between programming an erase block and erasing an erase block), the average of multiple previous dwell times of the storage cell set, error statistics of the storage cell set, or the like. The media characteristics of a set of storage cells may be substantially static or dynamic and change over time. In one embodiment, media characteristics are statistics, heuristics, mathematical models, transformations, or other descriptors associated with the properties of a non-volatile memory medium. In one embodiment, media characteristics include or relate to the brand, model, manufacturer, product version, or the like of the storage device and / or non-volatile memory medium. In another embodiment, media characteristics may include or relate to the environmental conditions or use of the storage device and / or the non-volatile memory media, such as temperature, use cases (e.g., cache use cases, archive use cases, server use cases, enterprise use cases, consumer use cases, etc.) or the like. Storage controller 104 can manage metadata identifying the logical addresses of logically erased block storage data, and logical address space 114 ( Figure 1 The storage controller 104 stores a corresponding number of stored data packets for each logical erase block, data block, or sector within the storage. The storage controller 104 may store metadata or media characteristic data in various locations, including on non-volatile storage media, in volatile memory, in a structure stored with each logical erase block, or the like.

[0126] "Metadata" refers to system data that can be used to facilitate the operation of non-volatile storage devices. Metadata contrasts with data such as data generated by applications (i.e., "application data"), data generated by users, hosts, or data that the operating system will treat as "user data". For example, a logical erase block may contain metadata that specifies, but is not limited to, usage statistics (e.g., the number of programmable erase cycles performed on the logical erase block), health statistics (e.g., values ​​indicating the frequency at which damaged data has been read from the logical erase block), security or access control parameters, sequence information (e.g., sequence indicators), persistent metadata flags (e.g., indicating inclusion in atomic storage operations), transaction identifiers, or the like. In some embodiments, the logical erase block contains metadata identifying the logical address of the data stored in the logical erase block, and the corresponding number of stored data blocks / packets for each logical block or sector. In some embodiments, the metadata includes the crossover temperature of the logical erase block, the average crossover temperature of the open logical erase block in the non-volatile storage device, the rate of temperature change, the average programmable erase count of the logical erase block, the uncorrectable BER (UBER) of the logical erase block, the BER, the failure bit count of the logical erase block, and the charge leakage rate. In one embodiment, the metadata may include media characteristics.

[0127] "Cross temperature" refers to a condition where the die temperature of a memory cell is different when the memory cell is read / sensed from the die temperature of the same memory cell when the memory cell is written to (programmed). More generally, as previously stated, the term can also refer to the difference between the temperatures when a block is opened and closed for programming, or the temperature difference between closing two different blocks. The meaning of the term will be readily understood in the context. In some embodiments, cross temperature may be represented by a value called a cross temperature metric. In some types of non-volatile memory media (e.g., NAND memory cells), when the difference between the die temperature when a memory cell is written to and the die temperature when the memory cell is read is sufficiently high, the data in the memory cell may become unreadable (read commands result in errors). Currently, non-volatile memory devices have countermeasures to make it possible to read data stored in non-volatile memory subjected to cross temperature conditions; however, non-volatile memory devices should detect cross temperature conditions so that these countermeasures can be employed.

[0128] "Charge leakage rate" refers to the rate at which charge leaks from a memory cell when the memory cell is in a passive state and is not being read or written. In one embodiment, metadata may include media characteristics.

[0129] Figure 3BFurther details depict the organization of a memory array 300 according to one embodiment. The memory array 300 includes multiple memory dies, such as die 0 318, die 1 319, etc., to die n 320. Examples depict dies partitioned into physical planes, such as planes 0 321 and 1 322 of die 0 318, planes 0 323 and 1 324 of die 1 319, etc., to planes 0 325 and 1 326 of die n 320.

[0130] Each plane can be divided into physical erase blocks, as shown in the diagram: physical erase blocks 0327 to n328 of plane 0 321, physical erase blocks 0329 to n330 of plane 0 322, physical erase blocks 0331 to n332 of plane 0 323, physical erase blocks 0333 to n334 of plane 0 324, physical erase blocks 0335 to n336 of plane 0 325, and physical erase blocks 0337 to n338 of plane 0 326.

[0131] Each physical erase block can be divided into physical pages. For example, physical erase block 0 327 may contain physical pages 0339 to n 340, physical erase block 0 329 may contain physical pages 0 341 to n 342, physical erase block 0331 may contain physical pages 0 343 to n 344, physical erase block 0 333 may contain physical pages 0 345 to n 346, physical erase block 0 335 may contain physical pages 0 347 to n 348, and physical erase block 0 337 may contain physical pages 0 349 to n 350.

[0132] The memory array 300 is further organized into logical erase blocks (LEBs), as shown by logical erase block / memory block 0 351 and logical erase block / memory block N 352 (also referred to herein as “meta-blocks” or “memory blocks”). These LEBs contain multiple physical erase blocks (PEBs), as shown by physical erase block 0 327, physical erase block n 328, etc. Physical erase blocks may reside in individual memory dies, shown as die 0 318, die 1 319, and die n 320.

[0133] Those skilled in the art understand the relationship and differences between physical erase blocks and logical erase blocks, and that one or both can be referred to by shorthand names such as erase block, block, or storage block. Those skilled in the art will understand from the context in which an erase block is mentioned whether it refers to a physical erase block or a logical erase block (or meta-block or superblock). The concepts and techniques used in the art and the concepts and techniques set forth in the claims can be equally applied to physical erase blocks or logical erase blocks.

[0134] As used herein, a “physical” structure, such as a physical page, physical word line, physical erase block, physical plane, physical memory die, or the like, refers to a single physical structure that a system’s controller, manager, module, or other logical component can control and / or communicate at one or more levels within a physical abstraction of the organization of a device, system, or equipment. Similarly, a “logical” structure, such as a logical page, logical word line, logical erase block, logical plane, logical memory die, or the like, refers to a single physical structure of the same type that a system’s controller, manager, module, or other logical component can control and / or communicate at one or more levels within a physical abstraction of the organization of a device, system, or equipment. It should be noted that one or the other, or both, of a “physical” structure and a “logical” structure may have distinct addresses that can be used to identify a “physical” structure or a “logical” structure relative to other structures of similar nature and type.

[0135] For example, logical erase blocks / memory blocks 0 351 or n 352 are further divided into multiple logical pages (logical pages 353), which in turn contain multiple physical pages, such as physical pages 0 339, 0 341, 0 343, 0 345, 0 347, and 0 349 as described. A physical page may contain multiple packets, which can be grouped into error correction code (ECC) blocks.

[0136] In one embodiment, a physical page represents the smallest block of memory within a given die that can be written to at a given time. In one embodiment, a physical page may contain a single word line.

[0137] In another embodiment, a logical page is the minimum writable block of memory supported by the memory controller. (In one embodiment, the memory controller may include a buffer configured to store up to one logical page of data; when filling the buffer, the memory controller may simultaneously write the contents of the buffer to a single logical page.) In some embodiments, a logical page may be simply referred to as a word line, and it should be understood that a logical page comprises one word line on each plane of the memory array 300 and / or on the memory die.

[0138] In some embodiments, logical pages span a plane within a memory die or span planes across multiple memory dies. In some cases, dividing logical pages across multiple dies can result in faster access times for data sets when accessing multiple dies in parallel. Logical pages can be configured to map to any physical page on the die or across multiple memory dies, just like logical erase blocks.

[0139] For example, a logical erase block may contain metadata that specifies, but is not limited to, usage statistics (e.g., the number of programmed erase cycles performed on the logical erase block), health statistics (e.g., values ​​indicating the frequency at which corrupted data has been read from the logical erase block), security or access control parameters, sequence information (e.g., sequence indicators), persistent metadata flags (e.g., indicating inclusion in atomic storage operations), transaction identifiers, or the like. In some embodiments, a logical erase block contains metadata identifying the logical address of the data stored in the logical erase block, and a corresponding number of stored data blocks / packets for each logical block or sector.

[0140] In some embodiments, the metadata includes one or more of the following: the crossover temperature of the logical erase block, the average crossover temperature of the open logical erase block of the non-volatile storage device, the rate of temperature change, the average programmed erase count of the logical erase block, the uncorrectable bit error rate (UBER) of the logical erase block, the bit error rate (BER), the failure bit count of the logical erase block, and the charge leakage rate. In one embodiment, the metadata may include media characteristics.

[0141] Figure 4 A graph depicts the programming temperature variation 400 in one embodiment. The graph depicts the change in block-to-block shutdown temperature 402 in degrees Celsius as execution time passes. Blocks M and Q are shut down in hot zone 3, but there is an intervention cross-temperature event for hot zone 5; similarly, for blocks K and P, both are shut down in hot zone 4. The intervention cross-temperature event for hot zone 5 causes blocks Q and P to be placed in different block groups than blocks M and K, respectively. Both blocks M and Q are associated with hot zone 3, but the hot zone label for block Q further indicates additional read verification to be performed on its associated blocks. Because block Q is the first block to shut down in hot zone 3 after the cross-temperature event for hot zone 5, a BER test can be performed on block Q and the read parameters for block Q can be set accordingly. A similar procedure is invoked for block P for hot zone 4.

[0142] When blocks B and C are programmed, another cross-temperature event occurs that enters hot zone 0. This is another extreme cross-temperature event that triggers separation of the block population. Therefore, block D will be associated with the hot zone label used for hot zone 3, but will be marked as separate from the population of block M or block Q. Because the cross-temperature event is an extreme cross-temperature event, block D can be marked for priority relocation or associated with a hot outlier block region, such as hot zone 0 or hot zone 6.

[0143] Figure 5 A block marking routine 500 is depicted in one embodiment. Block marking routine 500 can be used to improve read performance in operating environments with frequently changing device temperature conditions. The depicted actions should not be assumed to occur in the order they are presented, unless the actions depend on the result of a preceding action to be performed. If two or more actions are not conditional on each other in some way, those skilled in the art will readily determine that they can be performed in parallel, in a time-division manner, or in a different order. The depicted actions may, for example, be performed by first in… Figure 1 and Figure 2 The storage controller 104 and / or die controller 202 described herein are implemented.

[0144] At box 502, hot zones can be preconfigured to ensure that memory read parameters used in the preconfigured hot zones within the N-hop neighborhood are compatible. This action provides hot zone compatibility within the N-hop neighborhood. Compatible read parameters are read parameters that are not incompatible read parameters. "Incompatible read parameters" refer to memory read parameters, such as threshold voltages, that cannot be reliably applied to blocks shut down across different hot zones on different sides of a cross-temperature event that can degrade or change read parameters.

[0145] At box 504, a first temperature corresponding to the time at which programming of the memory block begins can be measured. This first temperature may be located within the first pre-configured hot zone.

[0146] At box 506, a second temperature corresponding to the time the memory block is turned off for programming can be measured. The second temperature can be located within the second pre-configured hot zone in the N-hop neighborhood of the first pre-configured hot zone, where N ≥ 1. At box 508, the memory block can be assigned to the second pre-configured hot zone.

[0147] Temperature tracking can also be performed on the block when it is opened for programming (box 510). Temperature tracking can be used to detect cross-temperature events that occur when the block is opened and to determine whether the block is a thermal outlier.

[0148] Figure 6A A block labeling routine 600a is depicted in one embodiment. Block labeling routine 600a can be used with... Figure 6BThe hot outlier block processing routine 600b described herein is used in conjunction with a hot zone to configure a hot zone, assign memory blocks to the hot zone, and apply read parameters associated with the hot zone to the memory blocks assigned therein. The described actions should not be assumed to occur in the order presented unless the actions depend on the result of a preceding action to be performed. If two or more actions are not conditional on each other in some way, those skilled in the art will readily determine that they can be performed in parallel, in a time-division manner, or in a different order. The described actions may, for example, be performed by first in Figure 1 and Figure 2 The storage controller 104 and / or die controller 202 described herein are implemented.

[0149] At block 602, multiple hot zones can be configured in the memory device. This action results in a set of hot zones that can be used in later steps of block marking routine 600a and hot outlier block processing routine 600b. According to block 612, hot zones can be configured such that for at least one subset M ≥ 2 of hot zones, the read parameters for any N neighboring hot zones of subset M are compatible.

[0150] At box 604, a first temperature corresponding to the block of the opened memory device can be measured. This action results in the first temperature being used in later steps of the block marking routine 600a and the thermal outlier block processing routine 600b.

[0151] At box 606, a second temperature corresponding to the temperature used for programming the shutdown block can be measured. This action results in the second temperature being used in later steps of the block marking routine 600a and the thermal outlier value processing routine 600b.

[0152] When a block is opened for programming, the system can track its temperature (e.g., with temperature measurements at periodic intervals) (box 614). These measurements can be used to determine whether a cross-temperature event has occurred on the block, and if so, to determine the temperature range and frequency of the cross-temperature event.

[0153] At box 608, a temperature range between the first and second temperatures can be determined using a first temperature from box 604 and a second temperature from box 606. This range can span a thermal region where N ≥ 2.

[0154] At box 610, provided that N satisfies the threshold, the storage blocks whose temperatures are measured in boxes 604 and 606 can be assigned to the hot zone configured in box 602 and containing the second temperature of box 606. The steps of the thermal outlier block processing routine 600b can be followed from box 610.

[0155] Figure 6B A hot outlier block processing routine 600b is depicted in one embodiment. The hot outlier block processing routine 600b can be used with... Figure 6AThe block marking routine 600a described herein is used in conjunction to configure hot zones, assign memory blocks to hot zones, and apply read parameters associated with the hot zones to the memory blocks assigned therein. The described actions should not be assumed to occur in the order presented unless the actions depend on the result of a preceding action to be performed. If two or more actions are not conditional on each other in some way, those skilled in the art will readily determine that they can be performed in parallel, in a time-division manner, or in a different order. The described actions may, for example, be performed by first in Figure 1 and Figure 2 The storage controller 104 and / or die controller 202 described herein are implemented.

[0156] The hot outlier block processing routine 600b continues from the block marking routine 600a at box 616. At box 616, if N does not meet the threshold from box 610, then the storage block can be marked as a hot outlier block. The block can also be marked as a hot outlier block (box 620) if the range, number, or frequency, or combination thereof, of the cross-temperature events experienced by the block does not meet the condition or threshold. This can result in data evacuation in box 622. According to box 622, marking a storage block as a hot outlier block can trigger data evacuation from the storage block.

[0157] At box 618, you can... Figure 6A The read parameters associated with a specific hot zone in box 612 described herein are applied to the storage block assigned to the specific hot zone.

[0158] Figure 7 A block marking routine 700 is depicted in one embodiment. The block marking routine 700 can be used to pre-configure compatible hot zones within an N-hop neighborhood and assign memory blocks to appropriate hot zones. The depicted actions should not be assumed to occur in the order they are presented, unless the actions depend on the result of a preceding action to be performed. If two or more actions are not conditional on each other in some way, those skilled in the art will readily determine that they can be performed in parallel, in a time-division manner, or in a different order. The depicted actions may, for example, be performed by first in Figure 1 and Figure 2 The storage controller 104 and / or die controller 202 described herein are implemented.

[0159] At box 702, hot zones can be preconfigured to ensure that memory read parameters for preconfigured hot zones within an N-hop neighborhood are compatible. This action results in a compatible set of hot zones within the N-hop neighborhood. All N-hop neighborhoods with preconfigured hot zones can be compatible, or only a subset M of preconfigured hot zones can be compatible.

[0160] At box 704, a first temperature corresponding to the opening of a memory block for programming of the non-volatile memory array is measured. This first temperature may be located within the first of a plurality of pre-configured hot zones.

[0161] At box 706, a second temperature corresponding to the shutdown of the memory block for programming can be measured. The second temperature can be located within the second of the plurality of pre-configured hot zones in the N-hop neighborhood of the first pre-configured hot zone, where N≥1.

[0162] At box 708, based on the second temperature measured in box 706, the storage block can be assigned to the second of the pre-configured hot zones.

[0163] Figure 8 A block relocation routine 800 is depicted in one embodiment. The block relocation routine 800 can be used to relocate storage blocks based on hotspot tags. The depicted actions should not be assumed to occur in the order they are presented, unless the actions depend on the result of a preceding action to be performed. If two or more actions are not conditional on each other in some way, those skilled in the art will readily determine that they can be performed in parallel, in a time-division manner, or in a different order. The depicted actions may, for example, be performed by first in Figure 1 and Figure 2 The storage controller 104 and / or die controller 202 described herein are implemented.

[0164] At box 802, a first temperature can be measured when a block of the memory array is opened. This first temperature can be used in a later step of the block relocation routine 800.

[0165] At box 804, a second temperature can be measured when a block of the memory array is turned off. This second temperature can be used in a later step of the block relocation routine 800.

[0166] At box 806, a tag can be assigned to a block corresponding to one of a plurality of pre-configured hot zones containing a second temperature from box 804. Thus, a tag can be assigned within a range of 1 ≤ N ≤ M adjacent pre-configured hot zones between the first temperature from box 802 and the second temperature from box 804.

[0167] At box 808, blocks containing the same label can be relocated to be adjacent in the memory array.

[0168] Figure 9A A block labeling routine 900a is depicted in one embodiment. Block labeling routine 900a can be used with... Figure 9BThe block tagging routine 900b is used in conjunction with BER and cross-temperature events to assign hot zone tags and read parameters. The described actions should not be assumed to occur in the order they are presented, unless the actions depend on the result of a preceding action to be performed. If two or more actions are not conditional on each other in some way, those skilled in the art will readily determine that they can be performed in parallel, in a time-division manner, or in a different order. The described actions may, for example, be performed by first in Figure 1 and Figure 2 The storage controller 104 and / or die controller 202 described herein are implemented.

[0169] At box 902, a cross temperature event can be detected. The cross temperature event detected by the action at box 902 can serve as a trigger for the start block marker routine 900a.

[0170] At block 904, the read parameters for one or more pre-configured hot zones can be updated due to the cross-temperature event detected in block 902. In some embodiments, according to block 912, step block 904 can be conditional on the cross-temperature event being an extreme cross-temperature event.

[0171] At block 906, the BER can be tested for a storage block that was shut down after the crossover temperature event detected in block 902. In one embodiment, as described in block 914, the BER can be tested if the storage block shut down after the crossover temperature event is the first storage block shut down after the crossover temperature event, and if the storage block was assigned to the same hot zone as the block shut down before the crossover temperature event. At block 916, in one embodiment, read parameters assigned to the storage block shut down before the crossover temperature event can be applied to read data from the storage block shut down after the crossover temperature event.

[0172] At box 908, it is possible to distinguish between blocks that are closed after a cross-temperature event from box 906 and blocks that are closed before the cross-temperature event. Blocks closed after the cross-temperature event and blocks closed before the cross-temperature event can be assigned to the same thermal zone.

[0173] In one embodiment, the additional steps discussed in block tagging routine 900b can be performed after block 908 and can subsequently return to block 910. At block 910, the hot zone tag of the block programmed before the cross-temperature event can be deactivated.

[0174] Figure 9B A block labeling routine 900b is depicted in one embodiment. Block labeling routine 900b can be used with... Figure 9AThe block labeling routine 900a is used in conjunction to create and assign new hotspot labels to invoke additional read verification for some storage blocks. The described actions should not be assumed to occur in the order they are presented, unless the actions depend on the result of a preceding action to be performed. If two or more actions are not conditional on each other in some way, those skilled in the art will readily determine that they can be performed in parallel, in a time-division manner, or in a different order. The described actions may, for example, be performed by first in Figure 1 and Figure 2 The storage controller 104 and / or die controller 202 described herein are implemented.

[0175] The hot outlier block processing routine 600b continues from the block marking routine 900a at box 918, where the BER can be compared for storage blocks that were closed before and after the cross temperature event. This comparison allows for block differentiation in subsequent steps.

[0176] Several additional actions may occur after or involve the BER comparison in box 918. These additional actions do not necessarily have to occur in a specific order unless the order implies a causal relationship.

[0177] At box 920, if the BER of box 918 meets the threshold voltage, then a memory block that was shut down after the crossover temperature event can be distinguished from a memory block that was shut down before the crossover temperature event. This distinction can lead to block assignment as described in a later step of the block marking routine 900b.

[0178] At box 922, a memory block closed after a cross temperature event can be distinguished from a memory block closed before a cross temperature event, independent of the time interval between cross temperature events. This distinction can lead to block assignment as described in a later step of block marking routine 900b.

[0179] At box 924, a new hot zone label can be created that includes the same hot zone as the storage blocks assigned to them before the cross-temperature event. This label can be applied to the storage blocks so that they can be assigned to hot zones, for example, in box 926.

[0180] At box 926, a new hot zone label created in box 924 can be assigned to a storage block that is shut down after a cross-temperature event. This assignment can be used to distinguish the storage block during future storage operations.

[0181] At box 928, the new hotspot label created in box 924 can be configured to invoke additional read verification for the associated storage block. Configuring hotspot labels in this way can improve performance by more quickly identifying storage blocks that may experience data loss due to cross-temperature events. Once box 928 is complete, the block labeling routine 900b can return to... Figure 9AThe steps of block marking routine 900a as described in [the document].

[0182] Those skilled in the art will understand that the techniques disclosed herein and their variations can be implemented by various forms of logic suitable for the details of the implementation.

[0183] Within this disclosure, various entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. The expression “an entity configured to [perform one or more tasks]” is used herein to refer to a structure (i.e., a physical object such as an electronic circuit). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. Even if the structure is not currently being operated, it may be referred to as being “configured” to perform some tasks. “A credit allocation circuit configured to allocate credits to multiple processors” inherently encompasses, for example, an integrated circuit having circuitry that performs this function during operation, even if the integrated circuit in question is not currently in use (e.g., not connected to a power supply). Therefore, an entity described or stated as being “configured” to perform some tasks refers to a physical object, such as a device, circuit, memory storing program instructions executable to perform the task, etc. This phrase is not used herein to refer to intangible objects.

[0184] The term "configured as" is not intended to mean "configurable as". For example, although an unprogrammed FPGA may be "configurable as" to perform certain functions after programming, the unprogrammed FPGA will not be considered "configured as" to perform those functions.

[0185] As used herein, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on the specified factor or on the specified factor plus other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies B as the factor used to determine A or the determination that influences A. This phrase does not exclude that the determination of A may also be based on another factor, such as C. This phrase is also intended to cover embodiments in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0186] As used herein, the phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may affect or otherwise trigger the effect. That is, the effect may respond only to those factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase "execute A in response to B." This phrase specifies B as the factor that triggers the execution of A. This phrase does not exclude the possibility that A may also be executed in response to another factor, such as C. This phrase also implicitly covers embodiments in which A is executed only in response to B.

[0187] As used herein, unless otherwise stated, the terms “first,” “second,” etc., are used as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, in a register set with eight registers, the terms “first register” and “second register” can be used to refer to any two of the eight registers, rather than, for example, only logic registers 0 and 1.

[0188] When used in the claims, the term "or" is used as an inclusive "or," not an exclusive "or." For example, the phrase "at least one of x, y, or z" means any one of x, y, and z, and any combination thereof.

Claims

1. A method for operating a memory device, comprising: The measurement corresponds to the first temperature at which the memory block of the memory device is opened for programming. The measurement corresponds to a second temperature at which the storage block is turned off for programming; Determine the range between the first temperature and the second temperature, the range spanning N≥2 pre-configured thermal zones; as well as If N satisfies the threshold, the storage block is assigned to the hot zone containing the second temperature.

2. The method according to claim 1, further comprising: If N does not meet the threshold, then the storage block is marked as a hot outlier block.

3. The method of claim 2, wherein marking the storage block as the hot outlier block triggers data evacuation from the storage block.

4. The method according to claim 1, further comprising: The temperature of the block is tracked when the block is opened for programming. Determine one or more of the following: the number of cross-temperature events, the temperature range of one or more cross-temperature events, and the frequency of the cross-temperature events; as well as The storage block is conditionally marked as a thermal outlier block based on one or more of the number of cross-temperature events, the temperature range of one or more cross-temperature events, and the frequency of the cross-temperature events.

5. The method of claim 1, wherein the read parameters applied to the storage block assigned to the specific hot zone are specifically applied to the block assigned to the specific hot zone.

6. The method of claim 5, wherein the hot zone is configured such that for at least one subset M ≥ 2 of the hot zone, the reading parameters for any N neighboring hot zones of the subset M are compatible.

7. A memory device comprising: Non-volatile memory array; Controller; as well as The first logic, used to configure the controller to: The measurement corresponds to a first temperature at which the memory block of the non-volatile memory array is opened for programming, the first temperature being located within the first of a plurality of pre-configured hot zones; The measurement corresponds to a second temperature at which the memory block is turned off for programming, the second temperature being located within the second of the plurality of pre-configured hot zones in the N-hop neighborhood of the first of the pre-configured hot zones, where N≥1; as well as The storage block is assigned to the second of the pre-configured hot zones; The plurality of pre-configured hot zones are configured such that the memory read parameters for the hot zones in the N-hop neighborhood are compatible.

8. The memory device of claim 7, further comprising second logic for performing the following operations: Detecting cross-temperature events; and The read parameters for one or more of the pre-configured hot zones are updated due to the cross-temperature event.

9. The memory device of claim 8, wherein the update of the read parameter is conditional upon the cross temperature event being an extreme cross temperature event.

10. The memory device of claim 7, further comprising third logic for performing the following operations: Detect cross-temperature events; The bit error rate of the memory block shut down after the said cross-temperature event was tested; and Distinguish between storage blocks that are shut down after the cross temperature event and storage blocks that are shut down before the cross temperature event, wherein storage blocks that are shut down after the cross temperature event and storage blocks that are shut down before the cross temperature event are assigned to the same hot zone.

11. The memory device of claim 10, wherein the bit error rate test is performed under the following conditions: the memory block shut down after the cross temperature event is the first shut-down memory block after the cross temperature event, and the memory block shut down after the cross temperature event is assigned to the same hot zone as the memory block shut down before the cross temperature event.

12. The memory device of claim 10, wherein distinguishing between the memory block shut down after the cross temperature event and the memory block shut down before the cross temperature event comprises: Create a new hot zone label containing the same hot zone of the storage block that was assigned to the hot zone before the cross temperature event; The storage block that was shut down after the cross-temperature event will be assigned to the new hot zone label; as well as The new hot zone label is marked to invoke additional read verification of the storage block associated with the new hot zone label.

13. The memory device of claim 10, further comprising fourth logic for performing the following operations: The hot zone label of the block programmed before the cross temperature event is deactivated, so that a storage block closed after the cross temperature event cannot be assigned to the hot zone label of the storage block closed before the cross temperature event.

14. The memory device of claim 10, wherein the bit error rate test and differentiation comprises: The application is assigned read parameters to the storage block that was closed before the cross temperature event in order to read data from the storage block that was closed after the cross temperature event; The bit error rates of the memory blocks that were shut down before the cross temperature event and the memory blocks that were shut down after the cross temperature event are compared. as well as The storage block that was shut down after the cross temperature event is distinguished from the storage block that was shut down before the cross temperature event, provided that the comparison meets the threshold.

15. The memory device of claim 10, wherein the distinction between a memory block shut down after the cross temperature event and a memory block shut down before the cross temperature event is a time interval independent of the cross temperature event.

16. A memory system comprising: Memory array; as well as The controller is configured to: Measure the first temperature when the blocks of the memory array are opened; Measure the second temperature when the block is closed; Given that the range between the first temperature and the second temperature spans 1 ≤ N ≤ M adjacent hot zones among a plurality of pre-configured hot zones, assign a label to the block corresponding to one of the pre-configured hot zones containing the second temperature; as well as Blocks with the same label are relocated to be adjacent in the memory array.

17. The memory system of claim 16, wherein the controller is further configured to: A block that spans more than M adjacent thermal zones within the range between the first temperature and the second temperature is marked as a thermal outlier block.

18. The memory system of claim 17, wherein the controller is further configured to: When the block is opened for programming, the storage block is conditionally marked as a thermal outlier block based on one or more of the following: the number of cross-temperature events, the temperature range of one or more cross-temperature events, and the frequency of the cross-temperature events.

19. The memory system of claim 16, wherein the controller is further configured to: Detecting extreme cross-temperature events; Distinguish between blocks that were closed after the extreme cross-temperature event and assigned a specific tag, and blocks with the specific tag that were closed before the extreme cross-temperature event; and The block with the specific tag that was shut down after the extreme cross temperature event is relocated to a position adjacent to the memory array, different from the block with the specific tag that was shut down before the extreme cross temperature event.

20. The memory system of claim 19, wherein the controller is further configured to: The block that was closed before the extreme cross temperature event is distinguished from the block that was closed after the extreme cross temperature event if the bit error rate of the first block that was closed after the extreme cross temperature event is worse than the bit error rate of one of the blocks that was closed before the extreme cross temperature event.

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