Chip packaging structure and manufacturing method thereof

Abstract

The present invention provides a chip packaging structure and a manufacturing method thereof, wherein an edge connector and a plurality of components are packaged in a plastic packaging layer, the components include electrical connection points, the electrical connection points are located on the functional surface of the components, and the functional surface is covered with a component protection layer exposing the electrical connection points; a rewiring layer is provided on the front of the electrical connection points, the component protection layer, and the plastic packaging layer to electrically connect the components through the electrical connection points; a plurality of conductive plugs are provided in the plastic packaging layer to lead the edge connector and the rewiring layer to the back of the plastic packaging layer; a connecting line is provided on the back of the plastic packaging layer to connect the conductive plugs. The rewiring layer is combined with the connecting line, and the circuit layout on two surfaces can improve the density of wiring, compared with the circuit layout on only one surface through the rewiring layer, to form a packaging structure with more complex wiring and smaller volume. In addition, the production of multiple chip packaging structures can be realized at one time, which is conducive to mass production and cost reduction.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] In recent years, with the continuous development of circuit integration technology, electronic products are increasingly moving towards miniaturization, intelligence, high integration, high performance and high reliability. Packaging technology not only affects the performance of products, but also restricts the miniaturization of products.

[0003] In view of this, the present invention provides a new chip packaging structure and a manufacturing method thereof to achieve the requirements of small size, compact structure and high integration of the packaging structure. Summary of the invention

[0004] The object of the present invention is to provide a chip packaging structure and a manufacturing method thereof, so as to achieve the requirements of small volume, compact structure and high integration of the packaging structure.

[0005] To achieve the above object, a first aspect of the present invention provides a chip packaging structure, comprising:

[0006] A plurality of components, each of which comprises an electrical connection point, wherein the electrical connection point is located on a functional surface of the component;

[0007] A component protection layer, covering the functional surface of the component, wherein the component protection layer exposes the electrical connection point;

[0008] an edge connector, the edge connector comprising a coupling surface;

[0009] A plastic encapsulation layer, covering the edge connector and the plurality of components, wherein the front side of the plastic encapsulation layer exposes the component protection layer, the electrical connection points and the coupling surface of the edge connector;

[0010] A rewiring layer, located on the front of the electrical connection point, the component protection layer and the plastic packaging layer, and the rewiring layer is used to electrically connect the components through the electrical connection point;

[0011] A plurality of conductive plugs are located in the plastic packaging layer, and the plurality of conductive plugs are used to lead the edge connector and the redistribution layer to the back side of the plastic packaging layer;

[0012] A connecting wire, located on the back of the plastic packaging layer, to electrically connect the conductive plugs;

[0013] A first dielectric layer, embedding the rewiring layer, the first dielectric layer exposing a coupling surface of the edge connector;

[0014] The second dielectric layer buries the connecting wire.

[0015] Optionally, the component includes a bare chip, or the component includes a bare chip and a passive device; the electrical connection point of the bare chip is a pad.

[0016] Optionally, the material of the component protection layer is an insulating resin material or an inorganic material.

[0017] Optionally, the material of the first dielectric layer is an insulating resin material or an inorganic material; and / or the material of the second dielectric layer is an insulating resin material or an inorganic material.

[0018] Optionally, the rewiring layer includes two or more layers.

[0019] A second aspect of the present invention provides a method for manufacturing a chip packaging structure, comprising:

[0020] Providing a carrier board and multiple groups of components to be packaged, each group of the components to be packaged includes an edge connector and multiple components, the components include electrical connection points, the electrical connection points are located on the functional surface of the components, the functional surface is covered with a component protection layer, and the edge connector includes a coupling surface; fixing the multiple groups of components to be packaged on the surface of the carrier board, wherein the coupling surface of the component protection layer and the edge connector faces the carrier board;

[0021] Forming a plastic encapsulation layer on the surface of the carrier board to bury the groups of components to be packaged; removing the carrier board to expose the component protection layer, the coupling surface of the edge connector and the front side of the plastic encapsulation layer;

[0022] An opening is formed in the component protection layer to expose the electrical connection point; a rewiring layer is formed on the component protection layer, the electrical connection point and the front surface of the plastic packaging layer to electrically connect the components in the group through the electrical connection point; and a first dielectric layer is formed to embed the coupling surface of the edge connector and the rewiring layer;

[0023] forming a plurality of conductive plugs in the plastic encapsulation layer through the back side of the plastic encapsulation layer to lead the edge connector and the redistribution layer to the back side of the plastic encapsulation layer;

[0024] forming a connecting wire on the back side of the plastic encapsulation layer to electrically connect the conductive plugs in the group; and forming a second dielectric layer to bury the connecting wire;

[0025] removing a first dielectric layer embedding a coupling surface of the edge connector;

[0026] A plurality of chip packaging structures are formed by cutting, each of which contains a group of components to be packaged.

[0027] Optionally, in the step of fixing the multiple groups of components to be packaged on the surface of the carrier, the component protection layer has openings exposing the electrical connection points; after removing the carrier, the electrical connection points are exposed; before the step of forming the rewiring layer, the step of forming openings in the component protection layer is omitted.

[0028] Optionally, the component includes a bare chip, or the component includes a bare chip and a passive device; the electrical connection point of the bare chip is a pad.

[0029] Optionally, the material of the component protection layer is an insulating resin material or an inorganic material.

[0030] Optionally, the material of the first dielectric layer is an insulating resin material or an inorganic material; and / or the material of the second dielectric layer is an insulating resin material or an inorganic material.

[0031] Optionally, the material of the first dielectric layer is a laser reactive material, and the first dielectric layer on the coupling surface of the edge connector is removed by laser patterning.

[0032] Optionally, the rewiring layer includes two or more layers.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] First, an edge connector and multiple components are encapsulated in a plastic layer, wherein the components include electrical connection points, the electrical connection points are located on the functional surface of the components, the functional surface is covered with a component protection layer that exposes the electrical connection points, and the edge connector includes a coupling surface; then, on the one hand, a rewiring layer is formed on the component protection layer, the electrical connection points, and the front of the plastic layer to electrically connect the components in the group through the electrical connection points; on the other hand, multiple conductive plugs are formed in the plastic layer through the back of the plastic layer to lead the edge connector and the rewiring layer to the back of the plastic layer; and connecting wires are formed on the back of the plastic layer to electrically connect the conductive plugs in the group. The rewiring layer is combined with the connecting wires, and the circuit layout on two surfaces can improve the density of wiring, compared with the circuit layout on only one surface through the rewiring layer, so as to form a packaging structure with more complex wiring and smaller volume. The chip packaging structure realizes external circuit connection through the edge connector, so that the performance of the chip packaging structure is reliable. In addition, the production of multiple chip packaging structures can be realized at one time, which is conducive to mass production and cost reduction.

[0035] In addition, due to the presence of the component protection layer, a re-wiring layer can be formed directly on the component protection layer and the surface of the plastic packaging layer after the plastic packaging process is completed, without forming a dielectric layer on the entire panel; in panel packaging, due to the large area of ​​the panel, the process of forming a dielectric layer on a large area panel is difficult, and the dielectric layer uses more materials. The presence of the component protection layer reduces the difficulty and cost of the packaging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic top view of the chip packaging structure according to the first embodiment of the present invention;

[0037] Figure 2 is a schematic cross-sectional view of a chip packaging structure according to a first embodiment of the present invention;

[0038] Figure 3 yes Figure 1 and Figure 2 A flowchart of a method for manufacturing a chip packaging structure;

[0039] Figures 4 to 12 yes Figure 3 Schematic diagram of the intermediate structure corresponding to the process in;

[0040] Fig.13 is a schematic cross-sectional view of a chip packaging structure according to a second embodiment of the present invention;

[0041] Fig.14 is a schematic top view of a chip packaging structure according to a third embodiment of the present invention;

[0042] Fig.15 It is a schematic cross-sectional structure diagram of a chip packaging structure according to a third embodiment of the present invention.

[0043] To facilitate understanding of the present invention, all reference numerals appearing in the present invention are listed below:

[0044] Chip packaging structure 1, 2, 3 components 11

[0045] Functional surface 11a of the component Component protection layer 110

[0046] Edge connector 12 Coupling surface 12a

[0047] Plastic sealing layer 13 Plastic sealing layer front side 13a

[0048] Back side of plastic packaging layer 13b Rewiring layer 14

[0049] Conductive plug 15 Connecting wire 16

[0050] First dielectric layer 17 Second dielectric layer 18

[0051] Bare die 111 Bare die active surface 111a

[0052] Pad 112 Metal blocks 14a, 14b

[0053] Component to be packaged 10 Carrier 2

[0054] Opening 110a First support plate 3

[0055] Second support plate 4 Passive components 113

[0056] Functional surface 113a of passive device Through hole 13c DETAILED DESCRIPTION

[0057] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0058] Figure 1 It is a schematic top view of the chip packaging structure of the first embodiment of the present invention. Figure 2 It is a schematic cross-sectional structure diagram of a chip packaging structure according to a first embodiment of the present invention.

[0059] Reference Figure 1 and Figure 2 As shown, the chip packaging structure 1 includes:

[0060] A plurality of components 11, wherein the components 11 include electrical connection points, and the electrical connection points are located on a functional surface 11a of the components 11;

[0061] A component protection layer 110 covers the functional surface 11a of the component 11, and the component protection layer 110 exposes the electrical connection points;

[0062] An edge connector 12 (Edge connector), the edge connector 12 includes a coupling surface 12a;

[0063] The plastic encapsulation layer 13 covers the edge connector 12 and the plurality of components 11, and the front side 13a of the plastic encapsulation layer 13 exposes the coupling surface 12a of the component protection layer 110 and the edge connector 12;

[0064] The rewiring layer 14 is located on the electrical connection points, the component protection layer 110 and the front side 13a of the plastic packaging layer 13. The rewiring layer 14 is used to electrically connect the components 11 through the electrical connection points.

[0065] A plurality of conductive plugs 15 are located in the plastic packaging layer 13 , and the plurality of conductive plugs 15 are used to lead the edge connector 12 and the redistribution layer 14 to the back side 13 b of the plastic packaging layer 13 ;

[0066] The connecting wire 16 is located on the back side 13b of the plastic packaging layer 13 to electrically connect the conductive plugs 15;

[0067] A first dielectric layer 17 burying the redistribution layer 14 , the first dielectric layer 17 exposing the coupling surface 12 a of the edge connector 12 ;

[0068] The second dielectric layer 18 embeds the connecting wire 16 .

[0069] Reference Figure 1 and Figure 2 As shown, in this embodiment, the component 11 includes a bare chip 111. Specifically, it includes three bare chips 111. In other embodiments, the number of bare chips 111 can also be two or other numbers, which is not limited in the present invention.

[0070] The functions of the dies 111 may be the same or different. The dies 111 may be a power die, a memory die, a sensor die, or a radio frequency die.

[0071] The active surface 111a of the die 111 is provided with a pad 112. The die 111 may include a variety of devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device. The pad 112 is connected to the electrical interconnection structure and is used to input / output electrical signals of each device. The active surface 111a of the die 111 corresponds to the functional surface 11a of the component 11, and the pad 112 corresponds to an electrical connection point.

[0072] The component protection layer 110 is an insulating material, which can be an insulating resin material or an inorganic material. The insulating resin material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties. The inorganic material is, for example, at least one of silicon dioxide and silicon nitride.

[0073] The edge connector 12 is located at one side of the plurality of components 11. The edge connector 12 includes a coupling surface 12a for realizing external circuit connection of the chip packaging structure 1.

[0074] The material of the edge connector 12 may be a metal with good conductivity such as copper. The coupling surface 12a of the edge connector 12 may have an anti-oxidation layer to prevent copper oxidation, thereby preventing the electrical connection performance from being deteriorated due to copper oxidation. The anti-oxidation layer may include: a) a tin layer, or b) a nickel layer and a gold layer stacked from bottom to top, or c) a nickel layer, a palladium layer and a gold layer stacked from bottom to top.

[0075] The material of the plastic encapsulation layer 13 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc. The plastic encapsulation layer may be various polymers, resins or resin-polymer composite materials, such as resins with fillers, or other materials with similar properties.

[0076] The plastic layer 13 includes a front side 13 a and a back side 13 b opposite to each other. In this embodiment, the front side 13 a of the plastic layer 13 exposes the component protection layer 110 , the electrical connection points and the coupling surface 12 a of the edge connector 12 .

[0077] Figure 2 In the illustrated embodiment, the redistribution layer 14 includes a plurality of metal blocks 14 a having one layer, and the metal blocks 14 a are electrically connected to the pads 112 .

[0078] Among the plurality of conductive plugs 15, some conductive plugs 15 contact the edge connector 12, and some conductive plugs 15 contact the redistribution layer 14. The number and position of the conductive plugs 15 contacting the redistribution layer 14 and the layout of the connection lines 16 can be determined according to a preset circuit layout.

[0079] The materials of the first dielectric layer 17 and the second dielectric layer 18 can be insulating resin materials or inorganic materials. The insulating resin materials are, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties. The inorganic material is, for example, at least one of silicon dioxide and silicon nitride. Compared with inorganic materials, the tensile stress of insulating resin materials is smaller, which can prevent the surface of the chip packaging structure 1 from warping.

[0080] Reference Figure 1 and Figure 2 As shown, the chip packaging structure 1 in this embodiment realizes external circuit connection of multiple chips through the edge connector 12.

[0081] In the chip packaging structure 1, on the one hand, the circuit layout is realized on the front side 13a of the plastic packaging layer 13 through the rewiring layer 14, and on the other hand, the circuit layout is realized on the back side 13b of the plastic packaging layer 13 through the conductive plug 15 and the connecting wire 16. Compared with the circuit layout on only one side through the rewiring layer 14, the two-side circuit layout method of this embodiment can improve the density of wiring, forming a chip packaging structure 1 with more complex wiring and smaller volume.

[0082] In addition, the chip packaging structure 1 realizes external circuit connection through the edge connector 12, so that the performance of the chip packaging structure 1 is reliable.

[0083] One embodiment of the present invention provides Figure 1 and Figure 2 A method for manufacturing a chip packaging structure 1. Figure 3 It is a flowchart of the production method. Figures 4 to 12 yes Figure 3 Schematic diagram of the intermediate structure corresponding to the process in .

[0084] First, refer to Figure 3 Step S1 in Figure 4 and Figure 5 As shown, a carrier board 2 and multiple groups of components to be packaged 10 are provided, each group of components to be packaged 10 includes an edge connector 12 and multiple components 11, the component 11 includes an electrical connection point, the electrical connection point is located on the functional surface 11a of the component 11, the functional surface 11a is covered with a component protection layer 110, the component protection layer 110 has an opening 110a exposing the electrical connection point, and the edge connector 12 includes a coupling surface 12a; the multiple groups of components to be packaged 10 are fixed to the surface of the carrier board 2, wherein the coupling surface 12a of the component protection layer 110 and the edge connector 12 faces the carrier board 2. Figure 4 is a top view of a carrier board and multiple groups of components to be packaged; Figure 5 It is along Figure 4 Sectional view along line AA.

[0085] In this embodiment, the component 11 includes a bare chip 111. Specifically, it includes three bare chips 111. In other embodiments, the number of bare chips 111 can also be two or other numbers, which is not limited in the present invention.

[0086] The functions of the dies 111 may be the same or different. The dies 111 may be a power die, a memory die, a sensor die, or a radio frequency die.

[0087] The bare die 111 is formed by dividing the wafer, and the wafer includes an active surface of the wafer, and the active surface of the wafer is provided with a pad 112 and an insulating layer (not shown) protecting the pad 112. The bare die 111 is formed after the wafer is cut, and accordingly, the bare die 111 includes an active surface 111a of the bare die, and the active surface 111a of the bare die is provided with a pad 112 and an insulating layer protecting the pad 112. A component protection layer 110 is applied on the active surface 111a of the bare die 111, and the application process of the component protection layer 110 can be: before the wafer is cut into bare die 111, the component protection layer 110 is applied on the active surface of the wafer, and the wafer with the component protection layer 110 is cut to form the bare die 111 with the component protection layer 110, or it can be: after the wafer is cut into bare die 111, the component protection layer 110 is applied on the bare die 111.

[0088] Compared with applying a dielectric layer on the molding layer after the plurality of groups of components 10 to be packaged are molded, applying a component protection layer 110 on the bare chip 111 before molding can avoid large-area dielectric layer production, which wastes materials on the one hand, and can avoid warping of the molding body on the other hand.

[0089] The bare die 111 may include a variety of devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device. The pads 112 on the bare die active surface 111a are connected to the electrical interconnection structure for inputting / outputting electrical signals of each device.

[0090] The active surface 111 a of the die 111 corresponds to the functional surface 11 a of the component 11 , and the pads 112 correspond to the electrical connection points.

[0091] The component protection layer 110 is an insulating material, specifically an insulating resin material or an inorganic material, such as polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film, organic polymer composite material or other organic materials with similar insulating properties.

[0092] The insulating resin material can be pressed onto the pad 112 and the insulating layer between adjacent pads 112 by a) a lamination process, or b) first coated or printed on the insulating layer between the pad 112 and the adjacent pad 112 and then cured, or c) cured on the insulating layer between the pad 112 and the adjacent pad 112 by an injection molding process.

[0093] When the material of the component protection layer 110 is an inorganic material such as silicon dioxide or silicon nitride, it can be formed on the pads 112 and the insulating layer between adjacent pads 112 through a deposition process.

[0094] The component protection layer 110 may include one or more layers.

[0095] Reference Figure 5 As shown, the component protection layer 110 has an opening 110a exposing the pad 112. In some embodiments, the pad 112 on the die 111 can be embedded in the component protection layer 110, and the opening 110a is in the redistribution layer 14 (see Figure 8 As shown) is produced before the forming process.

[0096] Figure 5 In the illustrated embodiment, one opening 110 a exposes a partial area of ​​one pad 112 . In other embodiments, one opening 110 a may also expose partial areas of two or more pads 112 .

[0097] The wafer may be thinned from the back side before dicing to reduce the thickness of the die 111 .

[0098] The carrier plate 2 is a hard plate, which may include a plastic plate, a glass plate, a ceramic plate or a metal plate.

[0099] An adhesive layer may be provided between the bare chip 111 and the carrier board 2, and between the edge connector 12 and the carrier board 2, so as to achieve fixation between the two. Specifically, an adhesive layer may be coated on the entire surface of the carrier board 2, and multiple bare chips 111 and multiple edge connectors 12 may be placed on the adhesive layer. The adhesive layer may be made of an easily peelable material so that the carrier board 2 can be peeled off, for example, a thermal separation material that can lose its stickiness by heating or a UV separation material that can lose its stickiness by ultraviolet irradiation may be used.

[0100] The height of the edge connector 12 is smaller than the thickness of the die 111. The height of the edge connector 12 refers to the maximum dimension of the edge connector 12 in a direction perpendicular to the coupling surface 12a.

[0101] In some embodiments, the edge connector 12 is a prefabricated component directly bonded to the surface of the carrier 2. In other embodiments, a metal sheet may be bonded to the carrier 2 first, and then etched at a predetermined position of the carrier 2 by etching.

[0102] The edge connector 12 and the plurality of bare chips 111 may be arranged on the carrier 2 in any order and may be arranged simultaneously.

[0103] The plurality of edge connectors 12 or the plurality of bare chips 111 may be first arranged on a transfer carrier and then transferred to the carrier 2. Specifically, a whole adhesive layer may be coated on the surface of the transfer carrier, and the plurality of edge connectors 12 or the plurality of bare chips 111 may be placed on the adhesive layer. The adhesive layer may be made of an easily peelable material so that the plurality of edge connectors 12 and the plurality of bare chips 111 may be peeled off from the transfer carrier, for example, a thermal separation material that can lose its viscosity by heating or a UV separation material that can lose its viscosity by ultraviolet irradiation may be used.

[0104] A group of components to be packaged 10 is located in an area on the surface of the carrier 2, which is convenient for subsequent cutting. Multiple groups of components to be packaged 10 can be fixed on the surface of the carrier 2 to simultaneously manufacture multiple chip packaging structures 1, which is conducive to mass production and cost reduction.

[0105] Next, refer to Figure 3 Step S2 in Figure 4 and Figure 6 As shown, a plastic sealing layer 13 is formed on the surface of the carrier board 2 to embed each group of components 10 to be packaged; Figure 7 As shown, the carrier board 2 is removed, exposing the component protection layer 110 , the electrical connection points, the coupling surface 12 a of the edge connector 12 , and the front surface 13 a of the plastic packaging layer 13 .

[0106] The material of the plastic encapsulation layer 13 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol. The plastic encapsulation layer can be various polymers, resins or resin-polymer composite materials, such as resins with fillers, or other materials with similar properties. Correspondingly, the encapsulation can be carried out by filling liquid plastic encapsulation materials between each component 11 and each edge connector 12, and then curing at high temperature through the plastic encapsulation mold. In some embodiments, the plastic encapsulation layer 13 can also be formed by plastic material molding methods such as hot pressing molding and transfer molding.

[0107] The plastic packaging layer 13 may include a front surface 13 a and a back surface 13 b opposite to each other.

[0108] The plastic packaging layer 13 can be thinned from the back side 13 b by mechanical grinding, for example, by grinding with a grinding wheel, to reduce the volume.

[0109] During the process of forming the plastic encapsulation layer 13 and grinding the plastic encapsulation layer 13 , the component protection layer 110 can prevent the pad 112 and the electrical interconnection structure in the bare chip 111 from being damaged.

[0110] This step forms a plastic package body of the component 10 to be packaged.

[0111] Continue to refer to Figure 7 As shown, after the carrier 2 is removed, the component protection layer 110 provided on each component 11 and the coupling surface 12a of the edge connector 12 are in the same plane. In addition, a first support plate 3 can be provided on the back surface 13b of the plastic layer 13. The first support plate 3 can support each component 11 embedded in the plastic layer 13 in the subsequent process.

[0112] The first support plate 3 is a hard plate, which may include a glass plate, a ceramic plate, a metal plate, etc.

[0113] Next, refer to Figure 3 Step S3 in Figure 8 As shown, a rewiring layer 14 is formed on the component protection layer 110, the electrical connection points and the front side 13a of the plastic packaging layer 13 to electrically connect the components 11 in the group through the electrical connection points; and a first dielectric layer 17 is formed to embed the coupling surface 12a of the edge connector 12 and the rewiring layer 14.

[0114] In this embodiment, forming the redistribution layer 14 includes the following steps S31 - S34 .

[0115] Step S31 : forming a photoresist layer on the component protection layer 110 provided on each component 11 , the electrical connection point, the coupling surface 12 a of each edge connector 12 , and the front surface 13 a of the plastic packaging layer 13 .

[0116] In this step S31, in an optional solution, the photoresist layer formed can be a photosensitive film. The photosensitive film can be torn off from the tape and applied to the component protection layer 110, the electrical connection point, the coupling surface 12a of each edge connector 12 and the front surface 13a of the plastic layer 13 provided on each component 11. In other optional solutions, the photoresist layer can also be formed by first applying liquid photoresist and then heating and curing.

[0117] Step S32: exposing and developing the photoresist layer, and retaining the photoresist layer in a first predetermined area, the first predetermined area being complementary to the area where the metal block 14a of the rewiring layer 14 to be formed is located.

[0118] In this step S32, the photoresist layer is patterned. In other optional solutions, other easily removable sacrificial materials can also be used to replace the photoresist layer.

[0119] Step S33 : filling a metal layer in a complementary region of the first predetermined region to form a metal block 14 a of the rewiring layer 14 .

[0120] The locations of the metal blocks 14 a enable electrical connection to the pads 112 of one or more components 11 .

[0121] This step S33 can be completed by using an electroplating process. The process of electroplating copper or aluminum is relatively mature.

[0122] Specifically, before forming the photoresist layer in step S31, a seed layer (Seed Layer) can be formed by physical vapor deposition or chemical vapor deposition on the component protection layer 110, the electrical connection point, the coupling surface 12a of the edge connector 12 and the front surface 13a of the plastic layer 13 provided on each component 11. The seed layer can be used as a power supply layer for electroplating copper or aluminum.

[0123] Electroplating may include electrolytic plating or electrodeless plating. Electrolytic plating is to use the workpiece to be plated as a cathode to electrolyze the electrolyte, thereby forming a layer of metal on the workpiece to be plated. Electroless plating is a method of reducing and precipitating metal ions in the solution to form a metal layer on the workpiece to be plated. In some embodiments, the metal block 14a may also be formed by a method of first sputtering and then etching.

[0124] Step S34: removing the remaining photoresist layer in the first predetermined area by ashing.

[0125] After ashing, the seed layer in the first predetermined area is removed by dry etching or wet etching.

[0126] The metal blocks 14 a of the rewiring layer 14 may be polished to achieve a smooth upper surface, for example, by chemical mechanical polishing.

[0127] It should be noted that the metal blocks 14a of the rewiring layer 14 in step S3 are arranged according to design requirements, and the distribution of the rewiring layer 14 on each component 11 in different groups of the packaged parts 10 may be the same or different.

[0128] In the step of forming the first dielectric layer 17 , in order to prevent the plastic encapsulation layer 13 from being scratched during the process, the first dielectric layer 17 may also be formed on the front side 13 a of the plastic encapsulation layer 13 .

[0129] The first dielectric layer 17 is an insulating material, specifically an insulating resin material or an inorganic material. The insulating resin material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), an organic polymer film, an organic polymer composite material or other organic materials with similar insulating properties.

[0130] The insulating resin material can be pressed onto the coupling surface 12a of the edge connector 12, the rewiring layer 14 and the front side 13a of the plastic layer 13 by a) a lamination process, or b) first coated on the coupling surface 12a of the edge connector 12, the rewiring layer 14 and the front side 13a of the plastic layer 13 and then cured, or c) cured on the coupling surface 12a of the edge connector 12, the rewiring layer 14 and the front side 13a of the plastic layer 13 by an injection molding process.

[0131] When the material of the first dielectric layer 17 is an inorganic material such as silicon dioxide or silicon nitride, it can be formed on the coupling surface 12 a of the edge connector 12 , the rewiring layer 14 , and the front surface 13 a of the plastic layer 13 through a deposition process.

[0132] Compared with inorganic materials, the tensile stress of the insulating resin material is smaller, which can prevent the plastic package from warping when the first dielectric layer 17 is formed over a large area.

[0133] The first dielectric layer 17 may include one or more layers.

[0134] After the first dielectric layer 17 is formed, refer to Fig. 9 As shown, the first support plate 3 may be removed, and a second support plate 4 may be disposed on the first dielectric layer 17 .

[0135] The first support plate 3 can be removed by conventional removal methods such as laser stripping and UV irradiation.

[0136] The second support plate 4 may play a supporting role in the subsequent steps of forming the conductive plug 15 , and / or forming the connecting line 16 , and / or forming the second dielectric layer 18 .

[0137] The second support plate 4 is a hard plate, which may include a glass plate, a ceramic plate, a metal plate, etc.

[0138] Afterwards, refer to Figure 3 Step S4 in Fig.10 As shown, a plurality of conductive plugs 15 are formed in the plastic layer 13 through the back side 13 b of the plastic layer 13 to lead the edge connector 12 and the redistribution layer 14 to the back side 13 b of the plastic layer 13 .

[0139] This step S4 may include the following steps S41 to S42.

[0140] Step S41 : forming a plurality of through holes 13 c in the plastic packaging layer 13 through the back side 13 b of the plastic packaging layer 13 , wherein a portion of the through holes 13 c expose the edge connector 12 , and a portion of the through holes 13 c expose the redistribution layer 14 .

[0141] Step S42 : Fill the through hole 13 c with a conductive material to form a conductive plug 15 .

[0142] The conductive material may be copper, aluminum, etc. The method of filling the conductive material may refer to the method of forming the metal block 14 a of the rewiring layer 14 .

[0143] The conductive material outside the through hole 13c can be removed by chemical mechanical polishing.

[0144] The number and position of the conductive plugs 15 contacting the redistribution layer 14 may be determined according to a predetermined circuit layout.

[0145] Next, refer to Figure 3 Step S5 in Fig.11 As shown, a connection line 16 is formed on the back side 13 b of the plastic packaging layer 13 to connect the conductive plugs 15 in the group; and a second dielectric layer 18 is formed to bury the connection line 16 .

[0146] The method for forming the connection line 16 may refer to the method for forming the metal block 14a in the redistribution layer 14. The layout of the connection line 16 may be determined according to a predetermined layout.

[0147] The formation of the connection line 16 may also be performed in the same process as step S42, and the process of planarizing and removing the conductive material outside the through hole 13c may be omitted.

[0148] The material and formation method of the second dielectric layer 18 may refer to the material and formation method of the first dielectric layer 17 .

[0149] In the step of forming the second dielectric layer 18 , in order to prevent the plastic encapsulation layer 13 from being scratched during the process, the second dielectric layer 18 may also be formed on the back side 13 b of the plastic encapsulation layer 13 .

[0150] The second dielectric layer 18 may include one or more layers.

[0151] Next, refer to Figure 3 Step S6 in Fig.12 As shown, the first dielectric layer 17 embedding the coupling surface 12a of the edge connector 12 is removed.

[0152] When the first dielectric layer 17 is a laser-reactive material, it is removed by laser patterning. When the first dielectric layer 17 is a material that can be removed by dry etching or wet etching, it is removed by dry etching or wet etching. When the first dielectric layer 17 is a photosensitive material, it is removed by first exposing and then developing.

[0153] After the coupling surface 12 a of the edge connector 12 is exposed, an anti-oxidation layer may be formed on the coupling surface 12 a .

[0154] The anti-oxidation layer may include: a) a tin layer, or b) a nickel layer and a gold layer stacked from bottom to top, or c) a nickel layer, a palladium layer and a gold layer stacked from bottom to top. The anti-oxidation layer may be formed by an electroplating process. The material of the edge connector 12 may be copper, and the anti-oxidation layer may prevent copper oxidation, thereby preventing the electrical connection performance from being deteriorated due to copper oxidation.

[0155] In some embodiments, the anti-oxidation layer may have been formed in the edge connector 12 provided in step S1 .

[0156] After the first dielectric layer 17 of the coupling surface 12a of the embedded edge connector 12 is removed, refer to Fig.12 As shown, the second support plate 4 can be removed.

[0157] The second support plate 4 can be removed by conventional removal methods such as laser stripping and UV irradiation.

[0158] Afterwards, refer to Figure 3 Step S7 in Fig.12 and Figure 2 As shown, a plurality of chip packaging structures 1 are formed by cutting, and each chip packaging structure 1 includes a group of components 10 to be packaged.

[0159] After the above steps, each component 11 in a group of components to be packaged 10 can be connected to an external circuit through the edge connector 12, so that the performance of the chip packaging structure 1 is reliable.

[0160] Fig.13 FIG. 2 is a schematic cross-sectional view of a chip packaging structure according to a second embodiment of the present invention. Fig.13As shown, the chip packaging structure 2 and its manufacturing method in this embodiment are similar to Figure 1 The chip packaging structure 1 and the manufacturing method thereof are substantially the same, with the only difference being that the redistribution layer 14 includes two layers.

[0161] The metal blocks 14 b of the second re-wiring layer are selectively electrically interconnected with the metal blocks 14 a of the first re-wiring layer, so that a more complex circuit layout can be realized.

[0162] In some embodiments, the redistribution layer 14 may include three or more layers.

[0163] Fig.14 1 is a schematic top view of a chip packaging structure according to a third embodiment of the present invention. Fig.15 FIG. 1 is a schematic cross-sectional view of a chip packaging structure according to a third embodiment of the present invention. Fig.14 and Fig.15 As shown, the chip packaging structure 3 and its manufacturing method in this embodiment are similar to Figure 2 , Fig.13 The chip packaging structures 1 and 2 and their manufacturing methods are substantially the same, with the only difference being that the component 11 includes a bare chip 111 and a passive device 113 .

[0164] The passive device 113 may include resistors, inductors and capacitors, and their common feature is that they can work when there is a signal without adding power to the circuit. The passive device 113 includes an electrical connection point, which is located on the functional surface 113a of the component to achieve the connection / output of the electrical signal of the passive device 113.

[0165] This embodiment does not limit the number and types of the bare chips 111 and passive components 113 in each packaged component 10 .

[0166] The chip packaging structure 3 in this embodiment realizes the external circuit connection between the chip and the passive device 113 through the edge connector 12 .

[0167] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A chip packaging structure, characterized in that: include: A plurality of components, each of which comprises an electrical connection point, wherein the electrical connection point is located on a functional surface of the component; A component protection layer, covering the functional surface of the component, wherein the component protection layer exposes the electrical connection point; an edge connector, the edge connector comprising a coupling surface; The edge connector is located on one side of the plurality of components; the plurality of components are arranged at intervals in a direction from close to the edge connector toward away from the edge connector; A plastic encapsulation layer, covering the edge connector and the plurality of components, wherein the front side of the plastic encapsulation layer exposes the component protection layer, the electrical connection points and the coupling surface of the edge connector; A rewiring layer, located on the front of the electrical connection points, the component protection layer and the plastic packaging layer, and the rewiring layer is used to electrically connect each of the components through the electrical connection points; A plurality of conductive plugs are located in the plastic packaging layer, and the plurality of conductive plugs are used to lead the edge connector and the redistribution layer to the back side of the plastic packaging layer; A connecting wire, located on the back of the plastic packaging layer, to electrically connect the conductive plugs; The edge connector included in the chip packaging structure and the plurality of components are arranged in a corresponding group, and the chip packaging structure realizes external circuit connection of the plurality of components in the same group through the included edge connector; A first dielectric layer, embedding the rewiring layer, the first dielectric layer exposing a coupling surface of the edge connector; The second dielectric layer buries the connecting wire.

2. The chip packaging structure according to claim 1, characterized in that: The component includes a bare chip, or the component includes a bare chip and a passive device; the electrical connection point of the bare chip is a pad.

3. The chip packaging structure according to claim 1, characterized in that: The material of the component protection layer is an insulating resin material or an inorganic material.

4. The chip packaging structure according to claim 1, characterized in that: The material of the first dielectric layer is an insulating resin material or an inorganic material; and / or the material of the second dielectric layer is an insulating resin material or an inorganic material.

5. The chip packaging structure according to claim 1, characterized in that: The rewiring layer includes two or more layers.

6. A method for manufacturing a chip packaging structure, characterized in that: include: A carrier board and a plurality of groups of components to be packaged are provided, each group of the components to be packaged includes an edge connector and a plurality of components, the components include electrical connection points, the electrical connection points are located on a functional surface of the components, the functional surface is covered with a component protection layer, the edge connector includes a coupling surface; the edge connector is located on one side of the plurality of components; the plurality of components are arranged at intervals in a direction from close to the edge connector to away from the edge connector; Fixing the plurality of groups of components to be packaged on the surface of the carrier, wherein the coupling surface of the component protection layer and the edge connector faces the carrier; Forming a plastic encapsulation layer on the surface of the carrier board to bury each group of the components to be packaged; removing the carrier board to expose the component protection layer, the coupling surface of the edge connector and the front side of the plastic encapsulation layer; An opening is formed in the component protection layer to expose the electrical connection point; a rewiring layer is formed on the component protection layer, the electrical connection point and the front surface of the plastic packaging layer to electrically connect the components in the group through the electrical connection point; a first dielectric layer is formed to embed the coupling surface of the edge connector and the rewiring layer; forming a plurality of conductive plugs in the plastic encapsulation layer through the back side of the plastic encapsulation layer to lead the edge connector and the redistribution layer to the back side of the plastic encapsulation layer; forming a connecting wire on the back side of the plastic encapsulation layer to electrically connect the conductive plugs in the group; and forming a second dielectric layer to bury the connecting wire; removing a first dielectric layer embedding a coupling surface of the edge connector; Cutting forms a plurality of chip packaging structures, each chip packaging structure contains a group of parts to be packaged, the edge connector of each chip packaging structure and a plurality of components are arranged in a corresponding group, and each of the chip packaging structures realizes external circuit connection of a plurality of components in the same group through the edge connector contained therein.

7. A method for manufacturing a chip packaging structure, characterized in that: include: A carrier board and a plurality of groups of components to be packaged are provided, each group of the components to be packaged includes an edge connector and a plurality of components, the components include electrical connection points, the electrical connection points are located on a functional surface of the components, the functional surface is covered with a component protection layer, the edge connector includes a coupling surface; the edge connector is located on one side of the plurality of components; the plurality of components are arranged at intervals in a direction from close to the edge connector to away from the edge connector; The plurality of groups of components to be packaged are fixed on the surface of the carrier, wherein the component protection layer has an opening exposing the electrical connection point, wherein the coupling surface of the component protection layer and the edge connector faces the carrier; Forming a plastic encapsulation layer on the surface of the carrier board to bury each group of the components to be packaged; removing the carrier board to expose the component protection layer, the coupling surface of the edge connector and the front side of the plastic encapsulation layer; After removing the carrier, the electrical connection points are exposed; a rewiring layer is formed on the front surface of the component protection layer, the electrical connection points and the plastic packaging layer to electrically connect the components in the group through the electrical connection points; and a first dielectric layer is formed to embed the coupling surface of the edge connector and the rewiring layer; forming a plurality of conductive plugs in the plastic encapsulation layer through the back side of the plastic encapsulation layer to lead the edge connector and the redistribution layer to the back side of the plastic encapsulation layer; forming a connecting wire on the back side of the plastic encapsulation layer to electrically connect the conductive plugs in the group; and forming a second dielectric layer to bury the connecting wire; removing a first dielectric layer embedding a coupling surface of the edge connector; Cutting forms a plurality of chip packaging structures, each chip packaging structure contains a group of parts to be packaged, the edge connector of each chip packaging structure and a plurality of components are arranged in a corresponding group, and each of the chip packaging structures realizes external circuit connection of a plurality of components in the same group through the edge connector contained therein.

8. The method for manufacturing a chip packaging structure according to claim 6 or 7, characterized in that: The component includes a bare chip, or the component includes a bare chip and a passive device; the electrical connection point of the bare chip is a pad.

9. The method for manufacturing a chip packaging structure according to claim 6 or 7, characterized in that: The material of the component protection layer is an insulating resin material or an inorganic material.

10. The method for manufacturing a chip packaging structure according to claim 6 or 7, characterized in that: The material of the first dielectric layer is an insulating resin material or an inorganic material; and / or the material of the second dielectric layer is an insulating resin material or an inorganic material.

11. The method for manufacturing a chip packaging structure according to claim 6 or 7, characterized in that: The material of the first dielectric layer is a laser reactive material, and the first dielectric layer on the coupling surface of the edge connector is removed by laser patterning.

12. The method for manufacturing a chip packaging structure according to claim 6 or 7, characterized in that: The rewiring layer includes two or more layers.

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