A high voltage integrated circuit

Abstract

The present invention relates to the field of electronic circuit technology, and specifically discloses a high-voltage integrated circuit, including a signal input circuit, a first Schmitt circuit, a filter, a level conversion circuit, a high-voltage DOMS circuit, an RS trigger, a signal output circuit and a temperature-controlled double pulse circuit, wherein the first Schmitt circuit is electrically connected to the signal input circuit and the filter respectively, the level conversion circuit is electrically connected to the filter, the temperature-controlled double pulse circuit is electrically connected to the level conversion circuit and the high-voltage DOMS circuit respectively, and the RS trigger is electrically connected to the high-voltage DOMS circuit and the signal output circuit respectively. The present invention adds a temperature-controlled double pulse circuit to control the distance between the double pulses according to the chip power consumption problem, so as to avoid the double pulse GEN from increasing the chip power consumption and heating in a short time, and ensure that the RS trigger can obtain a driving signal, and the higher the chip temperature, the farther the distance between the two pulses.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a high-voltage integrated circuit. Background Art

[0002] High voltage integrated circuit, or HVIC, is an integrated circuit product that converts MCU signals into IGBT driving signals. HVIC integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low voltage LEVELSHIFT, high voltage LEVELSHIFT, pulse generation circuit, delay circuit, filter circuit, overcurrent protection circuit, overheat protection circuit, undervoltage protection circuit, bootstrap circuit and other circuits. The single pulse GEN circuit in the existing HVIC high-side drive circuit generates pulses at the rising and falling edges of the HIN signal to drive DMOS. The pulse width is generally several hundred nanoseconds, so that HIN corresponds to HO. The basic high-side drive topology of HVIC is as follows: Figure 1 As shown. However, when the HVIC drives a large inductance circuit, the VS voltage will be pulled down in some cases, causing the RS trigger to be unable to record the signal from the single pulse GEN. To solve this problem, the single pulse signal GEN is changed to a double pulse GEN signal to ensure that the RS trigger can obtain the driving signal, but the double pulse GEN will increase the chip power consumption and heat in a short time. Summary of the invention

[0003] The technical problem to be solved by the present invention is that, in view of the above-mentioned defects of the prior art, a high-voltage integrated circuit is provided to solve the problem that when a single-pulse GEN circuit is used inside a traditional HVIC, when the driving load is a large inductance circuit, the VS voltage will be pulled down under certain circumstances, resulting in the RS trigger being unable to record the signal sent by the single-pulse GEN circuit. A temperature-controlled delay circuit is added to the double-pulse GEN circuit, that is, a temperature-controlled double-pulse circuit is added to control the distance between the double pulses according to the chip power consumption problem, thereby avoiding the double-pulse GEN from increasing the chip power consumption and generating heat in a short period of time, and ensuring that the RS trigger can obtain the driving signal.

[0004] In order to solve the above technical problems, the technical solution of the present invention is:

[0005] A high-voltage integrated circuit comprises a signal input circuit, a first Schmitt circuit, a filter, a level conversion circuit, a high-voltage DOMS circuit, an RS trigger, a signal output circuit and a temperature-controlled dual-pulse circuit, wherein the first Schmitt circuit is electrically connected to the signal input circuit and the filter, respectively, the level conversion circuit is electrically connected to the filter, the temperature-controlled dual-pulse circuit is electrically connected to the level conversion circuit and the high-voltage DOMS circuit, respectively, and the RS trigger is electrically connected to the high-voltage DOMS circuit and the signal output circuit, respectively.

[0006] Preferably, the temperature-controlled double-pulse circuit is composed of a temperature-controlled delay circuit, two single-pulse GEN circuits, and two OR gates.

[0007] Preferably, the OR gate includes a first OR gate and a second OR gate, the first OR gate and the second OR gate are electrically connected to the single-pulse GEN circuit respectively, the level conversion circuit is electrically connected to the single-pulse GEN circuit and the temperature-controlled delay circuit respectively, and the temperature-controlled delay circuit is electrically connected to the level conversion circuit and the single-pulse GEN circuit respectively.

[0008] Preferably, the temperature-controlled delay circuit includes a bandgap reference circuit, a PMOS tube Q3, a capacitor C1, a second Schmitt circuit and a pulse width adjustment circuit. The output end of the level conversion circuit is electrically connected to the PMOS tube Q3 and the pulse width adjustment circuit, respectively, the bandgap reference circuit is electrically connected to the capacitor C1 and the second Schmitt circuit, and the second Schmitt circuit is electrically connected to the single pulse GEN circuit.

[0009] Preferably, the bandgap reference circuit comprises a resistor R1, a resistor R2, a resistor R3, a transistor Q4 and a transistor Q5.

[0010] Preferably, one end of the resistor R1 and one end of the resistor R2 are both connected to the drain of the transistor Q3, the other end of the resistor R1, the collector of the transistor Q4 and the base of the transistor Q4 are all connected to the base of the transistor Q5, the other end of the resistor R2, the collector of the transistor Q5 and one end of the capacitor C1 are all connected to the second Schmitt circuit, one end of the resistor R3 is connected to the emitter of the transistor Q5, and the emitter of the transistor Q4, the other end of the resistor R3 and the other end of the capacitor C1 are all grounded.

[0011] By adopting the above technical scheme, a high-voltage integrated circuit provided by the present invention has the following beneficial effects: the first Schmidt circuit in the high-voltage integrated circuit is electrically connected to the signal input circuit and the filter respectively, the level conversion circuit is electrically connected to the filter, the temperature-controlled dual-pulse circuit is electrically connected to the level conversion circuit and the high-voltage DOMS circuit respectively, and the RS trigger is electrically connected to the high-voltage DOMS circuit and the signal output circuit respectively. By adding a temperature-controlled dual-pulse circuit to control the distance between the dual pulses according to the chip power consumption problem, it is avoided that the dual pulse GEN will increase the chip power consumption and generate heat in a short time; and the single pulse signal GEN is changed to a dual-pulse GEN signal, which can ensure that the RS trigger can obtain the driving signal, and the chip adjusts the interval between the two pulse signals (pluse) by itself according to the temperature. The higher the temperature, the greater the distance between the two pulse signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of a basic high-side driver topology structure of an existing HVIC;

[0013] Figure 2 It is a control system diagram of the temperature-controlled double-pulse circuit in the present invention;

[0014] Figure 3 The output pulse signal waveform diagram of the temperature control double pulse circuit of the present invention;

[0015] Figure 4 It is a working principle diagram of the temperature control double pulse circuit in the present invention;

[0016] Figure 5 This is a waveform diagram of an output pulse signal of a temperature control double pulse circuit embodiment 1 of the present invention;

[0017] Figure 6 It is a control embodiment schematic diagram of the temperature control double pulse circuit in the present invention;

[0018] In the figure, 001-first Schmitt circuit, 002-filter, 003-level conversion circuit, 004-single pulse GEN circuit, 005-pulse width adjustment circuit, 006-temperature double pulse circuit, 007-temperature control delay circuit, 008-first OR gate, 009-second OR gate, 010-second Schmitt circuit. DETAILED DESCRIPTION

[0019] The specific embodiments of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0020] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0021] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0022] like Figure 2-6 As shown, the high-voltage integrated circuit includes a signal input circuit, a first Schmitt circuit 001, a filter 002, a level conversion circuit 003, a high-voltage DOMS circuit, an RS trigger, a signal output circuit and a temperature-controlled double pulse circuit 006. The first Schmitt circuit 001 is electrically connected to the signal input circuit and the filter 002, respectively. The level conversion circuit 003 is electrically connected to the filter 002. The temperature-controlled double pulse circuit 006 is electrically connected to the level conversion circuit 003 and the high-voltage DOMS circuit, respectively. The RS trigger is electrically connected to the high-voltage DOMS circuit and the signal output circuit, respectively. The high-voltage DOMS circuit is composed of a transistor Q1 and a transistor Q2. It can be understood that the temperature-controlled double pulse circuit 006 is composed of a temperature-controlled delay circuit 007, two single-pulse GEN circuits 004, and two OR gates; the OR gate includes a first OR gate 008 and a second OR gate 009, and the first OR gate 008 and the second OR gate 009 are electrically connected to the single-pulse GEN circuit 4 respectively, the level conversion circuit 003 is electrically connected to the single-pulse GEN circuit 004 and the temperature-controlled delay circuit 007 respectively, and the temperature-controlled delay circuit 007 is electrically connected to the level conversion circuit 003 and the single-pulse GEN circuit 004 respectively. The upper bridge of the high-voltage integrated circuit uses dual pluses to drive the DMOS to turn on and off: the interval between the two pluses is adjusted by the chip through the temperature (the higher the temperature, the larger the interval), which is used to solve: 1. When the HVIC drives a large inductance circuit, the VS voltage will be pulled down under certain circumstances, causing the RS trigger to be unable to record the signal sent by the single pulse GEN; 2. Add a temperature control & delay circuit to the dual-pulse GEN circuit to control the distance between the dual pulses according to the chip problem, so as to avoid the dual-pulse GEN from increasing the chip power consumption and heating in a short period of time.

[0023] It can be understood that, generally speaking, the input end HIN of the signal input circuit inputs a high-level signal, which is outputted as a HINa pulse signal through the Schmitt circuit 001, the filter 002, and the level conversion circuit 003. The single-pulse GEN circuit 004 outputs short pulse signals G1 and G2 respectively through the rising and falling edges of the HINa pulse signal to drive high-voltage DMOS circuits such as transistors Q1 and Q2. The high-voltage DMOS circuit turns on and off to trigger the RS trigger to output a pulse signal, and controls the HO to output a driving pulse signal. The working logic of the single-pulse GEN circuit: when the HINa input is high level, the single-pulse GEN circuit 004 detects the HIN rising edge signal, G1 outputs a short pulse signal, and at this time, G2 outputs a low-level signal; when the single-pulse GEN circuit 004 detects the HIN falling edge signal, G2 outputs a short pulse signal, that is, the pulse width of the HIN input signal is consistent with the distance between the short pulses output by G1 and G2.

[0024] Understandable, such as Figure 2 As shown, when the temperature-controlled double pulse circuit 006 detects that HINa is the rising edge of a high-level signal, a double pulse signal is output through G1, and the time distance between the double pulses is controlled by the temperature-controlled delay circuit in the temperature-controlled double pulse circuit 006, that is, when the temperature is higher, the distance between the double pulses is larger, and when the temperature is lower, the distance between the double pulses is closer. When the temperature-controlled double pulse circuit 006 detects that HINa is the falling edge of a high-level signal, a double pulse signal is output through G2, and the time distance between the double pulses is controlled by the temperature-controlled delay circuit in the temperature-controlled double pulse circuit 006, that is, when the temperature is higher, the distance between the double pulses is larger, and when the temperature is lower, the distance between the double pulses is closer. Figure 3 As shown in the figure, when HINa is at a high level, G1 and G2 output double pulse signals. The higher the chip temperature, the wider the distance between the double pulses. When the signal temperature is t1, the distance between the double pulses is S1. When the temperature reaches a higher temperature t2, the distance between the double pulses is S2.

[0025] Understandable, such as Figure 4-5As shown, when HINa is at a high level: when the single pulse GEN circuit 004 detects the rising edge of the HINa high level signal, it outputs a single pulse signal a1, and at this time, G1 of the first OR gate 008 outputs a high level; when the single pulse GEN004 detects the falling edge of the HINa high level signal, it outputs a single pulse signal b1, and at this time, G2 of the second OR gate 009 outputs a high level. When the temperature control delay circuit 007 detects that HINa is at a high level, the input signal of HINa is delayed to the single pulse GEN circuit 004 according to the detected temperature. The higher the detected temperature, the longer the delay time. When the single pulse GEN circuit 004 detects the rising edge of the high level signal output by the temperature control delay circuit 007, it outputs a single pulse signal b2, and at this time, G1 of the OR gate 008 outputs a high level; when the single pulse GEN circuit 004 detects the falling edge of the high level signal output by the temperature control delay circuit 007, it outputs a single pulse signal a2, and at this time, G2 of the second OR gate 009 outputs a high level.

[0026] Specifically, Figure 6 As shown, the temperature control delay circuit includes a bandgap reference circuit, a PMOS tube Q3, a capacitor C1, a second Schmitt circuit and a pulse width adjustment circuit. The output end of the level conversion circuit is electrically connected to the PMOS tube Q3 and the pulse width adjustment circuit respectively, the bandgap reference circuit is electrically connected to the capacitor C1 and the second Schmitt circuit respectively, the second Schmitt circuit is electrically connected to the single pulse GEN circuit, and the pulse width adjustment circuit adopts an RS trigger; the bandgap reference circuit includes a resistor R1, a resistor R2, a resistor R3, The transistor Q4 and the transistor Q5 are composed of one end of the resistor R1 and one end of the resistor R2 are connected to the drain of the transistor Q3, the other end of the resistor R1, the collector of the transistor Q4 and the base of the transistor Q4 are connected to the base of the transistor Q5, the other end of the resistor R2, the collector of the transistor Q5 and one end of the capacitor C1 are connected to the second Schmitt circuit, one end of the resistor R3 is connected to the emitter of the transistor Q5, the emitter of the transistor Q4, the other end of the resistor R3 and the other end of the capacitor C1 are grounded.

[0027] Understandable, such as Figure 6 As shown, resistors R1, R2, R3, transistor Q4, and Q5 form a bandgap reference as a PTAT current source, and the current Iout flowing through resistor R3 is the PTAT current. The voltage at point A As the temperature rises, the Iout current increases, V A The value becomes smaller, and the time for the voltage across the capacitor C1 to charge to the trigger threshold of the Schmitt circuit 010 is longer, that is, the higher the temperature, the longer the delay time for the HINa signal to be transmitted to the single pulse GEN circuit 004 is.

[0028] It can be understood that the present invention has a reasonable design and unique structure, and can solve the problem that when a single-pulse GEN circuit is used inside a traditional HVIC, when the driving load is a large inductance circuit, the VS voltage will be pulled down under certain circumstances, causing the RS trigger to be unable to record the signal sent by the single-pulse GEN circuit; a temperature control delay circuit is added to the double-pulse GEN circuit to control the distance between the double-pulse GEN signals according to the chip problem, so as to avoid the double-pulse GEN signal increasing the chip power consumption and heating in a short time.

[0029] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions and variations of these embodiments are made without departing from the principles and spirit of the present invention, and still fall within the scope of protection of the present invention.

Claims

1. A high voltage integrated circuit, comprising a signal input circuit, a first Schmitt circuit, a filter, a level conversion circuit, The high voltage DOMS circuit, RS trigger and signal output circuit are characterized by: It also includes a temperature-controlled double-pulse circuit, the first A Schmitt circuit is electrically connected to the signal input circuit and the filter respectively, and the level conversion circuit is electrically connected to the filter The temperature control double pulse circuit is electrically connected to the level conversion circuit and the high-voltage DOMS circuit respectively, and the RS trigger The transmitter is electrically connected to the high-voltage DOMS circuit and the signal output circuit respectively; the temperature-controlled double-pulse circuit consists of a temperature-controlled delay A delay circuit, two single pulse GEN circuits, and two OR gates, wherein the OR gates include a first OR gate and a second OR gate. The first OR gate and the second OR gate are electrically connected to the single pulse GEN circuit respectively, and the level conversion circuit is electrically connected to the single pulse The pulse GEN circuit and the temperature control delay circuit are electrically connected, and the temperature control delay circuit is respectively connected to the level conversion circuit and the single pulse The high voltage DOMS circuit is composed of a transistor Q1 and a transistor Q2. The gate of transistor Q2 is electrically connected to the temperature control double pulse circuit, and the drain of transistor Q1 is electrically connected to the S terminal of RS trigger. The drain of the transistor Q2 is electrically connected to the R terminal of the RS trigger, and the transistor Q1 and the transistor Q2 are electrically connected. The sources are grounded.

2. The high voltage integrated circuit according to claim 1, characterized in that: The temperature controlled delay circuit includes a bandgap reference circuit, PMOS tube Q3, capacitor C1, a second Schmitt circuit and a pulse width adjustment circuit, the input of the level conversion circuit The output ends are electrically connected to the PMOS tube Q3 and the pulse width adjustment circuit respectively, and the bandgap reference circuit is electrically connected to the capacitor C1 respectively. The second Schmitt circuit is electrically connected to the single-pulse GEN circuit.

3. The high voltage integrated circuit according to claim 2, characterized in that: The bandgap reference circuit includes a resistor R1, resistor R2, resistor R3, transistor Q4 and transistor Q5.

4. The high voltage integrated circuit according to claim 3, characterized in that: One end of the resistor R1 and the other end of the resistor R2 One end is connected to the drain of transistor Q3, the other end of the resistor R1, the collector of transistor Q4 and the The base is connected to the base of transistor Q5, the other end of the resistor R2, the collector of transistor Q5 and one end of capacitor C1. The ends of the resistor R3 are connected to the emitter of the transistor Q5. The emitter of the tube Q4, the other end of the resistor R3 and the other end of the capacitor C1 are all grounded.

Images