Display device and method of manufacturing the same

Abstract

A display device and a manufacturing method thereof may be provided herein. A display device according to an embodiment of the present disclosure may include: a substrate; a first electrode and a second electrode, which are on the substrate and spaced apart from each other; a light-emitting element, which is on the substrate and has a first end and a second end; a third electrode, which is on the light-emitting element and electrically couples the first electrode with the first end of the light-emitting element; an insulating pattern, which is on the third electrode and exposes the second end of the light-emitting element; and a fourth electrode, which is on the light-emitting element and electrically couples the second electrode with the second end of the light-emitting element. A gap may be formed between the light-emitting element and the insulating pattern.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a display device including a light emitting element and a method of manufacturing the display device. Background Art

[0002] A light emitting diode (hereinafter, referred to as "LED") can have relatively satisfactory durability even under harsh environmental conditions and has excellent performance in terms of life span and brightness. Recently, research on a technology for applying such a light emitting diode to various display devices has become quite active.

[0003] As part of such research, a technology is being developed to manufacture rod-type LEDs having a small size corresponding to the micrometer or nanometer scale using an inorganic crystal structure (e.g., a structure obtained by growing a nitride-based semiconductor). For example, the rod-type LED can be manufactured to a size small enough to form a pixel of a self-luminous display device, etc. Summary of the invention

[0004] Technical issues

[0005] An object of the present disclosure is to provide a display device capable of minimizing contact failure of a light emitting element and simplifying a manufacturing process, and a method of manufacturing the display device.

[0006] The objects of the present disclosure are not limited to the above-mentioned objects, and other unmentioned objects will be clearly understood by those skilled in the art from the appended claims.

[0007] Technical Solutions

[0008] A display device according to an embodiment of the present disclosure may include: a substrate; a first electrode and a second electrode, which are disposed on the substrate and spaced apart from each other; a light-emitting element, which is disposed on the substrate and has a first end and a second end; a third electrode, which is disposed on the light-emitting element and electrically couples the first electrode with the first end of the light-emitting element; an insulating pattern, which is disposed on the third electrode and exposes the second end of the light-emitting element; and a fourth electrode, which is disposed on the light-emitting element and electrically couples the second electrode with the second end of the light-emitting element. A gap may be formed between the light-emitting element and the insulating pattern.

[0009] The insulating pattern may include a first side overlapping the light emitting element and disposed adjacent to the second electrode. The third electrode may include a second side overlapping the light emitting element and disposed adjacent to the second electrode. In a plan view, the second side may be closer to the first electrode than the first side.

[0010] The gap may be closed and formed by a portion of the light emitting element, a portion of the third electrode, a portion of the insulating pattern, and a portion of the fourth electrode.

[0011] The insulating pattern may include an organic insulating layer including an organic material, and the insulating pattern may cover at least a portion of the second side of the third electrode.

[0012] The insulating pattern may include an inorganic insulating layer formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the insulating pattern does not cover the second side of the third electrode.

[0013] The display device may further include an insulating layer disposed on the first electrode and the second electrode. The insulating layer may include a first contact hole through which a portion of the first electrode is exposed and a second contact hole through which a portion of the second electrode is exposed.

[0014] The third electrode may be electrically coupled to the first electrode through the first contact hole, the fourth electrode may be electrically coupled to the second electrode through the second contact hole, and the third electrode and the fourth electrode may be electrically separated from each other.

[0015] The insulating layer may include an inorganic insulating layer formed of an inorganic material, and a groove may be formed between the insulating layer and the light emitting element.

[0016] A display device according to an embodiment of the present disclosure may include: a substrate; a first electrode and a second electrode, which are on the substrate and spaced apart from each other; a light-emitting element, which is on the substrate and has a first end and a second end; a third electrode, which is disposed on the light-emitting element and electrically couples the first electrode with the first end of the light-emitting element; an insulating pattern, which is on the third electrode and exposes the second end of the light-emitting element; and a fourth electrode, which is on the light-emitting element and electrically couples the second electrode with the second end of the light-emitting element. At least a portion of the insulating pattern may be in contact with the light-emitting element.

[0017] The insulating pattern may include a first side overlapping the light emitting element and disposed adjacent to the second electrode. The third electrode may include a second side overlapping the light emitting element and disposed adjacent to the second electrode. In a plan view, the second side may be closer to the first electrode than the first side.

[0018] The insulating pattern may include an organic insulating layer including an organic material, and the insulating pattern may cover at least a portion of the second side of the third electrode.

[0019] The display device may further include an insulating layer disposed on the first electrode and the second electrode. The insulating layer may include a first contact hole through which a portion of the first electrode is exposed and a second contact hole through which a portion of the second electrode is exposed.

[0020] The third electrode may be electrically coupled to the first electrode through the first contact hole, the fourth electrode may be electrically coupled to the second electrode through the second contact hole, and the third electrode and the fourth electrode may be electrically separated from each other.

[0021] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: forming a first electrode and a second electrode on a substrate; forming a first insulating material layer on the first electrode, the second electrode and the substrate; forming a first insulating layer exposing a portion of the first electrode and a portion of the second electrode by patterning the first insulating material layer; providing a light-emitting element on the first insulating layer and self-aligning the light-emitting element; sequentially forming a conductive material layer and a second insulating material layer on the light-emitting element and the first insulating layer; forming an insulating pattern exposing a first end of the light-emitting element by patterning the conductive material layer and the second insulating material layer through a first etching process; forming a third electrode having one end overlapping with the light-emitting element and having a concave shape by etching the patterned conductive material layer through a second etching process using the insulating pattern as a mask, the third electrode being electrically connected to the second end of the light-emitting element; and forming a fourth electrode electrically connected to the second electrode and the first end of the light-emitting element on the first insulating layer.

[0022] The first etching process may include a dry etching process, and the second etching process may include a wet etching process.

[0023] The insulating pattern may include an organic insulating layer including an organic material. The method may further include curing the insulating pattern after forming the third electrode and before forming the fourth electrode. The insulating pattern may fill at least a portion of the concave shape of the third electrode.

[0024] At least a portion of the insulating pattern may be in contact with the light emitting element.

[0025] The insulating pattern may include an inorganic insulating layer formed of an inorganic material. Forming the fourth electrode may include forming a gap surrounded by a portion of the light emitting element, a portion of the third electrode, a portion of the insulating pattern, and a portion of the fourth electrode.

[0026] The third electrode may be electrically separated from the fourth electrode.

[0027] The method may further include forming a second insulating layer covering the third electrode and the fourth electrode on the third electrode and the fourth electrode.

[0028] Details of various implementations are included in the detailed description and drawings.

[0029] Beneficial Effects

[0030] Various embodiments of the present disclosure may provide a display device capable of preventing the occurrence of a contact failure of a light emitting element and simplifying a manufacturing process, and a method of manufacturing the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1a and Figure 1bare perspective views each showing a light emitting element according to an embodiment of the present disclosure.

[0032] Figure 2a and Figure 2b are circuit diagrams each showing a unit emission area of ​​a display device according to an embodiment of the present disclosure.

[0033] Figure 3 is a plan view of a unit emission area of ​​a display device.

[0034] Figure 4a and Figure 4b It is along Figure 3 A cross-sectional view taken along line AA'.

[0035] Figure 5a yes Figure 4a An enlarged cross-sectional view of area Q.

[0036] Figure 5b and Figure 5c yes Figure 5a A modified example of the structure shown in .

[0037] Figures 6a to 6f The order is shown in the manufacturing Figure 3 A schematic plan view of a display device of the method.

[0038] Figures 7a to 7k The order is shown in the manufacturing Figure 4a A cross-sectional view of a method of displaying a device as shown in FIG.

[0039] Figure 8 is a plan view schematically showing a display device according to an embodiment of the present disclosure.

[0040] Fig. 9 It is schematically shown that the Figure 8 1 is a plan view of first to third sub-pixels in one of the pixels shown in .

[0041] Fig.10 It is along Fig. 9 A cross-sectional view taken along line BB'. DETAILED DESCRIPTION

[0042] The beneficial effects and features of the present disclosure and the methods for realizing the beneficial effects and features of the present disclosure will be apparent with reference to the embodiments described in detail later in conjunction with the accompanying drawings. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art, and the present invention will be limited only by the appended claims.

[0043] It will be understood that when an element or layer is referred to as being “on” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. The same reference numerals refer to the same elements throughout.

[0044] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure. In the present disclosure, the singular form is also intended to include the plural form unless the context clearly indicates otherwise.

[0045] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0046] Figure 1a and Figure 1b are perspective views each showing a light emitting element according to an embodiment of the present disclosure. Figure 1a and Figure 1b A cylindrical light emitting element LD is shown, but the present disclosure is not limited thereto.

[0047] refer to Figure 1a and Figure 1b The light emitting element LD according to the embodiment of the present disclosure may include a first conductive semiconductor layer 11 , a second conductive semiconductor layer 13 , and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 .

[0048] For example, the light emitting element LD may be implemented as a stacked body formed by sequentially stacking the first conductive semiconductor layer 11 , the active layer 12 , and the second conductive semiconductor layer 13 .

[0049] In an embodiment of the present disclosure, the light emitting element LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end in the longitudinal direction.

[0050] In an implementation, one of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the first end, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed on the second end.

[0051] In an embodiment of the present disclosure, the light emitting element LD may be arranged in a cylindrical shape. Here, the term "rod-type" includes a rod-like shape and a strip-like shape (such as a cylindrical shape and a prism shape) extending in the longitudinal direction (i.e., extending to have an aspect ratio greater than 1). For example, the length of the light emitting element LD may be greater than its diameter.

[0052] The light emitting element LD can be manufactured in a small size, with a diameter and / or a length corresponding to, for example, a micrometer-scale or nanometer-scale size.

[0053] However, the size of the light emitting element LD according to the embodiment of the present disclosure is not limited thereto, and the size of the light emitting element LD may be changed according to the conditions of the display device to which the light emitting element LD is applied.

[0054] The first conductive semiconductor layer 11 (or first semiconductor layer) may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include a semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant such as Si, Ge, or Sn.

[0055] The material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0056] The active layer 12 may be formed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12. For example, the cladding layer may be formed as an AlGaN layer or an InAlGaN layer. In addition, the active layer 12 may be formed using a material such as AlGaN or AlInGaN.

[0057] If an electric field having a predetermined voltage or more is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light by recombination of electron-hole pairs in the active layer 12 .

[0058] The second conductive semiconductor layer 13 (or the second semiconductor layer) may be disposed on the active layer 12 and include a semiconductor layer having a type different from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a semiconductor layer including any one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg.

[0059] The material forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may be formed of various other materials.

[0060] In an embodiment of the present disclosure, the light emitting element LD may include not only a first conductive semiconductor layer 11, an active layer 12 and a second conductive semiconductor layer 13, but also a fluorescent layer, another active layer, another semiconductor layer and / or an electrode layer arranged above and / or below each layer.

[0061] In an implementation, the light emitting element LD may further include at least one electrode layer disposed on one side (eg, upper surface) of the second conductive semiconductor layer 13 or one side (eg, lower surface) of the first conductive semiconductor layer 11 .

[0062] For example, Figure 1b As shown in , the light emitting element LD may further include an electrode layer 15 disposed on one side of the second conductive semiconductor layer 13. The electrode layer 15 may be an ohmic contact electrode, but is not limited thereto. In addition, the electrode layer 15 may include a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and oxides or alloys thereof or transparent conductive materials such as ITO may be used alone or in combination with each other. However, the present disclosure is not limited thereto. In an embodiment, the electrode layer 15 may be substantially transparent or translucent. Thus, the light generated from the light emitting element LD may be emitted to the outside after passing through the electrode layer 15.

[0063] The light emitting element LD may further include an insulating film 14. In the embodiment of the present disclosure, the insulating film 14 may be omitted, or may be provided to cover only some of the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13.

[0064] For example, the insulating film 14 may be provided on a portion of the light emitting element LD except for the opposite ends thereof so that the opposite ends of the light emitting element LD are exposed.

[0065] To illustrate, Figure 1a and Figure 1b The insulating film 14 of which a part has been removed is shown. The entire side surface of the light emitting element LD may be surrounded by the insulating film 14 .

[0066] The insulating film 14 may be provided to surround at least a portion of the outer peripheral surface of the first conductive semiconductor layer 11, the active layer 12, and / or the second conductive semiconductor layer 13. For example, the insulating film 14 may surround the outer peripheral surface of the active layer 12. In the case where the light emitting element LD includes the electrode layer 15, the insulating film 14 may surround at least a portion of the outer peripheral surface of the electrode layer 15.

[0067] In an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a material selected from SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 At least one insulating material selected from the group consisting of, but not limited to, In other words, various materials having insulating properties can be used.

[0068] If the insulating film 14 is provided on the light emitting element LD, the active layer 12 may be prevented from being short-circuited with the first electrode and / or the second electrode (not shown).

[0069] In addition, due to the insulating film 14, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In the case where a plurality of light emitting elements LD are arranged in close contact with each other, the insulating film 14 can prevent an undesirable short circuit from occurring between the light emitting elements LD.

[0070] The light emitting element LD can be used as a light source of various display devices. For example, the light emitting element LD can be used as a light source element of a lighting device or a self-emitting display device.

[0071] Figure 2a and Figure 2b are circuit diagrams each showing a unit emission area of ​​a display device according to an embodiment of the present disclosure.

[0072] Specifically, Figure 2a and Figure 2b An example of forming a pixel of an active emission display panel is shown. In an embodiment of the present disclosure, a unit emission area may be a pixel area in which a single sub-pixel is disposed.

[0073] refer to Figure 2a , the sub-pixel SP may include at least one light emitting element LD and a driving circuit 144 coupled to the light emitting element LD and configured to drive the light emitting element LD.

[0074] The light emitting element LD may include a first electrode (eg, an anode electrode) coupled to a first driving power source VDD via a driving circuit 144, and a second electrode (eg, a cathode electrode) coupled to a second driving power source VSS.

[0075] The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the potential of the second driving power source VSS may be lower than the potential of the first driving power source VDD by a value equal to or greater than the threshold voltage of the light emitting element LD.

[0076] Each of the light emitting elements LD may emit light with brightness corresponding to a driving current controlled by the driving circuit 144 .

[0077] although Figure 2a An embodiment in which the sub-pixel SP includes only one light emitting element LD is shown, but the present disclosure is not limited thereto. For example, the sub-pixel SP may include a plurality of light emitting elements LD coupled to each other in parallel.

[0078] In an embodiment of the present disclosure, the driving circuit 144 may include a first transistor M1 and a second transistor M2, and a storage capacitor Cst. However, the structure of the driving circuit 144 is not limited to Figure 2a The embodiment shown in .

[0079] The first transistor M1 (switching transistor) includes a first electrode coupled to the data line Dj, and a second electrode coupled to the first node N1. Here, the first electrode and the second electrode of the first transistor M1 may be different electrodes. For example, if the first electrode is a source electrode, the second electrode is a drain electrode. In addition, the first transistor M1 includes a gate electrode coupled to the scan line Si.

[0080] When a scan signal having a voltage (e.g., a low level voltage) capable of turning on the first transistor M1 is supplied from the scan line Si, the first transistor M1 is turned on to electrically couple the data line Dj with the first node N1. At this time, a data signal of a corresponding frame is supplied to the data line Dj, whereby the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 is charged to the storage capacitor Cst.

[0081] The second transistor M2 (driving transistor) may include a first electrode coupled to the first driving power source VDD, and a second electrode electrically coupled to the first electrode of each of the light emitting elements LD. The second transistor M2 includes a gate electrode coupled to the first node N1. The second transistor M2 may control the amount of driving current to be provided to the light emitting element LD in response to the voltage of the first node N1.

[0082] One electrode of the storage capacitor Cst is coupled to the first driving power source VDD, and the other electrode thereof is coupled to the first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal supplied to the first node N1 and maintain the charged voltage until a data signal of a subsequent frame is supplied.

[0083] To illustrate, Figure 2a A driving circuit 144 having a relatively simple structure is shown, which includes a first transistor M1 configured to transmit a data signal provided to the subpixel SP, a storage capacitor Cst configured to store the data signal, and a second transistor M2 configured to provide a driving current corresponding to the data signal to the light emitting element LD.

[0084] However, the present disclosure is not limited to the aforementioned structure, and the structure of the driving circuit 144 may be changed in various ways. For example, the driving circuit 144 may further include at least one transistor element (such as a transistor element configured to compensate for the threshold voltage of the second transistor M2, a transistor element configured to initialize the first node N1, and / or a transistor element configured to control the emission time of the light emitting element LD) or other circuit elements (such as a boost capacitor for boosting the voltage of the first node N1).

[0085] In addition, despite the Figure 2a , the transistors (e.g., the first transistor M1 and the second transistor M2) included in the driving circuit 144 are shown as being formed as P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor M1 and the second transistor M2 included in the driving circuit 144 may be changed to an N-type transistor.

[0086] refer to Figure 2b In the embodiment of the present disclosure, the first transistor M1 and the second transistor M2 may be implemented as N-type transistors. In addition to the change in the connection position of some components due to the change in the type of transistor, Figure 2b The configuration and operation of the drive circuit 144 shown in FIG. 1 is similar to that of FIG. Figure 2a Therefore, detailed descriptions thereof will be omitted.

[0087] Figure 3 is a plan view of a unit emission area of ​​a display device. Figure 4a and Figure 4b It is along Figure 3 A cross-sectional view taken along line AA'. Figure 5a yes Figure 4a An enlarged cross-sectional view of area Q. Figure 5b and Figure 5c Shows Figure 5a Modified examples Qa and Qb of the structure shown in FIG.

[0088] Although for convenience, Figure 3 It is shown that the plurality of light emitting elements LD are aligned in the first direction DR1, but the alignment of the light emitting elements LD is not limited thereto. For example, the light emitting elements LD may be aligned in an oblique direction between the first electrode and the second electrode. Figure 3 In the embodiment, the unit emission area may be a pixel area of ​​one of the sub-pixels included in the emission display panel.

[0089] refer to Figures 1a to 5cThe display device according to the embodiment of the present disclosure may include a substrate SUB, a barrier layer BRL, first and second partition walls PW1 and PW2, first and second reflective electrodes REL1 and REL2, first and second power lines PL1 and PL2, a plurality of light emitting elements LD, and first and second contact electrodes CNE1 and CNE2.

[0090] The substrate SUB may include an insulating material such as glass, an organic polymer, or a crystal. In addition, the substrate SUB may be made of a material having flexibility so as to be bendable or foldable, and have a single-layer or multi-layer structure.

[0091] The barrier layer BRL may be disposed on the entire surface of the substrate SUB to protect the substrate SUB, and according to an embodiment, the barrier layer BRL may not be disposed.

[0092] The first and second partition walls PW1 and PW2 may be disposed on the substrate SUB and define a unit emission area of ​​the display device.

[0093] The first partition wall PW1 and the second partition wall PW2 may be disposed on the substrate SUB at a predetermined distance from each other. For example, the first partition wall PW1 and the second partition wall PW2 may be disposed on the substrate SUB at a distance equal to or greater than the length of one light emitting element LD.

[0094] The first and second partition walls PW1 and PW2 may be formed of an insulating material including an inorganic material or an organic material, but the present disclosure is not limited thereto.

[0095] Each of the first and second partition walls PW1 and PW2 has a trapezoidal shape having a side surface inclined at a predetermined angle, but the present disclosure is not limited thereto and may have various shapes such as a semi-elliptical shape, a circular shape, and a rectangular shape.

[0096] The first reflective electrode REL1 (or first electrode) and the second reflective electrode REL2 (or second electrode) may be disposed on corresponding partition walls, respectively. For example, the first reflective electrode REL1 may be disposed on the first partition wall PW1, and the second reflective electrode REL2 may be disposed on the second partition wall PW2.

[0097] The first reflective electrode REL1 and the second reflective electrode REL2 may have shapes corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2, respectively. Therefore, the first reflective electrode REL1 may have a shape corresponding to the inclination of the first partition wall PW1, and the second reflective electrode REL2 may have a shape corresponding to the inclination of the second partition wall PW2.

[0098] The first reflective electrode REL1 and the second reflective electrode REL2 may be disposed at positions spaced apart from each other on the substrate SUB with the light emitting element LD interposed therebetween.

[0099] In an embodiment of the present disclosure, the first reflective electrode REL1 may be disposed adjacent to the respective first end EP1 of the light emitting element LD and may be electrically coupled to each of the light emitting elements LD through the first contact electrode CNE1. The second reflective electrode REL2 may be disposed adjacent to the respective second end EP2 of the light emitting element LD and may be electrically coupled to each of the light emitting elements LD through the second contact electrode CNE2.

[0100] The first reflective electrode REL1 and the second reflective electrode REL2 may be disposed on the same plane and have the same height. If the first reflective electrode REL1 and the second reflective electrode REL2 have the same height, one light emitting element LD may be more reliably coupled to the first reflective electrode REL1 and the second reflective electrode REL2.

[0101] The first reflective electrode REL1 and the second reflective electrode REL2 may be formed of a conductive material, which may include a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and alloys thereof.

[0102] In addition, each of the first reflective electrode REL1 and the second reflective electrode REL2 may be formed as a single layer, but the present disclosure is not limited thereto, and it may be formed as a multi-layer.

[0103] The materials of the first reflective electrode REL1 and the second reflective electrode REL2 are not limited to the above materials. For example, the first reflective electrode REL1 and the second reflective electrode REL2 may be made of a conductive material having a predetermined reflectivity to allow light emitted from the opposite ends EP1 and EP2 of the light emitting element LD to travel in a direction along which an image is displayed (e.g., in a forward direction).

[0104] Specifically, since the first reflective electrode REL1 and the second reflective electrode REL2 have shapes corresponding to those of the first partition wall PW1 and the second partition wall PW2, light emitted from the opposite ends EP1 and EP2 of each of the light emitting elements LD can be reflected by the first reflective electrode REL1 and the second reflective electrode REL2, whereby the light can travel in the forward direction more efficiently. Therefore, the efficiency of light emitted from the light emitting element LD can be improved.

[0105] In an embodiment of the present disclosure, the first and second partition walls PW1 and PW2 together with the first and second reflective electrodes REL1 and REL2 disposed thereon may function as a reflective member for enhancing the efficiency of light emitted from each of the light emitting elements LD.

[0106] Any one of the first reflective electrode REL1 and the second reflective electrode REL2 may be an anode electrode, and the other reflective electrode may be a cathode electrode. In an embodiment of the present disclosure, the first reflective electrode REL1 may be an anode electrode, and the second reflective electrode REL2 may be a cathode electrode.

[0107] Although the first reflective electrode REL1 and the second reflective electrode REL2 are shown as being directly disposed on the blocking layer BRL (or substrate SUB) for illustration, the present disclosure is not limited thereto. For example, a component for enabling the display device to be driven as a passive matrix or an active matrix may be further disposed between the blocking layer BRL (or substrate SUB) and the first reflective electrode REL1 and the second reflective electrode REL2.

[0108] The first reflective electrode REL1 may be coupled to the first power line PL1 through the first connection line CNL1. The second reflective electrode REL2 may be coupled to the second power line PL2 through the second connection line CNL2.

[0109] The first connection line CNL1 may be integrally provided with the first reflective electrode REL1. The second connection line CNL2 may be integrally provided with the second reflective electrode REL2.

[0110] The first power line PL1 may be disposed on the same layer as that of the first reflective electrode REL1. The second power line PL2 may be disposed on the same layer as that of the second reflective electrode REL2. However, the present disclosure is not limited thereto.

[0111] For example, each of the first and second power lines PL1 and PL2 may be disposed on a layer different from that of the corresponding reflective electrode. In this case, each of the first and second power lines PL1 and PL2 may be electrically coupled to the corresponding reflective electrode through a contact hole or the like.

[0112] In an embodiment of the present disclosure, the first and second power lines PL1 and PL2 may operate as alignment lines for providing an alignment voltage to the first and second reflective electrodes REL1 and REL2 when aligning the light emitting element LD on the substrate SUB.

[0113] A first capping layer CPL1 may be disposed on the first reflective electrode REL1. A second capping layer CPL2 may be disposed on the second reflective electrode REL2.

[0114] The first capping layer CPL1 and the second capping layer CPL2 may respectively prevent the first reflective electrode REL1 and the second reflective electrode REL2 from being damaged during a process of manufacturing the display device.

[0115] The first and second capping layers CPL1 and CPL2 may be formed of a transparent conductive material in order to reduce the loss of light emitted from the light emitting element LD and reflected in a forward direction by the first and second reflective electrodes REL1 and REL2.

[0116] The first capping layer CPL1 may be directly disposed on the first reflective electrode REL1 and electrically coupled to the first reflective electrode REL1. The second capping layer CPL2 may be directly disposed on the second reflective electrode REL2 and electrically coupled to the second reflective electrode REL2.

[0117] The first insulating layer INS1 may be disposed on the first and second capping layers CPL1 and CPL2. The first insulating layer INS1 may be disposed between the barrier layer BRL (or substrate SUB) and each of the light emitting elements LD.

[0118] In an implementation, the first insulating layer INS1 may include an organic material. The first insulating layer INS1 may be filled into a space between the barrier layer BRL (or the substrate SUB) and the one light emitting element LD, thereby stably supporting the one light emitting element LD.

[0119] In an embodiment, the first insulating layer INS1 may include an inorganic insulating layer formed of an inorganic material. Figure 4b As shown in FIG. 1 , a groove GRV may be formed between the first insulating layer INS1 and the light emitting element LD. In an embodiment, an organic layer filled in the groove GRV may be further provided, but the present disclosure is not limited thereto.

[0120] The first insulating layer INS1 may include a first contact hole CH1 through which a portion of the first capping layer CPL1 is exposed to the outside, and a second contact hole CH2 through which a portion of the second capping layer CPL2 is exposed to the outside.

[0121] In an embodiment, if the first capping layer CPL1 and the second capping layer CPL2 are omitted, the first insulating layer INS1 may be directly disposed on the first reflective electrode REL1 and the second reflective electrode REL2. In this case, the first contact hole CH1 of the first insulating layer INS1 may expose a portion of the first reflective electrode REL1 to the outside. The second contact hole CH2 of the first insulating layer INS1 may expose a portion of the second reflective electrode REL2 to the outside.

[0122] The light emitting element LD may be disposed between the first reflective electrode REL1 and the second reflective electrode REL2 over the substrate SUB. The light emitting element LD may be guided to self-align by an electric field formed between the first reflective electrode REL1 and the second reflective electrode REL2. Here, the light emitting element LD may be disposed in the form of a rod extending in the first direction DR1.

[0123] The first and second contact electrodes CNE1 and CNE2 may be disposed on the first insulating layer INS1 and the light emitting element LD.

[0124] In a plan view, the first contact electrode CNE1 (or the third electrode) may cover and overlap the first reflective electrode REL1.

[0125] In addition, the first contact electrode CNE1 may partially overlap one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. For example, the first contact electrode CNE1 may partially overlap the first end EP1 of each light emitting element LD.

[0126] The first contact electrode CNE1 may be electrically coupled to the first capping layer CPL1 through the first contact hole CH1 of the first insulating layer INS1. Since the first capping layer CPL1 is electrically coupled to the first reflective electrode REL1, the first contact electrode CNE1 may be coupled to the first reflective electrode REL1.

[0127] In an embodiment, in a case where the first capping layer CPL1 is omitted, the first contact electrode CNE1 may be directly coupled to the first reflective electrode REL1 through the first contact hole CH1 of the first insulating layer INS1.

[0128] In a plan view, the second contact electrode CNE2 (or the fourth electrode) may cover and overlap the second reflective electrode REL2.

[0129] The second contact electrode CNE2 may be electrically coupled to the second capping layer CPL2 through the second contact hole CH2 of the first insulating layer INS1. Since the second capping layer CPL2 is electrically coupled to the second reflective electrode REL2, the second contact electrode CNE2 may be coupled to the second reflective electrode REL2.

[0130] In an embodiment, in the case where the second capping layer CPL2 is omitted, the second contact electrode CNE2 may be directly coupled to the second reflective electrode REL2 through the second contact hole CH2 of the first insulating layer INS1.

[0131] Each of the first contact electrode CNE1 and the second contact electrode CNE2 may be formed of a transparent conductive material to allow light emitted from each of the light emitting elements LD to travel in a forward direction without loss. For example, the transparent conductive material may include ITO, IZO, ITZO, etc. The materials of the first contact electrode CNE1 and the second contact electrode CNE2 are not limited to the above materials.

[0132] In an embodiment of the present disclosure, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same plane.

[0133] An insulating pattern INSP may be disposed on the first contact electrode CNE1. The insulating pattern INSP may partially overlap the first contact electrode CNE1. In an embodiment, the insulating pattern INSP may include an organic insulating layer formed of an organic material, and in another embodiment, the insulating pattern INSP may include an inorganic insulating layer formed of an inorganic material. The organic material may be polyimide (PI), but the present disclosure is not limited thereto. In addition, the inorganic material may be silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiON), but the present disclosure is not limited thereto.

[0134] Although the insulation pattern INSP may be provided in a shape extending in the second direction DR2 intersecting the first direction DR1 , the present disclosure is not limited thereto.

[0135] In a plan view, the insulation pattern INSP may include a first side S1 adjacent to (eg, overlapping) the second contact electrode CNE2 , and a second side S2 opposite to the first side S1 and spaced apart from the second contact electrode CNE2 .

[0136] In a plan view, the first contact electrode CNE1 may include a third side S3 adjacent to (eg, overlapping) the second contact electrode CNE2, and a fourth side S4 opposite to the third side S3 and spaced apart from the second contact electrode CNE2.

[0137] The first side S1 of the insulation pattern INSP may be disposed at a position closer to the second contact electrode CNE2 than the third side S3 of the first contact electrode CNE1.

[0138] The third side S3 of the first contact electrode CNE1 may be provided in an under-cut shape with respect to the first side S1 of the insulation pattern INSP. Since the third side S3 of the first contact electrode CNE1 is provided in an under-cut shape, a void VO may be provided on each of the light emitting elements LD.

[0139] like Figure 5aAs shown in , the first contact electrode CNE1 may include a concave-cut shape, and the first side S1 of the insulation pattern INSP may be formed closer to the second contact electrode CNE2 than the third side S3 of the first contact electrode CNE1.

[0140] A gap VO may be provided between the first conductive semiconductor layer 11 (or the insulating film 14 ) and the insulating pattern INSP of each of the light emitting elements LD.

[0141] The void VO may be closed and defined by a portion of the first conductive semiconductor layer 11 (or a portion of the insulating film 14 ) of each of the light emitting elements LD, a portion of the first contact electrode CNE1 , a portion of the insulating pattern INSP, and a portion of the second contact electrode CNE2 .

[0142] In an embodiment, if Figure 5b As shown in , the insulating pattern INSPa may be formed to cover at least a portion of the third side S3 of the first contact electrode CNE1 and may provide a void VOa on the first conductive semiconductor layer 11 (or the insulating film 14) of each of the light emitting elements LD.

[0143] In an embodiment, if Figure 5c As shown in , the insulating pattern INSPb may be formed to cover the entire third side S3 of the first contact electrode CNE1. In this case, unlike the aforementioned embodiment, the void VO may not be provided on the first conductive semiconductor layer 11 (or the insulating film 14). In other words, the insulating pattern INSPb may be filled into the concave-cut shape portion formed in the first contact electrode CNE1. The insulating pattern INSPb may be in contact with at least a portion of the light emitting element LD.

[0144] Figure 5b and Figure 5c The insulating patterns INSPa and INSPb shown in FIG. 1 each may include an organic insulating layer formed of an organic material. A portion of the insulating patterns INSPa, INSPb including the organic insulating layer may be reflowed through a curing process to be described below and cover at least a portion of one side (e.g., the third side S3) of the first contact electrode CNE1. In other words, through the curing process, the insulating patterns INSPa, INSPb including the organic insulating layer may more effectively prevent the occurrence of a short circuit failure of the first contact electrode CNE1 and the second contact electrode CNE2.

[0145] The second contact electrode CNE2 may be electrically separated from the first contact electrode CNE1 by the gap VO.

[0146] In a range in which the second contact electrode CNE2 can be electrically separated from the first contact electrode CNE1, the second contact electrode CNE2 may be ensured to have a surface area overlapping the insulation pattern INSP at a predetermined level or more.

[0147] In an embodiment, in a plan view, the second contact electrode CNE2 may overlap the first contact electrode CNE1 by a predetermined distance and be disposed on the insulating pattern INSP. Therefore, the first contact electrode CNE1 and the second contact electrode CNE2 may be electrically separated from each other. In an embodiment, in a cross-sectional view, the second contact electrode CNE2 may be spaced apart from the first contact electrode CNE1 by a predetermined distance and be disposed on the insulating pattern INSP.

[0148] The second insulating layer INS2 may be disposed on the insulating pattern INSP and the first and second contact electrodes CNE1 and CNE2 .

[0149] The second insulating layer INS2 may prevent the first and second contact electrodes CNE1 and CNE2 from being exposed to the outside, thereby preventing the first and second contact electrodes CNE1 and CNE2 from being corroded.

[0150] In an embodiment, the second insulating layer INS2 may include an inorganic insulating layer formed of an inorganic material, and in another embodiment, the second insulating layer INS2 may include an organic insulating layer formed of an organic material. The second insulating layer INS2 may be formed as a single-layer structure as shown in the figure, but the present disclosure is not limited thereto and it may be formed as a plurality of layers.

[0151] An overcoat layer OC may be disposed on the second insulating layer INS2.

[0152] The overcoat layer OC may be a planarization layer for alleviating a step difference formed by first and second partition walls PW1 and PW2 , first and second reflective electrodes REL1 and REL2 , first and second contact electrodes CNE1 and CNE2 , and the like disposed under the overcoat layer OC.

[0153] Furthermore, the overcoat layer OC may be an encapsulation layer for preventing oxygen or water from penetrating into the light emitting element LD.

[0154] In some embodiments, the overcoat layer OC may be omitted. In the case where the overcoat layer OC is omitted, the second insulating layer INS2 may function as an encapsulation layer for preventing oxygen or water from penetrating into the light emitting element LD.

[0155] In the following, reference will be made to Figures 3 to 5a The configuration of the display device according to the embodiment of the present disclosure is described in a stacking order.

[0156] The first and second partition walls PW1 and PW2 may be disposed on the substrate SUB on which the barrier layer BRL is disposed.

[0157] The first reflective electrode REL1 may be disposed on the first partition wall PW1. The second reflective electrode REL2 may be disposed on the second partition wall PW2. The first reflective electrode REL1 and the second reflective electrode REL2 may be disposed on the same plane on the corresponding partition wall and may have a shape corresponding to that of the corresponding partition wall.

[0158] The first capping layer CPL1 may be disposed on the first reflective electrode REL1. The second capping layer CPL2 may be disposed on the second reflective electrode REL2.

[0159] The first insulating layer INS1 may be disposed on the substrate SUB on which the first and second capping layers CPL1 and CPL2 are disposed. The first insulating layer INS1 may include a first contact hole CH1 and a second contact hole CH2.

[0160] The light emitting element LD may be aligned on the first insulating layer INS1 to correspond to a space between the first reflective electrode REL1 and the second reflective electrode REL2.

[0161] After a first conductive layer (not shown) and an insulating material layer (not shown) are continuously applied to the light emitting element LD, the first contact electrode CNE1 and the insulating pattern INSP may be formed by an etching process. The third side S3 of the first contact electrode CNE1 may be spaced apart from the first side S1 of the insulating pattern INSP by a predetermined distance in a direction toward the first reflective electrode REL1 by an etching process. Therefore, the third side S3 of the first contact electrode CNE1 may have a shape that is recessed relative to the first side S1 of the insulating pattern INSP.

[0162] The second contact electrode CNE2 overlapping the second reflective electrode REL2 may be disposed on the substrate SUB having the insulating pattern INSP disposed thereon. The second contact electrode CNE2 may be disposed on the same layer as that of the first contact electrode CNE1 and have the same material as that of the first contact electrode CNE1.

[0163] The second insulating layer INS2 may be disposed on the first and second contact electrodes CNE1 and CNE2 and the insulating pattern INSP. An overcoat layer OC may be disposed on the second insulating layer INS2.

[0164] As described above, the second contact electrode CNE2 of the display device according to the embodiment of the present disclosure may be electrically separated from the first contact electrode CNE1 by the void VO and the insulating pattern INSP.

[0165] In the display device according to the embodiment, the first contact electrode CNE1 and the insulating pattern INSP may be disposed above each of the light emitting elements LD, so that an effective surface area (or effective area) of each of the first contact electrode CNE1 and the second contact electrode CNE2 may be ensured. Since the effective surface area of ​​each of the first contact electrode CNE1 and the second contact electrode CNE2 is ensured, a short-circuit failure rate of the first contact electrode CNE1 and the second contact electrode CNE2 may be reduced. Therefore, in the display device according to the embodiment of the present disclosure, the occurrence of a contact failure of the light emitting element LD due to a short-circuit failure of the first contact electrode CNE1 and the second contact electrode CNE2 may be minimized.

[0166] Figures 6a to 6f The order is shown in the manufacturing Figure 3 A schematic plan view of a display device of the method. Figures 7a to 7k The order is shown in the manufacturing Figure 4a A cross-sectional view of a method of displaying a device as shown in FIG.

[0167] refer to Figure 3 , Figure 4a , Figure 6a , Figure 7a and Figure 7b , a first partition wall PW1 and a second partition wall PW2 extending in the second direction DR2 may be formed in each unit emission region on the substrate SUB. The first partition wall PW1 and the second partition wall PW2 may be disposed at positions spaced apart from each other by a predetermined distance on the substrate SUB. In an embodiment, a barrier layer BRL may be further formed on the substrate SUB as shown in the figure.

[0168] Thereafter, first and second reflective electrodes REL1 and REL2 , first and second connection lines CNL1 and CNL2 , and first and second power lines PL1 and PL2 may be formed on the substrate SUB having the first and second partition walls PW1 and PW2 disposed thereon.

[0169] The first reflective electrode REL1 may branch in the second direction DR2 from the first connection line CNL1 extending in the first direction DR1 crossing the second direction DR2. The first reflective electrode REL1 may overlap the first partition wall PW1.

[0170] The first connection line CNL1 may be coupled to the first power line PL1 extending in the second direction DR2 .

[0171] The first connection line CNL1 may transmit an alignment voltage applied to the first power line PL1 to the first reflective electrode REL1 when aligning the light emitting element LD, or may transmit a driving voltage applied to the first power line PL1 to the first reflective electrode REL1 when the light emitting element LD is driven.

[0172] The second reflective electrode REL2 may branch from the second connection line CNL2 extending in the first direction DR1 in the second direction DR2. The second reflective electrode REL2 may overlap the second partition wall PW2.

[0173] The second connection line CNL2 may be coupled to the second power line PL2 extending in the second direction DR2.

[0174] The second connection line CNL2 may transmit an alignment voltage applied to the second power line PL2 to the second reflective electrode REL2 when aligning the light emitting element LD or a driving voltage applied to the second power line PL2 to the second reflective electrode REL2 when the light emitting element LD is driven.

[0175] In an embodiment of the present disclosure, the first and second reflective electrodes REL1 and REL2 , the first and second connection lines CNL1 and CNL2 , and the first and second power lines PL1 and PL2 may be disposed on the same plane.

[0176] In addition, the first reflective electrode REL1 and the second reflective electrode REL2, the first connection line CNL1 and the second connection line CNL2, and the first power line PL1 and the second power line PL2 may have the same material. For example, the first reflective electrode REL1 and the second reflective electrode REL2, the first connection line CNL1 and the second connection line CNL2, and the first power line PL1 and the second power line PL2 may include a conductive material having a predetermined reflectivity.

[0177] refer to Figure 3 , Figure 4a , Figure 6b and Figures 7a to 7c , the first and second capping layers CPL1 and CPL2 may be formed on the substrate SUB on which the first and second reflective electrodes REL1 and REL2 are disposed, and the like.

[0178] The first capping layer CPL1 and the second capping layer CPL2 may include the same material. For example, the first capping layer CPL1 and the second capping layer CPL2 may include a transparent conductive material.

[0179] In a plan view, the first capping layer CPL1 may overlap the first reflective electrode REL1 and the first connection line CNL1, and the second capping layer CPL2 may overlap the second reflective electrode REL2 and the second connection line CNL2.

[0180] refer to Figure 3 , Figure 4a , Figure 6c and Figures 7a to 7e A first insulating material layer INS1' may be formed on the substrate SUB on which the first and second capping layers CPL1 and CPL2 are disposed, and thereafter, a first insulating layer INS1 including first and second contact holes CH1 and CH2 exposing corresponding portions of the first and second capping layers CPL1 and CPL2 may be formed by patterning the first insulating material layer INS1' through a mask process.

[0181] refer to Figure 3 , Figure 4a , Figure 6d and Figures 7a to 7f , an electric field may be formed between the first reflective electrode REL1 and the second reflective electrode REL2 by applying an alignment voltage to the first reflective electrode REL1 and the second reflective electrode REL2 through the first power line PL1 and the second power line PL2 , respectively.

[0182] When an electric field is formed between the first reflective electrode REL1 and the second reflective electrode REL2 , the light emitting element LD may be input onto the substrate SUB through an inkjet printing scheme or the like.

[0183] If the light emitting element LD is input on the substrate SUB, the self-alignment of the light emitting element LD may be guided by the electric field formed between the first reflective electrode REL1 and the second reflective electrode REL2. Therefore, the light emitting element LD may be aligned between the first reflective electrode REL1 and the second reflective electrode REL2.

[0184] refer to Figure 3 , Figure 4a and Figure 7a to Figure 7g , a conductive material layer CNE1 ′ and a second insulating material layer INSP′ may be sequentially formed on the substrate SUB on which the light emitting element LD is aligned.

[0185] The conductive material layer CNE1 ′ may be formed of a transparent conductive material in order to minimize the loss of light emitted from each of the light emitting elements LD.

[0186] The second insulating material layer INSP' may be disposed on the conductive material layer CNE1' and include an inorganic insulating layer formed of an inorganic material. Here, the present disclosure is not limited thereto. In an embodiment, the second insulating material layer INSP' may include an organic insulating layer formed of an organic material.

[0187] refer to Figure 3 , Figure 4a , Figure 5a to Figure 5b , Figure 6e and Figure 7a to Figure 7h , the first contact electrode CNE1 and the insulating pattern INSP may be formed by simultaneously patterning the conductive material layer CNE1 ′ and the second insulating material layer INSP′ by sequentially performing the first etching process and the second etching process.

[0188] In an embodiment of the present disclosure, the first etching process may include a dry etching process, and the second etching process may include a wet etching process.

[0189] First, a first etching process is performed so that an insulating pattern INSP and a conductive pattern (not shown) may be formed by patterning the second insulating material layer INSP′ and the conductive material layer CNE1′ so that a portion of the first insulating layer INS1 and a portion of each light emitting element LD are exposed to the outside.

[0190] Although not directly shown in the drawings, one side of the insulating pattern INSP and one side of the conductive pattern may correspond to each other through patterning by the first etching process.

[0191] Thereafter, a second etching process may be performed using the insulating pattern INSP as an etching mask. A solvent capable of etching the conductive pattern disposed under the insulating pattern INSP may be used as an etchant used during the second etching process.

[0192] Through the second etching process, the conductive pattern may be formed into a concave shape under the first side S1 of the insulation pattern INSP and become the first contact electrode CNE1 having a third side S3 spaced inwardly from the first side S1 of the insulation pattern INSP.

[0193] In a plan view, the third side S3 of the first contact electrode CNE1 may be spaced apart from the second reflective electrode REL2 by a predetermined distance.

[0194] In addition, the first contact electrode CNE1 may overlap the remaining portion of each light emitting element LD except for the exposed portion thereof. Here, the first contact electrode CNE1 may be electrically coupled to one end of each of the light emitting elements LD.

[0195] refer to Figure 3 , Figure 4a , Figure 6f and Figures 7a to 7i The second contact electrode CNE2 may be formed by performing a mask process after forming a second conductive layer (not shown) on the substrate SUB having the insulating pattern INSP disposed thereon.

[0196] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same plane and spaced apart from each other by a predetermined distance in a cross-sectional view so as to be electrically separated from each other.

[0197] The first contact electrode CNE1 may be disposed on a portion of the first insulating layer INS1 including the first contact hole CH1 .

[0198] The first contact electrode CNE1 may be electrically coupled to the first capping layer CPL1 through the first contact hole CH1. In addition, the first contact electrode CNE1 may be electrically coupled to one end of each light emitting element LD.

[0199] The second contact electrode CNE2 may be disposed on a portion of the insulation pattern INSP and a portion of the first insulation layer INS1 including the second contact hole CH2 .

[0200] The second contact electrode CNE2 may be electrically coupled to the second capping layer CPL2 through the second contact hole CH2. In addition, the second contact electrode CNE2 may be electrically coupled to the other end of each light emitting element LD.

[0201] refer to Figure 3 , Figure 4a and Figure 7j , a second insulating layer INS2 may be formed on the first contact electrode CNE1 and the second contact electrode CNE2. Subsequently, an overcoat layer OC may be formed on the second insulating layer INS2.

[0202] Further references Figure 7k In the case where the insulating pattern INSP includes an organic insulating layer formed of an organic material, a curing process may be further performed after forming the first contact electrode CNE1 and the insulating pattern INSP by performing the first and second etching processes and before forming the second contact electrode CNE2.

[0203] The curing process may be a process of hardening and stabilizing the insulation pattern INSP. For example, the curing process may be a process of applying heat of a predetermined temperature or higher to the insulation pattern INSP for a predetermined time or longer.

[0204] In an embodiment, the shape of the insulation pattern INSP may be changed by the curing process. In detail, the insulation pattern INSP may reflow due to the curing process. When the insulation pattern INSP reflows, the shape of at least a portion of the insulation pattern INSP may be changed.

[0205] As mentioned above Figure 5b and Figure 5cAs described above, the insulating patterns INSPa, INSPb may be formed to cover a portion or all of one side of the first contact electrode CNE1, and may provide a gap VOa on the light emitting element LD or may not provide a gap on the light emitting element LD. In other words, the insulating patterns INSPa, INSPb may be reflowed to cover the concave-shaped portion formed in the first contact electrode CNE1.

[0206] In other words, through the curing process, the insulating patterns INSPa, INSPb including the organic insulating layer may more effectively prevent the occurrence of the short circuit failure of the first contact electrode CNE1 and the second contact electrode CNE2.

[0207] Figure 8 is a plan view schematically showing a display device according to an embodiment of the present disclosure.

[0208] refer to Figure 1a and Figure 8 , a display device according to an embodiment of the present disclosure includes a substrate SUB, a pixel PXL disposed on the substrate SUB, a driver disposed on the substrate SUB and configured to drive the pixel PXL, and a line component (not shown) disposed to connect the pixel PXL to the driver.

[0209] The substrate SUB may include a display area DA and a non-display area NDA.

[0210] The display area DA may be a region in which pixels PXL for displaying an image are disposed. The non-display area NDA may be a region in which a driver for driving the pixels PXL and a portion of a line member for coupling the pixels PXL to the driver are disposed.

[0211] The display area DA may have various shapes. For example, the display area DA may be provided in various forms, such as a closed polygon including sides formed by linear lines, a circle, an ellipse, etc. including sides formed by curved lines, and a semicircle, a semiellipse, etc. including sides formed by linear lines and curved lines.

[0212] In the case where the display area DA includes a plurality of areas, each area may also be provided in various forms such as a closed polygon including linear sides, and a semicircle, a semiellipse including sides formed by curved lines, etc. The surface areas of the plurality of areas may be the same or different from each other.

[0213] In an embodiment of the present disclosure, an example in which the display area DA is provided with a single area having a rectangular shape including linear sides will be described.

[0214] The non-display area NDA may be disposed on at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround the periphery of the display area DA.

[0215] The pixels PXL may be disposed in the display area DA on the substrate SUB. Each of the pixels PXL represents a minimum unit for displaying an image, and a plurality of pixels PXL may be provided.

[0216] Each of the pixels PXL may include at least one light emitting element LD that emits white light and / or colored light. Each pixel PXL may emit light having any one of red, green, and blue colors, and is not limited thereto. For example, each of the pixels PXL may emit light having any one of cyan, magenta, yellow, and white colors.

[0217] The pixels PXL may be arranged in a matrix along rows extending in a first direction DR1 and columns extending in a second direction DR2 intersecting the first direction DR1. However, the arrangement of the pixels PXL is not limited to a specific arrangement. In other words, the pixels PXL may be arranged in various forms.

[0218] The driver may provide a signal to each pixel PXL through the line component and thus control the operation of the pixel PXL. Figure 8 In the figure, line components are omitted for illustration.

[0219] The driver may include: a scan driver SDV configured to provide a scan signal to the pixel PXL through a scan line; an emission driver EDV configured to provide an emission control signal to the pixel PXL through an emission control line; a data driver DDV configured to provide a data signal to the pixel PXL through a data line; and a timing controller (not shown). The timing controller may control the scan driver SDV, the emission driver EDV, and the data driver DDV.

[0220] Fig. 9 It is schematically shown that the Figure 8 1 is a plan view of first to third sub-pixels in one of the pixels shown in . Fig.10 It is along Fig. 9 A cross-sectional view taken along line BB' of the embodiment of the present disclosure will be described below with emphasis on the differences from the previous embodiment to avoid repeated description. Components not described separately in the following description of the present embodiment are consistent with the components of the previous embodiment. The same reference numerals will be used to represent the same components, and similar reference numerals will be used to represent similar components.

[0221] To illustrate, in Fig. 9 The transistor connected to the light emitting element and the signal line connected to the transistor are omitted in the figure. Fig. 9 In the embodiment, the unit emission area may be a pixel area of ​​a sub-pixel.

[0222] refer to Figures 8 to 10 , a display device according to an embodiment of the present disclosure may include a substrate SUB on which a plurality of pixels PXL are disposed.

[0223] Each of the pixels PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 disposed on a substrate SUB.

[0224] Each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 may include a substrate SUB, a pixel circuit layer PCL disposed on the substrate SUB, and a display element layer DPL disposed on the pixel circuit layer PCL.

[0225] The pixel circuit layer PCL may include a buffer layer BFL disposed on a substrate SUB, first and second transistors T1 and T2 disposed on the buffer layer BFL, and a driving voltage line DVL. In addition, the pixel circuit layer PCL may further include a passivation layer PSV disposed on the first and second transistors T1 and T2 and the driving voltage line DVL.

[0226] The display element layer DPL may include first and second partition walls PW1 and PW2 , first and second reflective electrodes REL1 and REL2 , first and second connection lines CNL1 and CNL2 , a light emitting element LD, and first and second contact electrodes CNE1 and CNE2 disposed on the passivation layer PSV.

[0227] For convenience, the display element layer DPL will be described after describing the pixel circuit layer PCL.

[0228] The buffer layer BFL may be disposed on the substrate SUB and prevent impurities from diffusing into the first transistor T1 and the second transistor T2. The buffer layer BFL may be provided in a single-layer structure or a multi-layer structure having at least two layers.

[0229] In the case where the buffer layer BFL has a multi-layer structure, the layers may be formed of the same material or different materials. Depending on the material or processing conditions of the substrate SUB, the buffer layer BFL may be omitted.

[0230] The first transistor T1 may be a driving transistor electrically coupled to some of the light emitting elements LD provided in the display element layer DPL to drive the corresponding light emitting elements LD. The second transistor T2 may be a switching transistor configured to switch the first transistor T1.

[0231] Each of the first and second transistors T1 and T2 may include a semiconductor layer SCL, a gate electrode GE, and first and second transistor electrodes EL1 and EL2.

[0232] The semiconductor layer SCL may be disposed on the buffer layer BFL. The semiconductor layer SCL may include a first region in contact with the first transistor electrode EL1 and a second region in contact with the second transistor electrode EL2. The region between the first region and the second region may be a channel region. In an embodiment of the present disclosure, the first region may be any one of the source region and the drain region, and the second region may be the other region of the source region and the drain region.

[0233] The semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the first region and the second region may be a semiconductor pattern doped with impurities.

[0234] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. An interlayer insulating layer ILD may be disposed on the gate insulating layer GI.

[0235] The first and second transistor electrodes EL1 and EL2 may respectively contact the first and second regions of the semiconductor layer SCL through contact holes passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0236] The driving voltage line DVL may be disposed on the interlayer insulating layer ILD, but is not limited thereto. In some embodiments, the driving voltage line DVL may be disposed on any one of the insulating layers included in the pixel circuit layer PCL. The second driving power source VSS may be applied to the driving voltage line DVL.

[0237] The passivation layer PSV may include a through hole TH through which the first transistor electrode EL1 of the first transistor T1 is exposed, and a through hole VH through which the driving voltage line DVL is exposed.

[0238] The first and second partition walls PW1 and PW2 may be disposed on the passivation layer PSV at positions spaced apart from each other by a predetermined distance. Each of the first and second partition walls PW1 and PW2 may be disposed in a trapezoidal shape having sides inclined at a predetermined angle, but is not limited thereto.

[0239] The first reflective electrode REL1 may be disposed on the first partition wall PW1. The second reflective electrode REL2 may be disposed on the second partition wall PW2. Therefore, the first reflective electrode REL1 may have a shape corresponding to that of the first partition wall PW1, and the second reflective electrode REL2 may have a shape corresponding to that of the second partition wall PW2.

[0240] The first reflective electrode REL1 may branch from the first connection line CNL1 extending in the first direction DR1 in the second direction DR2 intersecting the first direction DR1. The second reflective electrode REL2 may branch from the second connection line CNL2 extending in the first direction DR1 in the second direction DR2.

[0241] The first connection line CNL1 disposed in the first subpixel SP1 may be electrically separated from the first connection line CNL1 disposed in the second subpixel SP2 disposed adjacent to the first subpixel SP1. In addition, the first connection line CNL1 disposed in the second subpixel SP2 may be electrically separated from the first connection line CNL1 disposed in the third subpixel SP3 disposed adjacent to the second subpixel SP2.

[0242] Therefore, the first connection line CNL1 disposed in one sub-pixel may be electrically separated from the first connection line CNL1 disposed in a sub-pixel disposed adjacent to the one sub-pixel. Therefore, each of the first to third sub-pixels SP1 to SP3 may be individually driven.

[0243] The second connection line CNL2 disposed in the first sub-pixel SP1 may be commonly disposed in the second sub-pixel SP2 and the third sub-pixel SP3 disposed adjacent to the first sub-pixel SP1 .

[0244] In a plan view, the first reflective electrode REL1 and the second reflective electrode REL2 may be spaced apart from each other by a predetermined distance, and the light emitting element LD is disposed between the first reflective electrode REL1 and the second reflective electrode REL2. The first reflective electrode REL1 may be disposed adjacent to any one of the opposite ends EP1 and EP2 of each light emitting element LD. The second reflective electrode REL2 may be disposed adjacent to the other of the opposite ends EP1 and EP2 of the light emitting element LD.

[0245] The first reflective electrode REL1 and the second reflective electrode REL2 may be disposed on the same plane.

[0246] The first reflective electrode REL1 may be electrically coupled to the first transistor electrode EL1 of the first transistor T1 through the through hole TH of the passivation layer PSV. Therefore, a voltage applied to the first transistor T1 may be transmitted to the first reflective electrode REL1.

[0247] The second reflective electrode REL2 may be electrically coupled to the driving voltage line DVL through the through hole VH of the passivation layer PSV.

[0248] The first capping layer CPL1 may be disposed on the first reflective electrode REL1. The second capping layer CPL2 may be disposed on the second reflective electrode REL2.

[0249] The first insulating layer INS1 may be disposed on the first and second capping layers CPL1 and CPL2. The first insulating layer INS1 may include an inorganic insulating layer or an organic insulating layer.

[0250] The first insulating layer INS1 may include a first contact hole CH1 through which a portion of the first capping layer CPL1 is exposed, and a second contact hole CH2 through which a portion of the second capping layer CPL2 is exposed.

[0251] Each of the light emitting elements LD may be disposed on the first insulating layer INS1 and aligned between the first reflective electrode REL1 and the second reflective electrode REL2 .

[0252] Each of the light emitting elements LD may include a first end EP1 and a second end EP2 in a longitudinal direction.

[0253] The first contact electrode CNE1 may be disposed on the first reflective electrode REL1 to reliably couple the first reflective electrode REL1 with the first end EP1 of each light emitting element LD electrically and / or physically.

[0254] The insulating pattern INSP may be disposed on the first contact electrode CNE1. The insulating pattern INSP may cover the first contact electrode CNE1 to prevent the first contact electrode CNE1 from being exposed to the outside and electrically separate the first contact electrode CNE1 from the second contact electrode CNE2.

[0255] The second contact electrode CNE2 may be disposed on the second reflective electrode REL2 to electrically couple the second reflective electrode REL2 with the second end EP2 of each light emitting element LD.

[0256] A gap VO may be formed between the light emitting device LD and the insulating pattern INSP.

[0257] The void VO may be closed and defined by a portion of each of the light emitting elements LD, a portion of the first contact electrode CNE1, a portion of the insulating pattern INSP, and a portion of the second contact electrode CNE2.

[0258] In each of the first to third sub-pixels SP1 to SP3 , the first contact electrode CNE1 may be spaced apart from the second reflective electrode REL2 and partially overlap the first reflective electrode REL1 in a plan view.

[0259] The first contact electrode CNE1 may be electrically coupled to the first end EP1 of each light emitting element LD.

[0260] When an electric field having a predetermined voltage or more is applied to each light emitting element LD, each light emitting element LD may emit light.

[0261] The second insulating layer INS2 may be disposed on the first and second contact electrodes CNE1 and CNE2. The second insulating layer INS2 may cover the first and second contact electrodes CNE1 and CNE2 disposed thereunder, thereby preventing the first and second contact electrodes CNE1 and CNE2 from being exposed to the outside.

[0262] An overcoat layer OC may be disposed on the second insulating layer INS2.

[0263] As described above, the second contact electrode CNE2 of the display device according to the embodiment of the present disclosure may be electrically separated from the first contact electrode CNE1 by the void VO and the insulating pattern INSP.

[0264] In other words, in the display device according to the embodiment of the present disclosure, a sufficient amount of effective surface area of ​​the first contact electrode CNE1 connected to the first end EP1 of each light emitting element LD and a sufficient amount of effective area of ​​the second contact electrode CNE2 connected to the second end EP2 of each light emitting element LD can be ensured.

[0265] Since the effective area of ​​each of the first contact electrode CNE1 and the second contact electrode CNE2 is ensured, the occurrence of a short-circuit failure of the first contact electrode CNE1 and the second contact electrode CNE2 can be reduced. Therefore, in the display device according to the embodiment of the present disclosure, the occurrence of a contact failure of the light emitting element LD due to the short-circuit failure of the first contact electrode CNE1 and the second contact electrode CNE2 can be minimized.

[0266] The display device according to the embodiment of the present disclosure can be used in various electronic devices. For example, the display device can be applied to televisions, notebook computers, cellular phones, smart phones, smart tablets, portable multimedia players (PMPs), personal digital assistants (PDAs), navigation devices, various types of wearable devices (such as smart watches), etc.

[0267] Although various embodiments have been described above, it will be understood by those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification are only for illustrative purposes, rather than limiting the technical spirit of the present disclosure. The scope of the present disclosure must be limited by the attached claims.

Claims

1. Display device, include: substrate; a first electrode and a second electrode on the substrate and spaced apart from each other; a light emitting element, on the substrate, and having a first end and a second end; a third electrode, disposed on the light emitting element and electrically connecting the first electrode to the first end of the light emitting element; an insulating pattern, on the third electrode and exposing the second end of the light emitting element; as well as a fourth electrode on the light emitting element and electrically connecting the second electrode to the second end of the light emitting element, A gap is formed between the light emitting element and the insulating pattern.

2. The display device according to claim 1, in, The insulating pattern includes a first side overlapping the light emitting element and disposed adjacent to the second electrode, wherein the third electrode includes a second side overlapping the light emitting element and disposed adjacent to the second electrode, and In a plan view, the second side is closer to the first electrode than the first side.

3. The display device according to claim 2, in, The gap is closed and formed by a portion of the light emitting element, a portion of the third electrode, a portion of the insulating pattern, and a portion of the fourth electrode.

4. The display device according to claim 3, in, The insulating pattern includes an organic insulating layer including an organic material, and the insulating pattern covers at least a portion of the second side of the third electrode.

5. The display device according to claim 3, in, The insulating pattern includes an inorganic insulating layer formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the insulating pattern does not cover the second side of the third electrode.

6. The display device according to claim 1, further comprising an insulating layer disposed on the first electrode and the second electrode, in, The insulating layer includes a first contact hole through which a portion of the first electrode is exposed, and a second contact hole through which a portion of the second electrode is exposed.

7. The display device according to claim 6, in, The third electrode is electrically coupled to the first electrode through the first contact hole, the fourth electrode is electrically coupled to the second electrode through the second contact hole, and the third electrode and the fourth electrode are electrically separated from each other.

8. The display device according to claim 6, in, The insulating layer includes an inorganic insulating layer formed of an inorganic material, and a groove is formed between the insulating layer and the light emitting element.

9. Display device, include: substrate; a first electrode and a second electrode, on the substrate and spaced apart from each other; a light emitting element, on the substrate, and having a first end and a second end; a third electrode, on the light emitting element, and electrically connecting the first electrode to the first end of the light emitting element; an insulating pattern, on the third electrode and exposing the second end of the light emitting element; as well as a fourth electrode on the light emitting element and electrically connecting the second electrode to the second end of the light emitting element, Wherein, at least a portion of the insulating pattern is in contact with the light emitting element.

10. The display device according to claim 9, in, The insulating pattern includes a first side overlapping the light emitting element and disposed adjacent to the second electrode, wherein the third electrode includes a second side overlapping the light emitting element and disposed adjacent to the second electrode, and In a plan view, the second side is closer to the first electrode than the first side.

11. The display device according to claim 10, in, The insulating pattern includes an organic insulating layer including an organic material, and the insulating pattern covers at least a portion of the second side of the third electrode.

12. The display device according to claim 9, further comprising an insulating layer disposed on the first electrode and the second electrode, in, The insulating layer includes a first contact hole through which a portion of the first electrode is exposed, and a second contact hole through which a portion of the second electrode is exposed.

13. The display device according to claim 12, in, The third electrode is electrically coupled to the first electrode through the first contact hole, the fourth electrode is electrically coupled to the second electrode through the second contact hole, and the third electrode and the fourth electrode are electrically separated from each other.

14. A method for manufacturing a display device, include: forming a first electrode and a second electrode on a substrate; forming a first insulating material layer on the first electrode, the second electrode and the substrate; Forming a first insulating layer exposing a portion of the first electrode and a portion of the second electrode by patterning the first insulating material layer; providing a light emitting element onto the first insulating layer and allowing the light emitting element to be self-aligned; sequentially forming a conductive material layer and a second insulating material layer on the light emitting element and the first insulating layer; Forming an insulating pattern exposing a first end of the light emitting element by patterning the conductive material layer and the second insulating material layer through a first etching process; forming a third electrode having one end overlapping with the light emitting element and having a concave-cut shape by etching the patterned conductive material layer through a second etching process using the insulating pattern as a mask, the third electrode being electrically coupled to a second end of the light emitting element; as well as A fourth electrode electrically coupled to the second electrode and the first end of the light emitting element is formed on the first insulating layer.

15. The method according to claim 14, in, The first etching process includes a dry etching process, and the second etching process includes a wet etching process.

16. The method according to claim 15, in, The insulating pattern includes an organic insulating layer, and the organic insulating layer includes an organic material, The method further includes curing the insulating pattern after forming the third electrode and before forming the fourth electrode, The insulating pattern is filled into at least a portion of the concave shape of the third electrode.

17. The method according to claim 16, in, At least a portion of the insulating pattern is in contact with the light emitting element.

18. The method according to claim 15, in, The insulating pattern includes an inorganic insulating layer formed of an inorganic material, and The forming of the fourth electrode includes forming a gap surrounded by a portion of the light emitting element, a portion of the third electrode, a portion of the insulating pattern, and a portion of the fourth electrode.

19. The method according to claim 14, in, The third electrode is electrically separated from the fourth electrode. 20 . The method according to claim 14 , further comprising forming a second insulating layer covering the third electrode and the fourth electrode on the third electrode and the fourth electrode.

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