Back contact heterojunction solar cell with improved insulation isolation effect and manufacturing method thereof

Abstract

The application relates to a manufacturing method of a back contact heterojunction solar cell with improved insulation isolation effect, which comprises the following steps: dividing a first main surface of a semiconductor substrate into a first conductive area of a first conductive type and a second conductive area of a second conductive type; etching an inner area of the first conductive area of the first main surface of the semiconductor substrate to form a first conductive area groove; and etching the second conductive area of the first main surface of the semiconductor substrate to form a second conductive area groove. The application aims to provide a back contact heterojunction solar cell with improved insulation isolation effect and a manufacturing method thereof, which improves the stability of a process, avoids the complexity of a process caused by multiple mask operations, and is suitable for large-scale process production.

Description

Technical Field

[0001] This invention relates to a back-contact heterojunction solar cell with improved insulation performance and a method for manufacturing the same. Background Technology

[0002] Improving the conversion efficiency of industrially produced solar cells is a key research topic for the development of the solar energy industry and its gradual replacement of traditional energy sources. The main methods for improving solar cell conversion efficiency are to enhance electrical parameters such as open-circuit voltage, fill factor, and short-circuit current density. Heterojunction solar cells, by inserting an intrinsic amorphous silicon layer between an amorphous silicon layer and a monocrystalline silicon substrate, significantly improve the surface passivation effect of the substrate silicon, achieving higher minority carrier lifetime and open-circuit voltage, thereby increasing conversion efficiency. Back-contact solar cells, on the other hand, have all electrodes distributed on the back side, with P- and N-electrodes arranged alternately on the back of the cell, collecting photogenerated carriers generated by the photovoltaic effect of crystalline silicon. There are no electrodes on the front side, thus eliminating optical losses caused by metal electrode grid lines, effectively increasing the short-circuit current and greatly improving conversion efficiency. Back-contact heterojunction monocrystalline silicon solar cells combine the advantages of the above two solar energy technologies, achieving extremely high photoelectric conversion efficiency. It has been reported that the highest laboratory efficiency of this type of solar cell can reach 26.63%.

[0003] However, manufacturing back-contact heterojunction solar cells presents numerous challenges. One key challenge is the formation of cross-arranged N-type and P-type regions on the back side, which must be completely isolated from each other to prevent short circuits that could severely impact cell performance. Therefore, two methods are employed: either using a mask during the coating process to prevent the two polarities from overlapping and causing carrier recombination; or removing the other polarity layer after coating through localized etching. Both of these methods require multiple masking operations and stringent alignment requirements, making it difficult to guarantee process stability and unsuitable for large-scale mass production. Summary of the Invention

[0004] The purpose of this invention is to provide a back-contact heterojunction solar cell with improved insulation performance and its fabrication method. This method improves process stability, avoids the complexity of the process caused by multiple masking operations, and is suitable for large-scale production.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A back-contact heterojunction solar cell with improved insulation performance includes a semiconductor substrate whose first main surface is divided into a first conductive region of a first conductivity type and a second conductive region of a second conductivity type; a first conductive region groove formed by etching the internal region of the semiconductor substrate of the first conductive region; and a second conductive region groove formed by etching the semiconductor substrate of the second conductive region; wherein the boundary region between the first conductive region and the second conductive region is not etched to form a protrusion.

[0007] A method for fabricating a back-contact heterojunction solar cell with improved insulation performance involves dividing a first main surface of a semiconductor substrate into a first conductive region of a first conductivity type and a second conductive region of a second conductivity type; etching the internal region of the first conductive region of the first main surface of the semiconductor substrate to form a first conductive region groove; and etching the second conductive region of the first main surface of the semiconductor substrate to form a second conductive region groove.

[0008] Compared with the prior art, the advantages of the present invention are as follows:

[0009] (1) By setting the first conductive region groove and the second conductive region groove, the semiconductor film layers of the first conductive region and the second conductive region are formed in the corresponding grooves, which effectively avoids leakage between the first conductive region and the second conductive region film layers and is conducive to improving the fill factor.

[0010] (2) In the manufacturing process, the use of laser etching technology reduces the performance damage and alignment complexity caused by multiple coating and mask etching processes, which is suitable for future large-scale mass production needs and greatly shortens the manufacturing process. Attached Figure Description

[0011] Figure 1 This is a simplified structural diagram of one embodiment of the solar cell of the present invention.

[0012] Figure 2 This is a flowchart of one embodiment of the solar cell manufacturing method of the present invention.

[0013] Figure 3 This is a cross-sectional schematic diagram of a manufacturing process of the solar cell unit of the present invention.

[0014] Figure 4 This is a cross-sectional schematic diagram of a manufacturing process of the solar cell unit of the present invention.

[0015] Figure 5 This is a cross-sectional schematic diagram of a manufacturing process of the solar cell unit of the present invention.

[0016] Figure 6 This is a cross-sectional schematic diagram of a manufacturing process of the solar cell unit of the present invention.

[0017] Figure 7This is a cross-sectional schematic diagram of a manufacturing process of the solar cell unit of the present invention.

[0018] Figure 8 This is a cross-sectional schematic diagram of a manufacturing process of the solar cell unit of the present invention.

[0019] Figure 9 This is a cross-sectional schematic diagram of a manufacturing process of the solar cell unit of the present invention.

[0020] Figure 10 This is a partial schematic diagram of a manufacturing process of the solar cell unit of the present invention.

[0021] Figure 11 This is a partial schematic diagram of a manufacturing process of the solar cell unit of the present invention.

[0022] Figure 12 This is a partial schematic diagram of a manufacturing process of the solar cell unit of the present invention.

[0023] Figure 13 This is a partial schematic diagram of a manufacturing process of the solar cell unit of the present invention. Detailed Implementation

[0024] A back-contact heterojunction solar cell with improved insulation performance includes a semiconductor substrate whose first main surface is divided into a first conductive region of a first conductivity type and a second conductive region of a second conductivity type; a first conductive region groove formed by etching the internal region of the semiconductor substrate of the first conductive region; and a second conductive region groove formed by etching the semiconductor substrate of the second conductive region; wherein the boundary region between the first conductive region and the second conductive region is not etched to form a protrusion.

[0025] The semiconductor substrate is a monocrystalline silicon wafer, a cast monocrystalline silicon wafer, or a polycrystalline silicon wafer.

[0026] The second main surface of the semiconductor substrate is provided with a third conductive film layer and an anti-reflection film layer from bottom to top.

[0027] The depth of the first conductive region groove is 10-50 μm; the depth of the second conductive region groove is 10-50 μm.

[0028] The first conductive region is covered with a first conductive film layer, and the surface of the first conductive film layer on the protruding edge of the first conductive region is covered with a first insulating film layer; the second conductive region and the first insulating film layer are covered with a second conductive film layer.

[0029] The first conductive film layer includes a first semiconductor passivation layer and a first semiconductor layer; the second conductive film layer includes a second semiconductor passivation layer and a second semiconductor layer.

[0030] The first semiconductor passivation layer and the second semiconductor passivation layer are composite films formed by combining silicon dioxide, an amorphous silicon intrinsic layer, or a combination of silicon dioxide and an amorphous silicon intrinsic layer, with a thickness controlled between 1 and 10 nm.

[0031] The first semiconductor layer and the second semiconductor layer are respectively N-type conductive semiconductor layers or P-type conductive semiconductor layers; the first semiconductor layer and the second semiconductor layer have different conductivity types.

[0032] The first semiconductor layer is an N-type amorphous silicon doped layer or a P-type amorphous silicon doped layer; when the semiconductor substrate is an N-type single crystal silicon substrate, the first semiconductor layer is an N-type amorphous silicon doped layer and the second semiconductor layer is a P-type amorphous silicon doped layer.

[0033] The first insulating film layer can be a single insulating film layer or a combination of an insulating film and a mask layer. To facilitate subsequent etching processes and protect the functional film, the first insulating film layer preferably includes a first insulating layer and a first mask layer sequentially disposed from bottom to top on a first conductive film layer as a substrate. The first mask layer can be a thin film such as amorphous silicon, and its solution resistance polarity should be opposite to that of the first insulating layer.

[0034] The back-contact heterojunction solar cell further includes a first conductive layer disposed on a first conductive region and electrically connected to a first conductive film layer, a first electrode disposed on the first conductive layer, a second conductive layer disposed on a second conductive region and electrically connected to a second conductive film layer, and a second electrode disposed on the second conductive layer; an insulating separation groove is provided between the first conductive layer and the second conductive layer.

[0035] In one embodiment, a back-contact heterojunction solar cell includes a silicon substrate. A first semiconductor passivation layer, a first semiconductor layer, and an anti-reflection layer are sequentially disposed on the front side of the silicon substrate. A first semiconductor passivation layer is disposed on the back side of the silicon substrate. A first semiconductor layer and a second semiconductor passivation layer are stacked on the first semiconductor passivation layer. A second semiconductor layer is stacked on the second semiconductor passivation layer. The stacks formed by the first semiconductor passivation layer and the first semiconductor layer (first semiconductor stack) and the stacks formed by the second semiconductor passivation layer and the second semiconductor layer (second semiconductor stack) are arranged alternately. An insulating isolation layer and an insulating opening are disposed between the first semiconductor stack and the second semiconductor stack. Both the first semiconductor stack and the second semiconductor stack are formed in grooves in the silicon substrate. A transparent conductive layer is disposed on each of the two semiconductor stacks, and an electrode is disposed on the transparent conductive layer.

[0036] The antireflective layer is a silicon oxide layer, a silicon nitride layer, or an aluminum oxide layer, with a thickness controlled between 50 and 150 nm.

[0037] A method for fabricating a back-contact heterojunction solar cell with improved insulation performance involves dividing a first main surface of a semiconductor substrate into a first conductive region of a first conductivity type and a second conductive region of a second conductivity type; etching the internal region of the first conductive region of the first main surface of the semiconductor substrate to form a first conductive region groove; and etching the second conductive region of the first main surface of the semiconductor substrate to form a second conductive region groove.

[0038] The steps of the fabrication method of the back contact heterojunction solar cell are as follows:

[0039] Step A: Etching is performed on a portion of the first conductive region on the first main surface of the semiconductor substrate, excluding the region bordering the second conductive region, to form a groove for the first conductive region;

[0040] Step B: A first conductive film layer and a first insulating film layer are sequentially formed on the first main surface of the semiconductor substrate;

[0041] Step C: Etch the first insulating film layer and the first conductive film layer in areas other than the first conductive region, and etch the exposed first main surface of the semiconductor substrate to form a first conductive region with the first insulating film layer attached to the surface and an exposed second conductive region groove.

[0042] Step D: A second conductive film layer is formed on the first main surface of the semiconductor substrate processed in step C;

[0043] Step E: Etch away the second conductive film layer and the first insulating film layer covering the groove region of the first conductive area;

[0044] Step F: Forming a conductive film layer on the first main surface of the semiconductor substrate;

[0045] Step G involves creating a groove in the first conductive region region where the first conductive region groove has not been etched to form an insulating separation between the first conductive region and the second conductive region, and forming electrodes for the first conductive region and the second conductive region.

[0046] The specific method of step A is as follows: Laser etching is performed on the first conductive region area where the first conductive region groove needs to be formed, followed by chemical etching to form the first conductive region groove in the first conductive region area excluding the area bordering the second conductive region; the depth of the first conductive region groove is 10-50 μm. In one embodiment, the first conductive region groove is formed by laser etching on one side of the semiconductor substrate and then etched with a solution. The depth of the first conductive region groove is 10-50 μm, and the solution is an alkaline solution, preferably potassium hydroxide and / or sodium hydroxide, etc., with a total mass percentage of 3%-10%.

[0047] The specific method of step C is as follows: the first insulating film layer covering the second conductive region is laser etched, and then chemical etching is performed to remove the film layer covering the second conductive region and to etch the semiconductor substrate to form a second conductive region groove on the first main surface of the semiconductor substrate; the depth of the second conductive region groove is 10-50um.

[0048] The first insulating film layer is composed of a first insulating layer and a first mask layer formed sequentially from bottom to top on a first conductive film layer as a substrate. The specific method of step C is as follows: the first mask layer covering the second conductive region is laser-etched, followed by chemical etching to remove the first insulating layer and the first conductive film layer covering the second conductive region, and then etching the semiconductor substrate to form a second conductive region groove on the first main surface of the semiconductor substrate. In one embodiment, a pulsed laser is used to remove the first mask layer, with a pulse width less than 20 nanoseconds, preferably less than 100 picoseconds, using low-energy-density green light at approximately 560 nm, followed by removal of the first insulating layer using an acidic solution.

[0049] In step E, a laser is used to remove the second conductive film layer in the groove region of the first conductive area, and then chemical etching is used to remove the exposed first insulating film layer. To prevent laser damage to the functional film layer in the first conductive area, preferably, a pulsed laser with a pulse width of less than 20 nanoseconds, low energy density, and a wavelength of about 560nm (green light) is used. Furthermore, the laser only etches and removes the second conductive film layer, and the exposed first insulating film layer is removed using an acidic solution.

[0050] In step G, the first conductive region electrode and the second conductive region electrode are formed by screen printing or electroplating.

[0051] The present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0052] like Figures 1 to 13 The diagram shown is an embodiment of a back-contact heterojunction solar cell with improved insulation performance and its fabrication method provided by the present invention.

[0053] The novel back-contact heterojunction solar cell designed in this invention, taking an N-type monocrystalline silicon substrate as an example, has the following structure: Figure 1The structure includes: an N-type single-crystal silicon substrate 1, front and back first semiconductor passivation layers 2a, front and back first semiconductor layers 2b, back second semiconductor passivation layer 3a, back second semiconductor layer 3b, front and back anti-reflection layers 4, back transparent conductive layer 5, back electrode 6, and the stack formed by the back first semiconductor layer 2b and the back transparent conductive layer 5 (first semiconductor stack) and the stack formed by the back second semiconductor layer 3b and the back transparent conductive layer 5 (second semiconductor stack) are both located in corresponding grooves of the silicon substrate 1 (i.e., the first semiconductor stack is located in the first conductive region groove 1b, and the second semiconductor stack is located in the second conductive region groove 1c), with an opening formed between the first semiconductor stack and the second semiconductor stack.

[0054] In the solar cell structure of this embodiment, the first semiconductor passivation layer 2a on both the front and back sides is an intrinsic amorphous silicon layer i containing H. The first semiconductor passivation layer 2a on the back side only needs to achieve the passivation effect; there is no specific requirement for its thickness, and its thickness can be as follows: Between; the first semiconductor passivation layer 2a on the front side requires passivation effect while also avoiding blocking incident light, and its thickness is preferably controlled within between;

[0055] The second semiconductor passivation layer 3a on the backlight surface is an intrinsic amorphous silicon layer i containing hydrogen. The second semiconductor passivation layer i on the backlight surface only needs to achieve the passivation effect; its thickness is not specifically required and can be within acceptable limits. between;

[0056] The first semiconductor layer 2b on both the front and back sides is an amorphous silicon semiconductor layer with added n-type dopant; the second semiconductor layer 3b on the back side is an amorphous silicon semiconductor layer with added p-type dopant. The thicknesses of the n-type and p-type semiconductor layers are not particularly limited; preferably, the thickness of the n-type semiconductor layer can be [missing information]. The thickness of the P-type amorphous semiconductor layer can be... The doping concentration of the P-type and N-type semiconductor layers is 10. 19 -10 20 cm -3 Its film layer has the characteristics of high concentration doping and high conductivity.

[0057] The N-type semiconductor region on the back side, composed of the first semiconductor passivation layer 2a and the first semiconductor layer 2b, and the P-type semiconductor region on the back side, composed of the second semiconductor passivation layer 3a and the second semiconductor layer 3b, are both distributed in the groove region of the silicon substrate. This can effectively avoid short circuits between the two regions and improve the fill factor.

[0058] The N-type semiconductor region and the P-type semiconductor region on the back are arranged in an alternating pattern, forming a finger-like cross-distribution pattern on the back.

[0059] An antireflection layer 4, which functions as both an antireflection film and a protective film, is provided on the front-side N-type semiconductor amorphous silicon layer. This antireflection layer can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., but is preferably a silicon nitride film. The thickness of the antireflection layer can be approximately 70 nm to 1.5 μm.

[0060] The insulating layer on the back N-type semiconductor amorphous silicon layer is a combination of an antireflective layer and a mask layer. The polarity of the solution resisted by the mask layer should be opposite to that of the insulating film. For example, the mask layer is a thin film such as amorphous silicon or polycrystalline silicon, which can resist acid corrosion, while the insulating film is a film such as silicon nitride, which can resist alkali corrosion.

[0061] An opening is formed between the stack of the N-type semiconductor polycrystalline layer and the transparent conductive layer on the back side and the stack of the P-type semiconductor amorphous layer and the transparent conductive layer. The purpose of this opening is to prevent short circuits between the two doped layers, which would reduce electrical performance.

[0062] Next, mainly refer to Figures 2-13 The manufacturing method of the back-contact heterojunction solar cell of this embodiment will be described below:

[0063] First, prepare an N-type single-crystal silicon substrate 1. Next, in step S1, clean the front and back sides of the silicon substrate. Polish both sides of the silicon substrate to remove the mechanically damaged layer, and then perform surface cleaning to reduce solution residue and surface recombination, such as... Figure 3 As shown. In this invention, the surface of the single-crystal silicon substrate can be a polished surface or a textured surface; preferably, the substrate surface is formed with a pyramidal textured surface to reduce reflectivity.

[0064] In step S2, a patterned area of ​​the first conductive region is etched on one side of the silicon substrate using a laser, while the area bordering the second conductive region is not etched. Figure 4 As shown; after laser scribing, the silicon substrate becomes loosely structured in certain areas, making it easier to etch compared to unscribing areas. Next, an alkaline solution is used to etch the first conductive region groove 1b, as shown. Figure 5 As shown, the groove depth is controlled at around 10-50 μm; the alkaline solution is preferably a potassium hydroxide or sodium hydroxide solution with a total mass percentage of 3%-10%.

[0065] In step S3, a first semiconductor passivation layer, namely a hydrogenated amorphous silicon intrinsic passivation layer 2a, an N-type amorphous silicon doped layer 2b, and an antireflection layer 4 are deposited on the front and back sides of the silicon substrate. The antireflection layer 4 can be formed from a single material such as silicon oxide, silicon nitride, or silicon oxynitride, or from a multilayer composite material. Preferably, in this embodiment, silicon nitride is used as the antireflection layer. Figure 5 The above three types of films can be formed using thin film formation methods such as sputtering or CVD. Preferably, they are formed by deposition using the PECVD method.

[0066] To avoid damage from subsequent laser scribing, a first mask layer is placed after the antireflection layer 4, which is located on the back side and forms the first insulating layer. Figure 5 (The first mask layer in the following diagrams is not shown separately, such as an amorphous silicon film layer, serves as a corrosion mask layer for the sacrificial film layer and subsequent insulating layer.) The solution resistance polarity of this first mask layer should be opposite to that of the antireflection layer 4. In this embodiment, the first mask layer, such as an amorphous silicon or polycrystalline silicon film, can resist acid corrosion, while the antireflection layer 4, such as a silicon nitride film layer, can resist alkaline corrosion.

[0067] In step S4, the first mask layer on the antireflection layer is removed from the back side using a laser, and then the antireflection layer is removed using a solution etching method to form a layer as shown in the figure. Figure 7 The structure is shown; subsequently, solution etching is used to remove the amorphous silicon layer and part of the bulk silicon beneath the antireflection layer, thereby forming the second conductive region groove 1c. The laser preferentially uses low-energy-density picosecond green light with a wavelength of approximately 560 nm to etch the antireflection layer, reducing damage to the first semiconductor layer in other non-laser areas. Then, solution etching is used to remove the amorphous silicon film layer and part of the silicon substrate, thereby forming the second conductive region groove 1c. Figure 8 As shown;

[0068] In step S5, as Figure 9 As shown, a second semiconductor passivation layer, namely an amorphous silicon intrinsic layer 3a and a P-type amorphous silicon layer 3b, is deposited on the back side of the silicon substrate. The amorphous silicon layer can be formed by thin film formation methods such as sputtering or CVD. Preferably, in this embodiment, the PECVD method is used for deposition.

[0069] In step S6, the second semiconductor passivation layer, the second semiconductor layer, and the antireflection layer on the first conductive region are removed, so that they are interleaved to form a first semiconductor stacked region and a second semiconductor stacked region, which facilitates subsequent contact with the transparent conductive layer. The film layer removal method can be carried out by screen printing etching ink, or by wet etching under the protection of protective ink, or by direct laser etching. Preferably, in this embodiment, laser etching is used to remove the second semiconductor layer, the second semiconductor passivation layer, and the first mask layer on the first conductive region, and then the antireflection layer is removed by etching solution, forming a layer as shown in the figure. Figure 10 As shown; the laser is pulsed, with a pulse width of less than 20 nanoseconds, preferably less than 100 picoseconds;

[0070] In step S7, a transparent conductive layer is deposited on the back side of the silicon substrate to form a layer as shown in the figure. Figure 11 As shown, the transparent conductive layer can be formed by transparent conductive oxides such as ITO and AZO. The transparent conductive layer can be formed by evaporation, sputtering, etc. Preferably, in this embodiment, it is formed by PVD sputtering.

[0071] In step S8, the stack formed by the N-type polycrystalline silicon and the transparent conductive layer on the back side of the silicon substrate is insulated and separated from the stack formed by the P-type amorphous silicon layer and the transparent conductive layer, such as... Figure 12 As shown; specifically, insulation between the two areas can be achieved by laser engraving or screen printing using etching ink to etch grooves. Preferably, in this embodiment, laser engraving is used.

[0072] In step S9, electrodes are formed on the first and second conductive regions on the back side of the silicon substrate, respectively. These electrodes can be formed by screen printing followed by low-temperature sintering (<250°C) to form silver gate electrodes, or by electroplating. Figure 13 As shown. Preferably, in this embodiment, the gate electrode is formed by electroplating.

[0073] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention.

[0074] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. If these modifications and variations of the invention fall within the scope of the claims of the invention and their equivalents, then the invention is also intended to include these modifications and variations.

Claims

1. A back-contact heterojunction solar cell with improved insulation performance, characterized in that: It includes a semiconductor substrate whose first main surface is divided into a first conductive region of a first conductivity type and a second conductive region of a second conductivity type; a first conductive region groove formed by etching the internal region of the semiconductor substrate of the first conductive region; and a second conductive region groove formed by etching the semiconductor substrate of the second conductive region. The boundary region between the first conductive region and the second conductive region is not etched to form a raised edge. The first conductive region is covered with a first conductivity type film layer, and the surface of the first conductivity type film layer at the raised edge of the first conductive region away from the semiconductor substrate is covered with a first insulating film layer. The second conductive region and the first insulating film layer are covered with a second conductive film layer. It also includes a first conductive layer disposed on the first conductive region and electrically connected to the first conductive film layer, a first electrode disposed on the first conductive layer, a second conductive layer disposed on the second conductive region and electrically connected to the second conductive film layer, and a second electrode disposed on the second conductive layer. An insulating separation groove is provided between the first conductive layer and the second conductive layer. The depth of the first conductive region groove is 10-50 μm; the depth of the second conductive region groove is 10-50 μm. The method for fabricating the back-contact heterojunction solar cell with improved insulation performance is as follows: The first main surface of the semiconductor substrate is divided into a first conductive region of a first conductivity type and a second conductive region of a second conductivity type; the internal region of the first conductive region of the first main surface of the semiconductor substrate is etched to form a first conductive region groove, and the second conductive region of the first main surface of the semiconductor substrate is etched to form a second conductive region groove. The steps are as follows: Step A: Etching is performed on a portion of the first conductive region on the first main surface of the semiconductor substrate, excluding the region bordering the second conductive region, to form a groove for the first conductive region; Step B: A first conductive film layer and a first insulating film layer are sequentially formed on the first main surface of the semiconductor substrate; Step C: Etch the first insulating film layer and the first conductive film layer in areas other than the first conductive region, and etch the exposed first main surface of the semiconductor substrate to form a first conductive region with the first insulating film layer attached to the surface and an exposed second conductive region groove. Step D: A second conductive film layer is formed on the first main surface of the semiconductor substrate processed in step C; Step E: Etch away the second conductive film layer and the first insulating film layer covering the groove region of the first conductive area; Step F: Forming a conductive film layer on the first main surface of the semiconductor substrate; Step G involves creating a groove in the first conductive region region where the first conductive region groove has not been etched to form an insulating separation between the first conductive region and the second conductive region, and forming a first electrode for the first conductive region and a second electrode for the second conductive region.

2. The back-contact heterojunction solar cell with improved insulation performance according to claim 1, characterized in that: The first insulating film layer includes a first insulating layer and a first mask layer disposed sequentially from bottom to surface, with the first conductive film layer as the base.

3. The back-contact heterojunction solar cell with improved insulation performance according to claim 1, characterized in that: The specific method of step A is as follows: laser etching is performed on the first conductive area where the first conductive area groove needs to be formed, and then chemical etching is performed to form the first conductive area groove in the first conductive area except for the area at the boundary with the second conductive area; the depth of the first conductive area groove is 10-50um.

4. The back-contact heterojunction solar cell with improved insulation performance according to claim 1 or 3, characterized in that: The specific method of step C is as follows: laser etching is performed on the first insulating film layer covering the second conductive region, and then chemical etching is performed to remove the film layer covering the second conductive region and to etch the semiconductor substrate to form a second conductive region groove on the first main surface of the semiconductor substrate; the depth of the second conductive region groove is 10-50um.

5. The back-contact heterojunction solar cell with improved insulation performance according to claim 4, characterized in that: The first insulating film layer is composed of a first insulating layer and a first mask layer formed sequentially from bottom to top on a first conductive film layer as a base. The specific method of step C is as follows: the first mask layer covered by the second conductive region is laser etched, and then chemical etching is performed to remove the first insulating layer and the first conductive film layer covering the second conductive region and to etch the semiconductor substrate to form a second conductive region groove on the first main surface of the semiconductor substrate.

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