A phase change memory system and access method thereof

Abstract

An embodiment of the present invention provides a phase change memory system, characterized in that it includes: a storage module, including multiple storage chips connected to host signals, each storage chip includes multiple storage banks arranged in parallel and all connected to the same data transmission channel by signal, and the multiple storage banks are configured to have different address attributes; each storage bank includes multiple storage blocks connected to the same data transmission channel by signal and at least two buffers arranged corresponding to each storage block; the buffer is connected to the corresponding storage block signal to receive and cache data according to instructions and / or output the cached data to the corresponding storage block; and a memory controller, the memory controller is coupled to the storage module.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a phase change memory system and an access method thereof. Background Art

[0002] Phase Change Memory (PCM) is a storage technology that uses chalcogenides as storage media and uses the resistance difference of materials in different states to save data. Phase change memory has the advantages of bit addressing, no data loss after power failure, high storage density, and fast read and write speed. It is considered to be the most promising next-generation memory. As information technology continues to increase the computing speed requirements, how to improve the access speed and access efficiency of memory has gradually become an important research direction in this field. Summary of the invention

[0003] To solve the related technical problems, an embodiment of the present invention provides a phase change memory and an access method thereof.

[0004] An embodiment of the present invention provides a phase change memory system, characterized by comprising:

[0005] A storage module, comprising a plurality of storage chips connected to a host signal, each of the storage chips comprising a plurality of storage banks arranged in parallel and all connected to the same data transmission channel by signal, the plurality of storage banks being configured to have different address attributes; each of the storage banks comprising a plurality of storage blocks connected to the same data transmission channel by signal and at least two buffers corresponding to each of the storage blocks; the buffers being connected to the corresponding storage blocks by signal, for receiving and caching data according to instructions and / or outputting the cached data to the corresponding storage blocks;

[0006] a memory controller coupled to the memory module and configured to:

[0007] In an access operation, according to a received address attribute signal, determining an accessed storage repository corresponding to the address attribute signal;

[0008] Inside the accessed storage library, all data are cached by the cache and output to the corresponding storage block, or data stored in the corresponding storage block are cached by the cache and output.

[0009] In the above scheme, it is characterized in that the size of the data volume Q of one access operation is determined by the following formula:

[0010]

[0011] Among them, K is the number of storage chips, L is the number of storage banks in each of the storage chips, M is the number of storage blocks accessed in each of the storage banks, N is the number of buffers connected to each of the storage block signals, and K, L, M and N are positive integers.

[0012] In the above scheme, it is characterized in that

[0013] The number L of the memory banks in each of the memory chips is a positive integer greater than or equal to 32.

[0014] In the above solution, it is characterized in that the memory controller further comprises:

[0015] A task allocation module is configured to select a buffer for executing and storing the data based on a task execution state and / or a remaining space amount of the buffer.

[0016] In the above scheme, it is characterized in that the step of selecting a buffer for storing the data based on the task execution status and / or the remaining space of the buffer comprises:

[0017] Select a buffer whose current working state is idle;

[0018] sorting the selected buffers according to the amount of remaining space;

[0019] Data is allocated one by one in the order of the remaining space from largest to smallest.

[0020] An embodiment of the present invention further provides a method for accessing a phase change memory, which is characterized by comprising:

[0021] In an access operation, a memory controller receives an address attribute signal and determines a storage bank corresponding to the address attribute signal in a storage module, wherein the memory controller is coupled to the storage module, the storage module includes a plurality of storage chips connected to a host signal, each of the storage chips includes a plurality of storage banks arranged in parallel and all connected to the same data transmission channel by signal, the plurality of storage banks are configured to have different address attributes; each of the storage banks includes a plurality of storage blocks connected to the same data transmission channel by signal and at least two buffers corresponding to each of the storage blocks; the buffer is connected to the storage block signal corresponding to it, so as to receive and cache data according to an instruction and / or output the cached data to the storage block corresponding to it;

[0022] In the accessed database, all data are stored in the buffer according to the instruction, and all data stored in the buffer are written into the corresponding storage block; or,

[0023] Inside the accessed database, data in the storage block is read according to the instruction, all the data is written into the corresponding buffer, and the read data is output to the host.

[0024] In the above scheme, it is characterized in that the size of the data volume Q of one access operation is determined by the following formula:

[0025]

[0026] Among them, K is the number of storage chips, L is the number of storage banks in each of the storage chips, M is the number of storage blocks accessed in each of the storage banks, N is the number of buffers connected to each of the storage block signals, and K, L, M and N are positive integers.

[0027] In the above scheme, it is characterized in that

[0028] The number L of the memory banks in each of the memory chips is a positive integer greater than or equal to 32.

[0029] In the above scheme, it is characterized in that the memory controller also includes a task allocation module, and the task allocation module is configured to select a cache for executing and storing the data based on the task execution status and / or the remaining space amount of the cache.

[0030] In the above scheme, it is characterized in that the step of selecting a buffer for storing the data based on the task execution status and / or the remaining space of the buffer comprises:

[0031] Select a buffer whose current working state is idle;

[0032] sorting the selected buffers according to the amount of remaining space;

[0033] Data is allocated one by one in the order of the remaining space from largest to smallest.

[0034] An embodiment of the present invention provides a phase change memory system, characterized by comprising:

[0035] A storage module comprises a plurality of storage chips connected to host signals, each of the storage chips comprises a plurality of storage banks arranged in parallel and all connected to the same data transmission channel by signals, and the plurality of storage banks are configured to have different address attributes; each of the storage banks comprises a plurality of storage blocks connected to the same data transmission channel by signals and at least two buffers arranged corresponding to each of the storage blocks; the buffers are connected to the corresponding storage block signals to receive and cache data according to instructions and / or output the cached data to the corresponding storage block; a memory controller is coupled to the storage module and is configured to: in the accessed storage bank, cache all data via the buffer and output them to the corresponding storage block or cache the data stored in the corresponding storage block via the buffer and output them.

[0036] In this way, by matching and scheduling the cache and the storage module through the memory controller, a larger amount of data can be accessed in one access operation, thereby greatly improving the access efficiency of the input / output operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the structure of a three-dimensional phase change memory in the related art;

[0038] Figure 2 The transmission electron microscope (TEM) image of the three-dimensional phase change memory in the related art;

[0039] Figure 3A A schematic diagram of a module of a phase change memory system provided by an embodiment of the present invention;

[0040] Figure 3B A schematic diagram of a magnified structure of a storage module in a phase change memory system provided by an embodiment of the present invention;

[0041] Figure 3C A schematic diagram of a magnified structure of a storage module in a phase change memory system provided by an embodiment of the present invention;

[0042] Figure 4A It is a schematic diagram of the internal modules of the memory chip;

[0043] Figure 4B A schematic diagram of a structure of an implementation method in which the storage library is a whole;

[0044] Figure 5 A schematic diagram of a module of a phase change memory system in which two buffers are configured for each storage block provided by an embodiment of the present invention;

[0045] Figure 6 A schematic diagram of a module of a phase change memory system in which each chip is configured with 32 memory banks provided by an embodiment of the present invention;

[0046] Figure 7 A schematic flow chart of a method for accessing a phase change memory system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The exemplary embodiments disclosed in the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0048] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0049] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0050] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present invention necessarily has the first element, component, region, layer or part.

[0051] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0052] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0053] As used in the description below, the term "three-dimensional memory" refers to a semiconductor device having memory cells arranged vertically on a laterally oriented substrate so that the number of memory cells increases in the vertical direction relative to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0054] Figure 1 is a schematic diagram of the structure of a three-dimensional phase change memory in the related art, Figure 2 3D phase change memory in the related art is a transmission electron microscope (TEM) image. Figure 1-2As shown, the three-dimensional phase change memory is usually a three-dimensional cross-point architecture, under which the phase change memory cell 110 is arranged at the intersection of the vertically crossed word line 112 and the bit line 111. Usually, the word line 112 and the bit line 111 can be formed by 20nm / 20nm equal width (line / space, L / S) conductive lines formed after the patterning process, and the adjacent memory cells 110 are close to each other. In the related art, each memory is usually composed of 8 chips, and each chip is composed of 16 memory banks. Usually, in each memory bank, 128 bits of data can be accessed during one input / output interaction. Then, in one input / output interaction process, the entire memory composed of 8 chips including 16 memory banks can have an access volume of 8×16×128 bits, that is, 2KB of data can be accessed. However, in a computing system, it is usually necessary to access 4KB or more of data at a time. In order to access 4KB or more of data, in related technologies, 2 or more accesses are required, which will inevitably reduce the access rate.

[0055] To this end, an embodiment of the present invention provides a phase change memory system. Figure 3A A schematic diagram of the enlarged structure of a phase change memory system provided in an embodiment of the present invention; in an embodiment of the present invention, a "system" may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device. Figure 3A It can be seen that the phase change memory system 300 provided in the embodiment of the present invention may include a host 330, one or more storage modules 310, and a memory controller 320. The host 330 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. In some embodiments, the host 330 may be configured to send data to the storage module 310 or receive data from the storage module 310. In some embodiments, the host may be a user logic unit or a user interface, so that a user may issue instructions to the host and transmit instructions to a storage device or a storage array.

[0056] The storage module 310 may be any storage device disclosed in the present disclosure. As disclosed in detail below, according to some embodiments, a storage module such as a PCRAM, DRAM, or NAND flash memory device may include a clock input, a command bus, an address bus, a data input, multiple storage bodies, multiple interface modules, etc.

[0057] According to some embodiments, the memory controller 320 is coupled to the storage module 310 and the host 330, and is configured to control the storage module 310. The memory controller 320 can manage the data stored in the storage module 310 and communicate with the host 330. In some embodiments, the memory controller 320 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices (such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 320 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC) used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., and an enterprise storage array. The memory controller 320 can be configured to control the operation of the storage module 310, such as read, erase, and program operations. The memory controller 320 may also be configured to manage various functions related to data stored or to be stored in the storage module 310, including but not limited to bad block management, garbage collection, logical to physical address conversion, and wear leveling; in some embodiments, the memory controller 320 is also configured to process error correction code (ECC) on data read from or written to the storage module 310. The memory controller 320 may also perform any other suitable functions, such as formatting the storage module 310. The memory controller 320 may communicate with an external device (e.g., the host 330) according to a specific communication protocol. For example, the memory controller 320 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, and the like.

[0058] Figure 3B and Figure 3C The schematic diagram of the enlarged structure of the storage module 310 in the phase change memory system provided by the embodiment of the present invention is as follows: Figure 3B-3CIt can be seen that the storage module 310 includes: a plurality of storage chips 301 (die) connected to the host 330 by signal (the connection line is not shown in the figure), each of the storage chips 301 includes a plurality of storage banks 302 (bank) arranged in parallel and all connected to the same data transmission channel by signal, and the plurality of storage banks 302 are configured to have different address attributes; each of the storage banks 302 includes a plurality of storage blocks 303 (block) connected to the same data transmission channel by signal, each of the storage banks 302 can be divided into different storage bands (tiles) 305, each storage band 305 includes a small number of storage blocks 303, and each of the storage blocks 303 is correspondingly provided with at least two buffers 304 (see Figure 3C ); the buffer 304 is connected to its corresponding storage block 303 signal, so as to receive and cache data according to the instruction and / or output the cached data to its corresponding storage block;

[0059] The phase change memory system provided by the embodiment of the present invention further includes a memory controller 320, and the memory controller is configured as follows:

[0060] In an access operation, according to the received address attribute signal, the accessed storage bank 302 corresponding to the address attribute signal is determined;

[0061] Inside the accessed storage library 302 , all data are cached by the cache 304 and output to its corresponding storage block 303 , or data stored in its corresponding storage block 303 are cached by the cache 304 and output.

[0062] In actual operation, a storage module may include, for example, eight storage chips 301, such as Die0...Die7. Figure 4A As shown, each of the memory chips 301 may include 16 memory banks 302. Figure 3B As shown, the storage bank 302 can also be divided into two sub-storage banks (Half Bank), and the two sub-storage banks are respectively connected to the logic main line (logic). Figure 4B As shown, the storage library 302 may also be composed of a complete storage library, which is directly connected to the data path, that is, the aforementioned logic path. Here, the storage library 302 may include multiple storage bands 305 (Tiles), for example, 128 storage bands 305 (Tiles). For an embodiment in which the storage library 302 includes two sub-storage banks (Half Bank), for example Figure 3BAs shown, each of the sub-memory banks may include 64 storage bands 305 (Tiles), Tile0, Tile1, ... Tile63. In some embodiments, one storage band 305 (Tile) may include 4 storage blocks, each of which includes a word line, a bit line, and a storage cell formed at the intersection of the word line and the bit line. In order to operate the storage cell, a word line voltage may be applied to each word line, and a bit line voltage may be applied to each bit line.

[0063] In actual operation, Figure 3C As shown, each storage block 303 is correspondingly provided with at least two buffers 304, for example Figure 3C Cache 1 . . . Cache N. Cache 304 may be coupled to memory controller 320 , and is configured to cache write data received from host 330 and forward and write the data to storage block 303 , read and cache read data from storage block 303 and forward the read data to host 330 .

[0064] In some specific embodiments, the buffer may be a first-in-first-out buffer (FIFO Data Cache).

[0065] Specifically, during an access operation, the memory controller 320 receives an address attribute signal from the host 330, and determines the accessed storage bank 302 corresponding to the address attribute signal. In addition, the memory controller 320 may also receive a clock signal via a clock bus, a command signal via a command bus, and a data signal via a data bus; specifically, the memory controller 320 may receive an address attribute signal from the host 330 via an address bus, and determine the accessed storage bank 302 according to the address attribute signal. After determining the accessed storage bank 302, all data in the accessed storage bank 302 are cached by the cache 304 and output and written to the corresponding storage block 303, or the data stored in the corresponding storage block 303 are read and cached by the cache 304 and output to the host.

[0066] In actual operation, the memory controller 320 further includes a task allocation module 321 , which is configured to divide the data sent by the host into multiple parts and allocate the data of the multiple parts to the multiple buffers 304 respectively.

[0067] For details, see Figure 5For the write process, the memory controller 320 receives data from the host 330, and the task allocation module 321 divides the data received from the host 330 into N data according to the number N of buffers 304 corresponding to each storage block. For example, for the scheme of setting two buffers 304 corresponding to each storage block, the task allocation module 321 will divide the data into two data 1 and data 2. Then, data 1 and data 2 are respectively stored in Cache1 and Cache2 corresponding to the storage block, and data 1 and data 2 in Cache1 and Cache2 are respectively stored in the storage block 303.

[0068] In one access, each buffer can cache 1 bit of data. Therefore, for the embodiments of the present invention, 2 bits of data can be accessed under the triggering of one access command. In the related art, since no buffer is set, each storage block can only access 1 bit of data under the triggering of one clock signal. In the related art, if you want to access 2 bits of data in each storage block at one time, the host needs to send two access signals. The present invention allows 1 block to be accessed by 2 bits of data in one access operation through the matching scheduling of the buffer and the storage module by the memory controller. Although the step of writing data from the buffer to the storage block is added, the time required to write data from the buffer to the storage block is much shorter than the time required for the host to send two access commands. Therefore, the memory system provided by the present invention can access a larger amount of data in one access operation, greatly improving the access efficiency of input / output operations.

[0069] In some embodiments of the present invention, each storage band 305 is provided with 4 storage blocks, wherein each storage block is provided with 2 buffers correspondingly. Since only 1 storage block in a storage band 302 can be accessed in one access operation, each storage band 302 can access 2 bits of data. Since 128 storage bands 302 are provided in each storage bank, the amount of data accessible to each storage bank 302 is 2*128bits=32bytes; the number of storage banks L in each of the storage chips can be 16, therefore, the amount of data accessible to each storage chip is 16*32bytes=512bytes; in the storage system provided by the embodiment of the present invention, the number of storage chips K is 8, therefore, the amount of data accessible to the storage system provided by the embodiment of the present invention is 512bytes*8=4K at one time; this is doubled compared to the access amount of 2KB in the related art. In the related computing system, it is usually necessary to be able to access 4KB of data at one time, and the phase change memory provided by the embodiment of the present invention for accessing 4KB of data at one time is of great significance.

[0070] It should be understood that the above is an example of an implementation method in which two caches are configured for each storage block 303. Those skilled in the art should understand that when each storage block 303 is configured with more than two caches, the phase change memory provided in the embodiment of the present invention can achieve an access volume greater than 4KB in a single input / output process.

[0071] The amount of data accessed by the phase change memory system is related to multiple parameters. The amount of data Q accessed by the phase change memory system provided by the embodiment of the present invention is determined by the following formula:

[0072]

[0073] Among them, K is the number of storage chips, L is the number of storage banks in each of the storage chips, M is the number of storage blocks accessed in each of the storage banks, N is the number of buffers connected to each of the storage block signals, and K, L, M and N are positive integers.

[0074] In some embodiments, each buffer 304 is not limited to corresponding to only one storage block 303, and each buffer 304 can also correspond to multiple storage blocks 303, that is, multiple storage blocks 303 can share the buffer 304, and use the task allocation module to coordinate the entire system as a whole.

[0075] In some embodiments, Figure 3C As shown, the memory controller 320 also includes:

[0076] The task allocation module 321 is configured to select a buffer 304 for executing and storing the data based on a task execution state and / or a remaining space of the buffer 304 .

[0077] In some specific embodiments, selecting the buffer 304 for storing the data based on the task execution state and / or the remaining space of the buffer 304 includes:

[0078] Select the buffer 304 whose current working state is idle;

[0079] Sort the selected caches 304 according to the amount of remaining space;

[0080] Data is allocated one by one in the order of the remaining space from largest to smallest.

[0081] By setting up a task allocation module, the allocation of tasks can be efficiently scheduled and arranged, and the number of required buffers can be reduced, thereby simplifying the device structure and reducing costs.

[0082] In another embodiment, the number L of the memory banks 302 in each memory chip 301 is a positive integer greater than or equal to 32. In a specific embodiment, the number L of the memory banks 302 in each memory chip 301 is equal to 32. Figure 6 As shown, a memory chip 301 includes 32 memory banks 302 (Bank) including Bank0...BankN...Bank31. As can be seen from the above content, each memory bank 302 can only achieve 128×1 bits, that is, 16B of access in one access operation, and when a memory chip 301 includes 32 memory banks 302, finally, one memory chip 301 can also achieve 512B of data access in one input / output operation. Compared with the related technology of setting 16 memory banks, the amount of data that can be accessed in one access operation is greatly increased.

[0083] It should be understood that the above is an example of an implementation in which the number L of storage libraries 302 in each of the storage chips 301 is equal to 32. Those skilled in the art should understand that when the number L of storage libraries 302 in each of the storage chips 301 is greater than 32, the phase change memory system provided in the embodiment of the present invention can achieve an access volume greater than 4KB in a single access process.

[0084] like Figure 7 As shown, an embodiment of the present invention further provides a method for accessing a phase change memory system, comprising:

[0085] S701. In an access operation, a memory controller receives an address attribute signal and determines a storage memory bank corresponding to the address attribute signal in a storage module, wherein the memory controller is coupled to the storage module, the storage module includes a plurality of storage chips connected to a host signal, each of the storage chips includes a plurality of storage memory banks arranged in parallel and all connected to the same data transmission channel by signal, the plurality of storage memory banks are configured to have different address attributes; each of the storage memory banks includes a plurality of storage blocks connected to the same data transmission channel by signal and at least two buffers corresponding to each of the storage blocks; the buffer is connected to the storage block signal corresponding to the buffer, so as to receive and cache data according to an instruction and / or output the cached data to the storage block corresponding to the buffer;

[0086] S702. Within the accessed storage repository, all data are stored in the cache according to the instruction, and all data stored in the cache are written into the corresponding storage block; or, within the accessed storage repository, data in the storage block are read according to the instruction, all data are written into the corresponding cache, and the read data is output to the host.

[0087] Specifically, when performing a write operation, S701 is executed first, and the memory controller 320 receives a control signal from the host 330 via the bus. The control signal includes an access instruction, address attribute information and data. The memory controller 320 determines the storage library 302 corresponding to the address attribute signal in the storage module 300 according to the address attribute information.

[0088] In actual operation, the memory controller 320 further includes a task allocation module 321 , which is configured to divide the storage data into multiple parts and allocate the storage data of the multiple parts to the multiple buffers 304 respectively according to the design rules.

[0089] Specifically, the memory controller 320 receives data from the host 330, and the task allocation module 321 divides the data received from the host 330 into N data according to the number N of buffers 304 corresponding to each storage block. For example, for a solution in which two buffers 304 are set corresponding to each storage block, the task allocation module 321 will divide the data into data 1 and data 2.

[0090] Then, step S702 is executed to store all data in the buffer 304 according to the instruction inside the accessed storage bank, and write all data stored in the buffer 304 into the corresponding storage block.

[0091] Specifically, for example, data 1 and data 2 are respectively stored in Cache 1 and Cache 2 corresponding to the storage block, and data 1 and data 2 in Cache 1 and Cache 2 are respectively stored in the storage block.

[0092] The storage block supports the read and write operations of the cache. In one embodiment, while Cache1 writes the previous data, i.e., data 1, to the storage block (Cache1→storage block), the next data to be written, i.e., data 2, is transmitted to Cache2 (task allocation module→Cache2). In this way, the time for the latter data to be transmitted on the bus can be hidden in the write time of the previous data, thereby further improving the access speed.

[0093] Similarly, for the read operation, S701 is first executed, and the memory controller 320 receives a control signal from the host 330 via the bus. The control signal includes an access instruction and address attribute information. The memory controller 320 determines the storage library 302 corresponding to the address attribute signal in the storage module 300 according to the address attribute information.

[0094] Then, step S702 is executed, in which data in the storage block is read according to the instruction inside the accessed storage bank, all the data is written into the corresponding buffer, and the read data is output to the host.

[0095] Specifically, the storage block supports read and write operations of the cache 304. For example, Cache1 reads data 1 from the corresponding storage block according to the instruction and sends data 1 to the host; Cache2 reads data 2 from the corresponding storage block according to the instruction and transmits data 2 to the host, thereby completing a read operation.

[0096] In one embodiment, when Cache1 transmits the previous data, i.e., data 1, to the host (Cache1→host), the next data that the host needs to read, i.e., data 2, can be read from the storage block to Cache2 (storage block→Cache2). In this way, the time when the data is output on the bus can be hidden in the time when the storage block is read, thereby further improving the access speed.

[0097] Since each buffer can cache 1 bit of data in one access operation, therefore, for the solution of configuring two buffers 304 for one storage block in the present invention, 2 bits of data can be accessed, while in the related art, each storage block can only access 1 bit of data under the triggering of one access command. In the related art, if you want to access 2 bits of data in each storage block at one time, the host needs to send two access signals. The present invention allows 2 bits of data to be accessed in one block in one access operation through the matching scheduling of the buffer and the storage module by the memory controller. Although the step of writing data from the buffer to the storage block is added, the time required to write data from the buffer to the storage block is much shorter than the time required for the host to send two access commands. Therefore, the memory system provided by the present invention can access a larger amount of data in one access operation, greatly improving the access efficiency of input / output operations.

[0098] In this embodiment, each storage band 305 is provided with 4 storage blocks, wherein each storage block is provided with 2 buffers correspondingly. Since one storage block in a storage band 302 can be accessed in one access operation, each storage band 302 can access 2 bits of data. Since 128 storage bands 302 are provided in each storage bank, the amount of data accessible to each storage bank 302 is 2*128bits=32bytes; the number of storage banks L in each of the storage chips can be 16, therefore, the amount of data accessible to each storage chip is 16*32bytes=512bytes; in the storage system provided by the embodiment of the present invention, the number of storage chips K is 8, therefore, the amount of data accessible to the storage system provided by the embodiment of the present invention is 512bytes*8=4K at one time; this is doubled compared to the access amount of 2KB in the related art. In the related computing system, it is usually necessary to be able to access 4KB of data at one time, and the phase change memory provided by the embodiment of the present invention for accessing 4KB of data at one time is of great significance.

[0099] In actual operation, the task allocation module 321 may be configured to select the buffer 304 for executing and storing the data based on the task execution status and / or the amount of remaining space in the buffer 304 .

[0100] Specifically, the step of selecting the buffer 304 for storing the data based on the task execution state and / or the remaining space of the buffer 304 includes:

[0101] Select the buffer 304 whose current working state is idle;

[0102] Sort the selected caches 304 according to the amount of remaining space;

[0103] Data is allocated one by one in the order of the remaining space from largest to smallest.

[0104] In the above embodiment, by setting the task allocation module, the storage space of the buffer can be efficiently utilized to achieve cost savings.

[0105] In actual operation, the memory controller 320 also includes a row decoder and a column decoder (not shown in the figure), and the row decoder and the column decoder can be configured to decode the address attribute signal received from the bus to obtain a row write decoding address signal and a column write decoding address signal. In some embodiments, the row decoder and the column decoder can also be configured to be controlled by the memory controller 320 and select one or more storage cells at the intersection of word lines and bit lines; in some embodiments, the row decoder is also configured to drive the selected word line, and the column decoder is also configured to drive the selected bit line. In some embodiments, the memory controller 320 also includes: a bit line precharge enable module, a GWL enable module, a MWL drive module, a read / write control circuit, a programming current module, and a data bias voltage switch module.

[0106] The amount of data accessed by the phase change memory system is related to multiple parameters. In some embodiments, the amount of data Q that can be accessed by the phase change memory system provided by the embodiment of the present invention in one access operation is determined by the following formula:

[0107]

[0108] Among them, K is the number of storage chips, L is the number of storage banks in each of the storage chips, M is the number of storage blocks accessed in each of the storage banks, N is the number of buffers connected to each of the storage block signals, and K, L, M and N are positive integers.

[0109] The memory controller is also configured to determine the number of storage chips, storage banks, and storage blocks accessed in one access operation based on the size of the data volume Q of one access operation and using the above formula.

[0110] In another embodiment, the number L of the memory banks 302 in each memory chip 301 is a positive integer greater than or equal to 32. In a specific embodiment, the number L of the memory banks 302 in each memory chip 301 is equal to 32. Figure 6 As shown, a memory chip 301 includes 32 memory banks 302 (Bank) including Bank0...BankN...Bank31. As can be seen from the above content, each memory bank 302 can only achieve 128×1 bits, that is, 16B of access in one access operation, and when a memory chip 301 includes 32 memory banks 302, finally, one memory chip 301 can also achieve 512B of data access in one input / output operation. Compared with the related technology of setting 16 memory banks, the amount of data that can be accessed in one access operation is greatly increased.

[0111] It should be noted that the phase change memory system embodiment and the access method embodiment provided by the present invention belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict.

[0112] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A phase change memory system, characterized in that: include: A storage module, comprising a plurality of storage chips connected to a host signal, each of the storage chips comprising a plurality of storage banks arranged in parallel and all connected to the same data transmission channel by signal, the plurality of storage banks being configured to have different address attributes; each of the storage banks comprising a plurality of storage blocks connected to the same data transmission channel by signal and at least two buffers corresponding to each of the storage blocks; the buffers being connected to the corresponding storage blocks by signal, for receiving and caching data according to instructions and / or outputting the cached data to the corresponding storage blocks; a memory controller coupled to the memory module and configured to: In an access operation, according to the received address attribute signal, the accessed storage bank corresponding to the address attribute signal is determined; Inside the accessed storage repository, all data are cached by the cache and output to the corresponding storage block, or data stored in the corresponding storage block are cached by the cache and output; The memory controller includes a task allocation module configured to select a buffer for performing storage of the data based on a task execution state and / or a remaining space amount of the buffer.

2. The system according to claim 1, characterized in that The size of the data volume Q of one access operation is determined by the following formula: Among them, K is the number of storage chips, L is the number of storage banks in each of the storage chips, M is the number of storage blocks accessed in each of the storage banks, N is the number of buffers connected to each of the storage block signals, and K, L, M and N are positive integers.

3. The system according to claim 1, characterized in that The number L of the memory banks in each of the memory chips is a positive integer greater than or equal to 32.

4. The system according to claim 1, characterized in that The step of selecting a buffer for storing the data based on the task execution state and / or the remaining space of the buffer comprises: Select a buffer whose current working state is idle; sorting the selected buffers according to the amount of remaining space; Data is allocated one by one in the order of the remaining space from largest to smallest.

5. A method for accessing a phase change memory, characterized in that: include: In an access operation, a memory controller receives an address attribute signal and determines a storage bank corresponding to the address attribute signal in a storage module, wherein the memory controller includes a task allocation module, the memory controller is coupled to the storage module, the storage module includes a plurality of storage chips connected to host signals, each of the storage chips includes a plurality of storage banks arranged in parallel and all connected to the same data transmission channel by signals, the plurality of storage banks are configured to have different address attributes; each of the storage banks includes a plurality of storage blocks connected to the same data transmission channel by signals and at least two buffers corresponding to each of the storage blocks; the buffer is connected to the corresponding storage block by signals, so as to receive and cache data according to instructions and / or output the cached data to the corresponding storage block; In the accessed storage repository, all data are stored in the buffer according to the instruction, and all data stored in the buffer are written to the corresponding storage block; wherein the task allocation module selects the buffer for executing and storing the data based on the task execution status and / or the remaining space of the buffer; or, Inside the accessed storage bank, data in the storage block is read according to the instruction, all the data is written into the corresponding buffer, and the read data is output to the host.

6. The method according to claim 5, characterized in that The size of the data volume Q of one access operation is determined by the following formula: Among them, K is the number of storage chips, L is the number of storage banks in each of the storage chips, M is the number of storage blocks accessed in each of the storage banks, N is the number of buffers connected to each of the storage block signals, and K, L, M and N are positive integers.

7. The method according to claim 5, characterized in that The number L of the memory banks in each of the memory chips is a positive integer greater than or equal to 32.

8. The method according to claim 5, characterized in that The step of selecting a buffer for storing the data based on the task execution state and / or the remaining space of the buffer comprises: Select a buffer whose current working state is idle; sorting the selected buffers according to the amount of remaining space; Data is allocated one by one in the order of the remaining space from largest to smallest.

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